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URL https://opencores.org/ocsvn/mips789/mips789/trunk

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    from Rev 43 to Rev 44
    Reverse comparison

Rev 43 → Rev 44

/trunk/bench/MODELSIM/mips789_tb.v Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/bench/MODELSIM/sim_ram.v
61,9 → 61,9
 
module sim_syn_ram0(
input [7:0] data,
input [10:0] wraddress,
input [10:0] rdaddress_a,
input [10:0] rdaddress_b,
input [29:0] wraddress,
input [29:0] rdaddress_a,
input [29:0] rdaddress_b,
input wren,
input clock,
output [7:0] qa,
71,16 → 71,16
);
 
reg [7:0] r_data;
reg [10:0] r_wraddress;
reg [10:0] r_rdaddress_a;
reg [10:0] r_rdaddress_b;
reg [29:0] r_wraddress;
reg [29:0] r_rdaddress_a;
reg [29:0] r_rdaddress_b;
reg r_wren;
reg [7:0] mem_bank [0:2047] ;
reg [7:0] mem_bank [0:12345] ;
initial begin
mem_bank[0] = 'h00 ; mem_bank[1] = 'h80 ; mem_bank[2] = 'h00 ; mem_bank[3] = 'h90 ; mem_bank[4] = 'h00 ; mem_bank[5] = 'h94 ; mem_bank[6] = 'h00 ; mem_bank[7] = 'h90 ; mem_bank[8] = 'h00 ; mem_bank[9] = 'h2a ;
mem_bank[10] = 'hfd ; mem_bank[11] = 'h04 ; mem_bank[12] = 'h00 ; mem_bank[13] = 'h00 ; mem_bank[14] = 'h9f ; mem_bank[15] = 'h00 ; mem_bank[16] = 'h00 ; mem_bank[17] = 'h10 ; mem_bank[18] = 'h00 ; mem_bank[19] = 'h00 ;
mem_bank[20] = 'h00 ; mem_bank[21] = 'h00 ; mem_bank[22] = 'h00 ; mem_bank[23] = 'hc4 ; mem_bank[24] = 'h00 ; mem_bank[25] = 'h00 ; mem_bank[26] = 'h00 ; mem_bank[27] = 'h00 ; mem_bank[28] = 'h09 ; mem_bank[29] = 'hff ;
mem_bank[0] = 'h00 ; mem_bank[1] = 'hc8 ; mem_bank[2] = 'h00 ; mem_bank[3] = 'hd8 ; mem_bank[4] = 'h00 ; mem_bank[5] = 'hdc ; mem_bank[6] = 'h00 ; mem_bank[7] = 'hd8 ; mem_bank[8] = 'h00 ; mem_bank[9] = 'h2a ;
mem_bank[10] = 'hfd ; mem_bank[11] = 'h04 ; mem_bank[12] = 'h00 ; mem_bank[13] = 'h00 ; mem_bank[14] = 'hf5 ; mem_bank[15] = 'h00 ; mem_bank[16] = 'h00 ; mem_bank[17] = 'h10 ; mem_bank[18] = 'h00 ; mem_bank[19] = 'h00 ;
mem_bank[20] = 'h00 ; mem_bank[21] = 'h00 ; mem_bank[22] = 'h00 ; mem_bank[23] = 'hfe ; mem_bank[24] = 'h00 ; mem_bank[25] = 'h00 ; mem_bank[26] = 'h00 ; mem_bank[27] = 'h00 ; mem_bank[28] = 'h09 ; mem_bank[29] = 'hff ;
mem_bank[30] = 'hff ; mem_bank[31] = 'h0d ; mem_bank[32] = 'hff ; mem_bank[33] = 'hff ; mem_bank[34] = 'hff ; mem_bank[35] = 'hff ; mem_bank[36] = 'hfa ; mem_bank[37] = 'h01 ; mem_bank[38] = 'h08 ; mem_bank[39] = 'h00 ;
mem_bank[40] = 'h40 ; mem_bank[41] = 'h23 ; mem_bank[42] = 'h80 ; mem_bank[43] = 'h21 ; mem_bank[44] = 'hc0 ; mem_bank[45] = 'hff ; mem_bank[46] = 'hff ; mem_bank[47] = 'h09 ; mem_bank[48] = 'h00 ; mem_bank[49] = 'h25 ;
mem_bank[50] = 'h0b ; mem_bank[51] = 'hff ; mem_bank[52] = 'hff ; mem_bank[53] = 'hff ; mem_bank[54] = 'hff ; mem_bank[55] = 'hfa ; mem_bank[56] = 'h01 ; mem_bank[57] = 'h08 ; mem_bank[58] = 'h00 ; mem_bank[59] = 'hff ;
107,7 → 107,7
mem_bank[260] = 'h25 ; mem_bank[261] = 'h14 ; mem_bank[262] = 'h10 ; mem_bank[263] = 'h08 ; mem_bank[264] = 'h18 ; mem_bank[265] = 'he8 ; mem_bank[266] = 'h14 ; mem_bank[267] = 'h10 ; mem_bank[268] = 'h25 ; mem_bank[269] = 'hff ;
mem_bank[270] = 'hed ; mem_bank[271] = 'hff ; mem_bank[272] = 'h00 ; mem_bank[273] = 'h00 ; mem_bank[274] = 'h07 ; mem_bank[275] = 'h25 ; mem_bank[276] = 'hce ; mem_bank[277] = 'h01 ; mem_bank[278] = 'h00 ; mem_bank[279] = 'h00 ;
mem_bank[280] = 'hfb ; mem_bank[281] = 'h00 ; mem_bank[282] = 'h14 ; mem_bank[283] = 'h10 ; mem_bank[284] = 'h08 ; mem_bank[285] = 'h18 ; mem_bank[286] = 'he0 ; mem_bank[287] = 'h18 ; mem_bank[288] = 'h14 ; mem_bank[289] = 'h10 ;
mem_bank[290] = 'h25 ; mem_bank[291] = 'h00 ; mem_bank[292] = 'h75 ; mem_bank[293] = 'h74 ; mem_bank[294] = 'hcc ; mem_bank[295] = 'h00 ; mem_bank[296] = 'h1c ; mem_bank[297] = 'h00 ; mem_bank[298] = 'h21 ; mem_bank[299] = 'h4d ;
mem_bank[290] = 'h25 ; mem_bank[291] = 'h00 ; mem_bank[292] = 'h75 ; mem_bank[293] = 'h18 ; mem_bank[294] = 'hcc ; mem_bank[295] = 'h00 ; mem_bank[296] = 'h1c ; mem_bank[297] = 'h00 ; mem_bank[298] = 'h21 ; mem_bank[299] = 'h4d ;
mem_bank[300] = 'h00 ; mem_bank[301] = 'hfd ; mem_bank[302] = 'h00 ; mem_bank[303] = 'h3b ; mem_bank[304] = 'h4f ; mem_bank[305] = 'h00 ; mem_bank[306] = 'h1c ; mem_bank[307] = 'h4d ; mem_bank[308] = 'h00 ; mem_bank[309] = 'h00 ;
mem_bank[310] = 'hff ; mem_bank[311] = 'h01 ; mem_bank[312] = 'hfa ; mem_bank[313] = 'h00 ; mem_bank[314] = 'he8 ; mem_bank[315] = 'h10 ; mem_bank[316] = 'h00 ; mem_bank[317] = 'h14 ; mem_bank[318] = 'h00 ; mem_bank[319] = 'h00 ;
mem_bank[320] = 'h00 ; mem_bank[321] = 'h00 ; mem_bank[322] = 'h00 ; mem_bank[323] = 'h34 ; mem_bank[324] = 'h55 ; mem_bank[325] = 'h00 ; mem_bank[326] = 'h10 ; mem_bank[327] = 'h00 ; mem_bank[328] = 'h08 ; mem_bank[329] = 'h18 ;
119,14 → 119,54
mem_bank[380] = 'h00 ; mem_bank[381] = 'h14 ; mem_bank[382] = 'h00 ; mem_bank[383] = 'hdf ; mem_bank[384] = 'h24 ; mem_bank[385] = 'h08 ; mem_bank[386] = 'h00 ; mem_bank[387] = 'h00 ; mem_bank[388] = 'h14 ; mem_bank[389] = 'h00 ;
mem_bank[390] = 'h00 ; mem_bank[391] = 'h20 ; mem_bank[392] = 'h08 ; mem_bank[393] = 'h00 ; mem_bank[394] = 'h00 ; mem_bank[395] = 'h14 ; mem_bank[396] = 'h00 ; mem_bank[397] = 'hbf ; mem_bank[398] = 'h24 ; mem_bank[399] = 'h08 ;
mem_bank[400] = 'h00 ; mem_bank[401] = 'h00 ; mem_bank[402] = 'h14 ; mem_bank[403] = 'h00 ; mem_bank[404] = 'h00 ; mem_bank[405] = 'h40 ; mem_bank[406] = 'h08 ; mem_bank[407] = 'h00 ; mem_bank[408] = 'hff ; mem_bank[409] = 'h00 ;
mem_bank[410] = 'h1c ; mem_bank[411] = 'h08 ; mem_bank[412] = 'h00 ; mem_bank[413] = 'h08 ; mem_bank[414] = 'h00 ; mem_bank[415] = 'he8 ; mem_bank[416] = 'h10 ; mem_bank[417] = 'h5c ; mem_bank[418] = 'h00 ; mem_bank[419] = 'h28 ;
mem_bank[420] = 'h00 ; mem_bank[421] = 'h00 ; mem_bank[422] = 'h2c ; mem_bank[423] = 'h00 ; mem_bank[424] = 'h00 ; mem_bank[425] = 'h30 ; mem_bank[426] = 'h83 ; mem_bank[427] = 'h00 ; mem_bank[428] = 'h00 ; mem_bank[429] = 'h14 ;
mem_bank[430] = 'h00 ; mem_bank[431] = 'h00 ; mem_bank[432] = 'h01 ; mem_bank[433] = 'h00 ; mem_bank[434] = 'h00 ; mem_bank[435] = 'h00 ; mem_bank[436] = 'h25 ; mem_bank[437] = 'h00 ; mem_bank[438] = 'h00 ; mem_bank[439] = 'h00 ;
mem_bank[440] = 'h25 ; mem_bank[441] = 'h00 ; mem_bank[442] = 'h00 ; mem_bank[443] = 'h00 ; mem_bank[444] = 'h25 ; mem_bank[445] = 'h00 ; mem_bank[446] = 'h8a ; mem_bank[447] = 'h00 ; mem_bank[448] = 'h91 ; mem_bank[449] = 'h00 ;
mem_bank[450] = 'hfb ; mem_bank[451] = 'h00 ; mem_bank[452] = 'he0 ; mem_bank[453] = 'h18 ; mem_bank[454] = 'h14 ; mem_bank[455] = 'h10 ; mem_bank[456] = 'h63 ; mem_bank[457] = 'hff ; mem_bank[458] = 'h7c ; mem_bank[459] = 'hff ;
mem_bank[460] = 'h83 ; mem_bank[461] = 'h00 ; mem_bank[462] = 'hfb ; mem_bank[463] = 'h00 ; mem_bank[464] = 'h14 ; mem_bank[465] = 'h00 ; mem_bank[466] = 'h18 ; mem_bank[467] = 'h14 ; mem_bank[468] = 'h10 ; mem_bank[469] = 'h08 ;
mem_bank[470] = 'h20 ; mem_bank[471] = 'h00 ; mem_bank[472] = 'h00 ; mem_bank[473] = 'h00 ; mem_bank[474] = 'h00 ; mem_bank[475] = 'h00 ; mem_bank[476] = 'h00 ; mem_bank[477] = 'h73 ; mem_bank[478] = 'h20 ; mem_bank[479] = 'h53 ;
mem_bank[480] = 'h20 ; mem_bank[481] = 'h54 ; mem_bank[482] = 'h44 ; mem_bank[483] = 'h00 ; mem_bank[484] = 'h00 ;
mem_bank[410] = 'h1c ; mem_bank[411] = 'h08 ; mem_bank[412] = 'h00 ; mem_bank[413] = 'h00 ; mem_bank[414] = 'he0 ; mem_bank[415] = 'h07 ; mem_bank[416] = 'h00 ; mem_bank[417] = 'hd8 ; mem_bank[418] = 'h0f ; mem_bank[419] = 'h0a ;
mem_bank[420] = 'h03 ; mem_bank[421] = 'h21 ; mem_bank[422] = 'h02 ; mem_bank[423] = 'h30 ; mem_bank[424] = 'h37 ; mem_bank[425] = 'h00 ; mem_bank[426] = 'hff ; mem_bank[427] = 'hf6 ; mem_bank[428] = 'h02 ; mem_bank[429] = 'h00 ;
mem_bank[430] = 'h08 ; mem_bank[431] = 'hd8 ; mem_bank[432] = 'h25 ; mem_bank[433] = 'h00 ; mem_bank[434] = 'hf2 ; mem_bank[435] = 'h09 ; mem_bank[436] = 'h00 ; mem_bank[437] = 'he8 ; mem_bank[438] = 'hcc ; mem_bank[439] = 'hcd ;
mem_bank[440] = 'h21 ; mem_bank[441] = 'h19 ; mem_bank[442] = 'h10 ; mem_bank[443] = 'hc2 ; mem_bank[444] = 'h80 ; mem_bank[445] = 'h21 ; mem_bank[446] = 'h40 ; mem_bank[447] = 'h23 ; mem_bank[448] = 'h30 ; mem_bank[449] = 'h00 ;
mem_bank[450] = 'hff ; mem_bank[451] = 'hf4 ; mem_bank[452] = 'h25 ; mem_bank[453] = 'h00 ; mem_bank[454] = 'h08 ; mem_bank[455] = 'he8 ; mem_bank[456] = 'he0 ; mem_bank[457] = 'h18 ; mem_bank[458] = 'h14 ; mem_bank[459] = 'h10 ;
mem_bank[460] = 'hb0 ; mem_bank[461] = 'h25 ; mem_bank[462] = 'h75 ; mem_bank[463] = 'h25 ; mem_bank[464] = 'h00 ; mem_bank[465] = 'h75 ; mem_bank[466] = 'h14 ; mem_bank[467] = 'h9a ; mem_bank[468] = 'hff ; mem_bank[469] = 'h2b ;
mem_bank[470] = 'h1e ; mem_bank[471] = 'h42 ; mem_bank[472] = 'h04 ; mem_bank[473] = 'h83 ; mem_bank[474] = 'h19 ; mem_bank[475] = 'h10 ; mem_bank[476] = 'hc2 ; mem_bank[477] = 'h00 ; mem_bank[478] = 'h60 ; mem_bank[479] = 'h80 ;
mem_bank[480] = 'h21 ; mem_bank[481] = 'h00 ; mem_bank[482] = 'h75 ; mem_bank[483] = 'h00 ; mem_bank[484] = 'h00 ; mem_bank[485] = 'h75 ; mem_bank[486] = 'h18 ; mem_bank[487] = 'h40 ; mem_bank[488] = 'h23 ; mem_bank[489] = 'h80 ;
mem_bank[490] = 'h23 ; mem_bank[491] = 'h00 ; mem_bank[492] = 'h21 ; mem_bank[493] = 'hc0 ; mem_bank[494] = 'h23 ; mem_bank[495] = 'h40 ; mem_bank[496] = 'h23 ; mem_bank[497] = 'h80 ; mem_bank[498] = 'h21 ; mem_bank[499] = 'h40 ;
mem_bank[500] = 'h23 ; mem_bank[501] = 'hf5 ; mem_bank[502] = 'hff ; mem_bank[503] = 'h2b ; mem_bank[504] = 'h23 ; mem_bank[505] = 'he6 ; mem_bank[506] = 'h89 ; mem_bank[507] = 'h19 ; mem_bank[508] = 'h10 ; mem_bank[509] = 'h42 ;
mem_bank[510] = 'h00 ; mem_bank[511] = 'h60 ; mem_bank[512] = 'h80 ; mem_bank[513] = 'h21 ; mem_bank[514] = 'h00 ; mem_bank[515] = 'h75 ; mem_bank[516] = 'h00 ; mem_bank[517] = 'h00 ; mem_bank[518] = 'h75 ; mem_bank[519] = 'h24 ;
mem_bank[520] = 'h40 ; mem_bank[521] = 'h21 ; mem_bank[522] = 'h80 ; mem_bank[523] = 'h23 ; mem_bank[524] = 'h80 ; mem_bank[525] = 'h23 ; mem_bank[526] = 'h00 ; mem_bank[527] = 'h23 ; mem_bank[528] = 'h40 ; mem_bank[529] = 'h21 ;
mem_bank[530] = 'h00 ; mem_bank[531] = 'h23 ; mem_bank[532] = 'h0f ; mem_bank[533] = 'h3f ; mem_bank[534] = 'h2b ; mem_bank[535] = 'h05 ; mem_bank[536] = 'h31 ; mem_bank[537] = 'h00 ; mem_bank[538] = 'h75 ; mem_bank[539] = 'h30 ;
mem_bank[540] = 'h31 ; mem_bank[541] = 'hff ; mem_bank[542] = 'h2b ; mem_bank[543] = 'h21 ; mem_bank[544] = 'h5f ; mem_bank[545] = 'h6b ; mem_bank[546] = 'h19 ; mem_bank[547] = 'h10 ; mem_bank[548] = 'h82 ; mem_bank[549] = 'h00 ;
mem_bank[550] = 'h60 ; mem_bank[551] = 'h14 ; mem_bank[552] = 'h80 ; mem_bank[553] = 'h21 ; mem_bank[554] = 'h00 ; mem_bank[555] = 'h75 ; mem_bank[556] = 'h00 ; mem_bank[557] = 'h3b ; mem_bank[558] = 'h20 ; mem_bank[559] = 'h40 ;
mem_bank[560] = 'h23 ; mem_bank[561] = 'h80 ; mem_bank[562] = 'h23 ; mem_bank[563] = 'hc0 ; mem_bank[564] = 'h21 ; mem_bank[565] = 'h80 ; mem_bank[566] = 'h21 ; mem_bank[567] = 'hc0 ; mem_bank[568] = 'h23 ; mem_bank[569] = 'h0f ;
mem_bank[570] = 'h3f ; mem_bank[571] = 'h2b ; mem_bank[572] = 'h09 ; mem_bank[573] = 'h1b ; mem_bank[574] = 'h00 ; mem_bank[575] = 'h75 ; mem_bank[576] = 'h30 ; mem_bank[577] = 'h0f ; mem_bank[578] = 'h3f ; mem_bank[579] = 'h2b ;
mem_bank[580] = 'h17 ; mem_bank[581] = 'h1b ; mem_bank[582] = 'h83 ; mem_bank[583] = 'h19 ; mem_bank[584] = 'h10 ; mem_bank[585] = 'h82 ; mem_bank[586] = 'h00 ; mem_bank[587] = 'h60 ; mem_bank[588] = 'h80 ; mem_bank[589] = 'h21 ;
mem_bank[590] = 'h00 ; mem_bank[591] = 'h75 ; mem_bank[592] = 'h00 ; mem_bank[593] = 'h00 ; mem_bank[594] = 'h75 ; mem_bank[595] = 'h3c ; mem_bank[596] = 'h40 ; mem_bank[597] = 'h23 ; mem_bank[598] = 'h80 ; mem_bank[599] = 'h23 ;
mem_bank[600] = 'hc0 ; mem_bank[601] = 'h21 ; mem_bank[602] = 'h80 ; mem_bank[603] = 'h23 ; mem_bank[604] = 'h01 ; mem_bank[605] = 'h9f ; mem_bank[606] = 'h2b ; mem_bank[607] = 'h20 ; mem_bank[608] = 'h42 ; mem_bank[609] = 'h7c ;
mem_bank[610] = 'hc5 ; mem_bank[611] = 'h19 ; mem_bank[612] = 'h10 ; mem_bank[613] = 'hc2 ; mem_bank[614] = 'h00 ; mem_bank[615] = 'h60 ; mem_bank[616] = 'h80 ; mem_bank[617] = 'h21 ; mem_bank[618] = 'h00 ; mem_bank[619] = 'h75 ;
mem_bank[620] = 'h00 ; mem_bank[621] = 'h00 ; mem_bank[622] = 'h75 ; mem_bank[623] = 'h24 ; mem_bank[624] = 'h40 ; mem_bank[625] = 'h21 ; mem_bank[626] = 'h80 ; mem_bank[627] = 'h21 ; mem_bank[628] = 'h80 ; mem_bank[629] = 'h21 ;
mem_bank[630] = 'h80 ; mem_bank[631] = 'h21 ; mem_bank[632] = 'h40 ; mem_bank[633] = 'h23 ; mem_bank[634] = 'he8 ; mem_bank[635] = 'h05 ; mem_bank[636] = 'h20 ; mem_bank[637] = 'h00 ; mem_bank[638] = 'h75 ; mem_bank[639] = 'h48 ;
mem_bank[640] = 'h20 ; mem_bank[641] = 'h1f ; mem_bank[642] = 'he8 ; mem_bank[643] = 'hb7 ; mem_bank[644] = 'h59 ; mem_bank[645] = 'h19 ; mem_bank[646] = 'h10 ; mem_bank[647] = 'h42 ; mem_bank[648] = 'h00 ; mem_bank[649] = 'h60 ;
mem_bank[650] = 'h14 ; mem_bank[651] = 'h80 ; mem_bank[652] = 'h21 ; mem_bank[653] = 'h00 ; mem_bank[654] = 'h75 ; mem_bank[655] = 'h00 ; mem_bank[656] = 'h3b ; mem_bank[657] = 'h20 ; mem_bank[658] = 'h80 ; mem_bank[659] = 'h21 ;
mem_bank[660] = 'hc0 ; mem_bank[661] = 'h23 ; mem_bank[662] = 'h00 ; mem_bank[663] = 'h21 ; mem_bank[664] = 'h00 ; mem_bank[665] = 'h23 ; mem_bank[666] = 'he8 ; mem_bank[667] = 'h08 ; mem_bank[668] = 'h62 ; mem_bank[669] = 'h00 ;
mem_bank[670] = 'h75 ; mem_bank[671] = 'h48 ; mem_bank[672] = 'he8 ; mem_bank[673] = 'h17 ; mem_bank[674] = 'h64 ; mem_bank[675] = 'h62 ; mem_bank[676] = 'hd3 ; mem_bank[677] = 'h19 ; mem_bank[678] = 'h10 ; mem_bank[679] = 'h82 ;
mem_bank[680] = 'h00 ; mem_bank[681] = 'h60 ; mem_bank[682] = 'h80 ; mem_bank[683] = 'h21 ; mem_bank[684] = 'h00 ; mem_bank[685] = 'h75 ; mem_bank[686] = 'h00 ; mem_bank[687] = 'h00 ; mem_bank[688] = 'h75 ; mem_bank[689] = 'h54 ;
mem_bank[690] = 'h40 ; mem_bank[691] = 'h23 ; mem_bank[692] = 'h80 ; mem_bank[693] = 'h21 ; mem_bank[694] = 'hc0 ; mem_bank[695] = 'h23 ; mem_bank[696] = 'h64 ; mem_bank[697] = 'h17 ; mem_bank[698] = 'h14 ; mem_bank[699] = 'heb ;
mem_bank[700] = 'h1f ; mem_bank[701] = 'h19 ; mem_bank[702] = 'h10 ; mem_bank[703] = 'h42 ; mem_bank[704] = 'h00 ; mem_bank[705] = 'h60 ; mem_bank[706] = 'h80 ; mem_bank[707] = 'h21 ; mem_bank[708] = 'h00 ; mem_bank[709] = 'h75 ;
mem_bank[710] = 'h00 ; mem_bank[711] = 'h00 ; mem_bank[712] = 'h75 ; mem_bank[713] = 'h24 ; mem_bank[714] = 'h40 ; mem_bank[715] = 'h21 ; mem_bank[716] = 'hc0 ; mem_bank[717] = 'h21 ; mem_bank[718] = 'h80 ; mem_bank[719] = 'h23 ;
mem_bank[720] = 'h14 ; mem_bank[721] = 'h14 ; mem_bank[722] = 'h00 ; mem_bank[723] = 'hcc ; mem_bank[724] = 'hcd ; mem_bank[725] = 'h19 ; mem_bank[726] = 'h10 ; mem_bank[727] = 'hc2 ; mem_bank[728] = 'h60 ; mem_bank[729] = 'h14 ;
mem_bank[730] = 'h80 ; mem_bank[731] = 'h21 ; mem_bank[732] = 'h00 ; mem_bank[733] = 'h75 ; mem_bank[734] = 'h00 ; mem_bank[735] = 'h3b ; mem_bank[736] = 'h20 ; mem_bank[737] = 'h80 ; mem_bank[738] = 'h21 ; mem_bank[739] = 'h40 ;
mem_bank[740] = 'h23 ; mem_bank[741] = 'h00 ; mem_bank[742] = 'h60 ; mem_bank[743] = 'h80 ; mem_bank[744] = 'h21 ; mem_bank[745] = 'h00 ; mem_bank[746] = 'h75 ; mem_bank[747] = 'h00 ; mem_bank[748] = 'h3b ; mem_bank[749] = 'h0d ;
mem_bank[750] = 'h3b ; mem_bank[751] = 'h0a ; mem_bank[752] = 'h18 ; mem_bank[753] = 'h14 ; mem_bank[754] = 'h10 ; mem_bank[755] = 'h08 ; mem_bank[756] = 'h20 ; mem_bank[757] = 'he8 ; mem_bank[758] = 'h14 ; mem_bank[759] = 'h10 ;
mem_bank[760] = 'h03 ; mem_bank[761] = 'hc8 ; mem_bank[762] = 'h25 ; mem_bank[763] = 'h40 ; mem_bank[764] = 'hfc ; mem_bank[765] = 'h21 ; mem_bank[766] = 'h08 ; mem_bank[767] = 'h00 ; mem_bank[768] = 'h00 ; mem_bank[769] = 'h00 ;
mem_bank[770] = 'h00 ; mem_bank[771] = 'h00 ; mem_bank[772] = 'h00 ; mem_bank[773] = 'h00 ; mem_bank[774] = 'h73 ; mem_bank[775] = 'h20 ; mem_bank[776] = 'h53 ; mem_bank[777] = 'h20 ; mem_bank[778] = 'h54 ; mem_bank[779] = 'h44 ;
mem_bank[780] = 'h00 ; mem_bank[781] = 'h65 ; mem_bank[782] = 'h00 ; mem_bank[783] = 'h68 ; mem_bank[784] = 'h00 ; mem_bank[785] = 'h65 ; mem_bank[786] = 'h00 ; mem_bank[787] = 'h74 ; mem_bank[788] = 'h00 ; mem_bank[789] = 'h74 ;
mem_bank[790] = 'h00 ; mem_bank[791] = 'h74 ; mem_bank[792] = 'h00 ; mem_bank[793] = 'h72 ; mem_bank[794] = 'h00 ; mem_bank[795] = 'h6e ; mem_bank[796] = 'h00 ; mem_bank[797] = 'h65 ; mem_bank[798] = 'h6e ; mem_bank[799] = 'h00 ;
mem_bank[800] = 'h68 ; mem_bank[801] = 'h6e ; mem_bank[802] = 'h00 ; mem_bank[803] = 'h65 ; mem_bank[804] = 'h65 ; mem_bank[805] = 'h00 ; mem_bank[806] = 'h74 ; mem_bank[807] = 'h00 ; mem_bank[808] = 'h74 ; mem_bank[809] = 'h00 ;
mem_bank[810] = 'h72 ; mem_bank[811] = 'h6e ; mem_bank[812] = 'h00 ; mem_bank[813] = 'h72 ; mem_bank[814] = 'h6e ; mem_bank[815] = 'h00 ; mem_bank[816] = 'h6c ; mem_bank[817] = 'h00 ; mem_bank[818] = 'h76 ; mem_bank[819] = 'h00 ;
mem_bank[820] = 'h00 ; mem_bank[821] = 'h65 ; mem_bank[822] = 'h00 ; mem_bank[823] = 'h68 ; mem_bank[824] = 'h00 ; mem_bank[825] = 'h65 ; mem_bank[826] = 'h00 ; mem_bank[827] = 'h00 ; mem_bank[828] = 'h65 ; mem_bank[829] = 'h00 ;
mem_bank[830] = 'h72 ; mem_bank[831] = 'h00 ; mem_bank[832] = 'h65 ; mem_bank[833] = 'h00 ; mem_bank[834] = 'h00 ; mem_bank[835] = 'h00 ; mem_bank[836] = 'h00 ; mem_bank[837] = 'h00 ; mem_bank[838] = 'h6c ; mem_bank[839] = 'h6e ;
mem_bank[840] = 'h00 ; mem_bank[841] = 'h6e ; mem_bank[842] = 'h64 ; mem_bank[843] = 'h00 ; mem_bank[844] = 'h6c ; mem_bank[845] = 'h20 ; mem_bank[846] = 'h00 ; mem_bank[847] = 'h6c ; mem_bank[848] = 'h6e ; mem_bank[849] = 'h00 ;
mem_bank[850] = 'h75 ; mem_bank[851] = 'h64 ; mem_bank[852] = 'h00 ; mem_bank[853] = 'h6f ; mem_bank[854] = 'h6e ; mem_bank[855] = 'h00 ; mem_bank[856] = 'h10 ; mem_bank[857] = 'h0c ; mem_bank[858] = 'h08 ; mem_bank[859] = 'h00 ;
mem_bank[860] = 'hf8 ; mem_bank[861] = 'hf0 ; mem_bank[862] = 'hec ; mem_bank[863] = 'he4 ; mem_bank[864] = 'hdc ; mem_bank[865] = 'hd4 ; mem_bank[866] = 'hd0 ; mem_bank[867] = 'hc8 ; mem_bank[868] = 'hc0 ; mem_bank[869] = 'hb4 ;
mem_bank[870] = 'ha8 ; mem_bank[871] = 'ha0 ; mem_bank[872] = 'h98 ; mem_bank[873] = 'h8c ; mem_bank[874] = 'h80 ; mem_bank[875] = 'h74 ; mem_bank[876] = 'h10 ; mem_bank[877] = 'hd0 ; mem_bank[878] = 'h6c ; mem_bank[879] = 'h64 ;
mem_bank[880] = 'h5c ; mem_bank[881] = 'h54 ; mem_bank[882] = 'h4c ; mem_bank[883] = 'h44 ; mem_bank[884] = 'h3c ; mem_bank[885] = 'h34 ; mem_bank[886] = 'h00 ;
end
always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;
always @ (posedge clock)
137,8 → 177,8
r_rdaddress_b<=rdaddress_b;
r_wren<=wren;
end
assign qa =(r_rdaddress_a>484)?0:mem_bank[r_rdaddress_a];
assign qb =(r_rdaddress_b>484)?0:mem_bank[r_rdaddress_b];
assign qa =mem_bank[r_rdaddress_a];
assign qb =mem_bank[r_rdaddress_b];
endmodule
 
 
145,9 → 185,9
 
module sim_syn_ram1(
input [7:0] data,
input [10:0] wraddress,
input [10:0] rdaddress_a,
input [10:0] rdaddress_b,
input [29:0] wraddress,
input [29:0] rdaddress_a,
input [29:0] rdaddress_b,
input wren,
input clock,
output [7:0] qa,
155,16 → 195,16
);
 
reg [7:0] r_data;
reg [10:0] r_wraddress;
reg [10:0] r_rdaddress_a;
reg [10:0] r_rdaddress_b;
reg [29:0] r_wraddress;
reg [29:0] r_rdaddress_a;
reg [29:0] r_rdaddress_b;
reg r_wren;
reg [7:0] mem_bank [0:2047] ;
reg [7:0] mem_bank [0:12345] ;
initial begin
mem_bank[0] = 'h00 ; mem_bank[1] = 'h87 ; mem_bank[2] = 'h00 ; mem_bank[3] = 'h07 ; mem_bank[4] = 'h00 ; mem_bank[5] = 'h07 ; mem_bank[6] = 'h00 ; mem_bank[7] = 'h09 ; mem_bank[8] = 'h00 ; mem_bank[9] = 'h18 ;
mem_bank[10] = 'hff ; mem_bank[11] = 'h00 ; mem_bank[12] = 'h00 ; mem_bank[13] = 'h00 ; mem_bank[14] = 'h01 ; mem_bank[15] = 'h00 ; mem_bank[16] = 'h00 ; mem_bank[17] = 'h00 ; mem_bank[18] = 'h00 ; mem_bank[19] = 'h00 ;
mem_bank[20] = 'h00 ; mem_bank[21] = 'h00 ; mem_bank[22] = 'h00 ; mem_bank[23] = 'h01 ; mem_bank[24] = 'h00 ; mem_bank[25] = 'h00 ; mem_bank[26] = 'h00 ; mem_bank[27] = 'h00 ; mem_bank[28] = 'h00 ; mem_bank[29] = 'hff ;
mem_bank[0] = 'h00 ; mem_bank[1] = 'h8d ; mem_bank[2] = 'h00 ; mem_bank[3] = 'h0d ; mem_bank[4] = 'h00 ; mem_bank[5] = 'h0d ; mem_bank[6] = 'h00 ; mem_bank[7] = 'h0f ; mem_bank[8] = 'h00 ; mem_bank[9] = 'h18 ;
mem_bank[10] = 'hff ; mem_bank[11] = 'h00 ; mem_bank[12] = 'h00 ; mem_bank[13] = 'h00 ; mem_bank[14] = 'h02 ; mem_bank[15] = 'h00 ; mem_bank[16] = 'h00 ; mem_bank[17] = 'h00 ; mem_bank[18] = 'h00 ; mem_bank[19] = 'h00 ;
mem_bank[20] = 'h00 ; mem_bank[21] = 'h00 ; mem_bank[22] = 'h00 ; mem_bank[23] = 'h02 ; mem_bank[24] = 'h00 ; mem_bank[25] = 'h00 ; mem_bank[26] = 'h00 ; mem_bank[27] = 'h00 ; mem_bank[28] = 'h00 ; mem_bank[29] = 'hff ;
mem_bank[30] = 'hff ; mem_bank[31] = 'h00 ; mem_bank[32] = 'hff ; mem_bank[33] = 'hff ; mem_bank[34] = 'hff ; mem_bank[35] = 'hff ; mem_bank[36] = 'hff ; mem_bank[37] = 'h00 ; mem_bank[38] = 'h00 ; mem_bank[39] = 'h00 ;
mem_bank[40] = 'h11 ; mem_bank[41] = 'h10 ; mem_bank[42] = 'h10 ; mem_bank[43] = 'h10 ; mem_bank[44] = 'h18 ; mem_bank[45] = 'hff ; mem_bank[46] = 'hff ; mem_bank[47] = 'h00 ; mem_bank[48] = 'h00 ; mem_bank[49] = 'h20 ;
mem_bank[50] = 'h00 ; mem_bank[51] = 'hff ; mem_bank[52] = 'hff ; mem_bank[53] = 'hff ; mem_bank[54] = 'hff ; mem_bank[55] = 'hff ; mem_bank[56] = 'h00 ; mem_bank[57] = 'h00 ; mem_bank[58] = 'h00 ; mem_bank[59] = 'h00 ;
191,7 → 231,7
mem_bank[260] = 'h20 ; mem_bank[261] = 'h00 ; mem_bank[262] = 'h00 ; mem_bank[263] = 'h00 ; mem_bank[264] = 'h00 ; mem_bank[265] = 'hff ; mem_bank[266] = 'h00 ; mem_bank[267] = 'h00 ; mem_bank[268] = 'h80 ; mem_bank[269] = 'h00 ;
mem_bank[270] = 'h00 ; mem_bank[271] = 'h00 ; mem_bank[272] = 'h00 ; mem_bank[273] = 'h00 ; mem_bank[274] = 'h00 ; mem_bank[275] = 'h20 ; mem_bank[276] = 'h00 ; mem_bank[277] = 'h00 ; mem_bank[278] = 'h00 ; mem_bank[279] = 'h00 ;
mem_bank[280] = 'hff ; mem_bank[281] = 'h00 ; mem_bank[282] = 'h00 ; mem_bank[283] = 'h00 ; mem_bank[284] = 'h00 ; mem_bank[285] = 'h00 ; mem_bank[286] = 'hff ; mem_bank[287] = 'h00 ; mem_bank[288] = 'h00 ; mem_bank[289] = 'h00 ;
mem_bank[290] = 'h80 ; mem_bank[291] = 'h00 ; mem_bank[292] = 'h00 ; mem_bank[293] = 'h07 ; mem_bank[294] = 'h00 ; mem_bank[295] = 'h80 ; mem_bank[296] = 'h00 ; mem_bank[297] = 'h00 ; mem_bank[298] = 'h00 ; mem_bank[299] = 'h00 ;
mem_bank[290] = 'h80 ; mem_bank[291] = 'h00 ; mem_bank[292] = 'h00 ; mem_bank[293] = 'h0c ; mem_bank[294] = 'h00 ; mem_bank[295] = 'h80 ; mem_bank[296] = 'h00 ; mem_bank[297] = 'h00 ; mem_bank[298] = 'h00 ; mem_bank[299] = 'h00 ;
mem_bank[300] = 'h00 ; mem_bank[301] = 'hff ; mem_bank[302] = 'h00 ; mem_bank[303] = 'h00 ; mem_bank[304] = 'h00 ; mem_bank[305] = 'h80 ; mem_bank[306] = 'h00 ; mem_bank[307] = 'h00 ; mem_bank[308] = 'h00 ; mem_bank[309] = 'h00 ;
mem_bank[310] = 'h00 ; mem_bank[311] = 'h00 ; mem_bank[312] = 'hff ; mem_bank[313] = 'h00 ; mem_bank[314] = 'hff ; mem_bank[315] = 'h00 ; mem_bank[316] = 'h80 ; mem_bank[317] = 'h00 ; mem_bank[318] = 'h00 ; mem_bank[319] = 'h00 ;
mem_bank[320] = 'h01 ; mem_bank[321] = 'h00 ; mem_bank[322] = 'h80 ; mem_bank[323] = 'h00 ; mem_bank[324] = 'h01 ; mem_bank[325] = 'h00 ; mem_bank[326] = 'h00 ; mem_bank[327] = 'h00 ; mem_bank[328] = 'h00 ; mem_bank[329] = 'h00 ;
203,14 → 243,54
mem_bank[380] = 'h80 ; mem_bank[381] = 'h00 ; mem_bank[382] = 'h00 ; mem_bank[383] = 'hff ; mem_bank[384] = 'h18 ; mem_bank[385] = 'h00 ; mem_bank[386] = 'h00 ; mem_bank[387] = 'h80 ; mem_bank[388] = 'h00 ; mem_bank[389] = 'h00 ;
mem_bank[390] = 'h00 ; mem_bank[391] = 'h00 ; mem_bank[392] = 'h00 ; mem_bank[393] = 'h00 ; mem_bank[394] = 'h80 ; mem_bank[395] = 'h00 ; mem_bank[396] = 'h00 ; mem_bank[397] = 'hff ; mem_bank[398] = 'h18 ; mem_bank[399] = 'h00 ;
mem_bank[400] = 'h00 ; mem_bank[401] = 'h80 ; mem_bank[402] = 'h00 ; mem_bank[403] = 'h00 ; mem_bank[404] = 'h00 ; mem_bank[405] = 'h00 ; mem_bank[406] = 'h00 ; mem_bank[407] = 'h00 ; mem_bank[408] = 'h00 ; mem_bank[409] = 'h80 ;
mem_bank[410] = 'h00 ; mem_bank[411] = 'h00 ; mem_bank[412] = 'h00 ; mem_bank[413] = 'h00 ; mem_bank[414] = 'h00 ; mem_bank[415] = 'hff ; mem_bank[416] = 'h00 ; mem_bank[417] = 'h00 ; mem_bank[418] = 'h80 ; mem_bank[419] = 'h00 ;
mem_bank[420] = 'h00 ; mem_bank[421] = 'h80 ; mem_bank[422] = 'h00 ; mem_bank[423] = 'h00 ; mem_bank[424] = 'h80 ; mem_bank[425] = 'h00 ; mem_bank[426] = 'h01 ; mem_bank[427] = 'h00 ; mem_bank[428] = 'h80 ; mem_bank[429] = 'h00 ;
mem_bank[430] = 'h00 ; mem_bank[431] = 'h00 ; mem_bank[432] = 'h00 ; mem_bank[433] = 'h00 ; mem_bank[434] = 'h00 ; mem_bank[435] = 'h80 ; mem_bank[436] = 'h10 ; mem_bank[437] = 'h00 ; mem_bank[438] = 'h00 ; mem_bank[439] = 'h20 ;
mem_bank[440] = 'h10 ; mem_bank[441] = 'h00 ; mem_bank[442] = 'h00 ; mem_bank[443] = 'h40 ; mem_bank[444] = 'h10 ; mem_bank[445] = 'h00 ; mem_bank[446] = 'h01 ; mem_bank[447] = 'h00 ; mem_bank[448] = 'h01 ; mem_bank[449] = 'h00 ;
mem_bank[450] = 'hff ; mem_bank[451] = 'h00 ; mem_bank[452] = 'hff ; mem_bank[453] = 'h00 ; mem_bank[454] = 'h00 ; mem_bank[455] = 'h00 ; mem_bank[456] = 'h00 ; mem_bank[457] = 'hff ; mem_bank[458] = 'h01 ; mem_bank[459] = 'hff ;
mem_bank[460] = 'h01 ; mem_bank[461] = 'h00 ; mem_bank[462] = 'hff ; mem_bank[463] = 'h80 ; mem_bank[464] = 'h00 ; mem_bank[465] = 'h00 ; mem_bank[466] = 'h00 ; mem_bank[467] = 'h00 ; mem_bank[468] = 'h00 ; mem_bank[469] = 'h00 ;
mem_bank[470] = 'h00 ; mem_bank[471] = 'h00 ; mem_bank[472] = 'h00 ; mem_bank[473] = 'h00 ; mem_bank[474] = 'h00 ; mem_bank[475] = 'h00 ; mem_bank[476] = 'h00 ; mem_bank[477] = 'h69 ; mem_bank[478] = 'h73 ; mem_bank[479] = 'h50 ;
mem_bank[480] = 'h39 ; mem_bank[481] = 'h4f ; mem_bank[482] = 'h41 ; mem_bank[483] = 'h0a ; mem_bank[484] = 'h00 ;
mem_bank[410] = 'h00 ; mem_bank[411] = 'h00 ; mem_bank[412] = 'h00 ; mem_bank[413] = 'h00 ; mem_bank[414] = 'h0d ; mem_bank[415] = 'h00 ; mem_bank[416] = 'h00 ; mem_bank[417] = 'h0d ; mem_bank[418] = 'h00 ; mem_bank[419] = 'h00 ;
mem_bank[420] = 'h00 ; mem_bank[421] = 'h28 ; mem_bank[422] = 'h00 ; mem_bank[423] = 'h00 ; mem_bank[424] = 'h00 ; mem_bank[425] = 'h00 ; mem_bank[426] = 'hff ; mem_bank[427] = 'hff ; mem_bank[428] = 'h21 ; mem_bank[429] = 'h00 ;
mem_bank[430] = 'h00 ; mem_bank[431] = 'h0d ; mem_bank[432] = 'h30 ; mem_bank[433] = 'h00 ; mem_bank[434] = 'h0d ; mem_bank[435] = 'h00 ; mem_bank[436] = 'h00 ; mem_bank[437] = 'h0d ; mem_bank[438] = 'hcc ; mem_bank[439] = 'hcc ;
mem_bank[440] = 'h20 ; mem_bank[441] = 'h00 ; mem_bank[442] = 'h48 ; mem_bank[443] = 'h18 ; mem_bank[444] = 'h10 ; mem_bank[445] = 'h10 ; mem_bank[446] = 'h10 ; mem_bank[447] = 'h10 ; mem_bank[448] = 'h00 ; mem_bank[449] = 'h00 ;
mem_bank[450] = 'hff ; mem_bank[451] = 'hff ; mem_bank[452] = 'h30 ; mem_bank[453] = 'h00 ; mem_bank[454] = 'h00 ; mem_bank[455] = 'h0d ; mem_bank[456] = 'hff ; mem_bank[457] = 'h00 ; mem_bank[458] = 'h00 ; mem_bank[459] = 'h00 ;
mem_bank[460] = 'h01 ; mem_bank[461] = 'h88 ; mem_bank[462] = 'h00 ; mem_bank[463] = 'h20 ; mem_bank[464] = 'h00 ; mem_bank[465] = 'h00 ; mem_bank[466] = 'h0d ; mem_bank[467] = 'h3b ; mem_bank[468] = 'hc9 ; mem_bank[469] = 'h10 ;
mem_bank[470] = 'h00 ; mem_bank[471] = 'h1a ; mem_bank[472] = 'h00 ; mem_bank[473] = 'h4b ; mem_bank[474] = 'h00 ; mem_bank[475] = 'h28 ; mem_bank[476] = 'h81 ; mem_bank[477] = 'h00 ; mem_bank[478] = 'h0d ; mem_bank[479] = 'h10 ;
mem_bank[480] = 'h10 ; mem_bank[481] = 'h00 ; mem_bank[482] = 'h00 ; mem_bank[483] = 'h00 ; mem_bank[484] = 'h00 ; mem_bank[485] = 'h00 ; mem_bank[486] = 'h0d ; mem_bank[487] = 'h11 ; mem_bank[488] = 'h10 ; mem_bank[489] = 'h10 ;
mem_bank[490] = 'h10 ; mem_bank[491] = 'h11 ; mem_bank[492] = 'h10 ; mem_bank[493] = 'h10 ; mem_bank[494] = 'h10 ; mem_bank[495] = 'h19 ; mem_bank[496] = 'h18 ; mem_bank[497] = 'h18 ; mem_bank[498] = 'h18 ; mem_bank[499] = 'h1a ;
mem_bank[500] = 'h88 ; mem_bank[501] = 'h05 ; mem_bank[502] = 'he0 ; mem_bank[503] = 'h10 ; mem_bank[504] = 'h00 ; mem_bank[505] = 'h55 ; mem_bank[506] = 'h3b ; mem_bank[507] = 'h00 ; mem_bank[508] = 'h28 ; mem_bank[509] = 'h86 ;
mem_bank[510] = 'h00 ; mem_bank[511] = 'h0d ; mem_bank[512] = 'h10 ; mem_bank[513] = 'h10 ; mem_bank[514] = 'h00 ; mem_bank[515] = 'h00 ; mem_bank[516] = 'h00 ; mem_bank[517] = 'h00 ; mem_bank[518] = 'h00 ; mem_bank[519] = 'h0d ;
mem_bank[520] = 'h10 ; mem_bank[521] = 'h10 ; mem_bank[522] = 'h11 ; mem_bank[523] = 'h10 ; mem_bank[524] = 'h10 ; mem_bank[525] = 'h10 ; mem_bank[526] = 'h11 ; mem_bank[527] = 'h10 ; mem_bank[528] = 'h11 ; mem_bank[529] = 'h10 ;
mem_bank[530] = 'h12 ; mem_bank[531] = 'h88 ; mem_bank[532] = 'h00 ; mem_bank[533] = 'h42 ; mem_bank[534] = 'h10 ; mem_bank[535] = 'h00 ; mem_bank[536] = 'h01 ; mem_bank[537] = 'h00 ; mem_bank[538] = 'h00 ; mem_bank[539] = 'h0d ;
mem_bank[540] = 'h01 ; mem_bank[541] = 'h2c ; mem_bank[542] = 'h10 ; mem_bank[543] = 'h00 ; mem_bank[544] = 'h6b ; mem_bank[545] = 'hca ; mem_bank[546] = 'h00 ; mem_bank[547] = 'h28 ; mem_bank[548] = 'h85 ; mem_bank[549] = 'h00 ;
mem_bank[550] = 'h0d ; mem_bank[551] = 'h00 ; mem_bank[552] = 'h10 ; mem_bank[553] = 'h10 ; mem_bank[554] = 'h00 ; mem_bank[555] = 'h00 ; mem_bank[556] = 'h00 ; mem_bank[557] = 'h00 ; mem_bank[558] = 'h00 ; mem_bank[559] = 'h19 ;
mem_bank[560] = 'h18 ; mem_bank[561] = 'h11 ; mem_bank[562] = 'h10 ; mem_bank[563] = 'h10 ; mem_bank[564] = 'h10 ; mem_bank[565] = 'h18 ; mem_bank[566] = 'h10 ; mem_bank[567] = 'h11 ; mem_bank[568] = 'h88 ; mem_bank[569] = 'h00 ;
mem_bank[570] = 'h42 ; mem_bank[571] = 'h10 ; mem_bank[572] = 'h00 ; mem_bank[573] = 'h43 ; mem_bank[574] = 'h00 ; mem_bank[575] = 'h00 ; mem_bank[576] = 'h0d ; mem_bank[577] = 'h00 ; mem_bank[578] = 'h42 ; mem_bank[579] = 'h10 ;
mem_bank[580] = 'h00 ; mem_bank[581] = 'h43 ; mem_bank[582] = 'hde ; mem_bank[583] = 'h00 ; mem_bank[584] = 'h28 ; mem_bank[585] = 'h84 ; mem_bank[586] = 'h00 ; mem_bank[587] = 'h0d ; mem_bank[588] = 'h10 ; mem_bank[589] = 'h10 ;
mem_bank[590] = 'h00 ; mem_bank[591] = 'h00 ; mem_bank[592] = 'h00 ; mem_bank[593] = 'h00 ; mem_bank[594] = 'h00 ; mem_bank[595] = 'h0d ; mem_bank[596] = 'h19 ; mem_bank[597] = 'h18 ; mem_bank[598] = 'h11 ; mem_bank[599] = 'h10 ;
mem_bank[600] = 'h10 ; mem_bank[601] = 'h10 ; mem_bank[602] = 'h11 ; mem_bank[603] = 'h88 ; mem_bank[604] = 'h00 ; mem_bank[605] = 'h86 ; mem_bank[606] = 'h10 ; mem_bank[607] = 'h00 ; mem_bank[608] = 'h19 ; mem_bank[609] = 'h0a ;
mem_bank[610] = 'h5a ; mem_bank[611] = 'h00 ; mem_bank[612] = 'h28 ; mem_bank[613] = 'h81 ; mem_bank[614] = 'h00 ; mem_bank[615] = 'h0d ; mem_bank[616] = 'h10 ; mem_bank[617] = 'h10 ; mem_bank[618] = 'h00 ; mem_bank[619] = 'h00 ;
mem_bank[620] = 'h00 ; mem_bank[621] = 'h00 ; mem_bank[622] = 'h00 ; mem_bank[623] = 'h0d ; mem_bank[624] = 'h10 ; mem_bank[625] = 'h10 ; mem_bank[626] = 'h19 ; mem_bank[627] = 'h10 ; mem_bank[628] = 'h10 ; mem_bank[629] = 'h10 ;
mem_bank[630] = 'h10 ; mem_bank[631] = 'h10 ; mem_bank[632] = 'h11 ; mem_bank[633] = 'h88 ; mem_bank[634] = 'h03 ; mem_bank[635] = 'h00 ; mem_bank[636] = 'h4e ; mem_bank[637] = 'h00 ; mem_bank[638] = 'h00 ; mem_bank[639] = 'h0d ;
mem_bank[640] = 'h4e ; mem_bank[641] = 'h00 ; mem_bank[642] = 'h03 ; mem_bank[643] = 'hd1 ; mem_bank[644] = 'h17 ; mem_bank[645] = 'h00 ; mem_bank[646] = 'h28 ; mem_bank[647] = 'h83 ; mem_bank[648] = 'h00 ; mem_bank[649] = 'h0d ;
mem_bank[650] = 'h00 ; mem_bank[651] = 'h10 ; mem_bank[652] = 'h10 ; mem_bank[653] = 'h00 ; mem_bank[654] = 'h00 ; mem_bank[655] = 'h00 ; mem_bank[656] = 'h00 ; mem_bank[657] = 'h00 ; mem_bank[658] = 'h10 ; mem_bank[659] = 'h10 ;
mem_bank[660] = 'h10 ; mem_bank[661] = 'h10 ; mem_bank[662] = 'h11 ; mem_bank[663] = 'h10 ; mem_bank[664] = 'h11 ; mem_bank[665] = 'h88 ; mem_bank[666] = 'h03 ; mem_bank[667] = 'h00 ; mem_bank[668] = 'h10 ; mem_bank[669] = 'h00 ;
mem_bank[670] = 'h00 ; mem_bank[671] = 'h0d ; mem_bank[672] = 'h03 ; mem_bank[673] = 'h00 ; mem_bank[674] = 'h00 ; mem_bank[675] = 'h10 ; mem_bank[676] = 'h4d ; mem_bank[677] = 'h00 ; mem_bank[678] = 'h28 ; mem_bank[679] = 'h81 ;
mem_bank[680] = 'h00 ; mem_bank[681] = 'h0d ; mem_bank[682] = 'h10 ; mem_bank[683] = 'h10 ; mem_bank[684] = 'h00 ; mem_bank[685] = 'h00 ; mem_bank[686] = 'h00 ; mem_bank[687] = 'h00 ; mem_bank[688] = 'h00 ; mem_bank[689] = 'h0d ;
mem_bank[690] = 'h11 ; mem_bank[691] = 'h10 ; mem_bank[692] = 'h10 ; mem_bank[693] = 'h10 ; mem_bank[694] = 'h10 ; mem_bank[695] = 'h88 ; mem_bank[696] = 'h00 ; mem_bank[697] = 'h00 ; mem_bank[698] = 'h00 ; mem_bank[699] = 'h51 ;
mem_bank[700] = 'h85 ; mem_bank[701] = 'h00 ; mem_bank[702] = 'h28 ; mem_bank[703] = 'h81 ; mem_bank[704] = 'h00 ; mem_bank[705] = 'h0d ; mem_bank[706] = 'h10 ; mem_bank[707] = 'h10 ; mem_bank[708] = 'h00 ; mem_bank[709] = 'h00 ;
mem_bank[710] = 'h00 ; mem_bank[711] = 'h00 ; mem_bank[712] = 'h00 ; mem_bank[713] = 'h0d ; mem_bank[714] = 'h10 ; mem_bank[715] = 'h10 ; mem_bank[716] = 'h10 ; mem_bank[717] = 'h10 ; mem_bank[718] = 'h10 ; mem_bank[719] = 'h88 ;
mem_bank[720] = 'h00 ; mem_bank[721] = 'h00 ; mem_bank[722] = 'h00 ; mem_bank[723] = 'hcc ; mem_bank[724] = 'hcc ; mem_bank[725] = 'h00 ; mem_bank[726] = 'h28 ; mem_bank[727] = 'h80 ; mem_bank[728] = 'h0d ; mem_bank[729] = 'h00 ;
mem_bank[730] = 'h10 ; mem_bank[731] = 'h10 ; mem_bank[732] = 'h00 ; mem_bank[733] = 'h00 ; mem_bank[734] = 'h00 ; mem_bank[735] = 'h00 ; mem_bank[736] = 'h00 ; mem_bank[737] = 'h10 ; mem_bank[738] = 'h10 ; mem_bank[739] = 'h10 ;
mem_bank[740] = 'h88 ; mem_bank[741] = 'h00 ; mem_bank[742] = 'h0d ; mem_bank[743] = 'h10 ; mem_bank[744] = 'h10 ; mem_bank[745] = 'h00 ; mem_bank[746] = 'h00 ; mem_bank[747] = 'h00 ; mem_bank[748] = 'h00 ; mem_bank[749] = 'h00 ;
mem_bank[750] = 'h00 ; mem_bank[751] = 'h00 ; mem_bank[752] = 'h00 ; mem_bank[753] = 'h00 ; mem_bank[754] = 'h00 ; mem_bank[755] = 'h00 ; mem_bank[756] = 'h00 ; mem_bank[757] = 'hff ; mem_bank[758] = 'h00 ; mem_bank[759] = 'h00 ;
mem_bank[760] = 'h00 ; mem_bank[761] = 'h01 ; mem_bank[762] = 'h20 ; mem_bank[763] = 'h10 ; mem_bank[764] = 'hff ; mem_bank[765] = 'h80 ; mem_bank[766] = 'h00 ; mem_bank[767] = 'h00 ; mem_bank[768] = 'h00 ; mem_bank[769] = 'h00 ;
mem_bank[770] = 'h00 ; mem_bank[771] = 'h00 ; mem_bank[772] = 'h00 ; mem_bank[773] = 'h00 ; mem_bank[774] = 'h69 ; mem_bank[775] = 'h73 ; mem_bank[776] = 'h50 ; mem_bank[777] = 'h39 ; mem_bank[778] = 'h4f ; mem_bank[779] = 'h41 ;
mem_bank[780] = 'h0a ; mem_bank[781] = 'h6e ; mem_bank[782] = 'h00 ; mem_bank[783] = 'h67 ; mem_bank[784] = 'h00 ; mem_bank[785] = 'h76 ; mem_bank[786] = 'h79 ; mem_bank[787] = 'h78 ; mem_bank[788] = 'h00 ; mem_bank[789] = 'h66 ;
mem_bank[790] = 'h00 ; mem_bank[791] = 'h72 ; mem_bank[792] = 'h00 ; mem_bank[793] = 'h69 ; mem_bank[794] = 'h00 ; mem_bank[795] = 'h65 ; mem_bank[796] = 'h00 ; mem_bank[797] = 'h6e ; mem_bank[798] = 'h65 ; mem_bank[799] = 'h00 ;
mem_bank[800] = 'h67 ; mem_bank[801] = 'h65 ; mem_bank[802] = 'h00 ; mem_bank[803] = 'h76 ; mem_bank[804] = 'h65 ; mem_bank[805] = 'h00 ; mem_bank[806] = 'h78 ; mem_bank[807] = 'h6e ; mem_bank[808] = 'h66 ; mem_bank[809] = 'h6e ;
mem_bank[810] = 'h75 ; mem_bank[811] = 'h65 ; mem_bank[812] = 'h00 ; mem_bank[813] = 'h69 ; mem_bank[814] = 'h65 ; mem_bank[815] = 'h00 ; mem_bank[816] = 'h65 ; mem_bank[817] = 'h00 ; mem_bank[818] = 'h65 ; mem_bank[819] = 'h00 ;
mem_bank[820] = 'h6e ; mem_bank[821] = 'h6e ; mem_bank[822] = 'h00 ; mem_bank[823] = 'h67 ; mem_bank[824] = 'h00 ; mem_bank[825] = 'h76 ; mem_bank[826] = 'h00 ; mem_bank[827] = 'h78 ; mem_bank[828] = 'h76 ; mem_bank[829] = 'h00 ;
mem_bank[830] = 'h75 ; mem_bank[831] = 'h00 ; mem_bank[832] = 'h72 ; mem_bank[833] = 'h00 ; mem_bank[834] = 'h6f ; mem_bank[835] = 'h65 ; mem_bank[836] = 'h00 ; mem_bank[837] = 'h00 ; mem_bank[838] = 'h69 ; mem_bank[839] = 'h6f ;
mem_bank[840] = 'h00 ; mem_bank[841] = 'h75 ; mem_bank[842] = 'h65 ; mem_bank[843] = 'h00 ; mem_bank[844] = 'h6c ; mem_bank[845] = 'h6e ; mem_bank[846] = 'h00 ; mem_bank[847] = 'h69 ; mem_bank[848] = 'h6f ; mem_bank[849] = 'h00 ;
mem_bank[850] = 'h6f ; mem_bank[851] = 'h6e ; mem_bank[852] = 'h00 ; mem_bank[853] = 'h68 ; mem_bank[854] = 'h61 ; mem_bank[855] = 'h00 ; mem_bank[856] = 'h0d ; mem_bank[857] = 'h0d ; mem_bank[858] = 'h0d ; mem_bank[859] = 'h0d ;
mem_bank[860] = 'h0c ; mem_bank[861] = 'h0c ; mem_bank[862] = 'h0c ; mem_bank[863] = 'h0c ; mem_bank[864] = 'h0c ; mem_bank[865] = 'h0c ; mem_bank[866] = 'h0c ; mem_bank[867] = 'h0c ; mem_bank[868] = 'h0c ; mem_bank[869] = 'h0c ;
mem_bank[870] = 'h0c ; mem_bank[871] = 'h0c ; mem_bank[872] = 'h0c ; mem_bank[873] = 'h0c ; mem_bank[874] = 'h0c ; mem_bank[875] = 'h0c ; mem_bank[876] = 'h0d ; mem_bank[877] = 'h0c ; mem_bank[878] = 'h0c ; mem_bank[879] = 'h0c ;
mem_bank[880] = 'h0c ; mem_bank[881] = 'h0c ; mem_bank[882] = 'h0c ; mem_bank[883] = 'h0c ; mem_bank[884] = 'h0c ; mem_bank[885] = 'h0c ; mem_bank[886] = 'h00 ;
end
always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;
always @ (posedge clock)
221,8 → 301,8
r_rdaddress_b<=rdaddress_b;
r_wren<=wren;
end
assign qa =(r_rdaddress_a>484)?0:mem_bank[r_rdaddress_a];
assign qb =(r_rdaddress_b>484)?0:mem_bank[r_rdaddress_b];
assign qa =mem_bank[r_rdaddress_a];
assign qb =mem_bank[r_rdaddress_b];
endmodule
 
 
229,9 → 309,9
 
module sim_syn_ram2(
input [7:0] data,
input [10:0] wraddress,
input [10:0] rdaddress_a,
input [10:0] rdaddress_b,
input [29:0] wraddress,
input [29:0] rdaddress_a,
input [29:0] rdaddress_b,
input wren,
input clock,
output [7:0] qa,
239,11 → 319,11
);
 
reg [7:0] r_data;
reg [10:0] r_wraddress;
reg [10:0] r_rdaddress_a;
reg [10:0] r_rdaddress_b;
reg [29:0] r_wraddress;
reg [29:0] r_rdaddress_a;
reg [29:0] r_rdaddress_b;
reg r_wren;
reg [7:0] mem_bank [0:2047] ;
reg [7:0] mem_bank [0:12345] ;
initial begin
mem_bank[0] = 'h1c ; mem_bank[1] = 'h9c ; mem_bank[2] = 'h04 ; mem_bank[3] = 'h84 ; mem_bank[4] = 'h05 ; mem_bank[5] = 'ha5 ; mem_bank[6] = 'h1d ; mem_bank[7] = 'hbd ; mem_bank[8] = 'h80 ; mem_bank[9] = 'h85 ;
287,14 → 367,54
mem_bank[380] = 'h02 ; mem_bank[381] = 'h42 ; mem_bank[382] = 'h43 ; mem_bank[383] = 'h04 ; mem_bank[384] = 'h64 ; mem_bank[385] = 'he0 ; mem_bank[386] = 'h43 ; mem_bank[387] = 'h03 ; mem_bank[388] = 'h63 ; mem_bank[389] = 'h62 ;
mem_bank[390] = 'h00 ; mem_bank[391] = 'h42 ; mem_bank[392] = 'he0 ; mem_bank[393] = 'h62 ; mem_bank[394] = 'h02 ; mem_bank[395] = 'h42 ; mem_bank[396] = 'h43 ; mem_bank[397] = 'h04 ; mem_bank[398] = 'h64 ; mem_bank[399] = 'he0 ;
mem_bank[400] = 'h43 ; mem_bank[401] = 'h03 ; mem_bank[402] = 'h63 ; mem_bank[403] = 'h62 ; mem_bank[404] = 'h00 ; mem_bank[405] = 'h42 ; mem_bank[406] = 'he0 ; mem_bank[407] = 'h62 ; mem_bank[408] = 'h84 ; mem_bank[409] = 'h02 ;
mem_bank[410] = 'h42 ; mem_bank[411] = 'he0 ; mem_bank[412] = 'h44 ; mem_bank[413] = 'he0 ; mem_bank[414] = 'h00 ; mem_bank[415] = 'hbd ; mem_bank[416] = 'hbf ; mem_bank[417] = 'h03 ; mem_bank[418] = 'h02 ; mem_bank[419] = 'h42 ;
mem_bank[420] = 'h43 ; mem_bank[421] = 'h02 ; mem_bank[422] = 'h42 ; mem_bank[423] = 'h43 ; mem_bank[424] = 'h02 ; mem_bank[425] = 'h42 ; mem_bank[426] = 'h00 ; mem_bank[427] = 'h43 ; mem_bank[428] = 'h04 ; mem_bank[429] = 'h84 ;
mem_bank[430] = 'h82 ; mem_bank[431] = 'h00 ; mem_bank[432] = 'h42 ; mem_bank[433] = 'h82 ; mem_bank[434] = 'h82 ; mem_bank[435] = 'h03 ; mem_bank[436] = 'h43 ; mem_bank[437] = 'h82 ; mem_bank[438] = 'h82 ; mem_bank[439] = 'h03 ;
mem_bank[440] = 'h43 ; mem_bank[441] = 'h82 ; mem_bank[442] = 'h82 ; mem_bank[443] = 'h03 ; mem_bank[444] = 'h43 ; mem_bank[445] = 'h82 ; mem_bank[446] = 'h00 ; mem_bank[447] = 'h00 ; mem_bank[448] = 'h00 ; mem_bank[449] = 'h00 ;
mem_bank[450] = 'h00 ; mem_bank[451] = 'h00 ; mem_bank[452] = 'hbd ; mem_bank[453] = 'hbf ; mem_bank[454] = 'hb1 ; mem_bank[455] = 'hb0 ; mem_bank[456] = 'h10 ; mem_bank[457] = 'h11 ; mem_bank[458] = 'h00 ; mem_bank[459] = 'h10 ;
mem_bank[460] = 'h00 ; mem_bank[461] = 'h00 ; mem_bank[462] = 'h11 ; mem_bank[463] = 'h02 ; mem_bank[464] = 'h42 ; mem_bank[465] = 'h40 ; mem_bank[466] = 'hbf ; mem_bank[467] = 'hb1 ; mem_bank[468] = 'hb0 ; mem_bank[469] = 'he0 ;
mem_bank[470] = 'hbd ; mem_bank[471] = 'h00 ; mem_bank[472] = 'h00 ; mem_bank[473] = 'h00 ; mem_bank[474] = 'h00 ; mem_bank[475] = 'h00 ; mem_bank[476] = 'h00 ; mem_bank[477] = 'h68 ; mem_bank[478] = 'h69 ; mem_bank[479] = 'h49 ;
mem_bank[480] = 'h38 ; mem_bank[481] = 'h4f ; mem_bank[482] = 'h4f ; mem_bank[483] = 'h52 ; mem_bank[484] = 'h00 ;
mem_bank[410] = 'h42 ; mem_bank[411] = 'he0 ; mem_bank[412] = 'h44 ; mem_bank[413] = 'h02 ; mem_bank[414] = 'h40 ; mem_bank[415] = 'h06 ; mem_bank[416] = 'h02 ; mem_bank[417] = 'h47 ; mem_bank[418] = 'h83 ; mem_bank[419] = 'h62 ;
mem_bank[420] = 'h40 ; mem_bank[421] = 'hc7 ; mem_bank[422] = 'h00 ; mem_bank[423] = 'h62 ; mem_bank[424] = 'h62 ; mem_bank[425] = 'ha2 ; mem_bank[426] = 'hc6 ; mem_bank[427] = 'hc1 ; mem_bank[428] = 'h04 ; mem_bank[429] = 'h02 ;
mem_bank[430] = 'he0 ; mem_bank[431] = 'h42 ; mem_bank[432] = 'h80 ; mem_bank[433] = 'h02 ; mem_bank[434] = 'h40 ; mem_bank[435] = 'h05 ; mem_bank[436] = 'h02 ; mem_bank[437] = 'h48 ; mem_bank[438] = 'h07 ; mem_bank[439] = 'he7 ;
mem_bank[440] = 'ha8 ; mem_bank[441] = 'hc7 ; mem_bank[442] = 'h00 ; mem_bank[443] = 'h09 ; mem_bank[444] = 'h03 ; mem_bank[445] = 'h43 ; mem_bank[446] = 'h02 ; mem_bank[447] = 'hc2 ; mem_bank[448] = 'h42 ; mem_bank[449] = 'h82 ;
mem_bank[450] = 'ha5 ; mem_bank[451] = 'ha1 ; mem_bank[452] = 'h60 ; mem_bank[453] = 'h02 ; mem_bank[454] = 'he0 ; mem_bank[455] = 'h42 ; mem_bank[456] = 'hbd ; mem_bank[457] = 'hbf ; mem_bank[458] = 'hb1 ; mem_bank[459] = 'hb0 ;
mem_bank[460] = 'h00 ; mem_bank[461] = 'h80 ; mem_bank[462] = 'h00 ; mem_bank[463] = 'h40 ; mem_bank[464] = 'h04 ; mem_bank[465] = 'h00 ; mem_bank[466] = 'h84 ; mem_bank[467] = 'h02 ; mem_bank[468] = 'h42 ; mem_bank[469] = 'h51 ;
mem_bank[470] = 'h40 ; mem_bank[471] = 'h11 ; mem_bank[472] = 'h02 ; mem_bank[473] = 'h42 ; mem_bank[474] = 'h62 ; mem_bank[475] = 'h00 ; mem_bank[476] = 'h05 ; mem_bank[477] = 'h03 ; mem_bank[478] = 'h63 ; mem_bank[479] = 'h10 ;
mem_bank[480] = 'h43 ; mem_bank[481] = 'h44 ; mem_bank[482] = 'h00 ; mem_bank[483] = 'h00 ; mem_bank[484] = 'h04 ; mem_bank[485] = 'h00 ; mem_bank[486] = 'h84 ; mem_bank[487] = 'h10 ; mem_bank[488] = 'h50 ; mem_bank[489] = 'h02 ;
mem_bank[490] = 'h50 ; mem_bank[491] = 'h02 ; mem_bank[492] = 'h50 ; mem_bank[493] = 'h02 ; mem_bank[494] = 'h50 ; mem_bank[495] = 'h02 ; mem_bank[496] = 'h62 ; mem_bank[497] = 'h03 ; mem_bank[498] = 'h70 ; mem_bank[499] = 'h03 ;
mem_bank[500] = 'h23 ; mem_bank[501] = 'h02 ; mem_bank[502] = 'h42 ; mem_bank[503] = 'h51 ; mem_bank[504] = 'h40 ; mem_bank[505] = 'h02 ; mem_bank[506] = 'h42 ; mem_bank[507] = 'h22 ; mem_bank[508] = 'h00 ; mem_bank[509] = 'h05 ;
mem_bank[510] = 'h03 ; mem_bank[511] = 'h63 ; mem_bank[512] = 'h10 ; mem_bank[513] = 'h43 ; mem_bank[514] = 'h44 ; mem_bank[515] = 'h00 ; mem_bank[516] = 'h00 ; mem_bank[517] = 'h04 ; mem_bank[518] = 'h00 ; mem_bank[519] = 'h84 ;
mem_bank[520] = 'h10 ; mem_bank[521] = 'h50 ; mem_bank[522] = 'h02 ; mem_bank[523] = 'h50 ; mem_bank[524] = 'h02 ; mem_bank[525] = 'h50 ; mem_bank[526] = 'h02 ; mem_bank[527] = 'h50 ; mem_bank[528] = 'h02 ; mem_bank[529] = 'h50 ;
mem_bank[530] = 'h02 ; mem_bank[531] = 'h22 ; mem_bank[532] = 'h02 ; mem_bank[533] = 'h42 ; mem_bank[534] = 'h51 ; mem_bank[535] = 'h40 ; mem_bank[536] = 'h02 ; mem_bank[537] = 'h04 ; mem_bank[538] = 'h00 ; mem_bank[539] = 'h84 ;
mem_bank[540] = 'h02 ; mem_bank[541] = 'h42 ; mem_bank[542] = 'h51 ; mem_bank[543] = 'h40 ; mem_bank[544] = 'h02 ; mem_bank[545] = 'h42 ; mem_bank[546] = 'h22 ; mem_bank[547] = 'h00 ; mem_bank[548] = 'h05 ; mem_bank[549] = 'h03 ;
mem_bank[550] = 'h63 ; mem_bank[551] = 'h02 ; mem_bank[552] = 'h02 ; mem_bank[553] = 'h43 ; mem_bank[554] = 'h44 ; mem_bank[555] = 'h00 ; mem_bank[556] = 'h00 ; mem_bank[557] = 'h00 ; mem_bank[558] = 'h04 ; mem_bank[559] = 'h10 ;
mem_bank[560] = 'h70 ; mem_bank[561] = 'h03 ; mem_bank[562] = 'h43 ; mem_bank[563] = 'h02 ; mem_bank[564] = 'h50 ; mem_bank[565] = 'h02 ; mem_bank[566] = 'h43 ; mem_bank[567] = 'h02 ; mem_bank[568] = 'h22 ; mem_bank[569] = 'h02 ;
mem_bank[570] = 'h42 ; mem_bank[571] = 'h51 ; mem_bank[572] = 'h40 ; mem_bank[573] = 'h02 ; mem_bank[574] = 'h04 ; mem_bank[575] = 'h00 ; mem_bank[576] = 'h84 ; mem_bank[577] = 'h02 ; mem_bank[578] = 'h42 ; mem_bank[579] = 'h51 ;
mem_bank[580] = 'h40 ; mem_bank[581] = 'h02 ; mem_bank[582] = 'h42 ; mem_bank[583] = 'h22 ; mem_bank[584] = 'h00 ; mem_bank[585] = 'h05 ; mem_bank[586] = 'h03 ; mem_bank[587] = 'h63 ; mem_bank[588] = 'h10 ; mem_bank[589] = 'h43 ;
mem_bank[590] = 'h44 ; mem_bank[591] = 'h00 ; mem_bank[592] = 'h00 ; mem_bank[593] = 'h04 ; mem_bank[594] = 'h00 ; mem_bank[595] = 'h84 ; mem_bank[596] = 'h10 ; mem_bank[597] = 'h70 ; mem_bank[598] = 'h03 ; mem_bank[599] = 'h43 ;
mem_bank[600] = 'h02 ; mem_bank[601] = 'h50 ; mem_bank[602] = 'h02 ; mem_bank[603] = 'h22 ; mem_bank[604] = 'h02 ; mem_bank[605] = 'h42 ; mem_bank[606] = 'h51 ; mem_bank[607] = 'h40 ; mem_bank[608] = 'h11 ; mem_bank[609] = 'h02 ;
mem_bank[610] = 'h42 ; mem_bank[611] = 'h62 ; mem_bank[612] = 'h00 ; mem_bank[613] = 'h05 ; mem_bank[614] = 'h03 ; mem_bank[615] = 'h63 ; mem_bank[616] = 'h10 ; mem_bank[617] = 'h43 ; mem_bank[618] = 'h44 ; mem_bank[619] = 'h00 ;
mem_bank[620] = 'h00 ; mem_bank[621] = 'h04 ; mem_bank[622] = 'h00 ; mem_bank[623] = 'h84 ; mem_bank[624] = 'h10 ; mem_bank[625] = 'h50 ; mem_bank[626] = 'h02 ; mem_bank[627] = 'h43 ; mem_bank[628] = 'h02 ; mem_bank[629] = 'h50 ;
mem_bank[630] = 'h02 ; mem_bank[631] = 'h50 ; mem_bank[632] = 'h02 ; mem_bank[633] = 'h22 ; mem_bank[634] = 'h22 ; mem_bank[635] = 'h40 ; mem_bank[636] = 'h22 ; mem_bank[637] = 'h04 ; mem_bank[638] = 'h00 ; mem_bank[639] = 'h84 ;
mem_bank[640] = 'h22 ; mem_bank[641] = 'h40 ; mem_bank[642] = 'h22 ; mem_bank[643] = 'h02 ; mem_bank[644] = 'h42 ; mem_bank[645] = 'h22 ; mem_bank[646] = 'h00 ; mem_bank[647] = 'h05 ; mem_bank[648] = 'h03 ; mem_bank[649] = 'h63 ;
mem_bank[650] = 'h02 ; mem_bank[651] = 'h02 ; mem_bank[652] = 'h43 ; mem_bank[653] = 'h44 ; mem_bank[654] = 'h00 ; mem_bank[655] = 'h00 ; mem_bank[656] = 'h00 ; mem_bank[657] = 'h04 ; mem_bank[658] = 'h10 ; mem_bank[659] = 'h50 ;
mem_bank[660] = 'h02 ; mem_bank[661] = 'h50 ; mem_bank[662] = 'h02 ; mem_bank[663] = 'h50 ; mem_bank[664] = 'h02 ; mem_bank[665] = 'h22 ; mem_bank[666] = 'h22 ; mem_bank[667] = 'h40 ; mem_bank[668] = 'h02 ; mem_bank[669] = 'h04 ;
mem_bank[670] = 'h00 ; mem_bank[671] = 'h84 ; mem_bank[672] = 'h22 ; mem_bank[673] = 'h40 ; mem_bank[674] = 'h22 ; mem_bank[675] = 'h02 ; mem_bank[676] = 'h42 ; mem_bank[677] = 'h22 ; mem_bank[678] = 'h00 ; mem_bank[679] = 'h05 ;
mem_bank[680] = 'h03 ; mem_bank[681] = 'h63 ; mem_bank[682] = 'h10 ; mem_bank[683] = 'h43 ; mem_bank[684] = 'h44 ; mem_bank[685] = 'h00 ; mem_bank[686] = 'h00 ; mem_bank[687] = 'h04 ; mem_bank[688] = 'h00 ; mem_bank[689] = 'h84 ;
mem_bank[690] = 'h10 ; mem_bank[691] = 'h50 ; mem_bank[692] = 'h02 ; mem_bank[693] = 'h50 ; mem_bank[694] = 'h02 ; mem_bank[695] = 'h22 ; mem_bank[696] = 'h22 ; mem_bank[697] = 'h40 ; mem_bank[698] = 'h22 ; mem_bank[699] = 'h02 ;
mem_bank[700] = 'h42 ; mem_bank[701] = 'h22 ; mem_bank[702] = 'h00 ; mem_bank[703] = 'h05 ; mem_bank[704] = 'h03 ; mem_bank[705] = 'h63 ; mem_bank[706] = 'h10 ; mem_bank[707] = 'h43 ; mem_bank[708] = 'h44 ; mem_bank[709] = 'h00 ;
mem_bank[710] = 'h00 ; mem_bank[711] = 'h04 ; mem_bank[712] = 'h00 ; mem_bank[713] = 'h84 ; mem_bank[714] = 'h10 ; mem_bank[715] = 'h50 ; mem_bank[716] = 'h02 ; mem_bank[717] = 'h50 ; mem_bank[718] = 'h02 ; mem_bank[719] = 'h22 ;
mem_bank[720] = 'h22 ; mem_bank[721] = 'h40 ; mem_bank[722] = 'h03 ; mem_bank[723] = 'h02 ; mem_bank[724] = 'h42 ; mem_bank[725] = 'h22 ; mem_bank[726] = 'h00 ; mem_bank[727] = 'h05 ; mem_bank[728] = 'h63 ; mem_bank[729] = 'h02 ;
mem_bank[730] = 'h02 ; mem_bank[731] = 'h43 ; mem_bank[732] = 'h44 ; mem_bank[733] = 'h00 ; mem_bank[734] = 'h00 ; mem_bank[735] = 'h00 ; mem_bank[736] = 'h04 ; mem_bank[737] = 'h10 ; mem_bank[738] = 'h50 ; mem_bank[739] = 'h02 ;
mem_bank[740] = 'h22 ; mem_bank[741] = 'h03 ; mem_bank[742] = 'h63 ; mem_bank[743] = 'h11 ; mem_bank[744] = 'h43 ; mem_bank[745] = 'h44 ; mem_bank[746] = 'h00 ; mem_bank[747] = 'h00 ; mem_bank[748] = 'h00 ; mem_bank[749] = 'h04 ;
mem_bank[750] = 'h00 ; mem_bank[751] = 'h04 ; mem_bank[752] = 'hbf ; mem_bank[753] = 'hb1 ; mem_bank[754] = 'hb0 ; mem_bank[755] = 'he0 ; mem_bank[756] = 'hbd ; mem_bank[757] = 'hbd ; mem_bank[758] = 'hbf ; mem_bank[759] = 'hb0 ;
mem_bank[760] = 'h10 ; mem_bank[761] = 'h00 ; mem_bank[762] = 'h00 ; mem_bank[763] = 'h10 ; mem_bank[764] = 'h00 ; mem_bank[765] = 'h02 ; mem_bank[766] = 'he0 ; mem_bank[767] = 'h00 ; mem_bank[768] = 'h00 ; mem_bank[769] = 'h00 ;
mem_bank[770] = 'h00 ; mem_bank[771] = 'h00 ; mem_bank[772] = 'h00 ; mem_bank[773] = 'h00 ; mem_bank[774] = 'h68 ; mem_bank[775] = 'h69 ; mem_bank[776] = 'h49 ; mem_bank[777] = 'h38 ; mem_bank[778] = 'h4f ; mem_bank[779] = 'h4f ;
mem_bank[780] = 'h52 ; mem_bank[781] = 'h69 ; mem_bank[782] = 'h79 ; mem_bank[783] = 'h69 ; mem_bank[784] = 'h79 ; mem_bank[785] = 'h65 ; mem_bank[786] = 'h74 ; mem_bank[787] = 'h69 ; mem_bank[788] = 'h00 ; mem_bank[789] = 'h69 ;
mem_bank[790] = 'h00 ; mem_bank[791] = 'h6f ; mem_bank[792] = 'h00 ; mem_bank[793] = 'h68 ; mem_bank[794] = 'h79 ; mem_bank[795] = 'h77 ; mem_bank[796] = 'h79 ; mem_bank[797] = 'h69 ; mem_bank[798] = 'h65 ; mem_bank[799] = 'h00 ;
mem_bank[800] = 'h69 ; mem_bank[801] = 'h65 ; mem_bank[802] = 'h00 ; mem_bank[803] = 'h65 ; mem_bank[804] = 'h74 ; mem_bank[805] = 'h00 ; mem_bank[806] = 'h69 ; mem_bank[807] = 'h65 ; mem_bank[808] = 'h69 ; mem_bank[809] = 'h65 ;
mem_bank[810] = 'h6f ; mem_bank[811] = 'h65 ; mem_bank[812] = 'h00 ; mem_bank[813] = 'h68 ; mem_bank[814] = 'h65 ; mem_bank[815] = 'h00 ; mem_bank[816] = 'h77 ; mem_bank[817] = 'h65 ; mem_bank[818] = 'h6c ; mem_bank[819] = 'h6e ;
mem_bank[820] = 'h65 ; mem_bank[821] = 'h69 ; mem_bank[822] = 'h00 ; mem_bank[823] = 'h69 ; mem_bank[824] = 'h00 ; mem_bank[825] = 'h65 ; mem_bank[826] = 'h00 ; mem_bank[827] = 'h69 ; mem_bank[828] = 'h69 ; mem_bank[829] = 'h00 ;
mem_bank[830] = 'h6f ; mem_bank[831] = 'h00 ; mem_bank[832] = 'h68 ; mem_bank[833] = 'h00 ; mem_bank[834] = 'h77 ; mem_bank[835] = 'h6e ; mem_bank[836] = 'h00 ; mem_bank[837] = 'h20 ; mem_bank[838] = 'h62 ; mem_bank[839] = 'h69 ;
mem_bank[840] = 'h00 ; mem_bank[841] = 'h68 ; mem_bank[842] = 'h72 ; mem_bank[843] = 'h00 ; mem_bank[844] = 'h69 ; mem_bank[845] = 'h6f ; mem_bank[846] = 'h00 ; mem_bank[847] = 'h6d ; mem_bank[848] = 'h69 ; mem_bank[849] = 'h00 ;
mem_bank[850] = 'h68 ; mem_bank[851] = 'h61 ; mem_bank[852] = 'h00 ; mem_bank[853] = 'h74 ; mem_bank[854] = 'h73 ; mem_bank[855] = 'h20 ; mem_bank[856] = 'h00 ; mem_bank[857] = 'h00 ; mem_bank[858] = 'h00 ; mem_bank[859] = 'h00 ;
mem_bank[860] = 'h00 ; mem_bank[861] = 'h00 ; mem_bank[862] = 'h00 ; mem_bank[863] = 'h00 ; mem_bank[864] = 'h00 ; mem_bank[865] = 'h00 ; mem_bank[866] = 'h00 ; mem_bank[867] = 'h00 ; mem_bank[868] = 'h00 ; mem_bank[869] = 'h00 ;
mem_bank[870] = 'h00 ; mem_bank[871] = 'h00 ; mem_bank[872] = 'h00 ; mem_bank[873] = 'h00 ; mem_bank[874] = 'h00 ; mem_bank[875] = 'h00 ; mem_bank[876] = 'h00 ; mem_bank[877] = 'h00 ; mem_bank[878] = 'h00 ; mem_bank[879] = 'h00 ;
mem_bank[880] = 'h00 ; mem_bank[881] = 'h00 ; mem_bank[882] = 'h00 ; mem_bank[883] = 'h00 ; mem_bank[884] = 'h00 ; mem_bank[885] = 'h00 ; mem_bank[886] = 'h00 ;
end
always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;
always @ (posedge clock)
305,8 → 425,8
r_rdaddress_b<=rdaddress_b;
r_wren<=wren;
end
assign qa =(r_rdaddress_a>484)?0:mem_bank[r_rdaddress_a];
assign qb =(r_rdaddress_b>484)?0:mem_bank[r_rdaddress_b];
assign qa =mem_bank[r_rdaddress_a];
assign qb =mem_bank[r_rdaddress_b];
endmodule
 
 
313,9 → 433,9
 
module sim_syn_ram3(
input [7:0] data,
input [10:0] wraddress,
input [10:0] rdaddress_a,
input [10:0] rdaddress_b,
input [29:0] wraddress,
input [29:0] rdaddress_a,
input [29:0] rdaddress_b,
input wren,
input clock,
output [7:0] qa,
323,11 → 443,11
);
 
reg [7:0] r_data;
reg [10:0] r_wraddress;
reg [10:0] r_rdaddress_a;
reg [10:0] r_rdaddress_b;
reg [29:0] r_wraddress;
reg [29:0] r_rdaddress_a;
reg [29:0] r_rdaddress_b;
reg r_wren;
reg [7:0] mem_bank [0:2047] ;
reg [7:0] mem_bank [0:12345] ;
initial begin
mem_bank[0] = 'h3c ; mem_bank[1] = 'h37 ; mem_bank[2] = 'h3c ; mem_bank[3] = 'h34 ; mem_bank[4] = 'h3c ; mem_bank[5] = 'h34 ; mem_bank[6] = 'h3c ; mem_bank[7] = 'h37 ; mem_bank[8] = 'hac ; mem_bank[9] = 'h00 ;
371,14 → 491,54
mem_bank[380] = 'h3c ; mem_bank[381] = 'h34 ; mem_bank[382] = 'h8c ; mem_bank[383] = 'h24 ; mem_bank[384] = 'h00 ; mem_bank[385] = 'h03 ; mem_bank[386] = 'hac ; mem_bank[387] = 'h3c ; mem_bank[388] = 'h34 ; mem_bank[389] = 'h8c ;
mem_bank[390] = 'h00 ; mem_bank[391] = 'h34 ; mem_bank[392] = 'h03 ; mem_bank[393] = 'hac ; mem_bank[394] = 'h3c ; mem_bank[395] = 'h34 ; mem_bank[396] = 'h8c ; mem_bank[397] = 'h24 ; mem_bank[398] = 'h00 ; mem_bank[399] = 'h03 ;
mem_bank[400] = 'hac ; mem_bank[401] = 'h3c ; mem_bank[402] = 'h34 ; mem_bank[403] = 'h8c ; mem_bank[404] = 'h00 ; mem_bank[405] = 'h34 ; mem_bank[406] = 'h03 ; mem_bank[407] = 'hac ; mem_bank[408] = 'h30 ; mem_bank[409] = 'h3c ;
mem_bank[410] = 'h34 ; mem_bank[411] = 'h03 ; mem_bank[412] = 'ha0 ; mem_bank[413] = 'h03 ; mem_bank[414] = 'h00 ; mem_bank[415] = 'h27 ; mem_bank[416] = 'haf ; mem_bank[417] = 'h24 ; mem_bank[418] = 'h3c ; mem_bank[419] = 'h34 ;
mem_bank[420] = 'hac ; mem_bank[421] = 'h3c ; mem_bank[422] = 'h34 ; mem_bank[423] = 'hac ; mem_bank[424] = 'h3c ; mem_bank[425] = 'h34 ; mem_bank[426] = 'h0c ; mem_bank[427] = 'hac ; mem_bank[428] = 'h3c ; mem_bank[429] = 'h34 ;
mem_bank[430] = 'h8c ; mem_bank[431] = 'h00 ; mem_bank[432] = 'h34 ; mem_bank[433] = 'hac ; mem_bank[434] = 'h8c ; mem_bank[435] = 'h3c ; mem_bank[436] = 'h00 ; mem_bank[437] = 'hac ; mem_bank[438] = 'h8c ; mem_bank[439] = 'h3c ;
mem_bank[440] = 'h00 ; mem_bank[441] = 'hac ; mem_bank[442] = 'h8c ; mem_bank[443] = 'h3c ; mem_bank[444] = 'h00 ; mem_bank[445] = 'hac ; mem_bank[446] = 'h0c ; mem_bank[447] = 'h00 ; mem_bank[448] = 'h0c ; mem_bank[449] = 'h00 ;
mem_bank[450] = 'h10 ; mem_bank[451] = 'h00 ; mem_bank[452] = 'h27 ; mem_bank[453] = 'haf ; mem_bank[454] = 'haf ; mem_bank[455] = 'haf ; mem_bank[456] = 'h24 ; mem_bank[457] = 'h24 ; mem_bank[458] = 'h0c ; mem_bank[459] = 'h26 ;
mem_bank[460] = 'h0c ; mem_bank[461] = 'h00 ; mem_bank[462] = 'h16 ; mem_bank[463] = 'h3c ; mem_bank[464] = 'h34 ; mem_bank[465] = 'hac ; mem_bank[466] = 'h8f ; mem_bank[467] = 'h8f ; mem_bank[468] = 'h8f ; mem_bank[469] = 'h03 ;
mem_bank[470] = 'h27 ; mem_bank[471] = 'h00 ; mem_bank[472] = 'h00 ; mem_bank[473] = 'h00 ; mem_bank[474] = 'h00 ; mem_bank[475] = 'h00 ; mem_bank[476] = 'h00 ; mem_bank[477] = 'h54 ; mem_bank[478] = 'h20 ; mem_bank[479] = 'h4d ;
mem_bank[480] = 'h37 ; mem_bank[481] = 'h42 ; mem_bank[482] = 'h4c ; mem_bank[483] = 'h45 ; mem_bank[484] = 'h00 ;
mem_bank[410] = 'h34 ; mem_bank[411] = 'h03 ; mem_bank[412] = 'ha0 ; mem_bank[413] = 'h3c ; mem_bank[414] = 'ha0 ; mem_bank[415] = 'h24 ; mem_bank[416] = 'h3c ; mem_bank[417] = 'h24 ; mem_bank[418] = 'h30 ; mem_bank[419] = 'h28 ;
mem_bank[420] = 'h10 ; mem_bank[421] = 'h00 ; mem_bank[422] = 'h10 ; mem_bank[423] = 'h24 ; mem_bank[424] = 'h24 ; mem_bank[425] = 'ha0 ; mem_bank[426] = 'h24 ; mem_bank[427] = 'h04 ; mem_bank[428] = 'h00 ; mem_bank[429] = 'h3c ;
mem_bank[430] = 'h03 ; mem_bank[431] = 'h24 ; mem_bank[432] = 'h00 ; mem_bank[433] = 'h3c ; mem_bank[434] = 'ha0 ; mem_bank[435] = 'h24 ; mem_bank[436] = 'h3c ; mem_bank[437] = 'h24 ; mem_bank[438] = 'h3c ; mem_bank[439] = 'h34 ;
mem_bank[440] = 'h00 ; mem_bank[441] = 'h00 ; mem_bank[442] = 'h00 ; mem_bank[443] = 'h00 ; mem_bank[444] = 'h00 ; mem_bank[445] = 'h00 ; mem_bank[446] = 'h00 ; mem_bank[447] = 'h00 ; mem_bank[448] = 'h24 ; mem_bank[449] = 'ha0 ;
mem_bank[450] = 'h24 ; mem_bank[451] = 'h04 ; mem_bank[452] = 'h00 ; mem_bank[453] = 'h3c ; mem_bank[454] = 'h03 ; mem_bank[455] = 'h24 ; mem_bank[456] = 'h27 ; mem_bank[457] = 'haf ; mem_bank[458] = 'haf ; mem_bank[459] = 'haf ;
mem_bank[460] = 'h0c ; mem_bank[461] = 'h00 ; mem_bank[462] = 'h0c ; mem_bank[463] = 'h00 ; mem_bank[464] = 'h3c ; mem_bank[465] = 'h0c ; mem_bank[466] = 'h24 ; mem_bank[467] = 'h3c ; mem_bank[468] = 'h34 ; mem_bank[469] = 'h00 ;
mem_bank[470] = 'h10 ; mem_bank[471] = 'h00 ; mem_bank[472] = 'h3c ; mem_bank[473] = 'h34 ; mem_bank[474] = 'h00 ; mem_bank[475] = 'h00 ; mem_bank[476] = 'h00 ; mem_bank[477] = 'h3c ; mem_bank[478] = 'h24 ; mem_bank[479] = 'h00 ;
mem_bank[480] = 'h00 ; mem_bank[481] = 'h8c ; mem_bank[482] = 'h0c ; mem_bank[483] = 'h00 ; mem_bank[484] = 'h3c ; mem_bank[485] = 'h0c ; mem_bank[486] = 'h24 ; mem_bank[487] = 'h00 ; mem_bank[488] = 'h00 ; mem_bank[489] = 'h00 ;
mem_bank[490] = 'h00 ; mem_bank[491] = 'h00 ; mem_bank[492] = 'h00 ; mem_bank[493] = 'h00 ; mem_bank[494] = 'h00 ; mem_bank[495] = 'h00 ; mem_bank[496] = 'h00 ; mem_bank[497] = 'h00 ; mem_bank[498] = 'h00 ; mem_bank[499] = 'h00 ;
mem_bank[500] = 'h02 ; mem_bank[501] = 'h3c ; mem_bank[502] = 'h34 ; mem_bank[503] = 'h00 ; mem_bank[504] = 'h10 ; mem_bank[505] = 'h3c ; mem_bank[506] = 'h34 ; mem_bank[507] = 'h02 ; mem_bank[508] = 'h00 ; mem_bank[509] = 'h00 ;
mem_bank[510] = 'h3c ; mem_bank[511] = 'h24 ; mem_bank[512] = 'h00 ; mem_bank[513] = 'h00 ; mem_bank[514] = 'h8c ; mem_bank[515] = 'h0c ; mem_bank[516] = 'h00 ; mem_bank[517] = 'h3c ; mem_bank[518] = 'h0c ; mem_bank[519] = 'h24 ;
mem_bank[520] = 'h00 ; mem_bank[521] = 'h00 ; mem_bank[522] = 'h00 ; mem_bank[523] = 'h00 ; mem_bank[524] = 'h00 ; mem_bank[525] = 'h00 ; mem_bank[526] = 'h00 ; mem_bank[527] = 'h00 ; mem_bank[528] = 'h00 ; mem_bank[529] = 'h00 ;
mem_bank[530] = 'h00 ; mem_bank[531] = 'h02 ; mem_bank[532] = 'h3c ; mem_bank[533] = 'h34 ; mem_bank[534] = 'h00 ; mem_bank[535] = 'h14 ; mem_bank[536] = 'h3c ; mem_bank[537] = 'h3c ; mem_bank[538] = 'h0c ; mem_bank[539] = 'h24 ;
mem_bank[540] = 'h3c ; mem_bank[541] = 'h34 ; mem_bank[542] = 'h00 ; mem_bank[543] = 'h10 ; mem_bank[544] = 'h3c ; mem_bank[545] = 'h34 ; mem_bank[546] = 'h02 ; mem_bank[547] = 'h00 ; mem_bank[548] = 'h00 ; mem_bank[549] = 'h3c ;
mem_bank[550] = 'h24 ; mem_bank[551] = 'h26 ; mem_bank[552] = 'h00 ; mem_bank[553] = 'h00 ; mem_bank[554] = 'h8c ; mem_bank[555] = 'h0c ; mem_bank[556] = 'h00 ; mem_bank[557] = 'h0c ; mem_bank[558] = 'h24 ; mem_bank[559] = 'h00 ;
mem_bank[560] = 'h00 ; mem_bank[561] = 'h00 ; mem_bank[562] = 'h00 ; mem_bank[563] = 'h00 ; mem_bank[564] = 'h00 ; mem_bank[565] = 'h00 ; mem_bank[566] = 'h00 ; mem_bank[567] = 'h00 ; mem_bank[568] = 'h02 ; mem_bank[569] = 'h3c ;
mem_bank[570] = 'h34 ; mem_bank[571] = 'h00 ; mem_bank[572] = 'h14 ; mem_bank[573] = 'h3c ; mem_bank[574] = 'h3c ; mem_bank[575] = 'h0c ; mem_bank[576] = 'h24 ; mem_bank[577] = 'h3c ; mem_bank[578] = 'h34 ; mem_bank[579] = 'h00 ;
mem_bank[580] = 'h10 ; mem_bank[581] = 'h3c ; mem_bank[582] = 'h34 ; mem_bank[583] = 'h02 ; mem_bank[584] = 'h00 ; mem_bank[585] = 'h00 ; mem_bank[586] = 'h3c ; mem_bank[587] = 'h24 ; mem_bank[588] = 'h00 ; mem_bank[589] = 'h00 ;
mem_bank[590] = 'h8c ; mem_bank[591] = 'h0c ; mem_bank[592] = 'h00 ; mem_bank[593] = 'h3c ; mem_bank[594] = 'h0c ; mem_bank[595] = 'h24 ; mem_bank[596] = 'h00 ; mem_bank[597] = 'h00 ; mem_bank[598] = 'h00 ; mem_bank[599] = 'h00 ;
mem_bank[600] = 'h00 ; mem_bank[601] = 'h00 ; mem_bank[602] = 'h00 ; mem_bank[603] = 'h02 ; mem_bank[604] = 'h3c ; mem_bank[605] = 'h34 ; mem_bank[606] = 'h00 ; mem_bank[607] = 'h10 ; mem_bank[608] = 'h00 ; mem_bank[609] = 'h3c ;
mem_bank[610] = 'h34 ; mem_bank[611] = 'h00 ; mem_bank[612] = 'h00 ; mem_bank[613] = 'h00 ; mem_bank[614] = 'h3c ; mem_bank[615] = 'h24 ; mem_bank[616] = 'h00 ; mem_bank[617] = 'h00 ; mem_bank[618] = 'h8c ; mem_bank[619] = 'h0c ;
mem_bank[620] = 'h00 ; mem_bank[621] = 'h3c ; mem_bank[622] = 'h0c ; mem_bank[623] = 'h24 ; mem_bank[624] = 'h00 ; mem_bank[625] = 'h00 ; mem_bank[626] = 'h00 ; mem_bank[627] = 'h00 ; mem_bank[628] = 'h00 ; mem_bank[629] = 'h00 ;
mem_bank[630] = 'h00 ; mem_bank[631] = 'h00 ; mem_bank[632] = 'h00 ; mem_bank[633] = 'h02 ; mem_bank[634] = 'h2e ; mem_bank[635] = 'h10 ; mem_bank[636] = 'h2e ; mem_bank[637] = 'h3c ; mem_bank[638] = 'h0c ; mem_bank[639] = 'h24 ;
mem_bank[640] = 'h2e ; mem_bank[641] = 'h14 ; mem_bank[642] = 'h2e ; mem_bank[643] = 'h3c ; mem_bank[644] = 'h34 ; mem_bank[645] = 'h02 ; mem_bank[646] = 'h00 ; mem_bank[647] = 'h00 ; mem_bank[648] = 'h3c ; mem_bank[649] = 'h24 ;
mem_bank[650] = 'h26 ; mem_bank[651] = 'h00 ; mem_bank[652] = 'h00 ; mem_bank[653] = 'h8c ; mem_bank[654] = 'h0c ; mem_bank[655] = 'h00 ; mem_bank[656] = 'h0c ; mem_bank[657] = 'h24 ; mem_bank[658] = 'h00 ; mem_bank[659] = 'h00 ;
mem_bank[660] = 'h00 ; mem_bank[661] = 'h00 ; mem_bank[662] = 'h00 ; mem_bank[663] = 'h00 ; mem_bank[664] = 'h00 ; mem_bank[665] = 'h02 ; mem_bank[666] = 'h2e ; mem_bank[667] = 'h10 ; mem_bank[668] = 'h3c ; mem_bank[669] = 'h3c ;
mem_bank[670] = 'h0c ; mem_bank[671] = 'h24 ; mem_bank[672] = 'h2e ; mem_bank[673] = 'h14 ; mem_bank[674] = 'h2e ; mem_bank[675] = 'h3c ; mem_bank[676] = 'h34 ; mem_bank[677] = 'h02 ; mem_bank[678] = 'h00 ; mem_bank[679] = 'h00 ;
mem_bank[680] = 'h3c ; mem_bank[681] = 'h24 ; mem_bank[682] = 'h00 ; mem_bank[683] = 'h00 ; mem_bank[684] = 'h8c ; mem_bank[685] = 'h0c ; mem_bank[686] = 'h00 ; mem_bank[687] = 'h3c ; mem_bank[688] = 'h0c ; mem_bank[689] = 'h24 ;
mem_bank[690] = 'h00 ; mem_bank[691] = 'h00 ; mem_bank[692] = 'h00 ; mem_bank[693] = 'h00 ; mem_bank[694] = 'h00 ; mem_bank[695] = 'h02 ; mem_bank[696] = 'h2e ; mem_bank[697] = 'h14 ; mem_bank[698] = 'h2e ; mem_bank[699] = 'h3c ;
mem_bank[700] = 'h34 ; mem_bank[701] = 'h02 ; mem_bank[702] = 'h00 ; mem_bank[703] = 'h00 ; mem_bank[704] = 'h3c ; mem_bank[705] = 'h24 ; mem_bank[706] = 'h00 ; mem_bank[707] = 'h00 ; mem_bank[708] = 'h8c ; mem_bank[709] = 'h0c ;
mem_bank[710] = 'h00 ; mem_bank[711] = 'h3c ; mem_bank[712] = 'h0c ; mem_bank[713] = 'h24 ; mem_bank[714] = 'h00 ; mem_bank[715] = 'h00 ; mem_bank[716] = 'h00 ; mem_bank[717] = 'h00 ; mem_bank[718] = 'h00 ; mem_bank[719] = 'h02 ;
mem_bank[720] = 'h2e ; mem_bank[721] = 'h14 ; mem_bank[722] = 'h3c ; mem_bank[723] = 'h3c ; mem_bank[724] = 'h34 ; mem_bank[725] = 'h02 ; mem_bank[726] = 'h00 ; mem_bank[727] = 'h00 ; mem_bank[728] = 'h24 ; mem_bank[729] = 'h26 ;
mem_bank[730] = 'h00 ; mem_bank[731] = 'h00 ; mem_bank[732] = 'h8c ; mem_bank[733] = 'h0c ; mem_bank[734] = 'h00 ; mem_bank[735] = 'h0c ; mem_bank[736] = 'h24 ; mem_bank[737] = 'h00 ; mem_bank[738] = 'h00 ; mem_bank[739] = 'h00 ;
mem_bank[740] = 'h02 ; mem_bank[741] = 'h3c ; mem_bank[742] = 'h24 ; mem_bank[743] = 'h00 ; mem_bank[744] = 'h00 ; mem_bank[745] = 'h8c ; mem_bank[746] = 'h0c ; mem_bank[747] = 'h00 ; mem_bank[748] = 'h0c ; mem_bank[749] = 'h24 ;
mem_bank[750] = 'h0c ; mem_bank[751] = 'h24 ; mem_bank[752] = 'h8f ; mem_bank[753] = 'h8f ; mem_bank[754] = 'h8f ; mem_bank[755] = 'h03 ; mem_bank[756] = 'h27 ; mem_bank[757] = 'h27 ; mem_bank[758] = 'haf ; mem_bank[759] = 'haf ;
mem_bank[760] = 'h24 ; mem_bank[761] = 'h0c ; mem_bank[762] = 'h02 ; mem_bank[763] = 'h00 ; mem_bank[764] = 'h10 ; mem_bank[765] = 'h02 ; mem_bank[766] = 'h03 ; mem_bank[767] = 'h00 ; mem_bank[768] = 'h00 ; mem_bank[769] = 'h00 ;
mem_bank[770] = 'h00 ; mem_bank[771] = 'h00 ; mem_bank[772] = 'h00 ; mem_bank[773] = 'h00 ; mem_bank[774] = 'h54 ; mem_bank[775] = 'h20 ; mem_bank[776] = 'h4d ; mem_bank[777] = 'h37 ; mem_bank[778] = 'h42 ; mem_bank[779] = 'h4c ;
mem_bank[780] = 'h45 ; mem_bank[781] = 'h6e ; mem_bank[782] = 'h74 ; mem_bank[783] = 'h65 ; mem_bank[784] = 'h74 ; mem_bank[785] = 'h73 ; mem_bank[786] = 'h6e ; mem_bank[787] = 'h73 ; mem_bank[788] = 'h79 ; mem_bank[789] = 'h66 ;
mem_bank[790] = 'h79 ; mem_bank[791] = 'h66 ; mem_bank[792] = 'h79 ; mem_bank[793] = 'h74 ; mem_bank[794] = 'h74 ; mem_bank[795] = 'h74 ; mem_bank[796] = 'h74 ; mem_bank[797] = 'h6e ; mem_bank[798] = 'h74 ; mem_bank[799] = 'h00 ;
mem_bank[800] = 'h65 ; mem_bank[801] = 'h74 ; mem_bank[802] = 'h00 ; mem_bank[803] = 'h73 ; mem_bank[804] = 'h6e ; mem_bank[805] = 'h6e ; mem_bank[806] = 'h73 ; mem_bank[807] = 'h65 ; mem_bank[808] = 'h66 ; mem_bank[809] = 'h65 ;
mem_bank[810] = 'h66 ; mem_bank[811] = 'h74 ; mem_bank[812] = 'h00 ; mem_bank[813] = 'h74 ; mem_bank[814] = 'h74 ; mem_bank[815] = 'h00 ; mem_bank[816] = 'h74 ; mem_bank[817] = 'h76 ; mem_bank[818] = 'h65 ; mem_bank[819] = 'h65 ;
mem_bank[820] = 'h74 ; mem_bank[821] = 'h6e ; mem_bank[822] = 'h00 ; mem_bank[823] = 'h65 ; mem_bank[824] = 'h74 ; mem_bank[825] = 'h73 ; mem_bank[826] = 'h6e ; mem_bank[827] = 'h73 ; mem_bank[828] = 'h66 ; mem_bank[829] = 'h00 ;
mem_bank[830] = 'h66 ; mem_bank[831] = 'h00 ; mem_bank[832] = 'h74 ; mem_bank[833] = 'h65 ; mem_bank[834] = 'h74 ; mem_bank[835] = 'h6f ; mem_bank[836] = 'h00 ; mem_bank[837] = 'h3a ; mem_bank[838] = 'h20 ; mem_bank[839] = 'h6c ;
mem_bank[840] = 'h20 ; mem_bank[841] = 'h20 ; mem_bank[842] = 'h64 ; mem_bank[843] = 'h20 ; mem_bank[844] = 'h6d ; mem_bank[845] = 'h69 ; mem_bank[846] = 'h00 ; mem_bank[847] = 'h20 ; mem_bank[848] = 'h6c ; mem_bank[849] = 'h20 ;
mem_bank[850] = 'h74 ; mem_bank[851] = 'h73 ; mem_bank[852] = 'h20 ; mem_bank[853] = 'h20 ; mem_bank[854] = 'h75 ; mem_bank[855] = 'h64 ; mem_bank[856] = 'h00 ; mem_bank[857] = 'h00 ; mem_bank[858] = 'h00 ; mem_bank[859] = 'h00 ;
mem_bank[860] = 'h00 ; mem_bank[861] = 'h00 ; mem_bank[862] = 'h00 ; mem_bank[863] = 'h00 ; mem_bank[864] = 'h00 ; mem_bank[865] = 'h00 ; mem_bank[866] = 'h00 ; mem_bank[867] = 'h00 ; mem_bank[868] = 'h00 ; mem_bank[869] = 'h00 ;
mem_bank[870] = 'h00 ; mem_bank[871] = 'h00 ; mem_bank[872] = 'h00 ; mem_bank[873] = 'h00 ; mem_bank[874] = 'h00 ; mem_bank[875] = 'h00 ; mem_bank[876] = 'h00 ; mem_bank[877] = 'h00 ; mem_bank[878] = 'h00 ; mem_bank[879] = 'h00 ;
mem_bank[880] = 'h00 ; mem_bank[881] = 'h00 ; mem_bank[882] = 'h00 ; mem_bank[883] = 'h00 ; mem_bank[884] = 'h00 ; mem_bank[885] = 'h00 ; mem_bank[886] = 'h00 ;
end
always @ (posedge clock) if (r_wren) mem_bank[r_wraddress]<=r_data;
always @ (posedge clock)
389,8 → 549,8
r_rdaddress_b<=rdaddress_b;
r_wren<=wren;
end
assign qa =(r_rdaddress_a>484)?0:mem_bank[r_rdaddress_a];
assign qb =(r_rdaddress_b>484)?0:mem_bank[r_rdaddress_b];
assign qa =mem_bank[r_rdaddress_a];
assign qb =mem_bank[r_rdaddress_b];
endmodule
 
 
/trunk/rtl/verilog/RF_components.v
104,10 → 104,11
clock,
qa,
qb,
rd_clk_cls,
rd_clk_cls
// pause
// bank_sel
);
 
// input pause;
input [31:0] data;
input [4:0] wraddress;
input [4:0] rdaddress_a;
134,7 → 135,8
reg_bank[i]=0;
end
 
always@(posedge clock)
always@(posedge clock)
// if( ~pause )
begin
r_data <=data;
r_wraddress<=wraddress;
141,8 → 143,8
r_wren<=wren;
end
 
always@(posedge clock)
if (~rd_clk_cls)
always@(posedge clock) // ||( 0==pause )
if(( 0==rd_clk_cls ))
begin
r_rdaddress_a <=rdaddress_a;
r_rdaddress_b <=rdaddress_b;
/trunk/rtl/verilog/ulit.v
27,7 → 27,7
 
always @(posedge clk )
if (~rst )ins_no=0;
else if (~is_nop)
else if (0==is_nop)
ins_no = 1+ins_no;
endmodule
 
138,8 → 138,10
module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule
module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule
module r32_reg_clr_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
/*
 
 
module ext_ctl_reg_clr(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr);always@(posedge clk)if(clr)ext_ctl_o<=0;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr);always@(posedge clk)if(clr)rd_sel_o<=0;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_clr(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr);always@(posedge clk)if(clr)cmp_ctl_o<=0;else cmp_ctl_o<=cmp_ctl_i;endmodule
209,3 → 211,4
module r32_reg_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input cls);always@(posedge clk)if(cls) r32_o<=r32_o;else r32_o<=r32_i;endmodule
 
 
*/
/trunk/rtl/verilog/mips_core.v
14,42 → 14,24
`include "mips789_defs.v"
 
module mips_core (
clk,irq_i,rst,cop_dout,irq_addr,
zz_din,zz_ins_i,iack_o,cop_addr_o,
cop_data_o,cop_mem_ctl_o,zz_addr_o,
zz_dout,zz_pc_o,zz_wr_en_o
input clk,
input irq_i,
input rst,
input [31:0] cop_dout,
input [31:0] irq_addr,
input [31:0] zz_din,
input [31:0] zz_ins_i,
output [31:0] zz_addr_o,
output [31:0] zz_dout,
output [31:0] zz_pc_o,
output [3:0] zz_wr_en_o,
output iack_o,
output [31:0] cop_addr_o,
output [31:0] cop_data_o,
output [3:0] cop_mem_ctl_o
 
);
 
input clk;
wire clk;
input irq_i;
wire irq_i;
input rst;
wire rst;
input [31:0] cop_dout;
wire [31:0] cop_dout;
input [31:0] irq_addr;
wire [31:0] irq_addr;
input [31:0] zz_din;
wire [31:0] zz_din;
input [31:0] zz_ins_i;
wire [31:0] zz_ins_i;
output [31:0] zz_addr_o;
wire [31:0] zz_addr_o;
output [31:0] zz_dout;
wire [31:0] zz_dout;
output [31:0] zz_pc_o;
wire [31:0] zz_pc_o;
output [3:0] zz_wr_en_o;
wire [3:0] zz_wr_en_o;
output iack_o;
wire iack_o;
output [31:0] cop_addr_o;
wire [31:0] cop_addr_o;
output [31:0] cop_data_o;
wire [31:0] cop_data_o;
output [3:0] cop_mem_ctl_o;
wire [3:0] cop_mem_ctl_o;
 
 
wire NET1375;
97,7 → 79,8
 
 
mem_module MEM_CTL
(
(
.pause(0),
.Zz_addr(zz_addr_o),
.Zz_dout(zz_dout),
.Zz_wr_en(zz_wr_en_o),
112,7 → 95,8
assign NET21531 = NET1572 | iack_o;
 
rf_stage iRF_stage
(
(
.pause(0),
.clk(clk),
.cmp_ctl_i(BUS109),
.ext_ctl_i(BUS117),
171,8 → 155,9
 
 
 
r32_reg alu_pass0
(
r32_reg_clr_cls alu_pass0
(
.cls(pause),.clr(0),
.clk(clk),
.r32_i(BUS9589),
.r32_o(cop_addr_o)
180,8 → 165,8
 
 
 
r32_reg alu_pass1
(
r32_reg_clr_cls alu_pass1
( .cls(pause),.clr(0),
.clk(clk),
.r32_i(cop_addr_o),
.r32_o(BUS422)
198,8 → 183,8
 
 
 
r32_reg cop_data_reg
(
r32_reg_clr_cls cop_data_reg
( .cls(pause),.clr(0),
.clk(clk),
.r32_i(BUS9884),
.r32_o(cop_data_o)
207,8 → 192,10
 
 
 
r32_reg cop_dout_reg
(
r32_reg_clr_cls cop_dout_reg
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS22401),
.r32_o(BUS7772)
217,7 → 204,7
 
 
decode_pipe decoder_pipe
(
( .pause(0),
.alu_func_o(BUS6275),
.alu_we_o(NET767),
.clk(clk),
240,8 → 227,10
 
 
 
r32_reg ext_reg
(
r32_reg_clr_cls ext_reg
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS7219),
.r32_o(BUS7231)
267,9 → 256,11
 
 
 
r32_reg pc
r32_reg_clr_cls pc
(
.clk(clk),
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(zz_pc_o),
.r32_o(BUS27031)
);
276,7 → 267,7
 
 
 
r5_reg rnd_pass0
r5_reg_clr_cls rnd_pass0
(
.clk(clk),
.r5_i(BUS775),
285,8 → 276,9
 
 
 
r5_reg rnd_pass1
(
r5_reg_clr_cls rnd_pass1
( .clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS1726),
.r5_o(BUS1724)
294,8 → 286,9
 
 
 
r5_reg rnd_pass2
(
r5_reg_clr_cls rnd_pass2
( .clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS1724),
.r5_o(BUS18211)
303,8 → 296,10
 
 
 
r32_reg rs_reg
(
r32_reg_clr_cls rs_reg
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS24839),
.r32_o(BUS7101)
312,8 → 307,9
 
 
 
r32_reg rt_reg
(
r32_reg_clr_cls rt_reg
( .clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS7160),
.r32_o(BUS7117)
/trunk/rtl/verilog/mips789_defs.v
10,13 → 10,16
* Email:mcupro@opencores.org or mcupro@163.com *
* *
******************************************************************/
 
`ifndef INCLUDE_H
`define INCLUDE_H
 
`define FRQ 50000000
`define SER_RATE 19200
 
`timescale 10ns / 1ns
 
`define FRQ 50000000
`define SER_RATE 192000 //specialy for simulate in order to make it faster
 
`define FW_ALU 3'b001
`define FW_MEM 3'b010
`define FW_NOP 3'b100
104,13 → 107,11
`define ALU_NOP 0
`define ALU_MTLO 30
`define ALU_MTHI 31
`define ALU_MULTU 8
 
`define ALU_MULTU 8
`define PC_IGN 1
`define PC_KEP 2
`define PC_IRQ 4
`define PC_RST 8
 
`define PC_RST 8
`define PC_J 1
`define PC_JR 2
`define PC_BC 4
117,8 → 118,7
`define PC_NEXT 5
`define PC_NOP 0
`define PC_RET 6
`define PC_SPC 6
 
`define PC_SPC 6
`define RF 13
`define EXEC 10
`define DMEM 4
179,10 → 179,11
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
 
`define DEFAULT_IRQ_ADDR 'H00_00_00_5C
 
`define ALTERA
 
 
//`define ALTERA //this is DEBUG model ,
 
`else
 
 
/trunk/rtl/verilog/mem_module.v
14,30 → 14,21
`include "mips789_defs.v"
 
 
module mem_module (
clk,din,dmem_addr_i,dmem_ctl,
zZ_din,Zz_addr,Zz_dout,Zz_wr_en,dout
module mem_module (
input pause,
input clk,
input [31:0] din,
input [31:0] dmem_addr_i,
input [3:0] dmem_ctl,
input [31:0] zZ_din,
output [31:0] Zz_addr,
output [31:0] Zz_dout,
output [3:0] Zz_wr_en,
output [31:0] dout
) ;
 
input clk;
wire clk;
input [31:0] din;
wire [31:0] din;
input [31:0] dmem_addr_i;
wire [31:0] dmem_addr_i;
input [3:0] dmem_ctl;
wire [3:0] dmem_ctl;
input [31:0] zZ_din;
wire [31:0] zZ_din;
output [31:0] Zz_addr;
wire [31:0] Zz_addr;
output [31:0] Zz_dout;
wire [31:0] Zz_dout;
output [3:0] Zz_wr_en;
wire [3:0] Zz_wr_en;
output [31:0] dout;
wire [31:0] dout;
 
 
wire [3:0] BUS512;
wire [1:0] BUS629;
wire [31:0] BUS650;
44,7 → 35,7
 
 
infile_dmem_ctl_reg dmem_ctl_post
(
( .pause(pause),
.byte_addr_o(BUS629),
.clk(clk),
.ctl_i(dmem_ctl),
89,7 → 80,8
endmodule
 
 
module infile_dmem_ctl_reg(
module infile_dmem_ctl_reg(
input pause,
input clk,
input [3:0]ctl_i,
input [31:0]dmem_addr_i,
101,6 → 93,7
assign byte_addr_i = dmem_addr_i[1:0] ;
 
always @(posedge clk)
if(0==pause)
begin
ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0;
byte_addr_o<=byte_addr_i;
/trunk/rtl/verilog/ctl_fsm.v
12,7 → 12,8
******************************************************************/
 
`include "mips789_defs.v"
module ctl_FSM (
module ctl_FSM (
input pause,
input clk,
input [2:0] id_cmd,
input irq,
63,7 → 64,10
// Finite State Machine
//
/*Finite State Machine part1*/
always @ (posedge clk) if (~rst) CurrState <= `RST; else CurrState <= NextState ;
always @ (posedge clk)
if (~rst) CurrState <= `RST;
else if (~pause)
CurrState <= NextState ;
 
always @ (*)/*Finite State Machine part2*/
begin
/trunk/rtl/verilog/RF_stage.v
14,74 → 14,40
`include "mips789_defs.v"
 
module rf_stage (
clk,irq_i,rst_i,wb_we_i,cmp_ctl_i,
ext_ctl_i,fw_alu_i,fw_cmp_rs,fw_cmp_rt,
fw_mem_i,id_cmd,ins_i,irq_addr_i,pc_gen_ctl,
pc_i,rd_sel_i,wb_addr_i,wb_din_i,zz_spc_i,iack_o,
id2ra_ctl_clr_o,id2ra_ctl_cls_o,ra2ex_ctl_clr_o,ext_o,
pc_next,rd_index_o,rs_n_o,rs_o,rt_n_o,rt_o
input pause,
input clk,
input irq_i,
input rst_i,
input wb_we_i,
input [2:0] cmp_ctl_i,
input [2:0] ext_ctl_i,
input [31:0] fw_alu_i,
input [2:0] fw_cmp_rs,
input [2:0] fw_cmp_rt,
input [31:0] fw_mem_i,
input [2:0] id_cmd,
input [31:0] ins_i,
input [31:0] irq_addr_i,
input [2:0] pc_gen_ctl,
input [31:0] pc_i,
input [1:0] rd_sel_i,
input [4:0] wb_addr_i,
input [31:0] wb_din_i,
input [31:0] zz_spc_i,
output iack_o,
output id2ra_ctl_clr_o,
output id2ra_ctl_cls_o,
output ra2ex_ctl_clr_o,
output [31:0] ext_o,
output [31:0] pc_next,
output [4:0] rd_index_o,
output [4:0] rs_n_o,
output [31:0] rs_o,
output [4:0] rt_n_o,
output [31:0] rt_o
) ;
 
input clk;
wire clk;
input irq_i;
wire irq_i;
input rst_i;
wire rst_i;
input wb_we_i;
wire wb_we_i;
input [2:0] cmp_ctl_i;
wire [2:0] cmp_ctl_i;
input [2:0] ext_ctl_i;
wire [2:0] ext_ctl_i;
input [31:0] fw_alu_i;
wire [31:0] fw_alu_i;
input [2:0] fw_cmp_rs;
wire [2:0] fw_cmp_rs;
input [2:0] fw_cmp_rt;
wire [2:0] fw_cmp_rt;
input [31:0] fw_mem_i;
wire [31:0] fw_mem_i;
input [2:0] id_cmd;
wire [2:0] id_cmd;
input [31:0] ins_i;
wire [31:0] ins_i;
input [31:0] irq_addr_i;
wire [31:0] irq_addr_i;
input [2:0] pc_gen_ctl;
wire [2:0] pc_gen_ctl;
input [31:0] pc_i;
wire [31:0] pc_i;
input [1:0] rd_sel_i;
wire [1:0] rd_sel_i;
input [4:0] wb_addr_i;
wire [4:0] wb_addr_i;
input [31:0] wb_din_i;
wire [31:0] wb_din_i;
input [31:0] zz_spc_i;
wire [31:0] zz_spc_i;
output iack_o;
wire iack_o;
output id2ra_ctl_clr_o;
wire id2ra_ctl_clr_o;
output id2ra_ctl_cls_o;
wire id2ra_ctl_cls_o;
output ra2ex_ctl_clr_o;
wire ra2ex_ctl_clr_o;
output [31:0] ext_o;
wire [31:0] ext_o;
output [31:0] pc_next;
wire [31:0] pc_next;
output [4:0] rd_index_o;
wire [4:0] rd_index_o;
output [4:0] rs_n_o;
wire [4:0] rs_n_o;
output [31:0] rs_o;
wire [31:0] rs_o;
output [4:0] rt_n_o;
wire [4:0] rt_n_o;
output [31:0] rt_o;
wire [31:0] rt_o;
 
 
wire NET6609;
112,7 → 78,8
 
 
ctl_FSM MAIN_FSM
(
(
.pause(pause),
.clk(clk),
.iack(iack_o),
.id2ra_ctl_clr(id2ra_ctl_clr_o),
167,7 → 134,7
(
.clk(clk),
.clr(NET6609),
.cls(NET6658),
.cls(NET6658|pause),
.r32_i(ins_i),
.r32_o(BUS2085)
);
208,7 → 175,7
);*/
 
reg_array reg_bank
(
( // .pause(pause),
.clock(clk),
.data(wb_din_i),
.qa(BUS6061),
/trunk/rtl/verilog/decode_pipe.v
1156,7 → 1156,7
 
 
 
module pipelinedregs (
module pipelinedregs (pause,
clk,id2ra_ctl_clr,id2ra_ctl_cls,ra2ex_ctl_clr,
alu_func_i,alu_we_i,cmp_ctl_i,dmem_ctl_i,ext_ctl_i,
muxa_ctl_i,muxb_ctl_i,pc_gen_ctl_i,rd_sel_i,wb_mux_ctl_i,
1163,7 → 1163,7
wb_we_i,alu_func_o,alu_we_o,cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,
ext_ctl,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,wb_mux_ctl_o,wb_we_o
) ;
 
input pause;
input clk;
wire clk;
input id2ra_ctl_clr;
1238,7 → 1238,7
muxb_ctl_reg_clr_cls U1
(
.clk(clk),
.clr(id2ra_ctl_clr),
.clr(id2ra_ctl_clr|pause),
.cls(id2ra_ctl_cls),
.muxb_ctl_i(muxb_ctl_i),
.muxb_ctl_o(BUS5483)
1250,7 → 1250,7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cls(id2ra_ctl_cls|pause),
.wb_mux_ctl_i(wb_mux_ctl_i),
.wb_mux_ctl_o(BUS5651)
);
1261,7 → 1261,7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cls(id2ra_ctl_cls|pause),
.wb_we_i(wb_we_i),
.wb_we_o(BUS5639)
);
1268,8 → 1268,10
 
 
 
wb_we_reg U12
wb_we_reg_clr_cls U12
(
.cls(pause),
.clr(0),
.clk(clk),
.wb_we_i(NET7643),
.wb_we_o(wb_we_o)
1277,8 → 1279,9
 
 
 
wb_mux_ctl_reg_clr U13
wb_mux_ctl_reg_clr_cls U13
(
.cls(pause),
.clk(clk),
.clr(ra2ex_ctl_clr),
.wb_mux_ctl_i(BUS5651),
1287,9 → 1290,9
 
 
 
muxb_ctl_reg_clr U14
muxb_ctl_reg_clr_cls U14
(
.clk(clk),
.clk(clk),.cls(pause),
.clr(ra2ex_ctl_clr),
.muxb_ctl_i(BUS5483),
.muxb_ctl_o(muxb_ctl_o)
1297,9 → 1300,10
 
 
 
dmem_ctl_reg_clr U15
dmem_ctl_reg_clr_cls U15
(
.clk(clk),
.cls(pause),
.clr(ra2ex_ctl_clr),
.dmem_ctl_i(BUS5666),
.dmem_ctl_o(dmem_ctl_ur_o)
1307,19 → 1311,20
 
 
 
alu_func_reg_clr U16
alu_func_reg_clr_cls U16
(
.alu_func_i(BUS5674),
.alu_func_o(alu_func_o),
.clk(clk),
.cls(pause),
.clr(ra2ex_ctl_clr)
);
 
 
 
muxa_ctl_reg_clr U17
muxa_ctl_reg_clr_cls U17
(
.clk(clk),
.cls(pause), .clk(clk),
.clr(ra2ex_ctl_clr),
.muxa_ctl_i(BUS5008),
.muxa_ctl_o(muxa_ctl_o)
1327,9 → 1332,10
 
 
 
wb_mux_ctl_reg U18
wb_mux_ctl_reg_clr_cls U18
(
.clk(clk),
.clk(clk), .cls(pause),
.clr(0),
.wb_mux_ctl_i(BUS5790),
.wb_mux_ctl_o(wb_mux_ctl_o)
);
1336,9 → 1342,9
 
 
 
wb_we_reg_clr U19
wb_we_reg_clr_cls U19
(
.clk(clk),
.clk(clk),.cls(pause),
.clr(ra2ex_ctl_clr),
.wb_we_i(BUS5639),
.wb_we_o(BUS5682)
1350,7 → 1356,7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cls(id2ra_ctl_cls|pause),
.cmp_ctl_i(cmp_ctl_i),
.cmp_ctl_o(cmp_ctl_o)
);
1357,9 → 1363,9
 
 
 
wb_we_reg U20
wb_we_reg_clr_cls U20
(
.clk(clk),
.clk(clk),.clr(0),.cls(pause),
.wb_we_i(BUS5682),
.wb_we_o(BUS7822)
);
1366,9 → 1372,11
 
 
 
wb_mux_ctl_reg U21
wb_mux_ctl_reg_clr_cls U21
(
.clk(clk),
.cls(pause),
.clr(0),
.wb_mux_ctl_i(BUS5690),
.wb_mux_ctl_o(BUS5790)
);
1375,9 → 1383,10
 
 
 
wb_we_reg U22
wb_we_reg_clr_cls U22
(
.clk(clk),
.clk(clk), .cls(pause),
.clr(0),
.wb_we_i(BUS7299),
.wb_we_o(alu_we_o)
);
1387,9 → 1396,11
assign NET7643 = alu_we_o[0] | BUS7822[0];
 
 
alu_we_reg_clr U24
alu_we_reg_clr_cls U24
(
.alu_we_i(BUS4987),
.cls(pause),
.alu_we_i(BUS4987),
.alu_we_o(BUS7299),
.clk(clk),
.clr(ra2ex_ctl_clr)
1403,7 → 1414,7
.alu_func_o(BUS5674),
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls)
.cls(id2ra_ctl_cls|pause)
);
 
 
1412,7 → 1423,7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cls(id2ra_ctl_cls|pause),
.dmem_ctl_i(dmem_ctl_i),
.dmem_ctl_o(BUS5666)
);
1423,7 → 1434,7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cls(id2ra_ctl_cls|pause),
.ext_ctl_i(ext_ctl_i),
.ext_ctl_o(ext_ctl)
);
1434,7 → 1445,7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cls(id2ra_ctl_cls|pause),
.rd_sel_i(rd_sel_i),
.rd_sel_o(rd_sel_o)
);
1447,7 → 1458,7
.alu_we_o(BUS4987),
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls)
.cls(id2ra_ctl_cls|pause)
);
 
 
1456,7 → 1467,7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cls(id2ra_ctl_cls|pause),
.muxa_ctl_i(muxa_ctl_i),
.muxa_ctl_o(BUS5008)
);
1467,7 → 1478,7
(
.clk(clk),
.clr(id2ra_ctl_clr),
.cls(id2ra_ctl_cls),
.cls(id2ra_ctl_cls|pause),
.pc_gen_ctl_i(pc_gen_ctl_i),
.pc_gen_ctl_o(pc_gen_ctl_o)
);
1474,9 → 1485,12
 
 
 
dmem_ctl_reg U9
dmem_ctl_reg_clr_cls U9
(
.clk(clk),
.cls(pause),
.clr(0),
.clk(clk),
.dmem_ctl_i(dmem_ctl_ur_o),
.dmem_ctl_o(dmem_ctl_o)
);
1487,6 → 1501,7
 
module decode_pipe
(
pause,
clk,id2ra_ctl_clr,id2ra_ctl_cls,
ra2ex_ctl_clr,ins_i,alu_func_o,alu_we_o,
cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,ext_ctl_o,
1493,7 → 1508,7
fsm_dly,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,
wb_mux_ctl_o,wb_we_o
) ;
 
input pause;
input clk;
wire clk;
input id2ra_ctl_clr;
1566,6 → 1581,11
 
pipelinedregs pipereg
(
.pause(pause),
.id2ra_ctl_cls(id2ra_ctl_cls),
.id2ra_ctl_clr(id2ra_ctl_clr),
.ra2ex_ctl_clr(ra2ex_ctl_clr),
.alu_func_i(BUS2040),
.alu_func_o(alu_func_o),
.alu_we_i(BUS2048),
1578,15 → 1598,15
.dmem_ctl_ur_o(dmem_ctl_ur_o),
.ext_ctl(ext_ctl_o),
.ext_ctl_i(BUS2072),
.id2ra_ctl_clr(id2ra_ctl_clr),
.id2ra_ctl_cls(id2ra_ctl_cls),
 
.muxa_ctl_i(BUS2086),
.muxa_ctl_o(muxa_ctl_o),
.muxb_ctl_i(BUS2094),
.muxb_ctl_o(muxb_ctl_o),
.pc_gen_ctl_i(BUS2102),
.pc_gen_ctl_o(pc_gen_ctl_o),
.ra2ex_ctl_clr(ra2ex_ctl_clr),
.pc_gen_ctl_o(pc_gen_ctl_o),
.rd_sel_i(BUS2110),
.rd_sel_o(rd_sel_o),
.wb_mux_ctl_i(BUS2118),
/trunk/rtl/verilog/mips_uart.v
23,31 → 23,26
endmodule
 
module uart0 (
clk,rst,rxd_ft,ser_rxd,txd_ld,
din,rxd_rdy,ser_txd,txd_busy,dout) ;
input clk;
wire clk;
input rst;
wire rst;
input rxd_ft;
wire rxd_ft;
input ser_rxd;
wire ser_rxd;
input txd_ld;
wire txd_ld;
input [7:0] din;
wire [7:0] din;
output rxd_rdy;
wire rxd_rdy;
output ser_txd;
wire ser_txd;
output txd_busy;
wire txd_busy;
output [7:0] dout;
wire [7:0] dout;
input clk,
input rst,
input rxd_ft,
input ser_rxd,
input txd_ld,
input [7:0] din,
output rxd_rdy,
output ser_txd,
output txd_busy,
output [7:0] dout
);
 
wire clk_uart=clk;
wire w_rxd_rdy;
wire w_rxd_rdy;
integer uart_send;
initial begin
60,7 → 55,11
 
always @ (txd_ld)
begin
if (txd_ld) $fwrite( uart_send,"%c",din[7:0]);
if (txd_ld)
begin
$fwrite( uart_send,"%c",din[7:0]);
$display("UART0 =>%c<",din[7:0]);
end
end
 
uart_read uart_rd_tak(
156,7 → 155,7
.q(queue_data),
.full(queue_full),
.empty(empty),
.rst(sync_reset));
.rst(sync_reset));
`endif
 
 
/trunk/rtl/verilog/EXEC_stage.v
14,7 → 14,7
`include "mips789_defs.v"
 
module exec_stage
(
( pause,
clk,rst,spc_cls_i,alu_func,
dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
21,7 → 21,7
muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
dmem_data_ur_o,zz_spc_o
);
 
input pause;
input clk;
wire clk;
input rst;
90,6 → 90,29
.fw_dmem(fw_dmem),
.din(rt_i)
);
/* alu_muxb1 i_alu_muxb
(
.b_o(BUS468),
.ctl(muxb_ctl_i),
.ext(ext_i),
.fw_alu(fw_alu),
.fw_ctl(muxb_fw_ctl),
.fw_mem(fw_dmem),
.rt(rt_i)
);
*/
alu_muxb i_alu_muxb
(
.b_o(BUS468),
.ctl(muxb_ctl_i),
.ext(ext_i),
// .fw_alu(fw_alu),
// .fw_ctl(muxb_fw_ctl),
// .fw_mem(fw_dmem),
.rt(dmem_data_ur_o)
);
 
 
 
108,24 → 131,16
 
 
 
alu_muxb i_alu_muxb
(
.b_o(BUS468),
.ctl(muxb_ctl_i),
.ext(ext_i),
.fw_alu(fw_alu),
.fw_ctl(muxb_fw_ctl),
.fw_mem(fw_dmem),
.rt(rt_i)
);
 
 
 
r32_reg pc_nxt
(
r32_reg_clr_cls pc_nxt
(
.cls(pause),
.clr(0),
.clk(clk),
.r32_i(BUS2446),
.r32_o(BUS2332)
.r32_o(BUS2332)
);
 
 
133,7 → 148,7
r32_reg_cls spc
(
.clk(clk),
.cls(spc_cls_i),
.cls(spc_cls_i|pause),
.r32_i(pc_i),
.r32_o(zz_spc_o)
);
173,12 → 188,19
.func(ctl)
);
*/
shifter_tak mips_shifter(
/* shifter_ff mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
*/ shifter_tak mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
/* */
 
 
alu mips_alu(
215,17 → 237,14
endmodule
 
module alu_muxb(
input [31:0] rt,
input [31:0]fw_alu,
input [31:0]fw_mem,
input [31:0] rt,
input [31:0]ext ,
input [1:0]ctl ,
input [2:0]fw_ctl ,
input [1:0]ctl ,
output reg [31:0] b_o
);
always@(*)
case (ctl)
`MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
// `MUXB_RT :b_o =rt; //(fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
`MUXB_EXT : b_o=ext;
default b_o=rt;
endcase

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