OpenCores
URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 43 to Rev 44
    ↔ Reverse comparison
  •

Rev 43 → Rev 44

/rio/branches/2.0.0-development/bench/vhdl/TestRioWbBridge.vhd
62,7 → 62,7
address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
byteSelect : std_logic_vector(7 downto 0);
length : natural range 1 to DATA_SIZE_MAX;
data : DoublewordArray(DATA_SIZE_MAX-1 downto 0);
data : DoublewordArray(0 to DATA_SIZE_MAX-1);
latency : natural;
end record;
 
97,7 → 97,7
adr_i : in std_logic_vector(30 downto 0);
sel_i : in std_logic_vector(7 downto 0);
dat_i : in std_logic_vector(63 downto 0);
dat_o : in std_logic_vector(63 downto 0);
dat_o : out std_logic_vector(63 downto 0);
err_o : out std_logic;
ack_o : out std_logic);
end component;
107,15 → 107,15
clk : in std_logic;
areset_n : in std_logic;
 
outboundEmpty_o : out std_logic;
outboundWrite_i : in std_logic;
outboundMessage_i : in TestPortMessagePacketBuffer;
outboundAck_o : out std_logic;
readEmpty_o : out std_logic;
readWrite_i : in std_logic;
readMessage_i : in TestPortMessagePacketBuffer;
readAck_o : out std_logic;
inboundEmpty_o : out std_logic;
inboundWrite_i : in std_logic;
inboundMessage_i : in TestPortMessagePacketBuffer;
inboundAck_o : out std_logic;
writeEmpty_o : out std_logic;
writeWrite_i : in std_logic;
writeMessage_i : in TestPortMessagePacketBuffer;
writeAck_o : out std_logic;
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
232,15 → 232,15
clk : in std_logic;
areset_n : in std_logic;
 
outboundEmpty_o : out std_logic;
outboundWrite_i : in std_logic;
outboundMessage_i : in TestPortMessagePacketBuffer;
outboundAck_o : out std_logic;
readEmpty_o : out std_logic;
readWrite_i : in std_logic;
readMessage_i : in TestPortMessagePacketBuffer;
readAck_o : out std_logic;
inboundEmpty_o : out std_logic;
inboundWrite_i : in std_logic;
inboundMessage_i : in TestPortMessagePacketBuffer;
inboundAck_o : out std_logic;
writeEmpty_o : out std_logic;
writeWrite_i : in std_logic;
writeMessage_i : in TestPortMessagePacketBuffer;
writeAck_o : out std_logic;
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
268,7 → 268,7
-------------------------------------------------------------------------------
architecture TestPortPacketBufferPortImpl of TestPortPacketBuffer is
constant QUEUE_SIZE : natural := 63;
type QueueArray is array (natural range <>) of MessageFrame;
type QueueArray is array (natural range <>) of TestPortMessagePacketBuffer;
function QueueIndexInc(constant i : natural) return natural is
variable returnValue : natural;
286,7 → 286,7
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
Outbound: process
Reader: process
variable frameQueue : QueueArray(0 to QUEUE_SIZE);
variable front, back, window : natural range 0 to QUEUE_SIZE;
variable frameIndex : natural;
304,11 → 304,11
back := 0;
window := 0;
frameIndex := 0;
outboundEmpty_o <= '1';
outboundAck_o <= '0';
readEmpty_o <= '1';
readAck_o <= '0';
 
loop
wait until clk = '1' or outboundWrite_i = '1';
wait until clk = '1' or readWrite_i = '1';
 
if (clk'event) then
if (readFrame_i = '1') then
315,7 → 315,7
if (back /= front) then
back := QueueIndexInc(back);
else
TestError("OUTBOUND:BACK:reading when no frame is present");
TestError("READ:BACK:reading when no frame is present");
end if;
end if;
 
333,7 → 333,7
window := QueueIndexInc(window);
frameIndex := 0;
else
TestError("OUTBOUND:WINDOW:reading when no frame is present");
TestError("READ:WINDOW:reading when no frame is present");
end if;
end if;
348,10 → 348,10
readContentEnd_o <= '0';
end if;
else
TestError("OUTBOUND:CONTENT:reading when frame has ended");
TestError("READ:CONTENT:reading when frame has ended");
end if;
else
TestError("OUTBOUND:CONTENT:reading when no frame is present");
TestError("READ:CONTENT:reading when no frame is present");
end if;
end if;
 
374,18 → 374,18
end if;
if (front = back) then
outboundEmpty_o <= '1';
readEmpty_o <= '1';
else
outboundEmpty_o <= '0';
readEmpty_o <= '0';
end if;
elsif (outboundWrite_i'event) then
frameQueue(front) := outboundMessage_i;
elsif (readWrite_i'event) then
frameQueue(front) := readMessage_i;
front := QueueIndexInc(front);
 
outboundEmpty_o <= '0';
outboundAck_o <= '1';
wait until outboundWrite_i = '0';
outboundAck_o <= '0';
readEmpty_o <= '0';
readAck_o <= '1';
wait until readWrite_i = '0';
readAck_o <= '0';
end if;
end loop;
end process;
393,7 → 393,7
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
Inbound: process
Writer: process
variable frameQueue : QueueArray(0 to QUEUE_SIZE);
variable front, back : natural range 0 to QUEUE_SIZE;
variable frameIndex : natural range 0 to 69;
400,8 → 400,8
begin
wait until areset_n = '1';
 
inboundEmpty_o <= '1';
inboundAck_o <= '0';
writeEmpty_o <= '1';
writeAck_o <= '0';
 
front := 0;
back := 0;
408,21 → 408,21
frameIndex := 0;
 
loop
wait until clk = '1' or inboundWrite_i = '1';
wait until clk = '1' or writeWrite_i = '1';
 
if (clk'event) then
 
if (writeFrame_i = '1') then
if (frameIndex = 0) then
TestError("INBOUND:Empty frame written.");
TestError("WRITE:Empty frame written.");
end if;
if (frameIndex /= frameQueue(back).frame.length) then
TestError("INBOUND:Frame with unmatching length was written.");
TestError("WRITE:Frame with unmatching length was written.");
end if;
if (back /= front) then
back := QueueIndexInc(back);
else
TestError("INBOUND:Unexpected frame written.");
TestError("WRITE:Unexpected frame written.");
end if;
frameIndex := 0;
end if;
430,12 → 430,12
if (writeFrameAbort_i = '1') then
if (back /= front) then
if (frameQueue(back).willAbort) then
if (frameIndex /= frameQueue(back).frame.length) then
TestError("INBOUND:Frame with unmatching length was aborted.");
end if;
TestCompare(frameIndex,
frameQueue(back).frame.length,
"frameIndex abort");
back := QueueIndexInc(back);
else
TestError("INBOUND:Not expecting this frame to abort.");
TestError("WRITE:Not expecting this frame to abort.");
end if;
end if;
frameIndex := 0;
443,28 → 443,28
 
if (writeContent_i = '1') then
if (frameIndex < frameQueue(back).frame.length) then
if (frameQueue(back).frame.payload(frameIndex) /= writeContentData_i) then
TestError("INBOUND:Unexpected frame content written.");
end if;
TestCompare(writeContentData_i,
frameQueue(back).frame.payload(frameIndex),
"frame content");
frameIndex := frameIndex + 1;
else
TestError("INBOUND:Receiving more frame content than expected.");
TestError("WRITE:Receiving more frame content than expected.");
end if;
end if;
if (front = back) then
inboundEmpty_o <= '1';
writeEmpty_o <= '1';
else
inboundEmpty_o <= '0';
writeEmpty_o <= '0';
end if;
elsif (inboundWrite_i'event) then
frameQueue(front) := inboundMessage_i;
elsif (writeWrite_i'event) then
frameQueue(front) := writeMessage_i;
front := QueueIndexInc(front);
 
inboundEmpty_o <= '0';
inboundAck_o <= '1';
wait until inboundWrite_i = '0';
inboundAck_o <= '0';
writeEmpty_o <= '0';
writeAck_o <= '1';
wait until writeWrite_i = '0';
writeAck_o <= '0';
end if;
end loop;
end process;
504,7 → 504,7
adr_i : in std_logic_vector(30 downto 0);
sel_i : in std_logic_vector(7 downto 0);
dat_i : in std_logic_vector(63 downto 0);
dat_o : in std_logic_vector(63 downto 0);
dat_o : out std_logic_vector(63 downto 0);
err_o : out std_logic;
ack_o : out std_logic);
end entity;
513,9 → 513,9
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture TestWishbonePortImpl of TestWishbonePort is
architecture TestPortWishboneImpl of TestPortWishbone is
constant QUEUE_SIZE : natural := 63;
type QueueArray is array (natural range <>) of MessageFrame;
type QueueArray is array (natural range <>) of TestPortMessageWishbone;
function QueueIndexInc(constant i : natural) return natural is
variable returnValue : natural;
559,34 → 559,42
if (clk'event) then
if (cyc_i = '1') then
if (front /= back) then
TestCompare(stb_i, '1', "stb_i");
if (queue(back).writeAccess) then
TestCompare(we_i, '1', "we_i");
else
TestCompare(we_i, '0', "we_i");
end if;
TestCompare(adr_i, queue(back).address, "adr_i");
TestCompare(sel_i, queue(back).byteSelect, "sel_i");
TestCompare(dat_i, queue(back).data(cyclePosition), "dat_i");
if (cyclePosition < queue(back).length) then
TestCompare(stb_i, '1', "stb_i");
if (queue(back).writeAccess) then
TestCompare(we_i, '1', "we_i");
else
TestCompare(we_i, '0', "we_i");
end if;
-- REMARK: Add this...
--TestCompare(adr_i, std_logic_vector(unsigned(queue(back).address)+cyclePosition), "adr_i");
TestCompare(sel_i, queue(back).byteSelect, "sel_i");
if (queue(back).writeAccess) then
TestCompare(dat_i, queue(back).data(cyclePosition), "dat_i");
end if;
 
if (latencyCounter = queue(back).latency) then
ack_o <= '1';
latencyCounter := 0;
if(cyclePosition = queue(back).length) then
back := QueueIndexInc(back);
cyclePosition := 0;
if (latencyCounter = queue(back).latency) then
dat_o <= queue(back).data(cyclePosition);
ack_o <= '1';
latencyCounter := 0;
cyclePosition := cyclePosition + 1;
else
cyclePosition := cyclePosition + 1;
dat_o <= (others=>'U');
ack_o <= '0';
latencyCounter := latencyCounter + 1;
end if;
else
back := QueueIndexInc(back);
cyclePosition := 0;
latencyCounter := 0;
dat_o <= (others=>'U');
ack_o <= '0';
latencyCounter := latencyCounter + 1;
end if;
else
TestError("Unexpected access.");
end if;
else
if (cyclePostion /= 0) or (latencyCounter /= 0) then
if (cyclePosition /= 0) or (latencyCounter /= 0) then
TestError("Cycle unexpectedly aborted.");
cyclePosition := 0;
latencyCounter := 0;
595,9 → 603,9
end if;
 
if (front = back) then
outboundWriteEmpty_o <= '1';
messageEmpty_o <= '1';
else
outboundWriteEmpty_o <= '0';
messageEmpty_o <= '0';
end if;
elsif (messageWrite_i'event) then
queue(front) := message_i;
652,6 → 660,7
port(
clk : in std_logic;
areset_n : in std_logic;
enable : in std_logic;
 
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
765,12 → 774,142
constant byteSelect : in std_logic_vector(7 downto 0);
constant length : in natural range 1 to DATA_SIZE_MAX;
constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);
constant latency : natural := 0) is
constant latency : natural := 1) is
begin
TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,
writeAccess, address, byteSelect, length, data, latency);
end procedure;
 
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
function getReadSize(constant rdsize : in std_logic_vector(3 downto 0);
constant wdptr : in std_logic) return natural is
begin
case rdsize is
when "0000" | "0001" | "0010" | "0011" =>
return 1;
when "0100" | "0110" =>
return 1;
when "0101" =>
return 1;
when "1000" =>
return 1;
when "0111" =>
return 1;
when "1001" =>
return 1;
when "1010" =>
return 1;
when "1011" =>
if (wdptr = '0') then
return 1;
else
return 2;
end if;
when "1100" =>
if (wdptr = '0') then
return 4;
else
return 8;
end if;
when "1101" =>
if (wdptr = '0') then
return 12;
else
return 16;
end if;
when "1110" =>
if (wdptr = '0') then
return 20;
else
return 24;
end if;
when "1111" =>
if (wdptr = '0') then
return 28;
else
return 32;
end if;
when others =>
return 0;
end case;
end function;
function getReadMask(constant rdsize : in std_logic_vector(3 downto 0);
constant wdptr : in std_logic) return std_logic_vector is
begin
case rdsize is
when "0000" =>
if (wdptr = '0') then
return "10000000";
else
return "00001000";
end if;
when "0001" =>
if (wdptr = '0') then
return "01000000";
else
return "00000100";
end if;
when "0010" =>
if (wdptr = '0') then
return "00100000";
else
return "00000010";
end if;
when "0011" =>
if (wdptr = '0') then
return "00010000";
else
return "00000001";
end if;
when "0100" =>
if (wdptr = '0') then
return "11000000";
else
return "00001100";
end if;
when "0110" =>
if (wdptr = '0') then
return "00110000";
else
return "00000011";
end if;
when "0101" =>
if (wdptr = '0') then
return "11100000";
else
return "00000111";
end if;
when "1000" =>
if (wdptr = '0') then
return "11110000";
else
return "00001111";
end if;
when "0111" =>
if (wdptr = '0') then
return "11111000";
else
return "00011111";
end if;
when "1001" =>
if (wdptr = '0') then
return "11111100";
else
return "00111111";
end if;
when "1010" =>
if (wdptr = '0') then
return "11111110";
else
return "01111111";
end if;
when others =>
return "11111111";
end case;
end function;
---------------------------------------------------------------------------
--
778,12 → 917,19
variable seed1 : positive := 1;
variable seed2: positive := 1;
 
variable rdsize : std_logic_vector(3 downto 0);
variable wdptr : std_logic;
variable ioData : DoubleWordArray(0 to 31);
variable frame : RioFrame;
begin
areset_n <= '0';
enable <= '1';
 
inboundWrite <= '0';
outboundWrite <= '0';
wbMessageWrite <= '0';
writeFrameFull <= '0';
 
wait until clk'event and clk = '1';
794,10 → 940,10
 
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioLogicalCommon");
PrintS("TG_RioWbBridge");
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioLogicalCommon-TC1");
PrintS("Description: Test maintenance read requests.");
PrintS("TG_RioWbBridge-TC1");
PrintS("Description: Test maintenance requests.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
805,33 → 951,61
PrintS("Result: Check the accesses on the external configuration port.");
PrintS("-----------------------------------------------------------------");
---------------------------------------------------------------------------
PrintR("TG_RioLogicalCommon-TC1-Step1");
PrintR("TG_RioWbBridge-TC1-Step1");
---------------------------------------------------------------------------
ioData(0) := x"deadbeefc0debabe";
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioWbBridge-TC2");
PrintS("Description: Test request class packets.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Send maintenance read request for one word on even offset.");
PrintS("Result: Check the accesses on the external configuration port.");
PrintS("-----------------------------------------------------------------");
---------------------------------------------------------------------------
PrintR("TG_RioWbBridge-TC2-Step1");
---------------------------------------------------------------------------
-- REMARK: Change the address also...
for i in 0 to 15 loop
for j in 0 to 1 loop
rdsize := std_logic_vector(to_unsigned(i, 4));
if (j = 0) then
wdptr := '0';
else
wdptr:= '1';
end if;
CreateRandomPayload(ioData, seed1, seed2);
 
InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>FTYPE_REQUEST_CLASS,
sourceId=>x"dead", destId=>x"beef",
payload=>RioNread(rdsize=>"0000",
tid=>x"aa",
address=>"00000000000000000000000000000",
wdptr=>'0',
xamsbs=>"00")));
 
OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
sourceId=>x"beef", destId=>x"dead",
payload=>RioResponse(status=>"0000",
InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>FTYPE_REQUEST_CLASS,
sourceId=>x"dead", destId=>x"beef",
payload=>RioNread(rdsize=>rdsize,
tid=>x"aa",
dataLength=>1,
data=>ioData)));
address=>"00000000000000000000000000000",
wdptr=>wdptr,
xamsbs=>"00")));
 
SetSlaveAccess(false, "0000000000000000000000000000000", "00000001", 1, ioData);
OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
sourceId=>x"beef", destId=>x"dead",
payload=>RioResponse(status=>"0000",
tid=>x"aa",
dataLength=>getReadSize(rdsize, wdptr),
data=>ioData)));
 
TestWait(inboundEmpty, '1', "inbound frame");
TestWait(outboundEmpty, '1', "outbound frame");
TestWait(wbMessageEmpty, '1', "wishbone access");
SetSlaveAccess(false, "0000000000000000000000000000000",
getReadMask(rdsize, wdptr),
getReadSize(rdsize, wdptr),
ioData);
 
TestWait(inboundEmpty, '1', "inbound frame");
TestWait(outboundEmpty, '1', "outbound frame");
TestWait(wbMessageEmpty, '1', "wishbone access");
end loop;
end loop;
---------------------------------------------------------------------------
-- Test completed.
845,10 → 1019,17
-----------------------------------------------------------------------------
TestObject: RioWbBridge
generic map(
EXTENDED_ADDRESS=>0)
EXTENDED_ADDRESS=>0,
DEVICE_IDENTITY=>x"dead",
DEVICE_VENDOR_IDENTITY=>x"beef",
DEVICE_REV=>x"c0debabe",
ASSY_IDENTITY=>x"1111",
ASSY_VENDOR_IDENTITY=>x"2222",
ASSY_REV=>x"3333")
port map(
clk=>clk,
areset_n=>areset_n,
areset_n=>areset_n,
enable=>enable,
readFrameEmpty_i=>readFrameEmpty,
readFrame_o=>readFrame,
readContent_o=>readContent,
876,18 → 1057,21
TestPortPacketBufferInst: TestPortPacketBuffer
port map(
clk=>clk, areset_n=>areset_n,
outboundEmpty_o=>outboundEmpty,
outboundWrite_i=>outboundWrite,
outboundMessage_i=>outboundMessage,
outboundAck_o=>outboundAck,
inboundEmpty_o=>inboundEmpty,
inboundWrite_i=>inboundWrite,
inboundMessage_i=>inboundMessage,
inboundAck_o=>inboundAck,
readEmpty_o=>inboundEmpty,
readWrite_i=>inboundWrite,
readMessage_i=>inboundMessage,
readAck_o=>inboundAck,
writeEmpty_o=>outboundEmpty,
writeWrite_i=>outboundWrite,
writeMessage_i=>outboundMessage,
writeAck_o=>outboundAck,
readFrameEmpty_o=>readFrameEmpty,
readFrame_i=>readFrame,
readFrameRestart_i=>readFrameRestart,
readFrameAborted_o=>readFrameAborted,
readFrameRestart_i=>'0',
readFrameAborted_o=>readFrameAborted,
readWindowEmpty_o=>open,
readWindowReset_i=>'0',
readWindowNext_i=>readFrame,
readContentEmpty_o=>readContentEmpty,
readContent_i=>readContent,
readContentEnd_o=>readContentEnd,
/rio/branches/2.0.0-development/rtl/vhdl/RioWbBridge.vhd
66,6 → 66,7
port(
clk : in std_logic;
areset_n : in std_logic;
enable : in std_logic;
 
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
112,7 → 113,7
srcId_o : out std_logic_vector(31 downto 0);
tid_o : out std_logic_vector(7 downto 0);
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
length_o : out std_logic_vector(3 downto 0);
length_o : out std_logic_vector(4 downto 0);
select_o : out std_logic_vector(7 downto 0);
done_i : in std_logic;
140,11 → 141,11
srcId_o : out std_logic_vector(31 downto 0);
tid_o : out std_logic_vector(7 downto 0);
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
length_o : out std_logic_vector(3 downto 0);
length_o : out std_logic_vector(4 downto 0);
select_o : out std_logic_vector(7 downto 0);
payloadSetFirst_i : in std_logic;
payloadSetNext_i : in std_logic;
payload_o : out std_logic_vector(31 downto 0);
payloadRead_i : in std_logic;
payloadIndex_i : in std_logic_vector(4 downto 0);
payload_o : out std_logic_vector(63 downto 0);
done_i : in std_logic;
slaveCyc_i : in std_logic;
170,10 → 171,10
tid_i : in std_logic_vector(7 downto 0);
error_i : in std_logic;
payloadPresent_i : in std_logic;
payloadLength_i : in std_logic_vector(3 downto 0);
payloadLength_i : in std_logic_vector(4 downto 0);
payloadWrite_i : in std_logic;
payloadIndex_i : in std_logic_vector(3 downto 0);
payload_i : in std_logic_vector(31 downto 0);
payloadIndex_i : in std_logic_vector(4 downto 0);
payload_i : in std_logic_vector(63 downto 0);
done_o : out std_logic;
masterCyc_o : out std_logic;
212,6 → 213,70
slaveAck_o : out std_logic);
end component;
 
type StateType is (IDLE,
REQUEST_CLASS, REQUEST_CLASS_RESPONSE,
WRITE_CLASS, WRITE_CLASS_RESPONSE);
signal state : StateType;
signal adr : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
signal datOut : std_logic_vector(63 downto 0);
 
signal payloadUpdate : std_logic;
signal payloadIndex : std_logic_vector(4 downto 0);
signal requestReady : std_logic;
signal requestVc : std_logic;
signal requestCrf : std_logic;
signal requestPrio : std_logic_vector(1 downto 0);
signal requestTt : std_logic_vector(1 downto 0);
signal requestDstId : std_logic_vector(31 downto 0);
signal requestSrcId : std_logic_vector(31 downto 0);
signal requestTid : std_logic_vector(7 downto 0);
signal requestAddress : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
signal requestLength : std_logic_vector(4 downto 0);
signal requestSelect : std_logic_vector(7 downto 0);
signal requestDone : std_logic;
signal requestAck : std_logic;
 
signal writeReady : std_logic;
signal writeVc : std_logic;
signal writeCrf : std_logic;
signal writePrio : std_logic_vector(1 downto 0);
signal writeTt : std_logic_vector(1 downto 0);
signal writeDstId : std_logic_vector(31 downto 0);
signal writeSrcId : std_logic_vector(31 downto 0);
signal writeTid : std_logic_vector(7 downto 0);
signal writeAddress : std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
signal writeLength : std_logic_vector(4 downto 0);
signal writeSelect : std_logic_vector(7 downto 0);
signal writePayload : std_logic_vector(63 downto 0);
signal writeDone : std_logic;
signal writeAck : std_logic;
 
signal responseReady : std_logic;
signal responseVc : std_logic;
signal responseCrf : std_logic;
signal responsePrio : std_logic_vector(1 downto 0);
signal responseTt : std_logic_vector(1 downto 0);
signal responseDstId : std_logic_vector(31 downto 0);
signal responseSrcId : std_logic_vector(31 downto 0);
signal responseTid : std_logic_vector(7 downto 0);
signal responseError : std_logic;
signal responsePayloadPresent : std_logic;
signal responsePayload : std_logic_vector(63 downto 0);
signal responseDone : std_logic;
 
signal inboundCyc : std_logic;
signal inboundStb : std_logic;
signal inboundAdr : std_logic_vector(7 downto 0);
signal inboundDat : std_logic_vector(31 downto 0);
signal inboundAck : std_logic;
 
signal outboundCyc : std_logic;
signal outboundStb : std_logic;
signal outboundDat : std_logic_vector(31 downto 0);
signal outboundAck : std_logic;
-- signal configStb : std_logic;
-- signal configWe : std_logic;
-- signal configAdr : std_logic_vector(23 downto 0);
226,6 → 291,14
 
begin
 
responseVc <= requestVc when (responsePayloadPresent = '1') else writeVc;
responseCrf <= requestCrf when (responsePayloadPresent = '1') else writeCrf;
responsePrio <= requestPrio when (responsePayloadPresent = '1') else writePrio;
responseTt <= requestTt when (responsePayloadPresent = '1') else writeTt;
responseDstId <= requestSrcId when (responsePayloadPresent = '1') else writeSrcId;
responseSrcId <= requestDstId when (responsePayloadPresent = '1') else writeDstId;
responseTid <= requestTid when (responsePayloadPresent = '1') else writeTid;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
241,107 → 314,125
adr <= (others=>'0');
datOut <= (others=>'0');
 
responseReadReady <= '0';
responseWriteReady <= '0';
responsePayloadWrite <= '0';
 
payloadUpdate <= '0';
payloadIndex <= (others=>'0');
requestDone <= '0';
requestPayloadIndex <= (others=>'0');
writeDone <= '0';
responseReady <= '0';
responseError <= '0';
responsePayloadPresent <= '0';
responsePayload <= (others=>'0');
elsif (clk'event and clk = '1') then
requestDone <= '0';
responsePayloadWrite <= '0';
if (enable = '1') then
requestDone <= '0';
writeDone <= '0';
responseReady <= '0';
payloadUpdate <= '0';
if (payloadUpdate = '1') then
payloadIndex <= std_logic_vector(unsigned(payloadIndex) + 1);
end if;
case state is
when IDLE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (requestReady = '1') then
cyc_o <= '1';
stb_o <= '1';
we_o <= '0';
adr <= requestAddress;
sel_o <= requestSelect;
payloadIndex <= (others=>'0');
responsePayloadPresent <= '1';
state <= REQUEST_CLASS;
elsif (writeReady = '1') then
cyc_o <= '1';
stb_o <= '1';
we_o <= '1';
adr <= writeAddress;
sel_o <= writeSelect;
datOut <= writePayload;
 
if (responsePayloadWrite = '1') then
responsePayloadIndex <= std_logic_vector(unsigned(responsePayloadIndex) + 1);
end if;
case state is
when IDLE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (requestReady = '1') then
cyc_o <= '1';
stb_o <= '1';
we_o <= '0';
adr <= requestAddress;
responsePayloadPresent <= '1';
state <= REQUEST_CLASS;
elsif (writeReady = '1') then
cyc_o <= '1';
stb_o <= '1';
we_o <= '1';
adr <= writeAddress;
datOut <= writePayload;
writePayloadNext <= '1';
responsePayloadPresent <= '0';
state <= WRITE_CLASS;
end if;
payloadUpdate <= '1';
payloadIndex <= (others=>'0');
responsePayloadPresent <= '0';
state <= WRITE_CLASS;
end if;
 
when REQUEST_CLASS =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (ack_i = '1') then
responsePayloadWrite <= '1';
if (responsePayloadIndex /= requestPayloadLength) then
when REQUEST_CLASS =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (ack_i = '1') then
-- Note that responsePayloadIndex is updated after the write has been made.
payloadUpdate <= '1';
responsePayload <= dat_i;
adr <= std_logic_vector(unsigned(adr) + 1);
else
requestDone <= '1';
cyc_o <= '0';
stb_o <= '0';
state <= NREAD_RESPONSE;
end if;
 
if (payloadIndex = requestLength) then
requestDone <= '1';
cyc_o <= '0';
stb_o <= '0';
state <= REQUEST_CLASS_RESPONSE;
end if;
-- elsif(err_i = '1') then
-- REMARK: Implement error indication from wb-bus...
end if;
end if;
 
when REQUEST_CLASS_RESPONSE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (responseDone = '1') then
responseReadReady <= '0';
state <= IDLE;
else
responseReadReady <= '1';
end if;
when REQUEST_CLASS_RESPONSE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (responseDone = '1') then
responseReady <= '0';
state <= IDLE;
else
responseReady <= '1';
end if;
 
when WRITE_CLASS =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (ack_i = '1') then
responsePayloadWrite <= '1';
when WRITE_CLASS =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (ack_i = '1') then
payloadUpdate <= '1';
 
if (responsePayloadIndex /= requestPayloadLength) then
adr <= std_logic_vector(unsigned(configAdr) + 1);
datOut <= writePayload;
requestPayloadIndex <= std_logic_vector(unsigned(requestPayloadIndex) + 1);
adr <= std_logic_vector(unsigned(adr) + 1);
if (payloadIndex /= writeLength) then
datOut <= writePayload;
else
writeDone <= '1';
cyc_o <= '0';
stb_o <= '0';
state <= WRITE_CLASS_RESPONSE;
end if;
end if;
 
when WRITE_CLASS_RESPONSE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (writeDone = '1') then
responseReady <= '0';
state <= IDLE;
else
writeDone <= '1';
cyc_o <= '0';
stb_o <= '0';
state <= WRITE_CLASS_RESPONSE;
responseReady <= '1';
end if;
end if;
 
when WRITE_CLASS_RESPONSE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (responseDone = '1') then
responseWriteReady <= '0';
state <= IDLE;
else
responseWriteReady <= '1';
end if;
when others =>
 
when others =>
 
end case;
end case;
end if;
end if;
end process;
365,7 → 456,7
srcId_o=>requestSrcId,
tid_o=>requestTid,
address_o=>requestAddress,
length_o=>requestPayloadLength,
length_o=>requestLength,
select_o=>requestSelect,
done_i=>requestDone,
slaveCyc_i=>inboundCyc,
372,7 → 463,7
slaveStb_i=>inboundStb,
slaveAdr_i=>inboundAdr,
slaveDat_i=>inboundDat,
slaveAck_o=>inboundAck);
slaveAck_o=>requestAck);
 
WriteClassInboundInst: WriteClassInbound
generic map(
392,15 → 483,15
address_o=>writeAddress,
length_o=>writeLength,
select_o=>writeSelect,
payloadSetFirst_i=>writePayloadFirst,
payloadSetNext_i=>writePayloadNext,
payloadRead_i=>payloadUpdate,
payloadIndex_i=>payloadIndex,
payload_o=>writePayload,
done_i=>writeDone,
slaveCyc_i=>inboundCyc_i,
slaveStb_i=>inboundStb_i,
slaveAdr_i=>inboundAdr_i,
slaveDat_i=>inboundDat_i,
slaveAck_o=>inboundAck_o);
slaveCyc_i=>inboundCyc,
slaveStb_i=>inboundStb,
slaveAdr_i=>inboundAdr,
slaveDat_i=>inboundDat,
slaveAck_o=>writeAck);
 
ResponseClassOutboundInst: ResponseClassOutbound
port map(
408,18 → 499,18
areset_n=>areset_n,
enable=>enable,
ready_i=>responseReady,
vc_i=>vc,
crf_i=>crf,
prio_i=>prio,
tt_i=>tt,
dstid_i=>srcid,
srcid_i=>dstid,
tid_i=>tid,
vc_i=>responseVc,
crf_i=>responseCrf,
prio_i=>responsePrio,
tt_i=>responseTt,
dstid_i=>responseDstId,
srcid_i=>responseSrcId,
tid_i=>responseTid,
error_i=>responseError,
payloadPresent_i=>responsePayloadPresent,
payloadLength_i=>responsePayloadLength,
payloadWrite_i=>responsePayloadWrite,
payloadIndex_i=>responsePayloadIndex,
payloadLength_i=>requestLength,
payloadWrite_i=>payloadUpdate,
payloadIndex_i=>payloadIndex,
payload_i=>responsePayload,
done_o=>responseDone,
masterCyc_o=>outboundCyc,
426,7 → 517,8
masterStb_o=>outboundStb,
masterDat_o=>outboundDat,
masterAck_i=>outboundAck);
 
inboundAck <= requestAck or writeAck;
RioLogicalCommonInst: RioLogicalCommon
port map(
clk=>clk,
586,7 → 678,7
srcId_o : out std_logic_vector(31 downto 0);
tid_o : out std_logic_vector(7 downto 0);
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
length_o : out std_logic_vector(3 downto 0);
length_o : out std_logic_vector(4 downto 0);
select_o : out std_logic_vector(7 downto 0);
done_i : in std_logic;
622,20 → 714,24
RequestClass: process(clk, areset_n)
begin
if (areset_n = '0') then
state <= RECEIVE_PACKET;
rdsize <= (others=>'0');
wdptr <= '0';
slaveAck <= '0';
 
complete <= '0';
packetIndex <= 0;
vc_o <= '0';
crf_o <= '0';
prio_o <= "00";
tt_o <= "00";
dstId_o <= (others=>'0');
srcId_o <= (others=>'0');
tid_o <= (others=>'0');
address_o <= (others=>'0');
 
rdsize <= (others=>'0');
wdptr <= '0';
packetIndex <= 0;
elsif (clk'event and clk = '1') then
case state is
when RECEIVE_PACKET =>
684,8 → 780,8
-- There should be no more content in an NREAD.
-- Discard.
end case;
slaveAck <= '1';
end if;
slaveAck <= '1';
end if;
else
slaveAck <= '0';
723,7 → 819,7
process(clk, areset_n)
begin
if (areset_n = '0') then
length_o <= 0;
length_o <= "00000";
select_o <= (others=>'0');
elsif (clk'event and clk = '1') then
if (complete = '1') then
730,103 → 826,103
if (wdptr = '0') then
case rdsize is
when "0000" =>
length_o <= 0;
length_o <= "00000";
select_o <= "10000000";
when "0001" =>
length_o <= 0;
length_o <= "00000";
select_o <= "01000000";
when "0010" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00100000";
when "0011" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00010000";
when "0100" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11000000";
when "0101" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11100000";
when "0110" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00110000";
when "0111" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11111000";
when "1000" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11110000";
when "1001" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11111100";
when "1010" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11111110";
when "1011" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11111111";
when "1100" =>
length_o <= 3;
length_o <= "00011";
select_o <= "11111111";
when "1101" =>
length_o <= 11;
length_o <= "01011";
select_o <= "11111111";
when "1110" =>
length_o <= 19;
length_o <= "10011";
select_o <= "11111111";
when others =>
length_o <= 27;
length_o <= "11011";
select_o <= "11111111";
end case;
else
case rdsize is
when "0000" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00001000";
when "0001" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000100";
when "0010" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000010";
when "0011" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000001";
when "0100" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00001100";
when "0101" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000111";
when "0110" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000011";
when "0111" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00011111";
when "1000" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00001111";
when "1001" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00111111";
when "1010" =>
length_o <= 0;
length_o <= "00000";
select_o <= "01111111";
when "1011" =>
length_o <= 1;
length_o <= "00001";
select_o <= "11111111";
when "1100" =>
length_o <= 7;
length_o <= "00111";
select_o <= "11111111";
when "1101" =>
length_o <= 15;
length_o <= "01111";
select_o <= "11111111";
when "1110" =>
length_o <= 23;
length_o <= "10111";
select_o <= "11111111";
when others =>
length_o <= 31;
length_o <= "11111";
select_o <= "11111111";
end case;
end if;
867,11 → 963,11
srcId_o : out std_logic_vector(31 downto 0);
tid_o : out std_logic_vector(7 downto 0);
address_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
length_o : out std_logic_vector(3 downto 0);
length_o : out std_logic_vector(4 downto 0);
select_o : out std_logic_vector(7 downto 0);
payloadSetFirst_i : in std_logic;
payloadSetNext_i : in std_logic;
payload_o : out std_logic_vector(31 downto 0);
payloadRead_i : in std_logic;
payloadIndex_i : in std_logic_vector(4 downto 0);
payload_o : out std_logic_vector(63 downto 0);
done_i : in std_logic;
slaveCyc_i : in std_logic;
912,13 → 1008,14
signal complete : std_logic;
 
signal packetIndex : natural range 0 to 68;
signal requestData : std_logic_vector(31 downto 0);
 
signal payloadIndex : std_logic_vector(4 downto 0);
signal doubleWord : std_logic_vector(63 downto 16);
signal memoryWrite : std_logic;
signal memoryAddress : std_logic_vector(4 downto 0);
signal memoryDataIn : std_logic_vector(63 downto 0);
 
begin
 
slaveAck_o <= slaveAck;
928,26 → 1025,29
WriteClass: process(clk, areset_n)
begin
if (areset_n = '0') then
state <= RECEIVE_PACKET;
 
wdptr <= '0';
wrsize <= (others=>'0');
slaveAck <= '0';
 
complete <= '0';
packetIndex <= 0;
doubleWord <= (others=>'0');
 
memoryWrite <= '0';
memoryAddress <= (others=>'0');
memoryDataIn <= (others=>'0');
 
vc_o <= '0';
crf_o <= '0';
prio_o <= "00";
tt_o <= "00";
dstId_o <= (others=>'0');
srcId_o <= (others=>'0');
tid_o <= (others=>'0');
address_o <= (others=>'0');
wdptr <= '0';
wrsize <= (others=>'0');
packetIndex <= 0;
 
memoryWrite <= '0';
memoryAddress <= (others=>'0');
memoryDataIn <= (others=>'0');
elsif (clk'event and clk = '1') then
case state is
when RECEIVE_PACKET =>
1010,8 → 1110,8
-- There should be no more content in an NWRITE request.
-- Discard.
end case;
slaveAck <= '1';
end if;
slaveAck <= '1';
end if;
else
if (memoryWrite = '1') then
1055,7 → 1155,7
process(clk, areset_n)
begin
if (areset_n = '0') then
length_o <= 0;
length_o <= "00000";
select_o <= (others=>'0');
elsif (clk'event and clk = '1') then
if (complete = '1') then
1062,40 → 1162,40
if (wdptr = '0') then
case wrsize is
when "0000" =>
length_o <= 0;
length_o <= "00000";
select_o <= "10000000";
when "0001" =>
length_o <= 0;
length_o <= "00000";
select_o <= "01000000";
when "0010" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00100000";
when "0011" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00010000";
when "0100" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11000000";
when "0101" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11100000";
when "0110" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00110000";
when "0111" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11111000";
when "1000" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11110000";
when "1001" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11111100";
when "1010" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11111110";
when "1011" =>
length_o <= 0;
length_o <= "00000";
select_o <= "11111111";
when others =>
length_o <= memoryAddress;
1104,37 → 1204,37
else
case wrsize is
when "0000" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00001000";
when "0001" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000100";
when "0010" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000010";
when "0011" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000001";
when "0100" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00001100";
when "0101" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000111";
when "0110" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00000011";
when "0111" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00011111";
when "1000" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00001111";
when "1001" =>
length_o <= 0;
length_o <= "00000";
select_o <= "00111111";
when "1010" =>
length_o <= 0;
length_o <= "00000";
select_o <= "01111111";
when others =>
length_o <= memoryAddress;
1148,19 → 1248,7
-----------------------------------------------------------------------------
-- Payload content memory.
-----------------------------------------------------------------------------
process(clk, areset_n)
begin
if (areset_n = '0') then
payloadIndex <= (others=>'0');
elsif (clk'event and clk = '1') then
if (payloadSetFirst_i = '1') then
payloadIndex <= (others=>'0');
elsif (payloadSetNext_i = '1') then
payloadIndex <= std_logic_vector(unsigned(payloadIndex) + 1);
end if;
end if;
end process;
 
PayloadMemory: MemorySimpleDualPort
generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>64)
port map(clkA_i=>clk,
1168,8 → 1256,8
addressA_i=>memoryAddress,
dataA_i=>memoryDataIn,
clkB_i=>clk,
enableB_i=>enable,
addressB_i=>payloadIndex,
enableB_i=>payloadRead_i,
addressB_i=>payloadIndex_i,
dataB_o=>payload_o);
 
end architecture;
1203,10 → 1291,10
tid_i : in std_logic_vector(7 downto 0);
error_i : in std_logic;
payloadPresent_i : in std_logic;
payloadLength_i : in std_logic_vector(3 downto 0);
payloadLength_i : in std_logic_vector(4 downto 0);
payloadWrite_i : in std_logic;
payloadIndex_i : in std_logic_vector(3 downto 0);
payload_i : in std_logic_vector(31 downto 0);
payloadIndex_i : in std_logic_vector(4 downto 0);
payload_i : in std_logic_vector(63 downto 0);
done_o : out std_logic;
masterCyc_o : out std_logic;
1236,15 → 1324,16
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
 
type StateType is (WAIT_PACKET,
READ_RESPONSE, WRITE_RESPONSE,
signal header : std_logic_vector(31 downto 0);
type StateType is (WAIT_PACKET, SEND_RESPONSE,
WAIT_COMPLETE, RESPONSE_DONE);
signal state : StateType;
 
signal packetIndex : natural range 0 to 65;
signal header : std_logic_vector(31 downto 0);
signal payload : std_logic_vector(63 downto 0);
signal payloadIndex : std_logic_vector(4 downto 0);
signal packetIndex : natural range 0 to 68;
 
signal responsePayloadIndex : std_logic_vector(4 downto 0);
signal responsePayload : std_logic_vector(15 downto 0);
signal memoryEnable : std_logic;
signal memoryAddress : std_logic_vector(4 downto 0);
1257,16 → 1346,21
Response: process(clk, areset_n)
begin
if (areset_n = '0') then
masterCyc_o <= '0';
masterStb_o <= '0';
state <= WAIT_PACKET;
 
packetIndex <= 0;
 
responsePayloadIndex <= (others=>'0');
responsePayload <= (others=>'0');
memoryEnable <= '0';
memoryAddress <= (others=>'0');
 
payloadIndex <= (others=>'0');
done_o <= '0';
state <= WAIT_PACKET;
masterCyc_o <= '0';
masterStb_o <= '0';
masterDat_o <= (others=>'0');
elsif (clk'event and clk = '1') then
if (enable = '1') then
case state is
1277,14 → 1371,14
if (ready_i = '1') then
masterCyc_o <= '1';
masterStb_o <= '1';
masterDat_o <= responseHeader;
masterDat_o <= header;
packetIndex <= 1;
responsePayloadIndex <= (others=>'0');
 
memoryEnable <= '1';
memoryAddress <= (others=>'0');
 
payloadIndex <= (others=>'0');
state <= SEND_RESPONSE;
end if;
 
1326,13 → 1420,13
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 | 33 | 35 |
37 | 39 | 41 | 43 | 45 | 47 | 49 | 51 | 53 | 55 | 57 | 59 | 61 | 63 | 65 | 67 =>
-- double-wordN(15:0) & double-wordN(63:48)
masterDat_o <= responsePayload & memoryDataRead(31 downto 16);
masterDat_o <= responsePayload & memoryDataRead(63 downto 48);
packetIndex <= packetIndex + 1;
 
responsePayloadIndex <=
std_logic_vector(unsigned(responsePayloadIndex) + 1);
if (responsePayloadIndex = responsePayloadLength_i) then
if (responsePayloadIndex = payloadLength_i) then
state <= WAIT_COMPLETE;
else
packetIndex <= packetIndex + 1;
/rio/branches/2.0.0-development/rtl/vhdl/RioLogicalCommon.vhd
57,7 → 57,8
-- 16-bit deviceAddress support. All fields are right-justified.
-------------------------------------------------------------------------------
-- REMARK: Egress; Places packets in different queues depending on the packet priority?
-- REMARK: Do not use Wishbone, use request/grant scheme instead...
-- REMARK: Do not use Wishbone, use request/grant scheme instead?
-- REMARK: 8-bit deviceId has not been verified, fix.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
227,12 → 228,11
process(clk, areset_n)
begin
if (areset_n = '0') then
masterCyc_o <= '0';
masterStb_o <= '0';
state <= IDLE;
state <= IDLE;
packetPosition <= 0;
packetContent <= (others=>'0');
tt <= "00";
ftype <= "0000";
transaction <= "0000";
239,6 → 239,11
 
readContent_o <= '0';
readFrame_o <= '0';
 
masterCyc_o <= '0';
masterStb_o <= '0';
masterAdr_o <= (others=>'0');
masterDat_o <= (others=>'0');
elsif (clk'event and clk = '1') then
readContent_o <= '0';
readFrame_o <= '0';
357,7 → 362,7
readContent_o <= '1';
else
readFrame_o <= '1';
state <= END_PACKET;
state <= FORWARD_LAST;
end if;
end if;
 
482,44 → 487,69
HEADER_GET, HEADER_ACK,
DESTINATION_GET, DESTINATION_ACK,
SOURCE_GET, SOURCE_ACK,
CONTENT_GET, CONTENT_ACK,
CRC_APPEND, SEND_FRAME,
CONTENT_GET, CONTENT_ACK,
CRC_APPEND, CRC_UPDATE, CRC_LAST, SEND_FRAME,
RESTART_FRAME, WAIT_UPDATE);
signal state : StateType;
signal packetPosition : natural range 0 to 31;
signal halfWordPending : std_logic;
signal halfWord : std_logic_vector(15 downto 0);
signal packetPosition : natural range 0 to 69;
signal header : std_logic_vector(15 downto 0);
signal temp : std_logic_vector(15 downto 0);
signal tt : std_logic_vector(1 downto 0);
signal dstAddr : std_logic_vector(7 downto 0);
signal writeContentData : std_logic_vector(31 downto 0);
 
signal writeContent : std_logic;
signal writeContentData1 : std_logic_vector(31 downto 0);
signal writeContentData2 : std_logic_vector(31 downto 0);
 
signal crcReset : std_logic;
signal crc16Current, crc16Temp, crc16Next: std_logic_vector(15 downto 0);
 
begin
 
writeContentData_o <= writeContentData;
writeContent_o <= writeContent;
writeContentData_o <= writeContentData1;
 
process(clk, areset_n)
begin
if (areset_n = '0') then
crc16Current <= x"0000";
elsif (clk'event and clk = '1') then
if (crcReset = '1') then
crc16Current <= x"ffff";
elsif (writeContent = '1') then
crc16Current <= crc16Next;
end if;
end if;
end process;
process(clk, areset_n)
begin
if (areset_n = '0') then
state <= IDLE;
crc16Current <= x"0000";
packetPosition <= 0;
 
tt <= (others=>'0');
dstAddr <= (others=>'0');
 
temp <= (others=>'0');
writeContent <= '0';
writeContentData1 <= (others=>'0');
writeContentData2 <= (others=>'0');
crcReset <= '0';
slaveAck_o <= '0';
 
halfWordPending <= '0';
writeContent_o <= '0';
writeFrame_o <= '0';
writeFrameAbort_o <= '0';
writeContentData <= (others=>'0');
elsif (clk'event and clk = '1') then
writeContent_o <= '0';
writeContent <= '0';
writeFrame_o <= '0';
crcReset <= '0';
case state is
when IDLE =>
---------------------------------------------------------------------
526,8 → 556,8
--
---------------------------------------------------------------------
packetPosition <= 0;
crcReset <= '1';
if (writeFrameFull_i = '0') then
crc16Current <= x"ffff";
state <= HEADER_GET;
end if;
 
536,7 → 566,7
--
---------------------------------------------------------------------
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
header <= slaveDat_i(15 downto 0);
temp <= slaveDat_i(15 downto 0);
tt <= slaveDat_i(5 downto 4);
 
slaveAck_o <= '1';
558,14 → 588,10
---------------------------------------------------------------------
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
if (tt = "00") then
dstAddr <= slaveDat_i(7 downto 0);
elsif (tt = "01") then
writeContent_o <= '1';
writeContentData <= header & slaveDat_i(15 downto 0);
packetPosition <= packetPosition + 1;
if (tt = "01") then
writeContentData2 <= temp & slaveDat_i(15 downto 0);
else
-- REMARK: Not supported.
report "TT-field not supported." severity error;
end if;
slaveAck_o <= '1';
581,10 → 607,6
slaveAck_o <= '0';
state <= SOURCE_GET;
 
if (tt = "01") then
crc16Current <= crc16Next;
end if;
 
when SOURCE_GET =>
---------------------------------------------------------------------
--
591,16 → 613,8
---------------------------------------------------------------------
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
if (tt = "00") then
halfWordPending <= '0';
writeContent_o <= '1';
writeContentData <= header & dstAddr & slaveDat_i(7 downto 0);
packetPosition <= packetPosition + 1;
elsif (tt = "01") then
halfWordPending <= '1';
halfWord <= slaveDat_i(15 downto 0);
else
-- REMARK: Not supported.
if (tt = "01") then
temp <= slaveDat_i(15 downto 0);
end if;
slaveAck_o <= '1';
621,61 → 635,95
--
---------------------------------------------------------------------
if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then
if (halfWordPending = '0') then
writeContent_o <= '1';
writeContentData <= slaveDat_i;
packetPosition <= packetPosition + 1;
if (packetPosition < 19) then
if (tt = "01") then
writeContentData2 <= temp & slaveDat_i(31 downto 16);
temp <= slaveDat_i(15 downto 0);
slaveAck_o <= '1';
end if;
elsif (packetPosition = 19) then
if (tt = "01") then
writeContentData2 <= crc16Next & temp;
end if;
else
writeContent_o <= '1';
writeContentData <= halfWord & slaveDat_i(31 downto 16);
packetPosition <= packetPosition + 1;
halfWord <= slaveDat_i(15 downto 0);
if (tt = "01") then
writeContentData2 <= slaveDat_i;
slaveAck_o <= '1';
end if;
end if;
slaveAck_o <= '1';
writeContent <= '1';
writeContentData1 <= writeContentData2;
packetPosition <= packetPosition + 1;
state <= CONTENT_ACK;
else
state <= CRC_APPEND;
end if;
 
when CONTENT_ACK =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (packetPosition = 20) then
if (tt = "01") then
writeContentData2 <= crc16Next & temp;
end if;
end if;
slaveAck_o <= '0';
crc16Current <= crc16Next;
state <= CONTENT_GET;
 
if (packetPosition = 20) then
if (halfWordPending = '0') then
halfWordPending <= '1';
halfWord <= crc16Next;
else
writeContent_o <= '1';
writeContentData <= halfWord & crc16Next;
crc16Current <= crc16Next;
when CRC_APPEND =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (packetPosition < 19) then
if (tt = "01") then
writeContent <= '1';
writeContentData1 <= writeContentData2;
packetPosition <= packetPosition + 1;
halfWordPending <= '0';
halfWord <= crc16Next;
end if;
elsif (packetPosition = 19) then
if (tt = "01") then
writeContent <= '1';
writeContentData1 <= writeContentData2;
packetPosition <= packetPosition + 1;
end if;
else
if (tt = "01") then
writeContentData1 <= writeContentData2(31 downto 16) & x"0000";
packetPosition <= packetPosition + 1;
end if;
end if;
state <= CRC_UPDATE;
state <= CONTENT_GET;
when CRC_UPDATE =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
state <= CRC_LAST;
 
when CRC_APPEND =>
when CRC_LAST =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
if (tt = "00") then
writeContent_o <= '1';
writeContentData <= crc16Current & x"0000";
elsif (tt = "01") then
writeContent_o <= '1';
writeContentData <= crc16Current & x"0000";
if (packetPosition < 19) then
if (tt = "01") then
writeContent <= '1';
writeContentData1 <= crc16Current & x"0000";
end if;
elsif (packetPosition = 19) then
if (tt = "01") then
 
end if;
else
if (tt = "01") then
writeContent <= '1';
writeContentData1 <= writeContentData2(31 downto 16) & crc16Temp;
packetPosition <= packetPosition + 1;
end if;
end if;
 
state <= SEND_FRAME;
 
when SEND_FRAME =>
---------------------------------------------------------------------
--
711,9 → 759,9
 
Crc16High: Crc16CITT
port map(
d_i=>writeContentData(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
d_i=>writeContentData1(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
Crc16Low: Crc16CITT
port map(
d_i=>writeContentData(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
d_i=>writeContentData1(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
 
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.