OpenCores
URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 44 to Rev 45
    ↔ Reverse comparison
  •

Rev 44 → Rev 45

/trunk/rtl-model/defines.v
23,4 → 23,5
`define ADD_IP `IR_SIZE'bx__0__1__0__1__10_001_001__0__01__0__0_1111_xxxx_xxxx_1111_xx
`define OP_NOP 8'h90
 
`define DEBUG 1
`define DEBUG 1
//`define DEBUG_TRACE 1
/trunk/rtl-model/regfile.v
22,8 → 22,11
 
module regfile (
`ifdef DEBUG
output [15:0] r1,
output [15:0] r2,
output [15:0] ax,
output [15:0] dx,
output [15:0] bp,
output [15:0] si,
output [15:0] es,
`endif
 
output [15:0] a,
61,8 → 64,11
 
// Assignments
`ifdef DEBUG
assign r1 = r[1];
assign r2 = r[7];
assign ax = r[0];
assign dx = r[2];
assign bp = r[5];
assign si = r[6];
assign es = r[8];
`endif
assign a = (a_byte & ~addr_a[3]) ? { {8{a8[7]}}, a8} : r[addr_a];
assign a8 = addr_a[2] ? r[addr_a[1:0]][15:8] : r[addr_a][7:0];
/trunk/rtl-model/exec.v
26,8 → 26,16
output [15:0] x,
output [15:0] y,
output [15:0] aluo,
output [15:0] r1,
output [15:0] r2,
output [15:0] ax,
output [15:0] dx,
output [15:0] bp,
output [15:0] si,
output [15:0] es,
output [15:0] c,
output [ 3:0] addr_c,
output [15:0] omemalu,
output [ 3:0] addr_d,
output [ 8:0] flags,
`endif
input [`IR_SIZE-1:0] ir,
input [15:0] off,
54,9 → 62,16
);
 
// Net declarations
wire [15:0] a, b, c, s, alu_iflags, omemalu, bus_b;
`ifndef DEBUG
wire [15:0] c;
wire [15:0] omemalu;
wire [ 3:0] addr_c;
wire [ 3:0] addr_d;
wire [8:0] flags;
`endif
wire [15:0] a, b, s, alu_iflags, bus_b;
wire [31:0] aluout;
wire [3:0] addr_a, addr_b, addr_c, addr_d;
wire [3:0] addr_a, addr_b;
wire [2:0] t, func;
wire [1:0] addr_s;
wire wrfl, high, memalu, r_byte, c_byte;
64,7 → 79,7
wire wr_cnd;
wire jmp;
wire b_imm;
wire [8:0] flags, iflags, oflags;
wire [8:0] iflags, oflags;
wire [4:0] logic_flags;
wire alu_word;
wire a_byte;
77,7 → 92,7
alu_word, s, off, clk, dive);
regfile reg0 (
`ifdef DEBUG
r1, r2,
ax, dx, bp, si, es,
`endif
a, b, c, cs, ip, {aluout[31:16], omemalu}, s, flags, wr_reg, wrfl,
wr_high, clk, rst, addr_a, addr_b, addr_c, addr_d, addr_s, iflags,
/trunk/rtl-model/cpu.v
31,8 → 31,22
output [15:0] y,
output [15:0] imm,
output [15:0] aluo,
output [15:0] r1,
output [15:0] r2,
output [15:0] ax,
output [15:0] dx,
output [15:0] bp,
output [15:0] si,
output [15:0] es,
input dbg_block,
output [15:0] c,
output [ 3:0] addr_c,
output [15:0] cpu_dat_o,
output [15:0] d,
output [ 3:0] addr_d,
output byte_exec,
output [ 8:0] flags,
output end_seq,
output ext_int,
output cpu_block,
`endif
 
// Wishbone master interface
55,12 → 69,15
`ifndef DEBUG
wire [15:0] cs, ip;
wire [15:0] imm;
wire [15:0] cpu_dat_o;
wire byte_exec;
wire cpu_block;
`endif
wire [`IR_SIZE-1:0] ir;
wire [15:0] off;
 
wire [19:0] addr_exec, addr_fetch;
wire byte_fetch, byte_exec, fetch_or_exec;
wire byte_fetch, fetch_or_exec;
wire of, zf, cx_zero;
wire div_exc;
wire wr_ip0;
69,9 → 86,8
wire cpu_byte_o;
wire cpu_m_io;
wire [19:0] cpu_adr_o;
wire cpu_block;
wire wb_block;
wire [15:0] cpu_dat_i;
wire [15:0] cpu_dat_o;
wire cpu_we_o;
wire [15:0] iid_dat_i;
 
80,6 → 96,8
`ifdef DEBUG
.state (state),
.next_state (next_state),
.ext_int (ext_int),
.end_seq (end_seq),
`endif
.clk (wb_clk_i),
.rst (wb_rst_i),
101,7 → 119,8
 
.wr_ip0 (wr_ip0),
 
.intr (wb_tgc_i & ifl),
.intr (wb_tgc_i),
.ifl (ifl),
.inta (wb_tgc_o)
);
 
110,8 → 129,16
.x (x),
.y (y),
.aluo (aluo),
.r1 (r1),
.r2 (r2),
.ax (ax),
.dx (dx),
.bp (bp),
.si (si),
.es (es),
.c (c),
.addr_c (addr_c),
.omemalu (d),
.addr_d (addr_d),
.flags (flags),
`endif
.ir (ir),
.off (off),
141,7 → 168,7
.cpu_memop (ir[`MEM_OP]),
.cpu_m_io (cpu_m_io),
.cpu_adr_o (cpu_adr_o),
.cpu_block (cpu_block),
.cpu_block (wb_block),
.cpu_dat_i (cpu_dat_i),
.cpu_dat_o (cpu_dat_o),
.cpu_we_o (cpu_we_o),
166,6 → 193,9
 
`ifdef DEBUG
assign iralu = ir[28:23];
assign cpu_block = wb_block | dbg_block;
`else
assign cpu_block = wb_block;
`endif
endmodule
 
/trunk/rtl-model/fetch.v
24,6 → 24,8
`ifdef DEBUG
output reg [2:0] state,
output [2:0] next_state,
output ext_int,
output end_seq,
`endif
input clk,
input rst,
43,6 → 45,7
input div_exc,
output wr_ip0,
input intr,
input ifl,
output inta
);
 
54,13 → 57,15
parameter execu_st = 3'h4;
 
`ifndef DEBUG
reg [2:0] state;
wire [2:0] next_state;
reg [2:0] state;
wire end_seq;
wire ext_int;
`endif
 
wire [`IR_SIZE-1:0] rom_ir;
wire [7:0] opcode, modrm;
wire exec_st, end_seq;
wire exec_st;
wire [15:0] imm_d;
wire prefix, repz_pr, sovr_pr;
wire next_in_opco, next_in_exec;
70,17 → 75,17
reg [15:0] off_l, imm_l;
reg [1:0] pref_l;
reg [2:0] sop_l;
wire ext_int;
 
// Module instantiation
decode decode0(opcode, modrm, off_l, imm_l, pref_l[1], clk, rst, block,
exec_st, div_exc, need_modrm, need_off, need_imm, off_size,
imm_size, rom_ir, off, imm_d, end_seq, sop_l, intr, inta, ext_int, pref_l[1]);
imm_size, rom_ir, off, imm_d, end_seq, sop_l, intr, ifl,
inta, ext_int, pref_l[1]);
next_or_not nn0(pref_l, opcode[7:1], cx_zero, zf, ext_int, next_in_opco,
next_in_exec);
nstate ns0(state, prefix, need_modrm, need_off, need_imm, end_seq,
rom_ir[28:23], of, next_in_opco, next_in_exec, block, div_exc,
intr, next_state);
intr, ifl, next_state);
 
// Assignments
assign pc = (cs << 4) + ip;
178,6 → 183,7
input block,
input div_exc,
input intr,
input ifl,
output [2:0] next_state
);
 
189,12 → 195,13
parameter execu_st = 3'h4;
wire into, end_instr, end_into;
wire [2:0] n_state;
wire ext_int;
wire intr_ifl;
 
// Assignments
assign into = (ftype==6'b111_010);
assign end_into = into ? ~of : end_seq;
assign end_instr = !div_exc && !intr && end_into && !next_in_exec;
assign end_instr = !div_exc && !intr_ifl && end_into && !next_in_exec;
assign intr_ifl = intr & ifl;
 
assign n_state = (state == opcod_st) ? (prefix ? opcod_st
: (next_in_opco ? opcod_st
263,6 → 270,7
input [2:0] sop_l,
 
input intr,
input ifl,
output reg inta,
output reg ext_int,
input repz_pr
305,7 → 313,7
always @(posedge clk)
if (rst) ext_int <= 1'b0;
else ext_int <= block ? ext_int
: ((intr && exec_st && end_seq) ? 1'b1
: ((intr & ifl & exec_st & end_seq) ? 1'b1
: (ext_int ? !end_seq : 1'b0));
 
// inta
339,7 → 347,6
wire [1:0] mod;
wire [2:0] regm;
wire [2:0] rm;
wire sw;
wire d, b, sm, dm;
wire off_size_mod, need_off_mod;
wire [2:0] srcm, dstm;
360,13 → 367,12
assign b = ~op[0];
assign off_size_mod = (base == 4'b1100 && index == 4'b1100) ? 1'b1 : mod[1];
assign need_off_mod = (base == 4'b1100 && index == 4'b1100) || ^mod;
assign sw = op[0] ~^ op[1];
assign off_size_from_mod = !op[7] | (!op[5] & !op[4]) | (op[6] & op[4]);
assign off_size = !off_size_from_mod | off_size_mod;
 
// Behaviour
always @(op or dm or b or need_off_mod or srcm or sm or dstm
or mod or rm or regm or rep or sw or modrm)
or mod or rm or regm or rep or modrm)
casex (op)
8'b0000_000x: // add r->r, r->m
begin
791,7 → 797,7
need_modrm <= 1'b1;
need_off <= need_off_mod;
need_imm <= 1'b1;
imm_size <= !sw;
imm_size <= !op[1] & op[0];
dst <= { 1'b0, modrm[2:0] };
src <= 4'b0;
end
/trunk/impl/virtex4-ml403ep/test/base.cpj
1,6 → 1,6
#ChipScope Pro Analyzer Project File, Version 3.0
#Fri Nov 07 17:28:21 GMT+01:00 2008
device.2.configFileDir=/home/zeus/zet/impl/virtex4-ml403ep/ise-kotku
#Sat Feb 28 19:48:19 GMT+01:00 2009
device.2.configFileDir=/home/zeus/tmp
device.2.configFilename=kotku_ml403.bit
deviceChain.deviceName0=System_ACE_CF
deviceChain.deviceName1=XCF32P
15,8 → 15,8
deviceChain.name2=MyDevice2
deviceChain.name3=MyDevice3
deviceIds=0a001093f505909321e5809359608093
mdiAreaHeight=0.7047872340425532
mdiAreaHeightLast=0.8218085106382979
mdiAreaHeight=0.7659574468085106
mdiAreaHeightLast=0.7659574468085106
mdiCount=2
mdiDevice0=2
mdiDevice1=2
25,24 → 25,24
mdiUnit0=0
mdiUnit1=0
navigatorHeight=0.4295212765957447
navigatorHeightLast=0.16356382978723405
navigatorWidth=0.14155629139072848
navigatorWidthLast=0.271523178807947
navigatorHeightLast=0.1595744680851064
navigatorWidth=0.09765625
navigatorWidthLast=0.1515625
unit.-1.-1.username=
unit.1.-1.username=
unit.2.-1.username=
unit.2.0.0.HEIGHT0=0.83111954
unit.2.0.0.HEIGHT0=0.91797554
unit.2.0.0.TriggerRow0=1
unit.2.0.0.TriggerRow1=1
unit.2.0.0.TriggerRow2=1
unit.2.0.0.WIDTH0=0.64630544
unit.2.0.0.X0=0.10640394
unit.2.0.0.Y0=0.032258064
unit.2.0.0.WIDTH0=0.8658429
unit.2.0.0.X0=0.0
unit.2.0.0.Y0=0.0
unit.2.0.1.HEIGHT1=1.0
unit.2.0.1.WIDTH1=1.0
unit.2.0.1.X1=0.0
unit.2.0.1.Y1=0.0
unit.2.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXX
unit.2.0.MFBitsA0=00110101110111001000
unit.2.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unit.2.0.MFBitsA10=XXXXXXXXXXXXXXXXXXXXX
unit.2.0.MFBitsA11=XXXXXXXXXXXXXXXX
49,12 → 49,12
unit.2.0.MFBitsA12=XXXXXXXXX
unit.2.0.MFBitsA13=XXX
unit.2.0.MFBitsA14=XXXXX
unit.2.0.MFBitsA15=10111111100000001000000000000000
unit.2.0.MFBitsA2=11000010100011100100
unit.2.0.MFBitsA3=XXXXXX
unit.2.0.MFBitsA15=01001011111111111001100110000000
unit.2.0.MFBitsA2=00110101110111001000
unit.2.0.MFBitsA3=X1XX1X
unit.2.0.MFBitsA4=XXXXXX
unit.2.0.MFBitsA5=XXXXXX
unit.2.0.MFBitsA6=XXXXXXXXXXXXXXXX
unit.2.0.MFBitsA5=XXX000
unit.2.0.MFBitsA6=XXXXXXXXXXX1XXXX
unit.2.0.MFBitsA7=XXXXXXXXXXXXXXXX
unit.2.0.MFBitsA8=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unit.2.0.MFBitsA9=XXXXXXXXXXXXXXXX
81,7 → 81,7
unit.2.0.MFCompareA12=0
unit.2.0.MFCompareA13=0
unit.2.0.MFCompareA14=0
unit.2.0.MFCompareA15=0
unit.2.0.MFCompareA15=2
unit.2.0.MFCompareA2=0
unit.2.0.MFCompareA3=0
unit.2.0.MFCompareA4=0
107,7 → 107,7
unit.2.0.MFCompareB8=999
unit.2.0.MFCompareB9=999
unit.2.0.MFCount=16
unit.2.0.MFDisplay0=0
unit.2.0.MFDisplay0=1
unit.2.0.MFDisplay1=1
unit.2.0.MFDisplay10=1
unit.2.0.MFDisplay11=0
120,7 → 120,7
unit.2.0.MFDisplay4=0
unit.2.0.MFDisplay5=0
unit.2.0.MFDisplay6=0
unit.2.0.MFDisplay7=0
unit.2.0.MFDisplay7=1
unit.2.0.MFDisplay8=0
unit.2.0.MFDisplay9=0
unit.2.0.MFEventType0=3
155,11 → 155,20
unit.2.0.TCOutputHigh0=1
unit.2.0.TCOutputMode0=0
unit.2.0.browser_tree_state<Data\ Port>=1
unit.2.0.browser_tree_state<addr_c>=1
unit.2.0.browser_tree_state<addr_d>=0
unit.2.0.browser_tree_state<adr>=0
unit.2.0.browser_tree_state<ax>=0
unit.2.0.browser_tree_state<bp>=0
unit.2.0.browser_tree_state<c>=0
unit.2.0.browser_tree_state<cnt>=0
unit.2.0.browser_tree_state<d>=0
unit.2.0.browser_tree_state<dat_i>=0
unit.2.0.browser_tree_state<dat_o>=0
unit.2.0.browser_tree_state<di>=1
unit.2.0.browser_tree_state<ds>=0
unit.2.0.browser_tree_state<dx>=0
unit.2.0.browser_tree_state<es>=0
unit.2.0.browser_tree_state<func>=0
unit.2.0.browser_tree_state<io_reg>=0
unit.2.0.browser_tree_state<next_state>=0
166,7 → 175,7
unit.2.0.browser_tree_state<pc>=0
unit.2.0.browser_tree_state<s_addr_>=0
unit.2.0.browser_tree_state<sp>=1
unit.2.0.browser_tree_state<state>=1
unit.2.0.browser_tree_state<state>=0
unit.2.0.browser_tree_state<x>=0
unit.2.0.browser_tree_state<y>=0
unit.2.0.coretype=ILA
189,8 → 198,8
unit.2.0.export.format=2
unit.2.0.export.signals=Waveform Signals/Buses
unit.2.0.export.unitName=DEV\:2 MyDevice2 (XC4VFX12) UNIT\:0 MyILA0 (ILA)
unit.2.0.port.-1.b.0.alias=adr
unit.2.0.port.-1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
unit.2.0.port.-1.b.0.alias=addr_d
unit.2.0.port.-1.b.0.channellist=90 91 92 93
unit.2.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.0.name=DataPort
unit.2.0.port.-1.b.0.orderindex=-1
203,8 → 212,8
unit.2.0.port.-1.b.0.unsignedPrecision=0
unit.2.0.port.-1.b.0.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.0.visible=1
unit.2.0.port.-1.b.1.alias=aluo
unit.2.0.port.-1.b.1.channellist=154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169
unit.2.0.port.-1.b.1.alias=adr
unit.2.0.port.-1.b.1.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
unit.2.0.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.1.name=DataPort
unit.2.0.port.-1.b.1.orderindex=-1
233,7 → 242,7
unit.2.0.port.-1.b.10.visible=1
unit.2.0.port.-1.b.11.alias=pc
unit.2.0.port.-1.b.11.channellist=52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
unit.2.0.port.-1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.11.color=java.awt.Color[r\=204,g\=0,b\=51]
unit.2.0.port.-1.b.11.name=DataPort
unit.2.0.port.-1.b.11.orderindex=-1
unit.2.0.port.-1.b.11.radix=Hex
247,7 → 256,7
unit.2.0.port.-1.b.11.visible=1
unit.2.0.port.-1.b.12.alias=state
unit.2.0.port.-1.b.12.channellist=87 88 89
unit.2.0.port.-1.b.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.12.color=java.awt.Color[r\=0,g\=51,b\=204]
unit.2.0.port.-1.b.12.name=DataPort
unit.2.0.port.-1.b.12.orderindex=-1
unit.2.0.port.-1.b.12.radix=Hex
343,8 → 352,22
unit.2.0.port.-1.b.18.unsignedPrecision=0
unit.2.0.port.-1.b.18.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.18.visible=1
unit.2.0.port.-1.b.2.alias=cnt
unit.2.0.port.-1.b.2.channellist=216 217 218
unit.2.0.port.-1.b.19.alias=y
unit.2.0.port.-1.b.19.channellist=122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137
unit.2.0.port.-1.b.19.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.19.name=DataPort
unit.2.0.port.-1.b.19.orderindex=-1
unit.2.0.port.-1.b.19.radix=Hex
unit.2.0.port.-1.b.19.signedOffset=0.0
unit.2.0.port.-1.b.19.signedPrecision=0
unit.2.0.port.-1.b.19.signedScaleFactor=1.0
unit.2.0.port.-1.b.19.tokencount=0
unit.2.0.port.-1.b.19.unsignedOffset=0.0
unit.2.0.port.-1.b.19.unsignedPrecision=0
unit.2.0.port.-1.b.19.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.19.visible=1
unit.2.0.port.-1.b.2.alias=aluo
unit.2.0.port.-1.b.2.channellist=154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169
unit.2.0.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.2.name=DataPort
unit.2.0.port.-1.b.2.orderindex=-1
357,8 → 380,8
unit.2.0.port.-1.b.2.unsignedPrecision=0
unit.2.0.port.-1.b.2.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.2.visible=1
unit.2.0.port.-1.b.3.alias=cx
unit.2.0.port.-1.b.3.channellist=240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
unit.2.0.port.-1.b.3.alias=cnt
unit.2.0.port.-1.b.3.channellist=216 217 218
unit.2.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.3.name=DataPort
unit.2.0.port.-1.b.3.orderindex=-1
371,8 → 394,8
unit.2.0.port.-1.b.3.unsignedPrecision=0
unit.2.0.port.-1.b.3.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.3.visible=1
unit.2.0.port.-1.b.4.alias=dat_i
unit.2.0.port.-1.b.4.channellist=20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
unit.2.0.port.-1.b.4.alias=cnt_time
unit.2.0.port.-1.b.4.channellist=224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
unit.2.0.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.4.name=DataPort
unit.2.0.port.-1.b.4.orderindex=-1
385,8 → 408,8
unit.2.0.port.-1.b.4.unsignedPrecision=0
unit.2.0.port.-1.b.4.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.4.visible=1
unit.2.0.port.-1.b.5.alias=dat_o
unit.2.0.port.-1.b.5.channellist=36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
unit.2.0.port.-1.b.5.alias=d
unit.2.0.port.-1.b.5.channellist=106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
unit.2.0.port.-1.b.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.5.name=DataPort
unit.2.0.port.-1.b.5.orderindex=-1
399,8 → 422,8
unit.2.0.port.-1.b.5.unsignedPrecision=0
unit.2.0.port.-1.b.5.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.5.visible=1
unit.2.0.port.-1.b.6.alias=di
unit.2.0.port.-1.b.6.channellist=224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239
unit.2.0.port.-1.b.6.alias=dat_i
unit.2.0.port.-1.b.6.channellist=20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
unit.2.0.port.-1.b.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.6.name=DataPort
unit.2.0.port.-1.b.6.orderindex=-1
413,8 → 436,8
unit.2.0.port.-1.b.6.unsignedPrecision=0
unit.2.0.port.-1.b.6.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.6.visible=1
unit.2.0.port.-1.b.7.alias=func
unit.2.0.port.-1.b.7.channellist=81 82 83
unit.2.0.port.-1.b.7.alias=dat_o
unit.2.0.port.-1.b.7.channellist=36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
unit.2.0.port.-1.b.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.7.name=DataPort
unit.2.0.port.-1.b.7.orderindex=-1
427,8 → 450,8
unit.2.0.port.-1.b.7.unsignedPrecision=0
unit.2.0.port.-1.b.7.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.7.visible=1
unit.2.0.port.-1.b.8.alias=imm
unit.2.0.port.-1.b.8.channellist=116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131
unit.2.0.port.-1.b.8.alias=flags
unit.2.0.port.-1.b.8.channellist=95 96 97 98 99 100 101 102 103
unit.2.0.port.-1.b.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.8.name=DataPort
unit.2.0.port.-1.b.8.orderindex=-1
441,8 → 464,8
unit.2.0.port.-1.b.8.unsignedPrecision=0
unit.2.0.port.-1.b.8.unsignedScaleFactor=1.0
unit.2.0.port.-1.b.8.visible=1
unit.2.0.port.-1.b.9.alias=io_reg
unit.2.0.port.-1.b.9.channellist=90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
unit.2.0.port.-1.b.9.alias=func
unit.2.0.port.-1.b.9.channellist=81 82 83
unit.2.0.port.-1.b.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.b.9.name=DataPort
unit.2.0.port.-1.b.9.orderindex=-1
492,12 → 515,12
unit.2.0.port.-1.s.103.name=DataPort[103]
unit.2.0.port.-1.s.103.orderindex=-1
unit.2.0.port.-1.s.103.visible=1
unit.2.0.port.-1.s.104.alias=
unit.2.0.port.-1.s.104.alias=inta
unit.2.0.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.104.name=DataPort[104]
unit.2.0.port.-1.s.104.orderindex=-1
unit.2.0.port.-1.s.104.visible=1
unit.2.0.port.-1.s.105.alias=
unit.2.0.port.-1.s.105.alias=intr
unit.2.0.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.105.name=DataPort[105]
unit.2.0.port.-1.s.105.orderindex=-1
1157,27 → 1180,27
unit.2.0.port.-1.s.223.name=DataPort[223]
unit.2.0.port.-1.s.223.orderindex=-1
unit.2.0.port.-1.s.223.visible=1
unit.2.0.port.-1.s.224.alias=
unit.2.0.port.-1.s.224.alias=cnt_time0
unit.2.0.port.-1.s.224.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.224.name=DataPort[224]
unit.2.0.port.-1.s.224.orderindex=-1
unit.2.0.port.-1.s.224.visible=1
unit.2.0.port.-1.s.225.alias=
unit.2.0.port.-1.s.225.alias=cnt_time1
unit.2.0.port.-1.s.225.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.225.name=DataPort[225]
unit.2.0.port.-1.s.225.orderindex=-1
unit.2.0.port.-1.s.225.visible=1
unit.2.0.port.-1.s.226.alias=
unit.2.0.port.-1.s.226.alias=cnt_time2
unit.2.0.port.-1.s.226.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.226.name=DataPort[226]
unit.2.0.port.-1.s.226.orderindex=-1
unit.2.0.port.-1.s.226.visible=1
unit.2.0.port.-1.s.227.alias=
unit.2.0.port.-1.s.227.alias=cnt_time3
unit.2.0.port.-1.s.227.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.227.name=DataPort[227]
unit.2.0.port.-1.s.227.orderindex=-1
unit.2.0.port.-1.s.227.visible=1
unit.2.0.port.-1.s.228.alias=
unit.2.0.port.-1.s.228.alias=cnt_time4
unit.2.0.port.-1.s.228.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.228.name=DataPort[228]
unit.2.0.port.-1.s.228.orderindex=-1
1707,7 → 1730,7
unit.2.0.port.-1.s.93.name=DataPort[93]
unit.2.0.port.-1.s.93.orderindex=-1
unit.2.0.port.-1.s.93.visible=1
unit.2.0.port.-1.s.94.alias=
unit.2.0.port.-1.s.94.alias=byte_op
unit.2.0.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.-1.s.94.name=DataPort[94]
unit.2.0.port.-1.s.94.orderindex=-1
2387,12 → 2410,12
unit.2.0.port.15.b.0.visible=1
unit.2.0.port.15.buscount=1
unit.2.0.port.15.channelcount=32
unit.2.0.port.15.s.0.alias=
unit.2.0.port.15.s.0.alias=cnt_time0
unit.2.0.port.15.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.15.s.0.name=TriggerPort15[0]
unit.2.0.port.15.s.0.orderindex=-1
unit.2.0.port.15.s.0.visible=1
unit.2.0.port.15.s.1.alias=
unit.2.0.port.15.s.1.alias=cnt_time1
unit.2.0.port.15.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.15.s.1.name=TriggerPort15[1]
unit.2.0.port.15.s.1.orderindex=-1
2447,7 → 2470,7
unit.2.0.port.15.s.19.name=TriggerPort15[19]
unit.2.0.port.15.s.19.orderindex=-1
unit.2.0.port.15.s.19.visible=1
unit.2.0.port.15.s.2.alias=
unit.2.0.port.15.s.2.alias=cnt_time2
unit.2.0.port.15.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.15.s.2.name=TriggerPort15[2]
unit.2.0.port.15.s.2.orderindex=-1
2502,7 → 2525,7
unit.2.0.port.15.s.29.name=TriggerPort15[29]
unit.2.0.port.15.s.29.orderindex=-1
unit.2.0.port.15.s.29.visible=1
unit.2.0.port.15.s.3.alias=
unit.2.0.port.15.s.3.alias=cnt_time3
unit.2.0.port.15.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.15.s.3.name=TriggerPort15[3]
unit.2.0.port.15.s.3.orderindex=-1
2517,12 → 2540,12
unit.2.0.port.15.s.31.name=TriggerPort15[31]
unit.2.0.port.15.s.31.orderindex=-1
unit.2.0.port.15.s.31.visible=1
unit.2.0.port.15.s.4.alias=
unit.2.0.port.15.s.4.alias=cnt_time4
unit.2.0.port.15.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.15.s.4.name=TriggerPort15[4]
unit.2.0.port.15.s.4.orderindex=-1
unit.2.0.port.15.s.4.visible=1
unit.2.0.port.15.s.5.alias=
unit.2.0.port.15.s.5.alias=DataPort[229]
unit.2.0.port.15.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.15.s.5.name=TriggerPort15[5]
unit.2.0.port.15.s.5.orderindex=-1
2892,12 → 2915,12
unit.2.0.port.6.s.13.name=TriggerPort6[13]
unit.2.0.port.6.s.13.orderindex=-1
unit.2.0.port.6.s.13.visible=1
unit.2.0.port.6.s.14.alias=
unit.2.0.port.6.s.14.alias=inta
unit.2.0.port.6.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.6.s.14.name=TriggerPort6[14]
unit.2.0.port.6.s.14.orderindex=-1
unit.2.0.port.6.s.14.visible=1
unit.2.0.port.6.s.15.alias=
unit.2.0.port.6.s.15.alias=intr
unit.2.0.port.6.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.6.s.15.name=TriggerPort6[15]
unit.2.0.port.6.s.15.orderindex=-1
2912,12 → 2935,12
unit.2.0.port.6.s.3.name=TriggerPort6[3]
unit.2.0.port.6.s.3.orderindex=-1
unit.2.0.port.6.s.3.visible=1
unit.2.0.port.6.s.4.alias=
unit.2.0.port.6.s.4.alias=byte_op
unit.2.0.port.6.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.6.s.4.name=TriggerPort6[4]
unit.2.0.port.6.s.4.orderindex=-1
unit.2.0.port.6.s.4.visible=1
unit.2.0.port.6.s.5.alias=
unit.2.0.port.6.s.5.alias=DataPort[95]
unit.2.0.port.6.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.6.s.5.name=TriggerPort6[5]
unit.2.0.port.6.s.5.orderindex=-1
2957,7 → 2980,7
unit.2.0.port.7.b.0.visible=1
unit.2.0.port.7.buscount=1
unit.2.0.port.7.channelcount=16
unit.2.0.port.7.s.0.alias=
unit.2.0.port.7.s.0.alias=DataPort[106]
unit.2.0.port.7.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.2.0.port.7.s.0.name=TriggerPort7[0]
unit.2.0.port.7.s.0.orderindex=-1
3396,7 → 3419,7
unit.2.0.triggerWindowDepth=1024
unit.2.0.triggerWindowTS=0
unit.2.0.username=MyILA0
unit.2.0.waveform.count=35
unit.2.0.waveform.count=38
unit.2.0.waveform.posn.0.channel=2147483646
unit.2.0.waveform.posn.0.name=aluo
unit.2.0.waveform.posn.0.radix=1
3406,7 → 3429,7
unit.2.0.waveform.posn.1.radix=1
unit.2.0.waveform.posn.1.type=bus
unit.2.0.waveform.posn.10.channel=2147483646
unit.2.0.waveform.posn.10.name=dat_o
unit.2.0.waveform.posn.10.name=dat_i
unit.2.0.waveform.posn.10.radix=1
unit.2.0.waveform.posn.10.type=bus
unit.2.0.waveform.posn.100.channel=2147483646
3450,7 → 3473,7
unit.2.0.waveform.posn.109.radix=1
unit.2.0.waveform.posn.109.type=bus
unit.2.0.waveform.posn.11.channel=2147483646
unit.2.0.waveform.posn.11.name=imm
unit.2.0.waveform.posn.11.name=dat_o
unit.2.0.waveform.posn.11.radix=1
unit.2.0.waveform.posn.11.type=bus
unit.2.0.waveform.posn.110.channel=2147483646
3493,10 → 3516,10
unit.2.0.waveform.posn.119.name=adr
unit.2.0.waveform.posn.119.radix=1
unit.2.0.waveform.posn.119.type=bus
unit.2.0.waveform.posn.12.channel=2147483646
unit.2.0.waveform.posn.12.name=pc
unit.2.0.waveform.posn.12.channel=72
unit.2.0.waveform.posn.12.name=ack
unit.2.0.waveform.posn.12.radix=1
unit.2.0.waveform.posn.12.type=bus
unit.2.0.waveform.posn.12.type=signal
unit.2.0.waveform.posn.120.channel=2147483646
unit.2.0.waveform.posn.120.name=adr
unit.2.0.waveform.posn.120.radix=1
3537,8 → 3560,8
unit.2.0.waveform.posn.129.name=adr
unit.2.0.waveform.posn.129.radix=1
unit.2.0.waveform.posn.129.type=bus
unit.2.0.waveform.posn.13.channel=72
unit.2.0.waveform.posn.13.name=ack
unit.2.0.waveform.posn.13.channel=73
unit.2.0.waveform.posn.13.name=stb
unit.2.0.waveform.posn.13.radix=1
unit.2.0.waveform.posn.13.type=signal
unit.2.0.waveform.posn.130.channel=2147483646
3545,28 → 3568,28
unit.2.0.waveform.posn.130.name=adr
unit.2.0.waveform.posn.130.radix=1
unit.2.0.waveform.posn.130.type=bus
unit.2.0.waveform.posn.14.channel=73
unit.2.0.waveform.posn.14.name=stb
unit.2.0.waveform.posn.14.channel=74
unit.2.0.waveform.posn.14.name=cyc
unit.2.0.waveform.posn.14.radix=1
unit.2.0.waveform.posn.14.type=signal
unit.2.0.waveform.posn.15.channel=74
unit.2.0.waveform.posn.15.name=cyc
unit.2.0.waveform.posn.15.channel=75
unit.2.0.waveform.posn.15.name=tga
unit.2.0.waveform.posn.15.radix=1
unit.2.0.waveform.posn.15.type=signal
unit.2.0.waveform.posn.16.channel=75
unit.2.0.waveform.posn.16.name=tga
unit.2.0.waveform.posn.16.channel=76
unit.2.0.waveform.posn.16.name=we
unit.2.0.waveform.posn.16.radix=1
unit.2.0.waveform.posn.16.type=signal
unit.2.0.waveform.posn.17.channel=76
unit.2.0.waveform.posn.17.name=we
unit.2.0.waveform.posn.17.channel=77
unit.2.0.waveform.posn.17.name=clk
unit.2.0.waveform.posn.17.radix=1
unit.2.0.waveform.posn.17.type=signal
unit.2.0.waveform.posn.18.channel=77
unit.2.0.waveform.posn.18.name=clk
unit.2.0.waveform.posn.18.channel=207
unit.2.0.waveform.posn.18.name=flash_ce2_
unit.2.0.waveform.posn.18.radix=1
unit.2.0.waveform.posn.18.type=signal
unit.2.0.waveform.posn.19.channel=207
unit.2.0.waveform.posn.19.name=flash_ce2_
unit.2.0.waveform.posn.19.channel=208
unit.2.0.waveform.posn.19.name=sram_adv_
unit.2.0.waveform.posn.19.radix=1
unit.2.0.waveform.posn.19.type=signal
unit.2.0.waveform.posn.2.channel=2147483646
3573,98 → 3596,98
unit.2.0.waveform.posn.2.name=y
unit.2.0.waveform.posn.2.radix=1
unit.2.0.waveform.posn.2.type=bus
unit.2.0.waveform.posn.20.channel=208
unit.2.0.waveform.posn.20.name=sram_adv_
unit.2.0.waveform.posn.20.channel=209
unit.2.0.waveform.posn.20.name=sram_cen_
unit.2.0.waveform.posn.20.radix=1
unit.2.0.waveform.posn.20.type=signal
unit.2.0.waveform.posn.21.channel=209
unit.2.0.waveform.posn.21.name=sram_cen_
unit.2.0.waveform.posn.21.channel=214
unit.2.0.waveform.posn.21.name=sf_we_
unit.2.0.waveform.posn.21.radix=1
unit.2.0.waveform.posn.21.type=signal
unit.2.0.waveform.posn.22.channel=214
unit.2.0.waveform.posn.22.name=sf_we_
unit.2.0.waveform.posn.22.channel=215
unit.2.0.waveform.posn.22.name=sf_oe_
unit.2.0.waveform.posn.22.radix=1
unit.2.0.waveform.posn.22.type=signal
unit.2.0.waveform.posn.23.channel=215
unit.2.0.waveform.posn.23.name=sf_oe_
unit.2.0.waveform.posn.23.channel=2147483646
unit.2.0.waveform.posn.23.name=s_bw_
unit.2.0.waveform.posn.23.radix=1
unit.2.0.waveform.posn.23.type=signal
unit.2.0.waveform.posn.23.type=bus
unit.2.0.waveform.posn.24.channel=2147483646
unit.2.0.waveform.posn.24.name=s_bw_
unit.2.0.waveform.posn.24.name=s_data_
unit.2.0.waveform.posn.24.radix=1
unit.2.0.waveform.posn.24.type=bus
unit.2.0.waveform.posn.25.channel=2147483646
unit.2.0.waveform.posn.25.name=s_data_
unit.2.0.waveform.posn.25.name=s_addr_
unit.2.0.waveform.posn.25.radix=1
unit.2.0.waveform.posn.25.type=bus
unit.2.0.waveform.posn.26.channel=2147483646
unit.2.0.waveform.posn.26.name=s_addr_
unit.2.0.waveform.posn.26.name=cnt
unit.2.0.waveform.posn.26.radix=1
unit.2.0.waveform.posn.26.type=bus
unit.2.0.waveform.posn.27.channel=2147483646
unit.2.0.waveform.posn.27.name=cnt
unit.2.0.waveform.posn.27.channel=219
unit.2.0.waveform.posn.27.name=op
unit.2.0.waveform.posn.27.radix=1
unit.2.0.waveform.posn.27.type=bus
unit.2.0.waveform.posn.28.channel=219
unit.2.0.waveform.posn.28.name=op
unit.2.0.waveform.posn.27.type=signal
unit.2.0.waveform.posn.28.channel=220
unit.2.0.waveform.posn.28.name=zbt_stb
unit.2.0.waveform.posn.28.radix=1
unit.2.0.waveform.posn.28.type=signal
unit.2.0.waveform.posn.29.channel=220
unit.2.0.waveform.posn.29.name=zbt_stb
unit.2.0.waveform.posn.29.channel=221
unit.2.0.waveform.posn.29.name=flash_stb
unit.2.0.waveform.posn.29.radix=1
unit.2.0.waveform.posn.29.type=signal
unit.2.0.waveform.posn.3.channel=2147483646
unit.2.0.waveform.posn.3.name=io_reg
unit.2.0.waveform.posn.3.name=pc
unit.2.0.waveform.posn.3.radix=1
unit.2.0.waveform.posn.3.type=bus
unit.2.0.waveform.posn.30.channel=221
unit.2.0.waveform.posn.30.name=flash_stb
unit.2.0.waveform.posn.30.channel=222
unit.2.0.waveform.posn.30.name=flash_arena
unit.2.0.waveform.posn.30.radix=1
unit.2.0.waveform.posn.30.type=signal
unit.2.0.waveform.posn.31.channel=222
unit.2.0.waveform.posn.31.name=flash_arena
unit.2.0.waveform.posn.31.channel=223
unit.2.0.waveform.posn.31.name=vdu_arena
unit.2.0.waveform.posn.31.radix=1
unit.2.0.waveform.posn.31.type=signal
unit.2.0.waveform.posn.32.channel=223
unit.2.0.waveform.posn.32.name=vdu_arena
unit.2.0.waveform.posn.32.channel=2147483646
unit.2.0.waveform.posn.32.name=d
unit.2.0.waveform.posn.32.radix=1
unit.2.0.waveform.posn.32.type=signal
unit.2.0.waveform.posn.32.type=bus
unit.2.0.waveform.posn.33.channel=2147483646
unit.2.0.waveform.posn.33.name=cx
unit.2.0.waveform.posn.33.name=addr_d
unit.2.0.waveform.posn.33.radix=1
unit.2.0.waveform.posn.33.type=bus
unit.2.0.waveform.posn.34.channel=2147483646
unit.2.0.waveform.posn.34.name=di
unit.2.0.waveform.posn.34.channel=94
unit.2.0.waveform.posn.34.name=byte_op
unit.2.0.waveform.posn.34.radix=1
unit.2.0.waveform.posn.34.type=bus
unit.2.0.waveform.posn.35.channel=2147483646
unit.2.0.waveform.posn.35.name=adr
unit.2.0.waveform.posn.34.type=signal
unit.2.0.waveform.posn.35.channel=104
unit.2.0.waveform.posn.35.name=inta
unit.2.0.waveform.posn.35.radix=1
unit.2.0.waveform.posn.35.type=bus
unit.2.0.waveform.posn.36.channel=2147483646
unit.2.0.waveform.posn.36.name=adr
unit.2.0.waveform.posn.35.type=signal
unit.2.0.waveform.posn.36.channel=105
unit.2.0.waveform.posn.36.name=intr
unit.2.0.waveform.posn.36.radix=1
unit.2.0.waveform.posn.36.type=bus
unit.2.0.waveform.posn.36.type=signal
unit.2.0.waveform.posn.37.channel=2147483646
unit.2.0.waveform.posn.37.name=adr
unit.2.0.waveform.posn.37.name=cnt_time
unit.2.0.waveform.posn.37.radix=1
unit.2.0.waveform.posn.37.type=bus
unit.2.0.waveform.posn.38.channel=2147483646
unit.2.0.waveform.posn.38.name=adr
unit.2.0.waveform.posn.38.channel=228
unit.2.0.waveform.posn.38.name=cpu_block
unit.2.0.waveform.posn.38.radix=1
unit.2.0.waveform.posn.38.type=bus
unit.2.0.waveform.posn.39.channel=2147483646
unit.2.0.waveform.posn.39.name=adr
unit.2.0.waveform.posn.38.type=signal
unit.2.0.waveform.posn.39.channel=228
unit.2.0.waveform.posn.39.name=cpu_block
unit.2.0.waveform.posn.39.radix=1
unit.2.0.waveform.posn.39.type=bus
unit.2.0.waveform.posn.39.type=signal
unit.2.0.waveform.posn.4.channel=2147483646
unit.2.0.waveform.posn.4.name=state
unit.2.0.waveform.posn.4.radix=1
unit.2.0.waveform.posn.4.type=bus
unit.2.0.waveform.posn.40.channel=2147483646
unit.2.0.waveform.posn.40.name=adr
unit.2.0.waveform.posn.40.channel=228
unit.2.0.waveform.posn.40.name=cpu_block
unit.2.0.waveform.posn.40.radix=1
unit.2.0.waveform.posn.40.type=bus
unit.2.0.waveform.posn.40.type=signal
unit.2.0.waveform.posn.41.channel=2147483646
unit.2.0.waveform.posn.41.name=adr
unit.2.0.waveform.posn.41.radix=1
3702,7 → 3725,7
unit.2.0.waveform.posn.49.radix=1
unit.2.0.waveform.posn.49.type=bus
unit.2.0.waveform.posn.5.channel=2147483646
unit.2.0.waveform.posn.5.name=next_state
unit.2.0.waveform.posn.5.name=flags
unit.2.0.waveform.posn.5.radix=1
unit.2.0.waveform.posn.5.type=bus
unit.2.0.waveform.posn.50.channel=2147483646
3746,7 → 3769,7
unit.2.0.waveform.posn.59.radix=1
unit.2.0.waveform.posn.59.type=bus
unit.2.0.waveform.posn.6.channel=2147483646
unit.2.0.waveform.posn.6.name=func
unit.2.0.waveform.posn.6.name=next_state
unit.2.0.waveform.posn.6.radix=1
unit.2.0.waveform.posn.6.type=bus
unit.2.0.waveform.posn.60.channel=2147483646
3790,7 → 3813,7
unit.2.0.waveform.posn.69.radix=1
unit.2.0.waveform.posn.69.type=bus
unit.2.0.waveform.posn.7.channel=2147483646
unit.2.0.waveform.posn.7.name=t
unit.2.0.waveform.posn.7.name=func
unit.2.0.waveform.posn.7.radix=1
unit.2.0.waveform.posn.7.type=bus
unit.2.0.waveform.posn.70.channel=2147483646
3834,7 → 3857,7
unit.2.0.waveform.posn.79.radix=1
unit.2.0.waveform.posn.79.type=bus
unit.2.0.waveform.posn.8.channel=2147483646
unit.2.0.waveform.posn.8.name=adr
unit.2.0.waveform.posn.8.name=t
unit.2.0.waveform.posn.8.radix=1
unit.2.0.waveform.posn.8.type=bus
unit.2.0.waveform.posn.80.channel=2147483646
3878,7 → 3901,7
unit.2.0.waveform.posn.89.radix=1
unit.2.0.waveform.posn.89.type=bus
unit.2.0.waveform.posn.9.channel=2147483646
unit.2.0.waveform.posn.9.name=dat_i
unit.2.0.waveform.posn.9.name=adr
unit.2.0.waveform.posn.9.radix=1
unit.2.0.waveform.posn.9.type=bus
unit.2.0.waveform.posn.90.channel=2147483646
/trunk/impl/virtex4-ml403ep/sim/test_kotku.v
8,9 → 8,10
wire lcd_hsync;
wire lcd_vsync;
reg clk;
reg but;
wire s_clk;
wire [20:0] sf_addr;
wire [15:0] sf_data;
wire [31:0] sf_data;
wire sf_oe;
wire sf_we;
wire [ 3:0] s_bw;
39,7 → 40,11
.sram_adv_ld_n_ (s_adv),
.flash_ce2_ (f_ce),
 
.but_ (1'b0)
.butc_ (but),
.bute_ (1'b0),
.butw_ (1'b0),
.butn_ (1'b0),
.buts_ (1'b0)
);
 
flash_stub fs0 (
72,6 → 77,10
initial
begin
clk <= 1'b1;
but <= 1'b0;
#100000 but <= 1'b1;
#700000 but <= 1'b0;
#700000 but <= 1'b1;
end
 
endmodule
/trunk/impl/virtex4-ml403ep/sim/t.do
1,11 → 1,12
quit -sim
vdel -all -lib work
vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
vlib work
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../dbg/hw_dbg.v
vlog -work work -lint +incdir+../../../rtl-model +incdir+../../../sim ../syn/kotku.v ../syn/clock.v ../../../rtl-model/regfile.v ../../../rtl-model/alu.v ../../../rtl-model/cpu.v ../../../rtl-model/exec.v ../../../rtl-model/fetch.v ../../../rtl-model/jmp_cond.v ../../../rtl-model/util/primitives.v ../../../rtl-model/util/div_su.v ../../../rtl-model/util/div_uu.v ../../../rtl-model/rotate.v test_kotku.v flash_stub.v ../../../sim/mult.v ../../../soc/vga/rtl/vdu.v ../../../soc/vga/rtl/char_rom_b16.v ../../../soc/vga/rtl/ram2k_b16_attr.v ../../../soc/vga/rtl/ram2k_b16.v ../mem/flash_cntrl.v ../mem/zbt_cntrl.v CY7C1354BV25.v ../../../soc/keyb/rtl/ps2_keyb.v ../dbg/hw_dbg.v ../dbg/pc_trace.v ../dbg/clk_uart.v ../dbg/send_addr.v ../dbg/send_serial.v
vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
vsim -L /opt/Xilinx/10.1/modelsim/verilog/unisims -novopt -t ps work.testbench work.glbl
add wave -label clk100 /testbench/clk
add wave -label clk /testbench/kotku/clk
add wave -label clk /testbench/kotku/zet_proc/wb_clk_i
add wave -label rst /testbench/kotku/rst
add wave -label pc -radix hexadecimal /testbench/kotku/zet_proc/fetch0/pc
add wave -divider fetch
17,14 → 18,25
add wave -label end_seq /testbench/kotku/zet_proc/fetch0/end_seq
add wave -label need_modrm /testbench/kotku/zet_proc/fetch0/need_modrm
add wave -label need_off /testbench/kotku/zet_proc/fetch0/need_off
add wave -label off_size /testbench/kotku/zet_proc/fetch0/off_size
add wave -label need_imm /testbench/kotku/zet_proc/fetch0/need_imm
add wave -label imm_size /testbench/kotku/zet_proc/fetch0/imm_size
add wave -label ir /testbench/kotku/zet_proc/fetch0/ir
add wave -label imm -radix hexadecimal /testbench/kotku/zet_proc/fetch0/imm
add wave -label off -radix hexadecimal /testbench/kotku/zet_proc/fetch0/off
add wave -divider mem
add wave -divider regfile
add wave -label ax -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[0\]
add wave -label cx -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[1\]
add wave -label dx -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[2\]
add wave -label si -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[6\]
add wave -label tmp -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[13\]
add wave -label d -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/d\[15:0\]
add wave -label wr -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/wr
add wave -divider wb_master
add wave -label cs -radix hexadecimal /testbench/kotku/zet_proc/wm0/cs
add wave -label op -radix hexadecimal /testbench/kotku/zet_proc/wm0/op
add wave -label block /testbench/kotku/zet_proc/wm0/cpu_block
add wave -label dbg_block /testbench/kotku/zet_proc/dbg_block
add wave -label wb_block /testbench/kotku/zet_proc/wb_block
add wave -label dat_o -radix hexadecimal sim:/testbench/kotku/dat_o
add wave -label dat_i -radix hexadecimal sim:/testbench/kotku/dat_i
add wave -label adr -radix hexadecimal /testbench/kotku/adr
36,12 → 48,17
add wave -label we_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_we_o
add wave -label tga_o -radix hexadecimal /testbench/kotku/zet_proc/wm0/wb_tga_o
add wave -label cpu_dat_i -radix hexadecimal /testbench/kotku/zet_proc/wm0/cpu_dat_i
add wave -divider flash
add wave -radix hexadecimal /sf_addr
add wave -radix hexadecimal /sf_data
add wave -radix hexadecimal /sf_oe
add wave -radix hexadecimal /sf_we
add wave -radix hexadecimal /f_ce
add wave -divider alu
add wave -label x -radix hexadecimal /testbench/kotku/zet_proc/exec0/a
add wave -label y -radix hexadecimal /testbench/kotku/zet_proc/exec0/bus_b
add wave -label t -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/t
add wave -label func -radix hexadecimal /testbench/kotku/zet_proc/exec0/alu0/func
add wave -label r\[1\] -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/r\[1\]
add wave -label d -radix hexadecimal /testbench/kotku/zet_proc/exec0/reg0/d
add wave -label addr_a /testbench/kotku/zet_proc/exec0/reg0/addr_a
add wave -label addr_d /testbench/kotku/zet_proc/exec0/reg0/addr_d
49,8 → 66,6
add wave -label we /testbench/kotku/we
add wave -label ack /testbench/kotku/ack
add wave -label fetch_or_exec /testbench/kotku/zet_proc/fetch_or_exec
add wave -divider vdu
add wave -radix hexadecimal /testbench/kotku/vdu0/*
add wave -divider hw_dbg
add wave -radix hexadecimal /testbench/kotku/dbg0/*
run 50us
add wave -divider zbt
add wave -radix hexadecimal -r /testbench/kotku/zbt0/*
run 300us
/trunk/impl/virtex4-ml403ep/sim/flash_stub.v
13,10 → 13,10
reg [31:0] dat_o;
 
// Continous assignments
assign flash_data_ = flash_ce2_ ? dat_o : 31'hzzzzzzzz;
assign flash_data_ = flash_ce2_ ? dat_o : 32'hzzzzzzzz;
 
// Behaviour
initial $readmemh("data.ml403", rom, 21'h0);
initial $readmemh("00_test2.ml403", rom, 21'h0);
initial $readmemh("hd.ml403", rom, 21'h100000);
 
always @(*) dat_o <= #110
/trunk/impl/virtex4-ml403ep/syn/kotku-dbg.prj
15,10 → 15,15
verilog work "../../../../rtl-model/exec.v"
verilog work "../../../../soc/vga/rtl/vdu.v"
verilog work "../../../../soc/keyb/rtl/ps2_keyb.v"
verilog work "../../../../soc/timer.v"
verilog work "../../../../rtl-model/cpu.v"
verilog work "../../mem/zbt_cntrl.v"
verilog work "../../mem/flash_cntrl.v"
verilog work "../../dbg/hw_dbg.v"
verilog work "../../dbg/send_serial.v"
verilog work "../../dbg/send_addr.v"
verilog work "../../dbg/pc_trace.v"
verilog work "../../dbg/clk_uart.v"
verilog work "../clock.v"
verilog work "../kotku.v"
verilog work "../../lcd/lcd_display.v"
/trunk/impl/virtex4-ml403ep/syn/kotku.v
30,6 → 30,8
input butw_,
input butn_,
input buts_,
 
output trx_,
`endif
 
output tft_lcd_clk_,
70,6 → 72,7
wire cyc;
wire [ 7:0] keyb_dat_o;
wire keyb_io_arena;
wire keyb_io_status;
wire keyb_arena;
 
wire [15:0] vdu_dat_o;
107,6 → 110,7
wire zbt_stb_i;
 
`ifdef DEBUG
reg [31:0] cnt_time;
wire [35:0] control0;
wire [ 5:0] funct;
wire [ 2:0] state, next_state;
119,7 → 123,19
wire [15:0] aluo;
wire [ 2:0] cnt;
wire op;
wire [15:0] r1, r2;
wire block;
wire cpu_block;
wire sys_clk;
wire rst2;
wire clk_921600;
wire [15:0] ax, dx, bp, si, es;
wire [15:0] c;
wire [ 3:0] addr_c;
wire [15:0] cpu_dat_o;
wire [15:0] d;
wire [ 3:0] addr_d;
wire byte_op;
wire [ 8:0] flags;
 
wire [15:0] dbg_vdu_dat_o;
wire [11:1] dbg_vdu_adr_o;
132,6 → 148,19
wire dbg_zbt_we_o;
wire [ 1:0] dbg_zbt_sel_o;
wire dbg_zbt_stb_o;
 
wire [ 2:0] old_zet_st;
wire [ 4:0] pack;
wire [19:0] tr_dat;
wire tr_new_pc;
wire tr_st;
wire tr_stb;
wire tr_ack;
wire addr_st;
 
wire end_seq;
wire ext_int;
wire cpu_block2;
`endif
 
// Register declarations
143,7 → 172,7
clock c0 (
.clk_100M (clk_100M),
.sys_clk_in_ (sys_clk_in_),
.clk (clk),
.clk (sys_clk),
.vdu_clk (tft_lcd_clk_),
.rst (rst_lck)
);
151,7 → 180,7
vdu vdu0 (
// Wishbone signals
.wb_clk_i (tft_lcd_clk_), // 25 Mhz VDU clock
.wb_rst_i (rst_lck),
.wb_rst_i (rst2),
.wb_dat_i (vdu_dat_i),
.wb_dat_o (vdu_dat_o),
.wb_adr_i (vdu_adr_i),
196,7 → 225,7
.op (op),
`endif
.wb_clk_i (clk),
.wb_rst_i (rst_lck),
.wb_rst_i (rst2),
.wb_dat_i (dat_o),
.wb_dat_o (zbt_dat_o),
.wb_adr_i (zbt_adr_i),
231,7 → 260,14
.ps2_clk_ (ps2_clk_),
.ps2_data_ (ps2_data_)
);
 
/*
timer timer0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_tgc_o (intr),
.wb_tgc_i (inta)
);
*/
cpu zet_proc (
`ifdef DEBUG
.cs (cs),
243,8 → 279,22
.y (y),
.imm (imm),
.aluo (aluo),
.r1 (r1),
.r2 (r2),
.ax (ax),
.dx (dx),
.bp (bp),
.si (si),
.es (es),
.dbg_block (cpu_block),
.c (c),
.addr_c (addr_c),
.cpu_dat_o (cpu_dat_o),
.d (d),
.byte_exec (byte_op),
.addr_d (addr_d),
.flags (flags),
.end_seq (end_seq),
.ext_int (ext_int),
.cpu_block (cpu_block2),
`endif
 
// Wishbone master interface
265,6 → 315,7
 
`ifdef DEBUG
// Module instantiations
 
icon icon0 (
.CONTROL0 (control0)
);
271,7 → 322,7
 
ila ila0 (
.CONTROL (control0),
.CLK (clk_100M),
.CLK (clk),
.TRIG0 (adr),
.TRIG1 ({dat_o,dat_i}),
.TRIG2 (pc),
278,8 → 329,10
.TRIG3 ({clk,we,tga,cyc,stb,ack}),
.TRIG4 (funct),
.TRIG5 ({state,next_state}),
.TRIG6 (io_reg),
.TRIG7 (imm),
.TRIG6 ({intr,inta,flags,byte_op,addr_d}),
// .TRIG7 (imm),
// .TRIG7 (tr_dat[15:0]),
.TRIG7 (d),
.TRIG8 ({x,y}),
.TRIG9 (aluo),
.TRIG10 (sram_flash_addr_),
288,7 → 341,8
sram_cen_, sram_adv_ld_n_, flash_ce2_}),
.TRIG13 (cnt),
.TRIG14 ({vdu_mem_arena,flash_mem_arena,flash_stb,zbt_stb,op}),
.TRIG15 ({r1,r2})
.TRIG15 (cnt_time)
// .TRIG15 ({block,trx_,rst2,rst,tr_ack,tr_stb,tr_st,tr_new_pc,addr_st,11'h0,pack,old_zet_st,tr_dat[19:16]})
);
 
lcd_display lcd0 (
309,7 → 363,7
 
hw_dbg dbg0 (
.clk (clk),
.rst_lck (rst_lck),
.rst_lck (rst2),
.rst (rst),
.butc_ (butc_),
.bute_ (bute_),
333,6 → 387,34
.zbt_ack_i (zbt_ack)
);
 
clk_uart clk0 (
.clk_100M (clk_100M),
.rst (rst_lck),
.clk_921600 (clk_921600),
.rst2 (rst2)
);
 
pc_trace pc0 (
`ifdef DEBUG
.old_zet_st (old_zet_st),
 
.dat (tr_dat),
.new_pc (tr_new_pc),
.st (tr_st),
.stb (tr_stb),
.ack (tr_ack),
.pack (pack),
.addr_st (addr_st),
`endif
.trx_ (trx_),
 
.clk (clk),
.rst (rst2),
.pc (pc),
.zet_st (state),
.block (block)
);
 
// Continuous assignments
assign f1 = { 3'b0, rst, 4'h0, io_reg, 4'h0, dat_o, 7'h0, tga, 7'h0, ack, 4'h0 };
assign f2 = { adr, 7'h0, we, 3'h0, stb, 3'h0, cyc, 8'h0, pc };
351,7 → 433,12
assign zbt_we_i = rst ? dbg_zbt_we_o : we;
assign zbt_sel_i = rst ? dbg_zbt_sel_o : sel;
assign zbt_stb_i = rst ? dbg_zbt_stb_o : zbt_stb;
`ifdef DEBUG_TRACE
assign cpu_block = block;
`else
assign cpu_block = 1'b0;
`endif
`else
assign vdu_dat_i = dat_o;
assign vdu_adr_i = adr[11:1];
assign vdu_we_i = we;
364,9 → 451,16
assign zbt_stb_i = zbt_stb;
`endif
 
`ifdef DEBUG_TRACE
assign clk = clk_921600;
`else
assign clk = sys_clk;
`endif
 
assign io_dat_i = flash_io_arena ? flash_dat_o
: (vdu_io_arena ? vdu_dat_o
: (keyb_io_arena ? keyb_dat_o : 16'h0));
: (keyb_io_arena ? keyb_dat_o
: (keyb_io_status ? 16'h10 : 16'h0)));
assign dat_i = inta ? 16'd9 : (tga ? io_dat_i
: (vdu_mem_arena ? vdu_dat_o
: (flash_mem_arena ? flash_dat_o : zbt_dat_o)));
379,6 → 473,9
(adr[15:1]==15'h01ed && !we);
assign keyb_io_arena = (adr[15:1]==15'h0030 && !we);
 
// MS-DOS is reading IO address 0x64 to check the inhibit bit
assign keyb_io_status = (adr[15:1]==15'h0032 && !we);
 
assign flash_arena = (!tga & flash_mem_arena)
| (tga & flash_io_arena);
assign vdu_arena = (!tga & vdu_mem_arena)
421,7 → 518,11
: ((tga && stb && cyc && we && adr[15:8]==8'hf1) ?
dat_o : io_reg );
 
`ifndef DEBUG
`ifdef DEBUG
// cnt_time
always @(posedge clk)
cnt_time <= rst ? 32'h0 : (cnt_time + 32'h1);
`else
assign rst = rst_lck;
`endif
endmodule
/trunk/impl/virtex4-ml403ep/syn/ml403.ucf
4,7 → 4,6
NET sys_clk_in_ LOC = AE14;
NET sys_clk_in_ IOSTANDARD = LVCMOS33;
 
#NET trx LOC = W1;
NET sram_clk_ LOC = AF7 ;
 
#NET sram_flash_addr_[24] LOC = T21;
115,6 → 114,8
NET butn_ LOC = E7; # N Button
NET buts_ LOC = A6; # S Button
 
NET trx_ LOC = W1;
 
#NET led_[0] LOC = G5; #GPLED0
#NET led_[1] LOC = G6; #GPLED1
#NET led_[2] LOC = A11; #GPLED2
/trunk/impl/virtex4-ml403ep/syn/Makefile
1,4 → 1,4
all: Zet.ace
all: kotku_ml403.bit
 
run: tmp/kotku_ml403.bit
(cd tmp/ && ../../../../bin/ml403 kotku_ml403.bit)
36,5 → 36,8
tmp/kotku_ml403.bit: tmp/kotku_ml403-par.ncd
(cd tmp/ && bitgen -w kotku_ml403-par.ncd kotku_ml403.bit)
 
kotku_ml403.bit: tmp/kotku_ml403.bit
cp tmp/kotku_ml403.bit /home/zeus/tmp
 
clean:
rm -fR Zet.ace tmp/
/trunk/impl/virtex4-ml403ep/syn/ila.xco
1,7 → 1,7
##############################################################
#
# Xilinx Core Generator version K.39
# Date: Fri Nov 7 05:42:19 2008
# Date: Sat Feb 28 12:16:13 2009
#
##############################################################
#
36,7 → 36,7
# END Select
# BEGIN Parameters
CSET component_name=ila
CSET counter_width_1=Disabled
CSET counter_width_1=32
CSET counter_width_10=Disabled
CSET counter_width_11=16
CSET counter_width_12=Disabled
79,7 → 79,7
CSET match_type_13=basic
CSET match_type_14=basic
CSET match_type_15=basic
CSET match_type_16=basic
CSET match_type_16=range
CSET match_type_2=basic
CSET match_type_3=basic
CSET match_type_4=basic
127,5 → 127,5
CSET use_rpms=true
# END Parameters
GENERATE
# CRC: 1d7360fb
# CRC: c1a9a9f1
 
/trunk/impl/virtex4-ml403ep/dbg/test_serial.v
0,0 → 1,48
 
 
module test_serial (
input clk_,
output trx_
);
 
// Registers and nets
wire clk_100M;
wire rst;
wire clk_921600;
wire rst2;
wire ack;
wire lock;
wire [19:0] inc_dat;
reg [19:0] dat;
 
// Module instantiation
clocks c0 (
.CLKIN_IN (clk_),
.CLK0_OUT (clk_100M),
.LOCKED_OUT (lock)
);
 
clk_uart clk0 (
.clk_100M (clk_100M),
.rst (rst),
.clk_921600 (clk_921600),
.rst2 (rst2)
);
 
send_addr ser0 (
.trx_ (trx_),
.wb_clk_i (clk_921600),
.wb_rst_i (rst2),
.wb_dat_i (dat),
.wb_we_i (1'b1),
.wb_stb_i (1'b1),
.wb_cyc_i (1'b1),
.wb_ack_o (ack)
);
 
assign rst = !lock;
assign inc_dat = dat + 20'h1;
 
always @(posedge clk_921600)
dat <= rst2 ? 20'h12345 : (ack ? inc_dat : dat);
endmodule
/trunk/impl/virtex4-ml403ep/dbg/pc_trace.v
0,0 → 1,85
`timescale 1ns/10ps
`include "defines.v"
 
module pc_trace (
`ifdef DEBUG
output reg [ 2:0] old_zet_st,
output reg [19:0] dat,
output reg new_pc,
output reg st,
output reg stb,
output ack,
output [ 4:0] pack,
output addr_st,
`endif
// PAD signals
output trx_,
 
input clk,
input rst,
input [19:0] pc,
input [ 2:0] zet_st,
output reg block
);
 
`ifndef DEBUG
// Registers and nets
reg [19:0] dat;
reg [ 2:0] old_zet_st;
reg new_pc;
reg st;
reg stb;
wire ack;
`endif
wire op_st;
wire rom;
 
// Module instantiations
send_addr ser0 (
`ifdef DEBUG
.pack (pack),
.st (addr_st),
`endif
.trx_ (trx_),
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat),
.wb_we_i (stb),
.wb_stb_i (stb),
.wb_cyc_i (stb),
.wb_ack_o (ack)
);
 
// Continous assignments
assign op_st = (zet_st == 3'b0);
assign rom = pc[19:16]==4'hf || pc[19:16]==4'hc;
 
// Behaviour
// old_zet_st
always @(posedge clk)
old_zet_st <= rst ? 3'b0 : zet_st;
 
// new_pc
always @(posedge clk)
new_pc <= rst ? 1'b0
: (op_st ? (zet_st!=old_zet_st && !rom) : 1'b0);
 
// block
always @(posedge clk)
block <= rst ? 1'b0
: (new_pc ? (st & !ack) : (ack ? 1'b0 : block));
 
// dat
always @(posedge clk)
dat <= rst ? 20'h0
: ((new_pc & !st) ? pc : (ack ? pc : dat));
 
// stb
always @(posedge clk)
stb <= rst ? 1'b0 : (ack ? 1'b0 : (st | new_pc));
 
// st
always @(posedge clk)
st <= rst ? 1'b0
: (st ? (ack ? (new_pc | block) : 1'b1) : new_pc);
endmodule
/trunk/impl/virtex4-ml403ep/dbg/sim_addr.v
0,0 → 1,46
`timescale 1ns/10ps
 
module sim_addr;
 
// Registers and nets
reg clk_100M;
reg rst;
reg stb;
wire clk_921600;
wire trx_;
wire rst2;
wire ack;
 
// Module instantiation
clk_uart clk0 (
.clk_100M (clk_100M),
.rst (rst),
.clk_921600 (clk_921600),
.rst2 (rst2)
);
 
send_addr ser0 (
.trx_ (trx_),
.wb_clk_i (clk_921600),
.wb_rst_i (rst2),
.wb_dat_i (20'h4fb31),
.wb_we_i (1'b1),
.wb_stb_i (stb),
.wb_cyc_i (1'b1),
.wb_ack_o (ack)
);
 
// Behaviour
initial
begin
stb <= 1'b1;
clk_100M <= 1'b0;
rst <= 1'b1;
#400 rst <= 1'b0;
#33635 stb <= 1'b0;
#10000 stb <= 1'b1;
end
 
// clk_50M
always #5 clk_100M <= !clk_100M;
endmodule
/trunk/impl/virtex4-ml403ep/dbg/send_addr.v
0,0 → 1,75
`timescale 1ns/10ps
`include "defines.v"
 
module send_addr (
`ifdef DEBUG
output reg [ 4:0] pack,
output reg st,
`endif
// Serial pad signal
output trx_,
 
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [19:0] wb_dat_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o
);
 
// Registers and nets
`ifndef DEBUG
reg [4:0] pack;
reg st;
`endif
wire op;
wire start;
wire sack;
wire [7:0] dat;
wire [7:0] b0, b1, b2, b3, b4;
 
// Module instantiation
send_serial ss0 (
.trx_ (trx_),
 
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (dat),
.wb_we_i (wb_we_i),
.wb_stb_i (wb_stb_i),
.wb_cyc_i (wb_cyc_i),
.wb_ack_o (sack)
);
 
// Continuous assignments
assign op = wb_we_i & wb_stb_i & wb_cyc_i;
assign start = !st & op;
assign wb_ack_o = st & sack & pack[4];
 
assign dat = st & pack[0] ?
(pack[1] ? (pack[2] ? (pack[3] ? (pack[4] ? 8'h0a : b0)
: b1) : b2) : b3) : b4;
 
assign b0 = { 1'b0, ascii(wb_dat_i[ 3: 0]) };
assign b1 = { 1'b0, ascii(wb_dat_i[ 7: 4]) };
assign b2 = { 1'b0, ascii(wb_dat_i[11: 8]) };
assign b3 = { 1'b0, ascii(wb_dat_i[15:12]) };
assign b4 = { 1'b0, ascii(wb_dat_i[19:16]) };
 
// Behaviour
// pack
always @(posedge wb_clk_i)
pack <= wb_rst_i ? 5'b0 : (start ? 5'b0
: (st ? (sack ? { pack[3:0], 1'b1 } : pack) : 5'b0));
 
// st
always @(posedge wb_clk_i)
st <= wb_rst_i ? 1'b0 : (st ? !wb_ack_o : op);
 
function [6:0] ascii(input [3:0] num);
if (num <= 4'd9) ascii = 7'h30 + num;
else ascii = 7'd87 + num;
endfunction
endmodule
/trunk/impl/virtex4-ml403ep/dbg/clk_uart.v
0,0 → 1,34
/*
* Phase accumulator clock:
* Fo = Fc * N / 2^bits
* here N: 154619 and bits: 24
*/
 
module clk_uart (
input clk_100M,
input rst,
output clk_921600,
output rst2
);
 
// Registers
reg [25:0] cnt;
reg [ 2:0] init;
 
// Continuous assignments
assign clk_921600 = cnt[25];
assign rst2 = init[2];
 
// Behaviour
// cnt
always @(posedge clk_100M)
cnt <= rst ? 26'd0 : cnt + 26'd154619;
 
// init[0]
always @(posedge clk_100M)
init[0] <= rst ? 1'b1 : (clk_921600 ? 1'b0 : init[0]);
 
// init[2:1]
always @(posedge clk_921600)
init[2:1] <= init[0] ? 2'b11 : init[1:0];
endmodule
/trunk/impl/virtex4-ml403ep/dbg/sim_serial.v
0,0 → 1,46
`timescale 1ns/10ps
 
module sim_serial;
 
// Registers and nets
reg clk_100M;
reg rst;
reg stb;
wire clk_921600;
wire trx_;
wire rst2;
wire ack;
 
// Module instantiation
clk_uart clk0 (
.clk_100M (clk_100M),
.rst (rst),
.clk_921600 (clk_921600),
.rst2 (rst2)
);
 
send_serial ser0 (
.trx_ (trx_),
.wb_clk_i (clk_921600),
.wb_rst_i (rst2),
.wb_dat_i (8'h4b),
.wb_we_i (1'b1),
.wb_stb_i (stb),
.wb_cyc_i (1'b1),
.wb_ack_o (ack)
);
 
// Behaviour
initial
begin
stb <= 1'b1;
clk_100M <= 1'b0;
rst <= 1'b1;
#400 rst <= 1'b0;
#95490 stb <= 1'b0;
#40000 stb <= 1'b1;
end
 
// clk_50M
always #5 clk_100M <= !clk_100M;
endmodule
/trunk/impl/virtex4-ml403ep/dbg/send_serial.v
0,0 → 1,44
 
module send_serial (
// Serial pad signal
output reg trx_,
 
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [7:0] wb_dat_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o
);
 
// Registers and nets
wire op;
wire start;
reg [8:0] tr;
reg st;
reg [7:0] sft;
 
// Continuous assignments
assign op = wb_we_i & wb_stb_i & wb_cyc_i;
assign start = !st & op;
 
// Behaviour
// trx_
always @(posedge wb_clk_i)
trx_ <= wb_rst_i ? 1'b1 : (start ? 1'b0 : tr[0]);
 
// tr
always @(posedge wb_clk_i)
tr <= wb_rst_i ? 9'h1ff
: { 1'b1, (start ? wb_dat_i : tr[8:1]) };
 
// sft, wb_ack_o
always @(posedge wb_clk_i)
{ sft, wb_ack_o } <= wb_rst_i ? 9'h0 : { start, sft };
 
// st
always @(posedge wb_clk_i)
st <= wb_rst_i ? 1'b0 : (st ? !wb_ack_o : op);
endmodule
/trunk/tests/.bochsrc
1,4 → 1,4
romimage: file=21_async.out
romimage: file=00_test2.out
cpu: count=1, ips=10000000, reset_on_triple_fault=1
megs: 2
vgaromimage: file=$BXSHARE/VGABIOS-lgpl-latest
/trunk/tests/Makefile
31,7 → 31,7
# paste -d\\ hd.img.rtl $< >../../impl/virtex4-ml403ep/sim/$@
 
%.ml403: %.rom
hexdump -v -e '4/1 "%02X"' -e '"\n"' $< > ../../impl/virtex4-ml403ep/sim/$@
hexdump -v -e '4/1 "%02X"' -e '"\n"' $< > ../impl/virtex4-ml403ep/sim/$@
 
%.fout: %.out hd.img.rtl
for i in $$(seq 32768); do echo FFFF; done >$@
/trunk/soc/timer.v
0,0 → 1,36
module timer (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
output reg wb_tgc_o, // intr
input wb_tgc_i // inta
);
 
// Registers and nets
reg [17:0] cnt;
reg old_clk2;
reg pulse;
wire clk2;
 
// Continuous assignments
assign clk2 = cnt[17];
 
// Behaviour
// cnt
always @(posedge wb_clk_i)
cnt <= wb_rst_i ? 18'h00 : (cnt + 18'h1);
 
// old_clk2
always @(posedge wb_clk_i)
old_clk2 <= wb_rst_i ? 1'b0 : clk2;
 
// pulse
always @(posedge wb_clk_i)
pulse <= wb_rst_i ? 1'b0 : (clk2!=old_clk2);
 
// intr
always @(posedge wb_clk_i)
wb_tgc_o <= wb_rst_i ? 1'b0
: ((pulse & !wb_tgc_i) ? 1'b1
: (wb_tgc_o ? !wb_tgc_i : 1'b0));
endmodule
/trunk/soc/bios/rombios.c
11,6 → 11,8
 
#include "rombios.h"
 
#define BX_CPU 0
 
/* model byte 0xFC = AT */
#define SYS_MODEL_ID 0xFC
 
960,7 → 962,7
}
}
 
static char bios_svn_version_string[] = "$Revision: 1.10 $ $Date: 2009-02-19 19:06:56 $";
static char bios_svn_version_string[] = "$Revision: 1.11 $ $Date: 2009-03-02 01:02:32 $";
 
//--------------------------------------------------------------------------
// print_bios_banner
2101,7 → 2103,7
 
;; Keyboard
SET_INT_VECTOR(0x09, #0xF000, #int09_handler)
;SET_INT_VECTOR(0x16, #0xF000, #int16_handler)
SET_INT_VECTOR(0x16, #0xF000, #int16_handler)
 
xor ax, ax
mov ds, ax
2113,7 → 2115,6
mov al, #0x10
mov 0x0496, al /* keyboard status flags 3 */
 
 
/* keyboard head of buffer pointer */
mov bx, #0x001E
mov 0x041A, bx
2186,8 → 2187,10
push bx
push sp
mov bx, sp
add [bx], #10
mov bx, [bx+2]
sseg
add [bx], #10
sseg
mov bx, [bx+2]
push bp
push si
push di
2283,9 → 2286,9
int09_handler:
cli
push ax
 
in al, #0x60 ;;read key from keyboard controller
sti
 
push ds
;pusha ; we do this instead:
 
2295,8 → 2298,10
push bx
push sp
mov bx, sp
add [bx], #10
mov bx, [bx+2]
sseg
add [bx], #10
sseg
mov bx, [bx+2]
push bp
push si
push di
2325,7 → 2330,6
mov bx, #0xf000
mov ds, bx
call _int09_function
 
int09_done:
; popa ; we do this instead:
pop di
2338,8 → 2342,8
pop ax
 
pop ds
 
cli
 
pop ax
iret
 
/trunk/soc/bios/vgabios.c
26,6 → 26,9
static void biosfn_set_cursor_pos();
static void biosfn_get_cursor_pos();
static void biosfn_scroll();
static void biosfn_read_char_attr();
static void biosfn_write_char_attr();
static void biosfn_write_char_only();
static void biosfn_write_teletype();
static void biosfn_load_text_8_16_pat();
static void biosfn_write_string();
173,8 → 176,10
push bx
push sp
mov bx, sp
add [bx], #10
mov bx, [bx+2]
sseg
add [bx], #10
sseg
mov bx, [bx+2]
push bp
push si
push di
234,7 → 239,7
 
#if defined(USE_BX_INFO) || defined(DEBUG)
msg_vga_init:
.ascii "VGABios $Id: vgabios.c,v 1.7 2009-02-06 03:48:27 zeus Exp $"
.ascii "VGABios $Id: vgabios.c,v 1.8 2009-03-02 01:02:33 zeus Exp $"
.byte 0x0d,0x0a,0x00
#endif
ASM_END
416,6 → 421,15
case 0x07:
biosfn_scroll(GET_AL(),GET_BH(),GET_CH(),GET_CL(),GET_DH(),GET_DL(),0xFF,SCROLL_DOWN);
break;
case 0x08:
biosfn_read_char_attr(GET_BH(),&AX);
break;
case 0x09:
biosfn_write_char_attr(GET_AL(),GET_BH(),GET_BL(),CX);
break;
case 0x0A:
biosfn_write_char_only(GET_AL(),GET_BH(),GET_BL(),CX);
break;
case 0x0E:
// Ralf Brown Interrupt list is WRONG on bh(page)
// We do output only on the current page !
738,6 → 752,91
}
 
// --------------------------------------------------------------------------------------------
static void biosfn_read_char_attr (page,car)
Bit8u page;Bit16u *car;
{Bit16u ss=get_SS();
Bit8u xcurs,ycurs,mode,line;
Bit16u nbcols,nbrows,address;
Bit16u cursor,dummy;
 
// Get the mode
mode=read_byte(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE);
line=find_vga_entry(mode);
if(line==0xFF)return;
 
// Get the cursor pos for the page
biosfn_get_cursor_pos(page,&dummy,&cursor);
xcurs=cursor&0x00ff;ycurs=(cursor&0xff00)>>8;
 
// Get the dimensions
nbrows=read_byte(BIOSMEM_SEG,BIOSMEM_NB_ROWS)+1;
nbcols=read_word(BIOSMEM_SEG,BIOSMEM_NB_COLS);
 
// Compute the address
address=SCREEN_MEM_START(nbcols,nbrows,page)+(xcurs+ycurs*nbcols)*2;
 
write_word(ss,car,read_word(vga_modes[line].sstart,address));
}
 
// --------------------------------------------------------------------------------------------
static void biosfn_write_char_attr (car,page,attr,count)
Bit8u car;Bit8u page;Bit8u attr;Bit16u count;
{
Bit8u cheight,xcurs,ycurs,mode,line,bpp;
Bit16u nbcols,nbrows,address;
Bit16u cursor,dummy;
 
// Get the mode
mode=read_byte(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE);
line=find_vga_entry(mode);
if(line==0xFF)return;
 
// Get the cursor pos for the page
biosfn_get_cursor_pos(page,&dummy,&cursor);
xcurs=cursor&0x00ff;ycurs=(cursor&0xff00)>>8;
 
// Get the dimensions
nbrows=read_byte(BIOSMEM_SEG,BIOSMEM_NB_ROWS)+1;
nbcols=read_word(BIOSMEM_SEG,BIOSMEM_NB_COLS);
 
// Compute the address
address=SCREEN_MEM_START(nbcols,nbrows,page)+(xcurs+ycurs*nbcols)*2;
 
dummy=((Bit16u)attr<<8)+car;
memsetw(vga_modes[line].sstart,address,dummy,count);
}
 
// --------------------------------------------------------------------------------------------
static void biosfn_write_char_only (car,page,attr,count)
Bit8u car;Bit8u page;Bit8u attr;Bit16u count;
{
Bit8u cheight,xcurs,ycurs,mode,line,bpp;
Bit16u nbcols,nbrows,address;
Bit16u cursor,dummy;
 
// Get the mode
mode=read_byte(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE);
line=find_vga_entry(mode);
if(line==0xFF)return;
 
// Get the cursor pos for the page
biosfn_get_cursor_pos(page,&dummy,&cursor);
xcurs=cursor&0x00ff;ycurs=(cursor&0xff00)>>8;
 
// Get the dimensions
nbrows=read_byte(BIOSMEM_SEG,BIOSMEM_NB_ROWS)+1;
nbcols=read_word(BIOSMEM_SEG,BIOSMEM_NB_COLS);
 
// Compute the address
address=SCREEN_MEM_START(nbcols,nbrows,page)+(xcurs+ycurs*nbcols)*2;
 
while(count-->0)
{write_byte(vga_modes[line].sstart,address,car);
address+=2;
}
}
 
// --------------------------------------------------------------------------------------------
static void biosfn_write_teletype (car, page, attr, flag)
Bit8u car;Bit8u page;Bit8u attr;Bit8u flag;
{// flag = WITH_ATTR / NO_ATTR
/trunk/src/tools/read-addr.c
0,0 → 1,58
#include <stdio.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <string.h>
 
int main (int argc, char *argv[])
{
int fd, n;
char buf[4096];
char *p, *q;
char s1[6], s2[6];
 
if (argc != 2) fprintf(stderr, "Syntax: %s tracefile\n",
argv[0]);
 
fd=open(argv[1], O_RDONLY);
if(fd < 0)
{
fprintf(stderr, "Error opening file\n");
return 1;
}
 
strcpy (s1, "");
strcpy (s2, "");
 
while (1)
{
n=read(fd, &buf, 4096);
if (n<11) break;
 
p=buf;
q=&buf[n-11];
while (1)
{
if (p = strstr(p, "[0x"))
{
// String found
if (p > q) break;
p+=6;
strncpy (s2, p, 5);
if (strcmp (s1, s2))
{
// They are different
printf ("%s\n", s2);
strcpy (s1, s2);
}
}
else break;
}
 
if (p > q) lseek(fd, (off_t) -10, SEEK_CUR);
if (buf[n-1]=='[') lseek(fd, (off_t) -1, SEEK_CUR);
else if (buf[n-2]=='[' && buf[n-1]=='0')
lseek(fd, (off_t) -2, SEEK_CUR);
}
 
return 0;
}

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