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Rev 444 → Rev 445

/openrisc/trunk/gnu-src/gdb-7.2/gdb/gdbserver/linux-or32-low.c
33,6 → 33,8
#include "regdef.h"
#include "linux-low.h"
 
#include <asm/ptrace.h> /* For openrisc kernel ptrace register offsets */
 
#ifdef HAVE_SYS_REG_H
#include <sys/reg.h>
#endif
48,41 → 50,39
init_registers_or32 ()
{
struct reg regs_or32[] = {
{ "r0", 0, 32 },
{ "sp", 32, 32 },
{ "fp", 64, 32 },
{ "r3", 96, 32 },
{ "r4", 128, 32 },
{ "r5", 160, 32 },
{ "r6", 192, 32 },
{ "r7", 224, 32 },
{ "r8", 256, 32 },
{ "lr", 288, 32 },
{ "r10", 320, 32 },
{ "r11", 352, 32 },
{ "r12", 384, 32 },
{ "r13", 416, 32 },
{ "r14", 448, 32 },
{ "r15", 480, 32 },
{ "r16", 512, 32 },
{ "r17", 544, 32 },
{ "r18", 576, 32 },
{ "r19", 608, 32 },
{ "r20", 640, 32 },
{ "r21", 672, 32 },
{ "r22", 704, 32 },
{ "r23", 736, 32 },
{ "r24", 768, 32 },
{ "r25", 800, 32 },
{ "r26", 832, 32 },
{ "r27", 864, 32 },
{ "r28", 896, 32 },
{ "r29", 928, 32 },
{ "r30", 960, 32 },
{ "r31", 992, 32 },
{ "ppc", 1024, 32 },
{ "npc", 1056, 32 },
{ "sr", 1088, 32 },
{ "npc", PC * 8, 32 },
{ "sr", SR * 8, 32 },
{ "sp", SP * 8, 32 },
{ "fp", GPR2 * 8, 32 },
{ "r3", GPR3 * 8, 32 },
{ "r4", GPR4 * 8, 32 },
{ "r5", GPR5 * 8, 32 },
{ "r6", GPR6 * 8, 32 },
{ "r7", GPR7 * 8, 32 },
{ "r8", GPR8 * 8, 32 },
{ "lr", GPR9 * 8, 32 },
{ "r10", GPR10 * 8, 32 },
{ "r11", GPR11 * 8, 32 },
{ "r12", GPR12 * 8, 32 },
{ "r13", GPR13 * 8, 32 },
{ "r14", GPR14 * 8, 32 },
{ "r15", GPR15 * 8, 32 },
{ "r16", GPR16 * 8, 32 },
{ "r17", GPR17 * 8, 32 },
{ "r18", GPR18 * 8, 32 },
{ "r19", GPR19 * 8, 32 },
{ "r20", GPR20 * 8, 32 },
{ "r21", GPR21 * 8, 32 },
{ "r22", GPR22 * 8, 32 },
{ "r23", GPR23 * 8, 32 },
{ "r24", GPR24 * 8, 32 },
{ "r25", GPR25 * 8, 32 },
{ "r26", GPR26 * 8, 32 },
{ "r27", GPR27 * 8, 32 },
{ "r28", GPR28 * 8, 32 },
{ "r29", GPR29 * 8, 32 },
{ "r30", GPR30 * 8, 32 },
{ "r31", GPR31 * 8, 32 },
};
static const char *expedite_regs_or32[] = { "sp", "lr", "npc", 0 };
 
92,24 → 92,21
}
 
 
/*! OpenRISC has 32 general purpose registers followed by PPC, NPC and SR in
that order. */
#define or32_num_regs (32 + 3)
/*! OpenRISC Linux ptrace provides NPC, SR, then GPRS 1 to 31 */
#define or32_num_regs (2 + 31)
 
 
/* -------------------------------------------------------------------------- */
/*!Provide the ptrace "address" of a register.
 
Not properly supported by uClibc/Linux just yet. The register offsets are
pure guesswork. */
*/
/* -------------------------------------------------------------------------- */
static int or32_regmap[] = {
#ifdef PT_R0
PT_R0, PT_SP, PT_FP, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
PT_R8, PT_LR, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
PT_PPC, PT_NPC, PT_SR
#ifdef PC
PC , SR , SP , GPR2 , GPR3 , GPR4 , GPR5 , GPR6 ,
GPR7 , GPR8 , GPR9 , GPR10, GPR11, GPR12, GPR13, GPR14,
GPR15, GPR16, GPR17, GPR18, GPR19, GPR20, GPR21, GPR22,
GPR23, GPR24, GPR25, GPR26, GPR27, GPR28, GPR29, GPR30,
GPR31
#else
4 * 0, 4 * 1, 4 * 2, 4 * 3, 4 * 4, 4 * 5, 4 * 6, 4 * 7,
4 * 8, 4 * 9, 4 * 10, 4 * 11, 4 * 12, 4 * 13, 4 * 14, 4 * 15,
169,13 → 166,13
or32_get_pc (struct regcache *regcache)
{
unsigned long int npc;
collect_register_by_name (regcache, "npc", &npc);
collect_register_by_name (regcache, "npc", &npc);
 
if (debug_threads)
if (debug_threads)
{
fprintf (stderr, "stop pc is %08lx\n", npc);
}
 
return npc;
 
} /* or32_get_pc () */
194,7 → 191,7
CORE_ADDR pc)
{
unsigned long int npc = pc;
supply_register_by_name (regcache, "pc", &npc);
supply_register_by_name (regcache, "npc", &npc);
 
} /* or32_set_pc () */
 
/openrisc/trunk/gnu-src/gdb-7.2/gdb/ChangeLog.or32
1,3 → 1,11
2010-12-11 Julius Baxter <julius@opencores.org>
* gdbserver/linux-or32-low.c: <regs_or32>: updated with correct PTRACE
mappings
<include asm/trace.>: Added for ptrace definitions.
<or32_regmap>: Updated to use correct ptrace defines.
<or32_num_regs>: Changed to reflect correct number of regs.
<or32_set_pc>: Change "pc" in supply_register_by_name to "npc".
 
2010-09-05 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* version.in: Updated for release 7.2-or32-1.0rc1.

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