URL
https://opencores.org/ocsvn/t80/t80/trunk
Subversion Repositories t80
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 45 to Rev 46
- ↔ Reverse comparison
Rev 45 → Rev 46
/trunk/rtl/vhdl/SSRAM2.vhd
68,7 → 68,7
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type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0); |
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1); |
signal A_r : std_logic_vector(AddrWidth - 1 downto 0); |
-- signal A_r : std_logic_vector(AddrWidth - 1 downto 0); |
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begin |
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83,9 → 83,9
end if; |
-- pragma translate_on |
if CE_n = '0' and WE_n = '0' then |
RAM(to_integer(unsigned(A_r))) <= DIn; |
RAM(to_integer(unsigned(A))) <= DIn; |
end if; |
A_r <= A; |
-- A_r <= A; |
end if; |
end process; |
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/trunk/rtl/vhdl/SSRAMX.vhd
90,7 → 90,7
signal bRAMOut : bRAMOut_a; |
signal biA_r : integer; |
signal A_r : unsigned(A'left downto 0); |
signal A_i : std_logic_vector(8 downto 0); |
-- signal A_i : std_logic_vector(8 downto 0); |
signal WEA : std_logic_vector(RAMs - 1 downto 0); |
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begin |
103,7 → 103,7
end process; |
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biA_r <= to_integer(A_r(A'left downto 9)); |
A_i <= std_logic_vector(A_r(8 downto 0)) when (CE_n nor WE_n) = '1' else A(8 downto 0); |
-- A_i <= std_logic_vector(A_r(8 downto 0)) when (CE_n nor WE_n) = '1' else A(8 downto 0); |
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bG1: for I in 0 to RAMs - 1 generate |
begin |
115,7 → 115,7
WE => WEA(I), |
RST => '0', |
CLK => Clk, |
ADDR => A_i, |
ADDR => A, |
DO => bRAMOut(I)); |
end generate; |
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/trunk/rtl/vhdl/SSRAM.vhd
71,7 → 71,6
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0); |
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1); |
signal A_r : std_logic_vector(AddrWidth - 1 downto 0); |
signal B : std_logic_vector(AddrWidth - 1 downto 0); |
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begin |
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79,10 → 78,9
begin |
if Clk'event and Clk = '1' then |
if (CE_n nor WE_n) = '1' then |
RAM(to_integer(unsigned(B))) <= DIn; |
RAM(to_integer(unsigned(A))) <= DIn; |
end if; |
A_r <= A; |
B <= A; |
end if; |
end process; |
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