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URL https://opencores.org/ocsvn/mips789/mips789/trunk

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  • This comparison shows the changes necessary to convert path 
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    from Rev 46 to Rev 47
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Rev 46 → Rev 47

/trunk/rtl/verilog/RF_components.v
76,8 → 76,8
`PC_J : pc_next ={pc[31:28],imm[27:0]};
`PC_JR : pc_next = s;
`PC_BC : pc_next = (check)?({br_addr[31:0]}):(pc+4);
default
/* `PC_NEXT :*/ pc_next = pc + 4 ;
default
/* `PC_NEXT :*/ pc_next = pc + 4 ;
endcase
end
else
85,9 → 85,9
case (pc_prectl)
`PC_KEP : pc_next=pc;
`PC_IRQ : pc_next=irq;
default
/* `PC_RST : pc_next='d0;*/
pc_next =0;
default
/* `PC_RST : pc_next='d0;*/
pc_next =0;
endcase
end
 
96,27 → 96,19
 
 
module reg_array(
data,
wraddress,
rdaddress_a,
rdaddress_b,
wren,
clock,
qa,
qb,
rd_clk_cls
// pause
// bank_sel
input pause,
input [31:0] data,
input [4:0] wraddress,
input [4:0] rdaddress_a,
input [4:0] rdaddress_b,
input rd_clk_cls,
input wren,
input clock,
output [31:0] qa,
output [31:0] qb
);
// input pause;
input [31:0] data;
input [4:0] wraddress;
input [4:0] rdaddress_a;
input [4:0] rdaddress_b;
// input bank_sel;
input rd_clk_cls;
input wren;
 
 
reg [31:0] r_data;
reg [4:0] r_wraddress;
reg [4:0] r_rdaddress_a;
123,9 → 115,7
reg [4:0] r_rdaddress_b;
 
reg r_wren;
input clock;
output [31:0] qa;
output [31:0] qb;
 
reg [31:0]reg_bank[0:31];
 
integer i;
135,16 → 125,16
reg_bank[i]=0;
end
 
always@(posedge clock)
// if( ~pause )
begin
r_data <=data;
r_wraddress<=wraddress;
r_wren<=wren;
end
always@(posedge clock)
if(0==pause )
begin
r_data <=data;
r_wraddress<=wraddress;
r_wren<=wren;
end
 
always@(posedge clock) // ||( 0==pause )
if(( 0==rd_clk_cls ))
always@(posedge clock)
if(( 0==rd_clk_cls )&&( 0==pause ))
begin
r_rdaddress_a <=rdaddress_a;
r_rdaddress_b <=rdaddress_b;
/trunk/rtl/verilog/dvc.v
70,7 → 70,7
input [3:0] addr;
begin
case(addr)
0: seg = 7'b011_1111;
0: seg = 7'b011_1111;
1: seg = 7'b000_0110;
2: seg = 7'b101_1011;
3: seg = 7'b100_1111;
80,12 → 80,12
7: seg = 7'b000_0111;
8: seg = 7'b111_1111;
9: seg = 7'b110_0111;
10: seg = 7'b111_0111;
11: seg = 7'b111_1100;
12: seg = 7'b101_1000;
13: seg = 7'b101_1110;
14: seg = 7'b111_1001;
15: seg = 7'b111_0001;
10: seg = 7'b111_0111;
11: seg = 7'b111_1100;
12: seg = 7'b101_1000;
13: seg = 7'b101_1110;
14: seg = 7'b111_1001;
15: seg = 7'b111_0001;
default seg = 7'bx;
endcase
end
/trunk/rtl/verilog/ulit.v
138,10 → 138,10
module r4_reg_clr_cls(input[`R4_LEN-1:0] r4_i,output reg[`R4_LEN-1:0] r4_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r4_o<=0;else if(cls)r4_o<=r4_o;else r4_o<=r4_i;endmodule
module r5_reg_clr_cls(input[`R5_LEN-1:0] r5_i,output reg[`R5_LEN-1:0] r5_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r5_o<=0;else if(cls)r5_o<=r5_o;else r5_o<=r5_i;endmodule
module r32_reg_clr_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
/*
 
 
/*
 
module ext_ctl_reg_clr(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr);always@(posedge clk)if(clr)ext_ctl_o<=0;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr);always@(posedge clk)if(clr)rd_sel_o<=0;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_clr(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr);always@(posedge clk)if(clr)cmp_ctl_o<=0;else cmp_ctl_o<=cmp_ctl_i;endmodule
211,4 → 211,39
module r32_reg_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input cls);always@(posedge clk)if(cls) r32_o<=r32_o;else r32_o<=r32_i;endmodule
 
 
*/
*/
 
 
 
 
 
 
 
module f_d_save( // Added by Liwei 2008,3,17
input clk,
input pause ,
input [31:0] din,
output reg [31:0] dout
);
reg [31:0] save_data; //temp register
always @(posedge clk) //latch data at posedge of clk
if (pause == 0 )save_data <= din;
 
always@(*) //A MUX to select data for output port
if (pause ==0 ) dout = din;
else dout =save_data;
endmodule
 
module b_d_save( // Added by Liwei 2008,3,17
input clk,
input pause ,
input [31:0] din,
output reg [31:0] dout);
reg lpause;
always @(posedge clk)lpause = pause ;
reg [31:0] save_data; //temp register
always @(posedge clk) //latch data at posedge of clk
if (lpause == 0)save_data <= din;
always@(*) //A MUX to select data for output port
if (lpause ==0 ) dout = din; else dout =save_data;
endmodule
/trunk/rtl/verilog/mips_core.v
14,21 → 14,22
`include "mips789_defs.v"
 
module mips_core (
input clk,
input irq_i,
input rst,
input [31:0] cop_dout,
input [31:0] irq_addr,
input [31:0] zz_din,
input [31:0] zz_ins_i,
output [31:0] zz_addr_o,
output [31:0] zz_dout,
output [31:0] zz_pc_o,
output [3:0] zz_wr_en_o,
output iack_o,
output [31:0] cop_addr_o,
output [31:0] cop_data_o,
output [3:0] cop_mem_ctl_o
input pause,
input clk,
input irq_i,
input rst,
input [31:0] cop_dout,
input [31:0] irq_addr,
input [31:0] zz_din,
input [31:0] zz_ins_i,
output [31:0] zz_addr_o,
output [31:0] zz_dout,
output [31:0] zz_pc_o,
output [3:0] zz_wr_en_o,
output iack_o,
output [31:0] cop_addr_o,
output [31:0] cop_data_o,
output [3:0] cop_mem_ctl_o
 
);
 
79,9 → 80,8
 
 
mem_module MEM_CTL
(
.pause(0),
// .rt_i(BUS9884),
(
.pause(pause),
.Zz_addr(zz_addr_o),
.Zz_dout(zz_dout),
.Zz_wr_en(zz_wr_en_o),
96,8 → 96,8
assign NET21531 = NET1572 | iack_o;
 
rf_stage iRF_stage
(
.pause(0),
(
.pause(pause),
.clk(clk),
.cmp_ctl_i(BUS109),
.ext_ctl_i(BUS117),
144,8 → 144,7
.fw_dmem(BUS15471),
.muxa_ctl_i(BUS5832),
.muxa_fw_ctl(BUS1158),
.muxb_ctl_i(BUS5840),
.muxb_fw_ctl(BUS1196),
.muxb_ctl_i(BUS5840),
.pc_i(BUS27031),
.rs_i(BUS7101),
.rst(rst),
157,21 → 156,24
 
 
r32_reg_clr_cls alu_pass0
(
.cls(pause),.clr(0),
.clk(clk),
.r32_i(BUS9589),
.r32_o(cop_addr_o)
);
(
.cls(pause),
.clr(0),
.clk(clk),
.r32_i(BUS9589),
.r32_o(cop_addr_o)
);
 
 
 
r32_reg_clr_cls alu_pass1
( .cls(pause),.clr(0),
.clk(clk),
.r32_i(cop_addr_o),
.r32_o(BUS422)
);
(
.cls(pause),
.clr(0),
.clk(clk),
.r32_i(cop_addr_o),
.r32_o(BUS422)
);
 
 
 
185,27 → 187,31
 
 
r32_reg_clr_cls cop_data_reg
( .cls(pause),.clr(0),
.clk(clk),
.r32_i(BUS9884),
.r32_o(cop_data_o)
);
(
.cls(pause),
.clr(0),
.clk(clk),
.r32_i(BUS9884),
.r32_o(cop_data_o)
);
 
 
 
r32_reg_clr_cls cop_dout_reg
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS22401),
.r32_o(BUS7772)
);
(
 
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS22401),
.r32_o(BUS7772)
);
 
 
 
decode_pipe decoder_pipe
( .pause(0),
(
.pause(pause),
.alu_func_o(BUS6275),
.alu_we_o(NET767),
.clk(clk),
226,22 → 232,20
.wb_we_o(NET1375)
);
 
 
 
r32_reg_clr_cls ext_reg
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS7219),
.r32_o(BUS7231)
);
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS7219),
.r32_o(BUS7231)
);
 
 
 
forward iforward
(
.pause(0),
.pause(pause),
.alu_rs_fw(BUS1158),
.alu_rt_fw(BUS1196),
.alu_we(NET767),
259,63 → 263,68
 
 
r32_reg_clr_cls pc
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(zz_pc_o),
.r32_o(BUS27031)
);
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(zz_pc_o),
.r32_o(BUS27031)
);
 
 
 
r5_reg_clr_cls rnd_pass0
(
.clk(clk),
.r5_i(BUS775),
.r5_o(BUS1726)
);
(
.clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS775),
.r5_o(BUS1726)
);
 
 
 
r5_reg_clr_cls rnd_pass1
( .clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS1726),
.r5_o(BUS1724)
);
(
.clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS1726),
.r5_o(BUS1724)
);
 
 
 
r5_reg_clr_cls rnd_pass2
( .clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS1724),
.r5_o(BUS18211)
);
(
.clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS1724),
.r5_o(BUS18211)
);
 
 
 
r32_reg_clr_cls rs_reg
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS24839),
.r32_o(BUS7101)
);
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS24839),
.r32_o(BUS7101)
);
 
 
 
r32_reg_clr_cls rt_reg
( .clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS7160),
.r32_o(BUS7117)
);
(
.clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS7160),
.r32_o(BUS7117)
);
 
 
 
/trunk/rtl/verilog/mips789_defs.v
18,8 → 18,8
 
`define FRQ 50000000
`define SER_RATE 192000 //specialy for simulate in order to make it faster
 
 
`define FW_ALU 3'b001
`define FW_MEM 3'b010
`define FW_NOP 3'b100
42,15 → 42,15
`define DMEM_LHS 8
`define DMEM_LH 9
`define DMEM_LHU 10
 
`define DMEM_LWL 11
`define DMEM_LWR 12
`define DMEM_SWL 13
`define DMEM_SWR 14
 
`define DMEM_NOP 0
 
 
`define ALU_SRL 1
`define ALU_SLL 2
`define ALU_SRA 4
114,11 → 114,15
`define ALU_NOP 0
`define ALU_MTLO 30
`define ALU_MTHI 31
`define ALU_MULTU 8
`define PC_IGN 1
`define ALU_MULTU 8
 
 
`define PC_IGN 5
`define PC_KEP 2
`define PC_IRQ 4
`define PC_RST 8
`define PC_RST 8
`define PC_J 1
`define PC_JR 2
`define PC_BC 4
125,7 → 129,9
`define PC_NEXT 5
`define PC_NOP 0
`define PC_RET 6
`define PC_SPC 6
`define PC_SPC 6
`define RF 13
`define EXEC 10
`define DMEM 4
180,7 → 186,8
`define TMR_IRQ_ADDR 'H80_00_00_28
`define TMR_DATA_ADDR 'H80_00_00_34
`define KEY1_IRQ_ADDR 'H80_00_00_2C
`define KEY2_IRQ_ADDR 'H80_00_00_30
`define KEY2_IRQ_ADDR 'H80_00_00_30
`define DIS_DATA_ADDR 'H80_00_00_34
 
`define COUNTER_VALUE1 (`FRQ/`SER_RATE/2-1)
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
188,10 → 195,9
 
 
 
`define ALTERA
//this is DEBUG model ,
 
`define ALTERA
//this is DEBUG model ,
 
`else
 
 
/trunk/rtl/verilog/mem_module.v
15,92 → 15,135
 
 
module mem_module (
//input [31:0] rt_i,
input pause,
input clk,
input [31:0] din,
input [31:0] dmem_addr_i,
input [3:0] dmem_ctl,
input [31:0] zZ_din,
output [31:0] Zz_addr,
output [31:0] Zz_dout,
output [3:0] Zz_wr_en,
output [31:0] dout
input pause,
input clk,
input [31:0] din,
input [31:0] dmem_addr_i,
input [3:0] dmem_ctl,
input [31:0] zZ_din,
output [31:0] Zz_addr,
output [31:0] Zz_dout,
output [3:0] Zz_wr_en,
output [31:0] dout
) ;
 
/*module r32_reg_clr_cls(
input[`R32_LEN-1:0] r32_i,
output reg[`R32_LEN-1:0] r32_o,
input clk,input clr,input cls
);always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
*/
 
wire [3:0] BUS512;
wire [1:0] BUS629;
wire [31:0] BUS650;
wire [31:0] dmem_addr_i;
wire [31:0] dmem_addr_s;// = dmem_addr_i;
 
wire [31:0]rt_r;
r32_reg_clr_cls rt_latch(
.r32_i(din),
.r32_o(rt_r),
.clk(clk),
.cls(pause),
.clr(0)
);
wire [3:0] dmem_ctl_s;
 
 
wire [31:0]rt_r;
r32_reg_clr_cls rt_latch(
.r32_i(din),
.r32_o(rt_r),
.clk(clk),
.cls(pause),
.clr(0)
);
 
infile_dmem_ctl_reg dmem_ctl_post
( .pause(pause),
.byte_addr_o(BUS629),
.clk(clk),
.ctl_i(dmem_ctl),
.ctl_o(BUS512),
.dmem_addr_i(BUS650)
.byte_addr_o(BUS629),
.clk(clk),
.ctl_i(dmem_ctl_s),
.ctl_o(BUS512),
.dmem_addr_i(dmem_addr_s)
);
 
 
 
mem_addr_ctl i_mem_addr_ctl
(
.addr_i(BUS650),
.ctl(dmem_ctl),
.addr_i(dmem_addr_s),
.ctl(dmem_ctl_s),
.wr_en(Zz_wr_en)
);
 
 
 
wire [31:0] din_s ;
mem_din_ctl i_mem_din_ctl
(
.ctl(dmem_ctl),
.din(din),
.ctl(dmem_ctl_s),
.din(din_s),
.dout(Zz_dout)
);
 
 
 
mem_dout_ctl i_mem_dout_ctl
(
.rt_r(rt_r),
/*
comment this coz the save module will connect to data output.
mem_save u3u(
.clk(clk),
.pause(pause) ,
.din(din),
.dout(din_s)
);
 
*/
 
assign din_s=din;
 
/*
comment this coz the save module will connect to data output.
mem_save u4u(
.clk(clk),
.pause(pause) ,
.din(dmem_ctl),
.dout(dmem_ctl_s)
);
*/
 
 
 
assign dmem_ctl_s = dmem_ctl;
 
/*
comment this coz the save module will connect to data output.
 
mem_save uu(
.clk(clk),
.pause(pause) ,
.din(dmem_addr_i),
.dout(dmem_addr_s)
);
*/
assign dmem_addr_s=dmem_addr_i;
 
 
wire [31:0]dout_s;
 
 
mem_dout_ctl i_mem_dout_ctl
 
(
.rt_r(rt_r),
.byte_addr(BUS629),
.ctl(BUS512),
.din(zZ_din),
.dout(dout)
.dout(dout_s)
);
 
//
b_d_save uu3(
.clk(clk),
.pause(pause) ,
.din(dout_s),
.dout(dout)
);
 
assign Zz_addr= dmem_addr_s;
 
assign BUS650[31:0] = dmem_addr_i[31:0];
endmodule
 
assign Zz_addr[31:0] = BUS650[31:0];
 
endmodule
 
 
module infile_dmem_ctl_reg(
input pause,
 
module infile_dmem_ctl_reg(
input pause,
input clk,
input [3:0]ctl_i,
input [31:0]dmem_addr_i,
112,7 → 155,9
assign byte_addr_i = dmem_addr_i[1:0] ;
 
always @(posedge clk)
if(0==pause)
// if(0==pause)
//the registers in SYN_RAM does not pause so ,
//the latch for delay need not to pause either
begin
ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0;
byte_addr_o<=byte_addr_i;
133,7 → 178,7
0:wr_en = 4'b1000;
1:wr_en = 4'b0100;
2:wr_en = 4'b0010;
3:wr_en = 4'b0001;
3:wr_en = 4'b0001;
endcase
end
`DMEM_SH :
143,25 → 188,25
'd2:wr_en=4'b0011;
default :wr_en = 4'b0000;
endcase
end
`DMEM_SWL :
end
 
`DMEM_SWL :
begin
case(addr_i[1:0])
case(addr_i[1:0])
0:wr_en = 4'b0001;
1:wr_en = 4'b0011;
2:wr_en = 4'b0111;
3:wr_en = 4'b1111;
3:wr_en = 4'b1111;
endcase
end
`DMEM_SWR :
end
 
`DMEM_SWR :
begin
case(addr_i[1:0])
case(addr_i[1:0])
0:wr_en = 4'b1000;
1:wr_en = 4'b1100;
2:wr_en = 4'b1110;
3:wr_en = 4'b1111;
3:wr_en = 4'b1111;
endcase
end
`DMEM_SW :
174,8 → 219,8
endmodule
 
 
module mem_dout_ctl(
input [31:0] rt_r,
module mem_dout_ctl(
input [31:0] rt_r,
input [1:0]byte_addr,
input [3:0]ctl,
input [31:0] din,
188,11 → 233,11
`DMEM_LBS :
case (byte_addr)
 
'd0:dout={{24{din[31]}},din[31:24]};
'd0:dout={{24{din[31]}},din[31:24]};
'd1:dout={{24{din[23]}},din[23:16]};
'd2:dout={{24{din[15]}},din[15:8]};
'd3:dout={{24{din[7]}},din[7:0] };
endcase
endcase
`DMEM_LBU :
case (byte_addr)
'd3:dout={24'b0,din[7:0]};
208,43 → 253,42
endcase
`DMEM_LHS :
case (byte_addr)
'd0 :dout={{16{din[31]}},din[31:24],din[23:16]};
'd0 :dout={{16{din[31]}},din[31:24],din[23:16]};
'd2 :dout={{16{din[15]}},din[15:8],din[7 :0]};
default:dout=32'bX;
endcase
`DMEM_LWL :begin
case (byte_addr)
endcase
 
'd0:dout={din[31:24],rt_r[23:0]};
'd1:dout={din[31:16],rt_r[15:0]};
'd2:dout={din[31:8],rt_r[7:0]};
default :
dout=din;
endcase
end
`DMEM_LWR : begin
case (byte_addr)
'd1:dout={rt_r[31:24],din[23:0]};
'd2:dout={rt_r[31:16],din[15:0]};
'd3:dout={rt_r[31:8],din[7:0]};
default :
dout=din;
endcase
end
`DMEM_LWL :begin
case (byte_addr)
 
'd0:dout={din[31:24],rt_r[23:0]};
'd1:dout={din[31:16],rt_r[15:0]};
'd2:dout={din[31:8],rt_r[7:0]};
default :
dout=din;
endcase
end
`DMEM_LWR : begin
case (byte_addr)
'd1:dout={rt_r[31:24],din[23:0]};
'd2:dout={rt_r[31:16],din[15:0]};
'd3:dout={rt_r[31:8],din[7:0]};
default :
dout=din;
endcase
end
 
`DMEM_LW :
dout=din;
default :
dout=32'b0;
endcase
endcase
 
endmodule
 
module mem_din_ctl(
input [3:0]ctl,
input [31:0]din,
input [31:0]din,
output reg [31:0]dout
);
 
255,26 → 299,9
dout={din[7:0],din[7:0],din[7:0],din[7:0]};
`DMEM_SH :
dout = {din[15:0],din[15:0]};
`DMEM_SWL ,/*:
begin
case(addr_i[1:0])
0:dout = 4'b0001;
1:dout = 4'b0011;
2:dout = 4'b0111;
3:dout = 4'b1111;
endcase
end
*/
`DMEM_SWR ,/* :
begin
case(addr_i[1:0])
0:dout = 4'b1000;
1:dout = 4'b1100;
2:dout = 4'b1110;
3:dout = 4'b1111;
endcase
end */
`DMEM_SW :
`DMEM_SWL ,
`DMEM_SWR ,
`DMEM_SW :
dout =din;
default dout=32'bX;
endcase
/trunk/rtl/verilog/ctl_fsm.v
12,26 → 12,26
******************************************************************/
 
`include "mips789_defs.v"
module ctl_FSM (
input pause,
input clk,
input [2:0] id_cmd,
input irq,
input rst,
output reg iack,
output reg zz_is_nop,
output reg id2ra_ctl_clr,
output reg id2ra_ctl_cls,
output reg id2ra_ins_clr,
output reg id2ra_ins_cls,
output reg [3:0] pc_prectl,
output reg ra2exec_ctl_clr
module ctl_FSM (
input pause,
input clk,
input [2:0] id_cmd,
input irq,
input rst,
output reg iack,
output reg zz_is_nop,
output reg id2ra_ctl_clr,
output reg id2ra_ctl_cls,
output reg id2ra_ins_clr,
output reg id2ra_ins_cls,
output reg [3:0] pc_prectl,
output reg ra2exec_ctl_clr
);
parameter
ID_CUR = `FSM_CUR, ID_LD = `FSM_LD ,
ID_MUL = `FSM_MUL, ID_NOI = `FSM_NOI,
ID_RET = `FSM_RET,
 
PC_IGN = `PC_IGN , PC_IRQ = `PC_IRQ,
PC_KEP = `PC_KEP , PC_RST = `PC_RST;
 
39,7 → 39,7
reg [4:0] CurrState ;
reg [4:0] NextState ;
reg riack;
always @(posedge clk) if (~rst) riack<=0; else riack<=iack;
always @(posedge clk) if (~rst) riack<=0; else riack<=iack;
 
always @(*)
begin //deal with iack
60,14 → 60,14
default : delay_counter <=0;
endcase
 
/////////////////////////////////////////////////////////
// Finite State Machine
//
/*Finite State Machine part1*/
always @ (posedge clk)
if (~rst) CurrState <= `RST;
else if (~pause)
CurrState <= NextState ;
/////////////////////////////////////////////////////////
// Finite State Machine
//
/*Finite State Machine part1*/
always @ (posedge clk)
if (~rst) CurrState <= `RST;
else if (~pause)
CurrState <= NextState ;
 
always @ (*)/*Finite State Machine part2*/
begin
82,7 → 82,7
else if (id_cmd==ID_LD) NextState = `LD;
else if (id_cmd==ID_RET) NextState = `RET;
else NextState = `IDLE;
end
end
`NOI:
begin
if (id_cmd ==ID_NOI) NextState = `NOI;
92,11 → 92,11
else if (id_cmd==ID_RET) NextState = `RET;
else NextState = `IDLE;
end
`CUR: NextState = `NOI;
`RET: NextState = `IDLE;
`IRQ: NextState = `IDLE;
`RST: NextState = `IDLE;
`LD: NextState = `IDLE;
`CUR: NextState = `NOI;
`RET: NextState = `IDLE;
`IRQ: NextState = `IDLE;
`RST: NextState = `IDLE;
`LD: NextState = `IDLE;
`MUL: NextState = (delay_counter==32)?`IDLE:`MUL;
default NextState =`IDLE;
endcase
111,8 → 111,8
id2ra_ctl_cls = 1'b0;
ra2exec_ctl_clr = 1'b0;
pc_prectl=PC_IGN;
zz_is_nop = 0;end
`MUL: begin
zz_is_nop = 0;end
`MUL: begin
id2ra_ins_clr = 1'b1;
id2ra_ins_cls = 1'b0;
id2ra_ctl_clr = 1'b1;
119,8 → 119,8
id2ra_ctl_cls = 1'b0;
ra2exec_ctl_clr = 1'b0;
pc_prectl =PC_KEP;
zz_is_nop =0; end
`CUR: begin
zz_is_nop =0; end
`CUR: begin
id2ra_ins_clr = 1'b0;
id2ra_ins_cls = 1'b1;
id2ra_ctl_clr = 1'b0;
127,15 → 127,15
id2ra_ctl_cls = 1'b1;
ra2exec_ctl_clr = 1'b1;
pc_prectl =PC_KEP;
zz_is_nop = 1; end
`RET: begin id2ra_ins_clr = 1'b0;
zz_is_nop = 1; end
`RET: begin id2ra_ins_clr = 1'b0;
id2ra_ins_cls = 1'b0;
id2ra_ctl_clr = 1'b0;
id2ra_ctl_cls = 1'b0;
ra2exec_ctl_clr = 1'b0;
pc_prectl =PC_IGN;
zz_is_nop = 1'b0; end
`IRQ: begin
zz_is_nop = 1'b0; end
`IRQ: begin
id2ra_ins_clr = 1'b1;
id2ra_ins_cls = 1'b0;
id2ra_ctl_clr = 1'b1;
142,8 → 142,8
id2ra_ctl_cls = 1'b0;
ra2exec_ctl_clr = 1'b1;
pc_prectl =PC_IRQ;
zz_is_nop = 1'b0;end
`RST: begin
zz_is_nop = 1'b0;end
`RST: begin
id2ra_ins_clr = 1'b1;
id2ra_ins_cls = 1'b0;
id2ra_ctl_clr = 1'b1;
150,8 → 150,8
id2ra_ctl_cls = 1'b0;
ra2exec_ctl_clr = 1'b1;
pc_prectl=PC_RST;
zz_is_nop = 1'b1; end
`LD:begin
zz_is_nop = 1'b1; end
`LD:begin
id2ra_ins_clr = 1'b1;
id2ra_ins_cls = 1'b0;
id2ra_ctl_clr = 1'b1;
158,8 → 158,8
id2ra_ctl_cls = 1'b0;
ra2exec_ctl_clr = 1'b0;
pc_prectl =PC_KEP;
zz_is_nop = 1'b0;end
`NOI:begin
zz_is_nop = 1'b0;end
`NOI:begin
id2ra_ins_clr = 1'b0;
id2ra_ins_cls = 1'b0;
id2ra_ctl_clr = 1'b0;
166,8 → 166,8
id2ra_ctl_cls = 1'b0;
ra2exec_ctl_clr = 1'b0;
pc_prectl=PC_IGN;
zz_is_nop = 1'b0;end
default begin
zz_is_nop = 1'b0;end
default begin
id2ra_ins_clr = 1'b1;
id2ra_ins_cls = 1'b0;
id2ra_ctl_clr = 1'b1;
174,8 → 174,8
id2ra_ctl_cls = 1'b0;
ra2exec_ctl_clr = 1'b1;
pc_prectl=PC_RST;
zz_is_nop = 1'b1;end
endcase
zz_is_nop = 1'b1;end
endcase
end
endmodule
 
/trunk/rtl/verilog/RF_stage.v
14,42 → 14,40
`include "mips789_defs.v"
 
module rf_stage (
input pause,
input clk,
input irq_i,
input rst_i,
input wb_we_i,
input [2:0] cmp_ctl_i,
input [2:0] ext_ctl_i,
input [31:0] fw_alu_i,
input [2:0] fw_cmp_rs,
input [2:0] fw_cmp_rt,
input [31:0] fw_mem_i,
input [2:0] id_cmd,
input [31:0] ins_i,
input [31:0] irq_addr_i,
input [2:0] pc_gen_ctl,
input [31:0] pc_i,
input [1:0] rd_sel_i,
input [4:0] wb_addr_i,
input [31:0] wb_din_i,
input [31:0] zz_spc_i,
output iack_o,
output id2ra_ctl_clr_o,
output id2ra_ctl_cls_o,
output ra2ex_ctl_clr_o,
output [31:0] ext_o,
output [31:0] pc_next,
output [4:0] rd_index_o,
output [4:0] rs_n_o,
output [31:0] rs_o,
output [4:0] rt_n_o,
output [31:0] rt_o
input pause,
input clk,
input irq_i,
input rst_i,
input wb_we_i,
input [2:0] cmp_ctl_i,
input [2:0] ext_ctl_i,
input [31:0] fw_alu_i,
input [2:0] fw_cmp_rs,
input [2:0] fw_cmp_rt,
input [31:0] fw_mem_i,
input [2:0] id_cmd,
input [31:0] ins_i,
input [31:0] irq_addr_i,
input [2:0] pc_gen_ctl,
input [31:0] pc_i,
input [1:0] rd_sel_i,
input [4:0] wb_addr_i,
input [31:0] wb_din_i,
input [31:0] zz_spc_i,
output iack_o,
output id2ra_ctl_clr_o,
output id2ra_ctl_cls_o,
output ra2ex_ctl_clr_o,
output [31:0] ext_o,
output [31:0] pc_next,
output [4:0] rd_index_o,
output [4:0] rs_n_o,
output [31:0] rs_o,
output [4:0] rt_n_o,
output [31:0] rt_o
) ;
 
 
 
wire NET6609;
wire NET6658;
wire NET7774;
75,11 → 73,9
.rst(rst_i)
);
 
 
 
ctl_FSM MAIN_FSM
(
.pause(pause),
(
.pause(pause),
.clk(clk),
.iack(iack_o),
.id2ra_ctl_clr(id2ra_ctl_clr_o),
164,28 → 160,19
.rd_i(BUS5421),
.rd_o(rd_index_o),
.rt_i(rt_n_o)
);/*
wire bank_sel;
dly3clk bank_sel_dly
(
.r1_i(iack_o),
.r1_o(bank_sel),
.clk(clk),
.rst(rst_i)
);*/
);
 
reg_array reg_bank
( // .pause(pause),
.clock(clk),
.data(wb_din_i),
.qa(BUS6061),
.qb(BUS6095),
.rd_clk_cls(NET6658),
.rdaddress_a(BUS3237),
.rdaddress_b(BUS3236),
.wraddress(wb_addr_i),
.wren(wb_we_i)/*,
.bank_sel(1'b0)*/
( .pause(pause),
.clock(clk),
.data(wb_din_i),
.qa(BUS6061),
.qb(BUS6095),
.rd_clk_cls(NET6658),
.rdaddress_a(BUS3237),
.rdaddress_b(BUS3236),
.wraddress(wb_addr_i),
.wren(wb_we_i)
);
 
fwd_mux rf_fwd_rt
/trunk/rtl/verilog/mips_top.v
14,6 → 14,7
`include "mips789_defs.v"
 
module mips_top (
input pause,
input clk,
input rst,
input ser_rxd,
47,6 → 48,10
 
wire sys_rst = rr_rst;
 
 
wire [31:0] pc_s ;
wire [31:0] ins2core_s;
 
`ifdef ALTERA
pll50 Ipll(
.inclk0(clk),
56,11 → 61,14
`else
assign CLK = clk;//clock for simultation
sim_mem_array sim_array//memory for simultion
`endif
`endif
 
//assign pc_s=pc;
 
(
.clk(CLK),
.pc_i(pc),
.ins_o(ins2core),
.ins_o(ins2core_s),
.wren(wr_en),
.din(data2mem),
.data_addr_i(mem_Addr),
67,8 → 75,17
.dout(data2core)
);
 
 
b_d_save u2u(
.clk(CLK),
.pause(pause) ,
.din(ins2core_s),
.dout(ins2core)
);
 
mips_sys isys
(
.pause(pause),
.zz_addr_o(mem_Addr),
.zz_din(data2core),
.zz_dout(data2mem),
/trunk/rtl/verilog/decode_pipe.v
966,7 → 966,7
'd34://LWL rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `LWL ;
//replaceID = `LW ;
//replaceID = `LW ;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_RT;
cmp_ctl = `CMP_NOP;
1086,7 → 1086,7
'd42://SWL rt,offset(base) (offset:signed;base:rs)
begin
//replaceID = `SWL ;
ext_ctl = `EXT_SIGN;
ext_ctl = `EXT_SIGN;
rd_sel = `RD_NOP;
cmp_ctl = `CMP_NOP;
pc_gen_ctl = `PC_NEXT;
1157,70 → 1157,39
 
 
 
module pipelinedregs (pause,
clk,id2ra_ctl_clr,id2ra_ctl_cls,ra2ex_ctl_clr,
alu_func_i,alu_we_i,cmp_ctl_i,dmem_ctl_i,ext_ctl_i,
muxa_ctl_i,muxb_ctl_i,pc_gen_ctl_i,rd_sel_i,wb_mux_ctl_i,
wb_we_i,alu_func_o,alu_we_o,cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,
ext_ctl,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,wb_mux_ctl_o,wb_we_o
) ;
input pause;
input clk;
wire clk;
input id2ra_ctl_clr;
wire id2ra_ctl_clr;
input id2ra_ctl_cls;
wire id2ra_ctl_cls;
input ra2ex_ctl_clr;
wire ra2ex_ctl_clr;
input [4:0] alu_func_i;
wire [4:0] alu_func_i;
input [0:0] alu_we_i;
wire [0:0] alu_we_i;
input [2:0] cmp_ctl_i;
wire [2:0] cmp_ctl_i;
input [3:0] dmem_ctl_i;
wire [3:0] dmem_ctl_i;
input [2:0] ext_ctl_i;
wire [2:0] ext_ctl_i;
input [1:0] muxa_ctl_i;
wire [1:0] muxa_ctl_i;
input [1:0] muxb_ctl_i;
wire [1:0] muxb_ctl_i;
input [2:0] pc_gen_ctl_i;
wire [2:0] pc_gen_ctl_i;
input [1:0] rd_sel_i;
wire [1:0] rd_sel_i;
input [0:0] wb_mux_ctl_i;
wire [0:0] wb_mux_ctl_i;
input [0:0] wb_we_i;
wire [0:0] wb_we_i;
output [4:0] alu_func_o;
wire [4:0] alu_func_o;
output [0:0] alu_we_o;
wire [0:0] alu_we_o;
output [2:0] cmp_ctl_o;
wire [2:0] cmp_ctl_o;
output [3:0] dmem_ctl_o;
wire [3:0] dmem_ctl_o;
output [3:0] dmem_ctl_ur_o;
wire [3:0] dmem_ctl_ur_o;
output [2:0] ext_ctl;
wire [2:0] ext_ctl;
output [1:0] muxa_ctl_o;
wire [1:0] muxa_ctl_o;
output [1:0] muxb_ctl_o;
wire [1:0] muxb_ctl_o;
output [2:0] pc_gen_ctl_o;
wire [2:0] pc_gen_ctl_o;
output [1:0] rd_sel_o;
wire [1:0] rd_sel_o;
output [0:0] wb_mux_ctl_o;
wire [0:0] wb_mux_ctl_o;
output [0:0] wb_we_o;
wire [0:0] wb_we_o;
module pipelinedregs (
 
 
input pause,
input clk,
input id2ra_ctl_clr,
input id2ra_ctl_cls,
input ra2ex_ctl_clr,
input [4:0] alu_func_i,
input [0:0] alu_we_i,
input [2:0] cmp_ctl_i,
input [3:0] dmem_ctl_i,
input [2:0] ext_ctl_i,
input [1:0] muxa_ctl_i,
input [1:0] muxb_ctl_i,
input [2:0] pc_gen_ctl_i,
input [1:0] rd_sel_i,
input [0:0] wb_mux_ctl_i,
input [0:0] wb_we_i,
output [4:0] alu_func_o,
output [0:0] alu_we_o,
output [2:0] cmp_ctl_o,
output [3:0] dmem_ctl_o,
output [3:0] dmem_ctl_ur_o,
output [2:0] ext_ctl,
output [1:0] muxa_ctl_o,
output [1:0] muxb_ctl_o,
output [2:0] pc_gen_ctl_o,
output [1:0] rd_sel_o,
output [0:0] wb_mux_ctl_o,
output [0:0] wb_we_o
) ;
wire NET7643;
wire [0:0] BUS4987;
wire [1:0] BUS5008;
1270,86 → 1239,86
 
 
wb_we_reg_clr_cls U12
(
.cls(pause),
.clr(0),
.clk(clk),
.wb_we_i(NET7643),
.wb_we_o(wb_we_o)
);
(
.cls(pause),
.clr(0),
.clk(clk),
.wb_we_i(NET7643),
.wb_we_o(wb_we_o)
);
 
 
 
wb_mux_ctl_reg_clr_cls U13
(
.cls(pause),
.clk(clk),
.clr(ra2ex_ctl_clr),
.wb_mux_ctl_i(BUS5651),
.wb_mux_ctl_o(BUS5690)
);
(
.cls(pause),
.clk(clk),
.clr(ra2ex_ctl_clr),
.wb_mux_ctl_i(BUS5651),
.wb_mux_ctl_o(BUS5690)
);
 
 
 
muxb_ctl_reg_clr_cls U14
(
.clk(clk),.cls(pause),
.clr(ra2ex_ctl_clr),
.muxb_ctl_i(BUS5483),
.muxb_ctl_o(muxb_ctl_o)
);
(
.clk(clk),.cls(pause),
.clr(ra2ex_ctl_clr),
.muxb_ctl_i(BUS5483),
.muxb_ctl_o(muxb_ctl_o)
);
 
 
 
dmem_ctl_reg_clr_cls U15
(
.clk(clk),
(
.clk(clk),
.cls(pause),
.clr(ra2ex_ctl_clr),
.dmem_ctl_i(BUS5666),
.dmem_ctl_o(dmem_ctl_ur_o)
);
.clr(ra2ex_ctl_clr),
.dmem_ctl_i(BUS5666),
.dmem_ctl_o(dmem_ctl_ur_o)
);
 
 
 
alu_func_reg_clr_cls U16
(
.alu_func_i(BUS5674),
.alu_func_o(alu_func_o),
.clk(clk),
(
.alu_func_i(BUS5674),
.alu_func_o(alu_func_o),
.clk(clk),
.cls(pause),
.clr(ra2ex_ctl_clr)
);
.clr(ra2ex_ctl_clr)
);
 
 
 
muxa_ctl_reg_clr_cls U17
(
.cls(pause), .clk(clk),
.clr(ra2ex_ctl_clr),
.muxa_ctl_i(BUS5008),
.muxa_ctl_o(muxa_ctl_o)
);
(
.cls(pause), .clk(clk),
.clr(ra2ex_ctl_clr),
.muxa_ctl_i(BUS5008),
.muxa_ctl_o(muxa_ctl_o)
);
 
 
 
wb_mux_ctl_reg_clr_cls U18
(
.clk(clk), .cls(pause),
.clr(0),
.wb_mux_ctl_i(BUS5790),
.wb_mux_ctl_o(wb_mux_ctl_o)
);
(
.clk(clk), .cls(pause),
.clr(0),
.wb_mux_ctl_i(BUS5790),
.wb_mux_ctl_o(wb_mux_ctl_o)
);
 
 
 
wb_we_reg_clr_cls U19
(
.clk(clk),.cls(pause),
.clr(ra2ex_ctl_clr),
.wb_we_i(BUS5639),
.wb_we_o(BUS5682)
);
(
.clk(clk),.cls(pause),
.clr(ra2ex_ctl_clr),
.wb_we_i(BUS5639),
.wb_we_o(BUS5682)
);
 
 
 
1365,32 → 1334,32
 
 
wb_we_reg_clr_cls U20
(
.clk(clk),.clr(0),.cls(pause),
.wb_we_i(BUS5682),
.wb_we_o(BUS7822)
);
(
.clk(clk),.clr(0),.cls(pause),
.wb_we_i(BUS5682),
.wb_we_o(BUS7822)
);
 
 
 
wb_mux_ctl_reg_clr_cls U21
(
.clk(clk),
.cls(pause),
.clr(0),
.wb_mux_ctl_i(BUS5690),
.wb_mux_ctl_o(BUS5790)
);
(
.clk(clk),
.cls(pause),
.clr(0),
.wb_mux_ctl_i(BUS5690),
.wb_mux_ctl_o(BUS5790)
);
 
 
 
wb_we_reg_clr_cls U22
(
.clk(clk), .cls(pause),
.clr(0),
.wb_we_i(BUS7299),
.wb_we_o(alu_we_o)
);
(
.clk(clk), .cls(pause),
.clr(0),
.wb_we_i(BUS7299),
.wb_we_o(alu_we_o)
);
 
 
 
1398,17 → 1367,17
 
 
alu_we_reg_clr_cls U24
(
.cls(pause),
.alu_we_i(BUS4987),
.alu_we_o(BUS7299),
.clk(clk),
.clr(ra2ex_ctl_clr)
);
(
.cls(pause),
 
.alu_we_i(BUS4987),
.alu_we_o(BUS7299),
.clk(clk),
.clr(ra2ex_ctl_clr)
);
 
 
 
alu_func_reg_clr_cls U26
(
.alu_func_i(alu_func_i),
1487,67 → 1456,43
 
 
dmem_ctl_reg_clr_cls U9
(
.cls(pause),
.clr(0),
.clk(clk),
.dmem_ctl_i(dmem_ctl_ur_o),
.dmem_ctl_o(dmem_ctl_o)
);
(
 
.cls(pause),
.clr(0),
.clk(clk),
.dmem_ctl_i(dmem_ctl_ur_o),
.dmem_ctl_o(dmem_ctl_o)
);
 
 
 
endmodule
 
module decode_pipe
module decode_pipe
(
pause,
clk,id2ra_ctl_clr,id2ra_ctl_cls,
ra2ex_ctl_clr,ins_i,alu_func_o,alu_we_o,
cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,ext_ctl_o,
fsm_dly,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,
wb_mux_ctl_o,wb_we_o
) ;
input pause;
input clk;
wire clk;
input id2ra_ctl_clr;
wire id2ra_ctl_clr;
input id2ra_ctl_cls;
wire id2ra_ctl_cls;
input ra2ex_ctl_clr;
wire ra2ex_ctl_clr;
input [31:0] ins_i;
wire [31:0] ins_i;
output [4:0] alu_func_o;
wire [4:0] alu_func_o;
output [0:0] alu_we_o;
wire [0:0] alu_we_o;
output [2:0] cmp_ctl_o;
wire [2:0] cmp_ctl_o;
output [3:0] dmem_ctl_o;
wire [3:0] dmem_ctl_o;
output [3:0] dmem_ctl_ur_o;
wire [3:0] dmem_ctl_ur_o;
output [2:0] ext_ctl_o;
wire [2:0] ext_ctl_o;
output [2:0] fsm_dly;
wire [2:0] fsm_dly;
output [1:0] muxa_ctl_o;
wire [1:0] muxa_ctl_o;
output [1:0] muxb_ctl_o;
wire [1:0] muxb_ctl_o;
output [2:0] pc_gen_ctl_o;
wire [2:0] pc_gen_ctl_o;
output [1:0] rd_sel_o;
wire [1:0] rd_sel_o;
output [0:0] wb_mux_ctl_o;
wire [0:0] wb_mux_ctl_o;
output [0:0] wb_we_o;
wire [0:0] wb_we_o;
 
 
input pause,
input clk,
input id2ra_ctl_clr,
input id2ra_ctl_cls,
input ra2ex_ctl_clr,
input [31:0] ins_i,
output [4:0] alu_func_o,
output [0:0] alu_we_o,
output [2:0] cmp_ctl_o,
output [3:0] dmem_ctl_o,
output [3:0] dmem_ctl_ur_o,
output [2:0] ext_ctl_o,
output [2:0] fsm_dly,
output [1:0] muxa_ctl_o,
output [1:0] muxb_ctl_o,
output [2:0] pc_gen_ctl_o,
output [1:0] rd_sel_o,
output [0:0] wb_mux_ctl_o,
output [0:0] wb_we_o
) ;
wire [4:0] BUS2040;
wire [0:0] BUS2048;
wire [2:0] BUS2056;
1582,11 → 1527,11
 
pipelinedregs pipereg
(
.pause(pause),
.pause(pause),
.id2ra_ctl_cls(id2ra_ctl_cls),
.id2ra_ctl_clr(id2ra_ctl_clr),
.ra2ex_ctl_clr(ra2ex_ctl_clr),
 
.alu_func_i(BUS2040),
.alu_func_o(alu_func_o),
.alu_we_i(BUS2048),
1599,15 → 1544,13
.dmem_ctl_ur_o(dmem_ctl_ur_o),
.ext_ctl(ext_ctl_o),
.ext_ctl_i(BUS2072),
 
.muxa_ctl_i(BUS2086),
.muxa_ctl_o(muxa_ctl_o),
.muxb_ctl_i(BUS2094),
.muxb_ctl_o(muxb_ctl_o),
.pc_gen_ctl_i(BUS2102),
.pc_gen_ctl_o(pc_gen_ctl_o),
.pc_gen_ctl_o(pc_gen_ctl_o),
.rd_sel_i(BUS2110),
.rd_sel_o(rd_sel_o),
.wb_mux_ctl_i(BUS2118),
1616,8 → 1559,6
.wb_we_o(wb_we_o)
);
 
 
 
endmodule
 
 
/trunk/rtl/verilog/mips_uart.v
23,45 → 23,45
endmodule
 
module uart0 (
input clk,
input rst,
input rxd_ft,
input ser_rxd,
input txd_ld,
input [7:0] din,
output rxd_rdy,
output ser_txd,
output txd_busy,
output [7:0] dout
);
input clk,
input rst,
input rxd_ft,
input ser_rxd,
input txd_ld,
input [7:0] din,
output rxd_rdy,
output ser_txd,
output txd_busy,
output [7:0] dout
 
);
 
 
 
 
wire clk_uart=clk;
wire w_rxd_rdy;
integer uart_send;
initial begin
wire w_rxd_rdy;
 
 
uart_send = $fopen("uart_send.txt");
integer uart_send;
initial begin
 
end
 
always @ (txd_ld)
begin
if (txd_ld)
begin
$fwrite( uart_send,"%c",din[7:0]);
$display("UART0 =>%c<",din[7:0]);
end
end
 
uart_send = $fopen("uart_send.txt");
 
 
end
 
always @ (txd_ld)
begin
if (txd_ld)
begin
$fwrite( uart_send,"%c",din[7:0]);
$display("UART0 =>%c<",din[7:0]);
end
end
 
uart_read uart_rd_tak(
.sync_reset(rst),
.clk(clk),
101,8 → 101,6
output txd,write_done;
output write_busy;
 
 
 
wire queue_full;
wire queing, read_request;
wire [7:0] queue_data;
155,7 → 153,7
.q(queue_data),
.full(queue_full),
.empty(empty),
.rst(sync_reset));
.rst(sync_reset));
`endif
 
 
/trunk/rtl/verilog/forward.v
47,30 → 47,27
case (fw_ctl)
`FW_ALU :dout=fw_alu;
`FW_MEM :dout=fw_dmem;
default
/*`FW_NOP :dout=din;*/
dout=din;
default
dout=din;
endcase
endmodule
 
module forward (
input pause,
input alu_we,
input clk,
input mem_We,
input [4:0] fw_alu_rn,
input [4:0] fw_mem_rn,
input [4:0] rns_i,
input [4:0] rnt_i,
output [2:0] alu_rs_fw,
output [2:0] alu_rt_fw,
output [2:0] cmp_rs_fw,
output [2:0] cmp_rt_fw,
output [2:0] dmem_fw
) ;
input pause,
input alu_we,
input clk,
input mem_We,
input [4:0] fw_alu_rn,
input [4:0] fw_mem_rn,
input [4:0] rns_i,
input [4:0] rnt_i,
output [2:0] alu_rs_fw,
output [2:0] alu_rt_fw,
output [2:0] cmp_rs_fw,
output [2:0] cmp_rt_fw,
output [2:0] dmem_fw
) ;
 
 
 
wire [2:0] BUS1345;
wire [4:0] BUS82;
wire [4:0] BUS937;
124,21 → 121,24
 
 
r5_reg_clr_cls fw_reg_rns
(
.clk(clk),.cls(pause),.clr(0),
.r5_i(rns_i),
.r5_o(BUS82)
);
(
.clk(clk),
.cls(pause),
.clr(0),
.r5_i(rns_i),
.r5_o(BUS82)
);
 
 
 
r1_reg_clr_cls fw_reg_rnt
(
.cls(pause),.clr(0),
.clk(clk),
.r1_i(rnt_i),
.r1_o(BUS937)
);
r5_reg_clr_cls fw_reg_rnt
(
.cls(pause),
.clr(0),
.clk(clk),
.r5_i(rnt_i),
.r5_o(BUS937)
);
 
 
assign alu_rt_fw[2:0] = BUS1345[2:0];
/trunk/rtl/verilog/mips_dvc.v
71,6 → 71,13
wire ld_wd = (mem_ctl==`DMEM_LW);
 
 
wire wr_dis_byte = addr==`DIS_DATA_ADDR && sv_byte;
 
always @ (posedge clk)
begin
if ( wr_dis_byte ) $display("HEX=>%x< CHAR=>%c<",din[7:0],din[7:0]);
end
 
wire wr_uartdata = addr==`UART_DATA_ADDR && sv_byte;
wire wr_lcddata = addr==`LCD_DATA_ADDR && sv_byte;
wire rd_uartdata = addr==`UART_DATA_ADDR && ld_byte;
112,6 → 119,9
wire w_txd_busy;
wire w_rx_rdy;
 
 
 
 
always@(posedge clk )
if (~rst)
begin
126,6 → 136,8
dout<=0;
end
 
 
 
always @(posedge clk)
if (~rst)
begin
/trunk/rtl/verilog/mips_sys.v
16,84 → 16,47
 
 
module mips_sys (
input pause,
input key1,
input key2,
 
zz_addr_o,
zz_din,
zz_dout,
zz_ins_i,
zz_pc_o,
zz_wr_en_o ,
input clk,
input rst,
output [6:0] seg7led1,
output [6:0] seg7led2,
 
clk,
rst,
output [7:0]lcd_data,
output lcd_rs,
output lcd_rw ,
output lcd_en ,
output led1,
output led2,
 
ser_rxd,
ser_txd,
input [31:0] zz_din,
input [31:0] zz_ins_i,
output [31:0] zz_addr_o,
output [31:0] zz_dout,
output [31:0] zz_pc_o,
output [3:0] zz_wr_en_o,
 
seg7led1,
seg7led2 ,
input ser_rxd,
output ser_txd
 
lcd_data,
lcd_rs,
lcd_rw,
lcd_en,
 
led1,
led2,
 
key1,
key2
 
) ;
input key1;
input key2;
 
input clk;
wire clk;
 
input rst;
wire rst;
 
 
output [6:0] seg7led1;
wire [6:0] seg7led1;
output [6:0] seg7led2;
wire [6:0] seg7led2;
 
output [7:0]lcd_data;
output lcd_rs;
output lcd_rw ;
output lcd_en ;
output led1;
output led2;
 
 
input [31:0] zz_din;
wire [31:0] zz_din;
input [31:0] zz_ins_i;
wire [31:0] zz_ins_i;
output [31:0] zz_addr_o;
wire [31:0] zz_addr_o;
output [31:0] zz_dout;
wire [31:0] zz_dout;
output [31:0] zz_pc_o;
wire [31:0] zz_pc_o;
output [3:0] zz_wr_en_o;
wire [3:0] zz_wr_en_o;
 
input ser_rxd;
output ser_txd;
 
wire [31:0] cop_addr;
wire [3:0] cop_mem_ctl;
wire [31:0] data2cop;
wire [31:0]cop_data;
wire clk_sys=clk;
wire [31:0]irq_addr;
wire [31:0]irq_addr;
wire w_irq;
 
mips_core i_mips_core
(
.pause(pause),
.clk(clk_sys),
.cop_addr_o(cop_addr),
.cop_data_o(data2cop),
/trunk/rtl/verilog/EXEC_stage.v
14,50 → 14,30
`include "mips789_defs.v"
 
module exec_stage
( pause,
clk,rst,spc_cls_i,alu_func,
dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
dmem_data_ur_o,zz_spc_o
(
input pause,
input clk,
input rst,
input spc_cls_i,
input [4:0] alu_func,
input [2:0] dmem_fw_ctl,
input [31:0] ext_i,
input [31:0] fw_alu,
input [31:0] fw_dmem,
input [1:0] muxa_ctl_i,
input [2:0] muxa_fw_ctl,
input [1:0] muxb_ctl_i,
// input [2:0] muxb_fw_ctl,
input [31:0] pc_i,
input [31:0] rs_i,
input [31:0] rt_i,
output [31:0] alu_ur_o,
output [31:0] dmem_data_ur_o ,
output [31:0] zz_spc_o
 
 
 
);
input pause;
input clk;
wire clk;
input rst;
wire rst;
input spc_cls_i;
wire spc_cls_i;
input [4:0] alu_func;
wire [4:0] alu_func;
input [2:0] dmem_fw_ctl;
wire [2:0] dmem_fw_ctl;
input [31:0] ext_i;
wire [31:0] ext_i;
input [31:0] fw_alu;
wire [31:0] fw_alu;
input [31:0] fw_dmem;
wire [31:0] fw_dmem;
input [1:0] muxa_ctl_i;
wire [1:0] muxa_ctl_i;
input [2:0] muxa_fw_ctl;
wire [2:0] muxa_fw_ctl;
input [1:0] muxb_ctl_i;
wire [1:0] muxb_ctl_i;
input [2:0] muxb_fw_ctl;
wire [2:0] muxb_fw_ctl;
input [31:0] pc_i;
wire [31:0] pc_i;
input [31:0] rs_i;
wire [31:0] rs_i;
input [31:0] rt_i;
wire [31:0] rt_i;
output [31:0] alu_ur_o;
wire [31:0] alu_ur_o;
output [31:0] dmem_data_ur_o;
wire [31:0] dmem_data_ur_o;
output [31:0] zz_spc_o;
wire [31:0] zz_spc_o;
 
wire [31:0] BUS2332;
wire [31:0] BUS2446;
66,14 → 46,14
 
 
mips_alu MIPS_alu
(
.a(BUS476),
.b(BUS468),
.c(alu_ur_o),
.clk(clk),
.ctl(alu_func),
.rst(rst)
);
(
.a(BUS476),
.b(BUS468),
.c(alu_ur_o),
.clk(clk),
.ctl(alu_func),
.rst(rst)
);
 
add32 add4
(
90,27 → 70,14
.fw_dmem(fw_dmem),
.din(rt_i)
);
/* alu_muxb1 i_alu_muxb
 
 
 
alu_muxb i_alu_muxb
(
.b_o(BUS468),
.ctl(muxb_ctl_i),
.ext(ext_i),
.fw_alu(fw_alu),
.fw_ctl(muxb_fw_ctl),
.fw_mem(fw_dmem),
.rt(rt_i)
);
*/
alu_muxb i_alu_muxb
(
.b_o(BUS468),
.ctl(muxb_ctl_i),
.ext(ext_i),
// .fw_alu(fw_alu),
// .fw_ctl(muxb_fw_ctl),
// .fw_mem(fw_dmem),
.rt(dmem_data_ur_o)
);
 
135,23 → 102,24
 
 
r32_reg_clr_cls pc_nxt
(
.cls(pause),
.clr(0),
.clk(clk),
.r32_i(BUS2446),
.r32_o(BUS2332)
);
(
.cls(pause),
.clr(0),
.clk(clk),
.r32_i(BUS2446),
.r32_o(BUS2332)
);
 
 
 
r32_reg_clr_cls spc
(
.clk(clk),.clr(0),
.cls(spc_cls_i|pause),
.r32_i(pc_i),
.r32_o(zz_spc_o)
);
(
.clk(clk),
.clr(0),
.cls(spc_cls_i|pause),
.r32_i(pc_i),
.r32_o(zz_spc_o)
);
 
endmodule
 
188,19 → 156,19
.func(ctl)
);
*/
/* shifter_ff mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
*/ shifter_tak mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
/* */
/* shifter_ff mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
*/ shifter_tak mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
/* */
 
 
alu mips_alu(
237,14 → 205,14
endmodule
 
module alu_muxb(
input [31:0] rt,
input [31:0] rt,
input [31:0]ext ,
input [1:0]ctl ,
input [1:0]ctl ,
output reg [31:0] b_o
);
always@(*)
case (ctl)
// `MUXB_RT :b_o =rt; //(fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
// `MUXB_RT :b_o =rt; //(fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
`MUXB_EXT : b_o=ext;
default b_o=rt;
endcase
255,11 → 223,11
//This file is based on YACC ->alu.v and UCORE ->alu.v
 
module alu (
input [31:0] a,
input [31:0]b,
output reg [31:0] alu_out,
input [4:0] alu_func
);
input [31:0] a,
input [31:0]b,
output reg [31:0] alu_out,
input [4:0] alu_func
);
 
reg [32:0] sum;
 
316,11 → 284,11
 
 
module shifter_tak(
input [31:0] a,
output reg [31:0] shift_out,
input [4:0] shift_func,//connect to alu_func_ctl
input [31:0] shift_amount//connect to b
);
input [31:0] a,
output reg [31:0] shift_out,
input [4:0] shift_func,//connect to alu_func_ctl
input [31:0] shift_amount//connect to b
);
 
always @ (*)
case( shift_func )
491,10 → 459,10
begin
mul_bit=0;
div_bit=0;
 
hi=32'bx;
lo=32'bx;
 
negative_output = 0;
end
else

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