OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 46 to Rev 47
    ↔ Reverse comparison
  •

Rev 46 → Rev 47

/opencpu32/trunk/hdl/opencpu32/openCpu.vhd
37,7 → 37,7
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
muxRegFile : in dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
45,7 → 45,7
regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
dpFlags : out STD_LOGIC_VECTOR (2 downto 0));
end COMPONENT;
 
COMPONENT ControlUnit is
56,7 → 56,7
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
outEnDp : out typeEnDis; --! Enable/Disable datapath output
MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
MuxRegDp : out dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
DpAluOp : out aluOps; --! Alu operations
DpRegFileWriteAddr : out generalRegisters; --! General register address to write
77,7 → 77,7
signal enableOutputDp : typeEnDis;
signal aluOperations : aluOps;
signal InputDataPathSelector : dpMuxInputs;
signal InputDataPathAluASelector : STD_LOGIC_VECTOR (1 downto 0);
signal InputDataPathAluASelector : dpMuxAluIn;
signal registerFileWriteAddress : generalRegisters;
signal registerFileWriteEnable : STD_LOGIC;
signal registerFileReadAddressA : generalRegisters;
/opencpu32/trunk/hdl/opencpu32/Multiplexer3_1.vhd
17,7 → 17,7
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
sel : in STD_LOGIC_VECTOR(1 downto 0); --! Select inputs (1, 2, 3)
sel : in dpMuxAluIn; --! Select inputs (fromMemory, fromImediate, fromRegFileA)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
end Multiplexer3_1;
 
27,9 → 27,9
 
begin
with sel select
S <= A when "00",
B when "01",
C when "10",
S <= A when fromMemory,
B when fromImediate,
C when fromRegFileA,
(others => 'Z') when others;
 
end Behavioral;
/opencpu32/trunk/hdl/opencpu32/ControlUnit.vhd
24,7 → 24,7
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
outEnDp : out typeEnDis; --! Enable/Disable datapath output
MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
MuxRegDp : out dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
DpAluOp : out aluOps; --! Alu operations
DpRegFileWriteAddr : out generalRegisters; --! General register address to write
238,7 → 238,7
-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
MuxDp <= fromAlu;
MuxRegDp <= muxRegPos(fromRegFileA);
MuxRegDp <= fromRegFileA;
DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2))); -- Read second operand
DpRegFileReadEnA <= '1';
257,7 → 257,7
-- ADD r3,2 (r2 <= r2+2) (See the testDatapath to see how to drive the datapath for this function)
when add_val | sub_val | and_val | or_val | xor_val =>
MuxDp <= fromAlu;
MuxRegDp <= muxRegPos(fromImediate);
MuxRegDp <= fromImediate;
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
DpRegFileReadEnB <= '1';
/opencpu32/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/testControlUnit.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/ControlUnit.vhd&quot; into library work</arg>
</msg>
 
</messages>
/opencpu32/trunk/hdl/opencpu32/opencpu32.gise
61,16 → 61,39
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="Alu_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Alu_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="ControlUnit.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="ControlUnit.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="ControlUnit.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ControlUnit.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="ControlUnit.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="ControlUnit.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="ControlUnit.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="ControlUnit.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="ControlUnit.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="ControlUnit.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ControlUnit.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="ControlUnit.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="ControlUnit.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="ControlUnit.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="ControlUnit.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="ControlUnit.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="ControlUnit.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="ControlUnit.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="ControlUnit.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="ControlUnit_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="ControlUnit_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ControlUnit_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ControlUnit_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ControlUnit_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="ControlUnit_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ControlUnit_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ControlUnit_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="ControlUnit_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="ControlUnit_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ControlUnit_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="ControlUnit_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="ControlUnit_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="ControlUnit_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ControlUnit_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ControlUnit_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="DataPath.bld"/>
232,7 → 255,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334678325" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334678325">
<transform xil_pn:end_ts="1334733522" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334733522">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
252,19 → 275,19
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334678810" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334678810">
<transform xil_pn:end_ts="1334733522" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334733522">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334678810" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334678810">
<transform xil_pn:end_ts="1334733522" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334733522">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334652206" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1334652206">
<transform xil_pn:end_ts="1334733522" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1334733522">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334678325" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334678325">
<transform xil_pn:end_ts="1334733522" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334733522">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
284,7 → 307,7
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334678812" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334678810">
<transform xil_pn:end_ts="1334733524" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334733522">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
296,11 → 319,9
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1334678812" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2257473906977297968" xil_pn:start_ts="1334678812">
<transform xil_pn:end_ts="1334733525" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2257473906977297968" xil_pn:start_ts="1334733524">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testOpenCpu_isim_beh.wdb"/>
309,6 → 330,57
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6268642977942111103" xil_pn:start_ts="1334733483">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1334733483">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1334733483">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5126426351813824259" xil_pn:start_ts="1334733483">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1334733483">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4767545221551224753" xil_pn:start_ts="1334733483">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733498" xil_pn:in_ck="-3059529097558291903" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-1259764691931299582" xil_pn:start_ts="1334733483">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="ControlUnit.ngr"/>
<outfile xil_pn:name="DataPath.ngr"/>
<outfile xil_pn:name="Multiplexer4_1.ngr"/>
<outfile xil_pn:name="RegisterFile.ngr"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="openCpu.lso"/>
<outfile xil_pn:name="openCpu.ngc"/>
<outfile xil_pn:name="openCpu.ngr"/>
<outfile xil_pn:name="openCpu.prj"/>
<outfile xil_pn:name="openCpu.stx"/>
<outfile xil_pn:name="openCpu.syr"/>
<outfile xil_pn:name="openCpu.xst"/>
<outfile xil_pn:name="openCpu_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1334733392" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8790877965723852007" xil_pn:start_ts="1334733392">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
</transforms>
 
</generated_project>
/opencpu32/trunk/hdl/opencpu32/DataPath.vhd
23,7 → 23,7
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
muxRegFile : in dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
56,7 → 56,7
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
sel : in STD_LOGIC_VECTOR(1 downto 0); --! Select inputs (1, 2, 3)
sel : in dpMuxAluIn; --! Select inputs (fromMemory, fromImediate, fromRegFileA)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
end COMPONENT;
 
/opencpu32/trunk/hdl/opencpu32/testDataPath.vhd
28,7 → 28,7
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
muxRegFile : in dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
47,7 → 47,7
signal outEn : typeEnDis := disable; --! Wire to connect Test signal to component
signal aluOp : aluOps := alu_pass; --! Wire to connect Test signal to component
signal muxSel : dpMuxInputs := fromMemory; --! Wire to connect Test signal to component
signal muxRegFile : std_logic_vector(1 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
signal muxRegFile : dpMuxAluIn := fromMemory; --! Wire to connect Test signal to component
signal regFileWriteAddr : generalRegisters := r0; --! Wire to connect Test signal to component
signal regFileWriteEn : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileReadAddrA : generalRegisters := r0; --! Wire to connect Test signal to component
101,7 → 101,7
regFileWriteAddr <= r0;
aluOp <= alu_pass;
muxSel <= fromImediate;
muxRegFile <= muxRegPos(fromRegFileA);
muxRegFile <= fromRegFileA;
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
-- Read value in r0 to verify if is equal to 20
125,7 → 125,7
regFileWriteAddr <= r1;
aluOp <= alu_pass;
muxSel <= fromImediate;
muxRegFile <= muxRegPos(fromRegFileA);
muxRegFile <= fromRegFileA;
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
-- Read value in r1 to verify if is equal to 20
149,7 → 149,7
regFileEnB <= '1';
regFileWriteAddr <= r2; -- Write data in r2
muxSel <= fromRegFileB; -- Select the PortB output from regFile
muxRegFile <= muxRegPos(fromRegFileA);
muxRegFile <= fromRegFileA;
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
-- Read value in r2 to verify if is equal to r1(20)
176,7 → 176,7
aluOp <= alu_sum;
regFileWriteAddr <= r2; -- Write data in r2
muxSel <= fromAlu; -- Select the Alu output
muxRegFile <= muxRegPos(fromRegFileA);
muxRegFile <= fromRegFileA;
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
-- Read value in r2 to verify if is equal to 30(10+20)
204,7 → 204,7
aluOp <= alu_sum;
regFileWriteAddr <= r3; -- Write data in r2
muxSel <= fromAlu; -- Select the Alu output
muxRegFile <= muxRegPos(fromRegFileA);
muxRegFile <= fromRegFileA;
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
-- Read value in r2 to verify if is equal to 30(10+20)
228,7 → 228,7
regFileReadAddrB <= r3; -- Read data from r2
regFileEnB <= '1';
regFileWriteAddr <= r3;
muxRegFile <= muxRegPos(fromImediate);
muxRegFile <= fromImediate;
aluOp <= alu_sum;
muxSel <= fromAlu; -- Select the Alu output
regFileWriteEn <= '1';

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