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common/trunk/220_edif-1_usage.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: common/trunk/220_verilog_usage.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: common/trunk/220_verilog_usage.pdf =================================================================== --- common/trunk/220_verilog_usage.pdf (nonexistent) +++ common/trunk/220_verilog_usage.pdf (revision 48)

common/trunk/220_verilog_usage.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: common/trunk/220_count4_example.vhd =================================================================== --- common/trunk/220_count4_example.vhd (nonexistent) +++ common/trunk/220_count4_example.vhd (revision 48) @@ -0,0 +1,44 @@ +-------------------------------------------------------------------------- +-- Copyright (c) 1996 Altera Corporation, all right reserved +-- +-- This VHDL file may be copied and/or distributed at no cost as long as +-- this copyright notice is retained. +-- +------------------------------------------------------------------ +-- Four-bit Loadable Up-Down Counter with synchronous set, load and clear +------------------------------------------------------------------ +-- Version 1.0 Date 05/20/96 +------------------------------------------------------------------ +-- +library IEEE; +use IEEE.std_logic_1164.all; +use work.lpm_components.all; + +entity COUNT4 is + port (DATA : in std_logic_vector(3 downto 0); + CLOCK : in std_logic; + CLK_EN : in std_logic; + CNT_EN : in std_logic; + UPDOWN : in std_logic; + SLOAD : in std_logic; + SSET : in std_logic; + SCLR : in std_logic; + ALOAD : in std_logic; + ASET : in std_logic; + ACLR : in std_logic; + EQ : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end COUNT4; + +architecture LPM of COUNT4 is + +begin + + U1: LPM_COUNTER + generic map (LPM_WIDTH => 4) + port map (DATA => DATA, CLOCK => CLOCK, CLK_EN => CLK_EN, + CNT_EN => CNT_EN, UPDOWN => UPDOWN, SLOAD => SLOAD, + SSET => SSET, SCLR => SCLR, ALOAD => ALOAD, ASET => ASET, + ACLR => ACLR, Q => Q); +end; + Index: common/trunk/220_convert_hex2ver_pli.c =================================================================== --- common/trunk/220_convert_hex2ver_pli.c (nonexistent) +++ common/trunk/220_convert_hex2ver_pli.c (revision 48) @@ -0,0 +1,319 @@ +#include +#include +#include +#include "veriuser.h" +#include "acc_user.h" + +#define TRUE 1 +#define FALSE 0 +#define MAX_BUFFER_SZ 2048 +#define MAX_NAME_SZ 128 +#define OUT_FILE_EXT ".ver" +#define COLON ':' +#define OFFSET 9 +#define H10 0x10L +#define AWORD 8 +#define WORDS_PER_LINE 8 +#define MASK15 0x000000FFL +#define EXT_STR ".ver" + +typedef enum { + OK = 0, + WARNING = 1, + ERROR = 2 +}STATUS; +static int line_no = 0; +/******************************************************************** + * char* trimAlteraExt(char* oldName, char* newName) + * oldName : original file name. + * newName : new file name which doesnt have file extension. + * + * This function trims the file extension + * Looks for first "." and trims the file name afterwords. +********************************************************************/ + +char* trimAlteraExt(oldName, newName) +char* oldName; +char* newName; +{ + char tempStr[MAX_BUFFER_SZ]; + char* tempPtr=NULL; + + newName[0]='\0'; + if(oldName[0]=='\0') + return NULL; + strcpy(tempStr, oldName); + if(tempPtr = strstr(tempStr, ".")) + { + *tempPtr = '\0'; + } + strcpy(newName, tempStr); + return newName; +} + +/****************************************************************/ +int display_msg(status, str, data_file) +STATUS status; +char *str; +char *data_file; +{ + switch(status) + { + case WARNING: + printf("WARNING: %s, %s\n\n", data_file, str); + break; + case ERROR: + printf("ERROR:%s, line %d, %s\n\n", data_file, line_no, str); + break; + default: + break; + } + return(TRUE); +} +/**************************************************************** + char *ltrim(str) + char *str; + Deletes leading blanks in string 'str' +****************************************************************/ +char *ltrim(str) +char *str; +{ + int i = 0,j = 0; + + /* Illeagal application. Returns NULL. */ + if (str == 0) return(0); + /* Deletes leading blanks */ + while (*(str + i) == ' ' || *(str + i) == '\n' || *(str + i) == '\t' || *(str + i) == '\b') i++; + for (; *(str + i) != '\0'; i++,j++) *(str + j) = *(str + i); + /* Appends a NULL character to the end of the string */ + *(str + j) = '\0'; + + return(str); +} + +/**************************************************************** + * Function: write_ver_data + * Description: This function ensures that each char (in hex) + * represents a nibble of the data. + * For example if (width<5) we need to output only 1 char hex. +****************************************************************/ +void write_ver_data(ofp, width, data) +FILE *ofp; +int width; +char *data; +{ + int num_nibbles; + int num_hex; + + num_nibbles = (width%4?(width/4 + 1):width/4); + num_hex = num_nibbles/2; + + while (num_hex--) + { + fprintf(ofp, "%c%c", data[0], data[1]); + data +=2; + } + /* NB: we skip the leading '0' in data[0]. */ + if (num_nibbles&1) fprintf(ofp, "%c", data[1]); +} + +/**************************************************************** +Function: write_data +Description: Write ROM data in the verilog format so that + it can be read using readmemh(infile, rom) +Format: example data format for the 8 bit data + @1 + 01 02 03 04 05 06 07 08 + @a + 0a 0b 0c +****************************************************************/ +int write_data(ofp, nn, aaaa, off_addr, dddd, width) +FILE *ofp; +long nn, aaaa, off_addr; +char *dddd; +int width; +{ + int count, i; + char data[MAX_BUFFER_SZ +1]; + int num_hexs, nibbles ; + + + if((width % AWORD) == 0) + { + num_hexs = width/AWORD; + } + else + { + num_hexs = (width/AWORD) + 1; + } + + fprintf(ofp, "@%x\n", aaaa + off_addr); + + nibbles = num_hexs*2; + count = 1; + while(nn > 0) + { + if(nn >= num_hexs) + { + strncpy(data, dddd, nibbles); + data[nibbles] = '\0'; + } + else + { + for(i = 0; i < (num_hexs - nn); i++) + { + sprintf(data + i*2, "%s", "00"); + } + strcat(data + (num_hexs - nn), dddd); + } + write_ver_data(ofp, width, data); + if(count < WORDS_PER_LINE) + { + count ++; + } + else + { + fprintf(ofp, "\n"); + count = 1; + } + dddd = dddd + nibbles; + nn -= num_hexs; + } + if(count > 1) + fprintf(ofp, "\n"); + + +} +/****************************************************************/ +/* Convert Intel-hex format data to verilog format data */ +/* Intel-hex format :nnaaaaattddddcc */ +/****************************************************************/ +convert_hex2ver() +{ + char buffer[MAX_BUFFER_SZ +1]; + char out_file[MAX_NAME_SZ +1]; + char init_filename[MAX_NAME_SZ +1]; + char dddd[MAX_BUFFER_SZ +1]; + char *in_file, *out_str; + + FILE *ifp, *ofp; + int i ; + int done = FALSE; + int first_rec = FALSE; + int last_rec = FALSE; + int width ; + long off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ; + handle wrk; + static s_setval_value user_s = {accStringVal}; + static s_setval_delay delay ; + + off_addr= nn= aaaa= tt= cc= aah= aal= dd= sum = 0; + + in_file = (char *)tf_getcstringp(1); + width = tf_getp(2); + trimAlteraExt(in_file, out_file); + strcat(out_file, OUT_FILE_EXT); + if ((ifp = fopen(in_file, "r")) == NULL) + { + printf("cannot read %s\n", in_file); + fclose(ifp); + return; + } + if ((ofp = fopen(out_file, "w")) == NULL) + { + printf("cannot write %s\n", out_file); + fclose(ofp); + return; + } + while(!done) + { + if(fgets(buffer, MAX_BUFFER_SZ, ifp) == NULL) + { + if(!first_rec) + done = display_msg(WARNING, "Intel-hex data file is empty.", in_file); + else if(!last_rec) + done = display_msg(ERROR, "Missing the last record.", in_file); + } + else if(strlen(ltrim(buffer)) == 0) + { + line_no++; + } + else if(buffer && (buffer[0] == COLON)) + { + line_no++; + first_rec = TRUE; + sscanf(buffer+1,"%02x%04x%02x", &nn, &aaaa, &tt); + if((tt == 2) && (nn != 2) ) + { + done = display_msg(ERROR, "Invalid data record.", in_file); + } + else + { + sscanf(buffer+3,"%02x%02x", &aah, &aal); + sum = nn + aah + aal + tt ; + for(i = 0; i < nn; i++) + { + sscanf(buffer+OFFSET+i*2, "%02x", &dd); + sprintf(dddd+i*2, "%02x", dd); + sum += dd; + } + sscanf(buffer+OFFSET+i*2, "%02x\n", &cc); + + switch(tt) { + case 0x00: /* normal_record */ + first_rec = TRUE; + if(((~sum + 1)& MASK15) == cc) + { + write_data(ofp, nn, aaaa, off_addr, dddd,width); + off_addr = 0; + } + else + { + done = display_msg(ERROR, "Invalid checksum.", in_file); + } + break; + case 0x01: /* last record */ + last_rec = TRUE; + if(((~sum+1)&MASK15) != cc) + { + display_msg(ERROR, "Invalid checksum.", in_file); + } + done = TRUE; + break; + case 0x02: /* address base record */ + sscanf(dddd,"%x\n", &off_addr); + if(((~sum +1)& MASK15) == cc) + { + off_addr *= H10; + } + else + { + done = display_msg(ERROR, "Invalid checksum.", in_file); + } + break; + default: + done = display_msg(ERROR, "Unknown record type.", in_file); + break; + } /* switch */ + } + } + else + { + line_no++; + display_msg(ERROR, "Invalid INTEL HEX record", in_file); + done = TRUE; + } + } + fclose(ifp); + fclose(ofp); + /* append EXT_STR to the input string and pass it back in arg 1 */ + delay.model = accNoDelay; + wrk = acc_handle_tfarg(3); + trimAlteraExt(in_file, init_filename); + strcat(init_filename, EXT_STR); + user_s.value.str = init_filename; + acc_set_value(wrk, &user_s, &delay); + + return(0); +} + Index: common/trunk/220_cells_specification.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: common/trunk/220_cells_specification.pdf =================================================================== --- common/trunk/220_cells_specification.pdf (nonexistent) +++ common/trunk/220_cells_specification.pdf (revision 48)

common/trunk/220_cells_specification.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: common/trunk/220_vhdl_declarations.htm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: common/trunk/220_vhdl_declarations.htm =================================================================== --- common/trunk/220_vhdl_declarations.htm (nonexistent) +++ common/trunk/220_vhdl_declarations.htm (revision 48)

common/trunk/220_vhdl_declarations.htm Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: common/trunk/220_vhdl_models.vhd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: common/trunk/220_vhdl_models.vhd =================================================================== --- common/trunk/220_vhdl_models.vhd (nonexistent) +++ common/trunk/220_vhdl_models.vhd (revision 48)

common/trunk/220_vhdl_models.vhd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: common/trunk/LPM_pads.v =================================================================== --- common/trunk/LPM_pads.v (nonexistent) +++ common/trunk/LPM_pads.v (revision 48) @@ -0,0 +1,217 @@ +//------------------------------------------------------------------------ +// This Verilog file was developed by Altera Corporation. It may be +// freely copied and/or distributed at no cost. Any persons using this +// file for any purpose do so at their own risk, and are responsible for +// the results of such use. Altera Corporation does not guarantee that +// this file is complete, correct, or fit for any particular purpose. +// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must +// accompany any copy of this file. +// +//------------------------------------------------------------------------ +// Imported to Opencores directory. Date Sept 10, 2001 +// Split related modules into separate files, as the manual splits them. +// Added example instantiations to the beginning of each file. +// +/* EXAMPLE INSTANTIATIONS: + +lpm_inpad +#( 1 // lpm_width (width of input) + ) lpm_inpad_example ( + .pad (data_in[lpm_width-1:0]), + .result (data_out[lpm_width-1:0]) +); + +lpm_outpad +#( 1 // lpm_width (width of input) + ) lpm_outpad_example ( + .pad (data_out[lpm_width-1:0]), + .data (data_in[lpm_width-1:0]) +); + +lpm_bipad +#( 1 // lpm_width (width of input) + ) lpm_bipad_example ( + .pad (data_bi[lpm_width-1:0]), + .result (data_out[lpm_width-1:0]), + .data (data_in[lpm_width-1:0]), + .enable (oe_data_to_pad) +); +*/ + +//------------------------------------------------------------------------ +// LPM Synthesizable Models +//------------------------------------------------------------------------ +// Version 1.5 (lpm 220) Date 12/17/99 +// +// Modified LPM_ADD_SUB and LPM_MULT to accomodate LPM_WIDTH = 1. +// Default values for LPM_WIDTH* are changed back to 1. +// Added LPM_HINT to LPM_DIVIDE. +// Rewritten LPM_FIFO_DC to output correctly. +// Modified LPM_FIFO to output 0s before first read, output correct +// values after aclr and sclr, and output LPM_NUMWORDS mod +// exp(2, LPM_WIDTHU) when FIFO is full. +// +//------------------------------------------------------------------------ +// Version 1.4.1 (lpm 220) Date 10/29/99 +// +// Default values for LPM_WIDTH* of LPM_ADD_SUB and LPM_MULT are changed +// from 1 to 2. +// +//------------------------------------------------------------------------ +// Version 1.4 (lpm 220) Date 10/18/99 +// +// Default values for each optional inputs for ALL modules are added. +// Some LPM_PVALUE implementations were missing, and now implemented. +// +//------------------------------------------------------------------------ +// Version 1.3 (lpm 220) Date 06/23/99 +// +// Corrected LPM_FIFO and LPM_FIFO_DC cout and empty/full flags. +// Implemented LPM_COUNTER cin/cout, and LPM_MODULUS is now working. +// +//------------------------------------------------------------------------ +// Version 1.2 (lpm 220) Date 06/16/99 +// +// Added LPM_RAM_DP, LPM_RAM_DQ, LPM_IO, LPM_ROM, LPM_FIFO, LPM_FIFO_DC. +// Parameters and ports are added/discarded according to the spec. +// +//------------------------------------------------------------------------ +// Version 1.1 (lpm 220) Date 02/05/99 +// +// Added LPM_DIVIDE module. +// +//------------------------------------------------------------------------ +// Version 1.0 Date 07/09/97 +// +//------------------------------------------------------------------------ +// Excluded Functions: +// +// LPM_FSM and LPM_TTABLE. +// +//------------------------------------------------------------------------ +// Assumptions: +// +// 1. LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS, +// LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE default value is +// string UNUSED. +// +//------------------------------------------------------------------------ +// Verilog Language Issues: +// +// Two dimensional ports are not supported. Modules with two dimensional +// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH) +// bits wide. +// +//------------------------------------------------------------------------ +// Synthesis Issues: +// +// 1. LPM_COUNTER +// +// Currently synthesis tools do not allow mixing of level and edge +// sensetive signals. To overcome that problem the "data" signal is +// removed from the clock always block of lpm_counter, however the +// synthesis result is accurate. For correct simulation add the "data" +// pin to the sensetivity list as follows: +// +// always @(posedge clock or posedge aclr or posedge aset or +// posedge aload or data) +//------------------------------------------------------------------------ + +module lpm_inpad ( result, pad ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_width = 1; + parameter lpm_type = "lpm_inpad"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + input [lpm_width-1:0] pad; + output [lpm_width-1:0] result; + + reg [lpm_width-1:0] result; + + always @(pad) + begin + result = pad; + end + +// Check for previous Parameter declaration order +initial if ((lpm_width === "lpm_inpad") || (lpm_type !== "lpm_inpad")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_inpad + +//------------------------------------------------------------------------ + +module lpm_outpad ( data, pad ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_width = 1; + parameter lpm_type = "lpm_outpad"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + input [lpm_width-1:0] data; + output [lpm_width-1:0] pad; + + reg [lpm_width-1:0] pad; + + always @(data) + begin + pad = data; + end + +// Check for previous Parameter declaration order +initial if ((lpm_width === "lpm_outpad") || (lpm_type !== "lpm_outpad")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_outpad + +//------------------------------------------------------------------------ + +module lpm_bipad ( result, pad, data, enable ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_width = 1; + parameter lpm_type = "lpm_bipad"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + input [lpm_width-1:0] data; + input enable; + inout [lpm_width-1:0] pad; + output [lpm_width-1:0] result; + + reg [lpm_width-1:0] tmp_pad; + reg [lpm_width-1:0] result; + + always @(data or pad or enable) + begin + if (enable == 1) + begin + tmp_pad = data; + result = 'bz; + end + else if (enable == 0) + begin + result = pad; + tmp_pad = 'bz; + end + end + + assign pad = tmp_pad; + +// Check for previous Parameter declaration order +initial if ((lpm_width === "lpm_bipad") || (lpm_type !== "lpm_bipad")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_bipad Index: common/trunk/LPM_edif_usage_example.htm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: common/trunk/LPM_edif_usage_example.htm =================================================================== --- common/trunk/LPM_edif_usage_example.htm (nonexistent) +++ common/trunk/LPM_edif_usage_example.htm (revision 48)

common/trunk/LPM_edif_usage_example.htm Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: common/trunk/LPM_arithmetic.v =================================================================== --- common/trunk/LPM_arithmetic.v (nonexistent) +++ common/trunk/LPM_arithmetic.v (revision 48) @@ -0,0 +1,989 @@ +//------------------------------------------------------------------------ +// This Verilog file was developed by Altera Corporation. It may be +// freely copied and/or distributed at no cost. Any persons using this +// file for any purpose do so at their own risk, and are responsible for +// the results of such use. Altera Corporation does not guarantee that +// this file is complete, correct, or fit for any particular purpose. +// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must +// accompany any copy of this file. +// +//------------------------------------------------------------------------ +// Imported to Opencores directory. Date Sept 10, 2001 +// Split related modules into separate files, as the manual splits them. +// Added example instantiations to the beginning of each file. +// +/* EXAMPLE INSTANTIATIONS: + +lpm_add_sub +#( 1, // lpm_width (width of input vector) + "UNUSED", // lpm_direction, optional, {ADD, SUB} + "UNSIGNED", // lpm_representation, optional, {UNSIGNED, SIGNED} + 0 // lpm_pipeline, optional, {0, 1} + ) lpm_add_sub_example ( + .result (data_out[lpm_width-1:0]), + .cout (carry_out_indicates_unsigned_result_too_big), // OPTIONAL + .overflow (overflow_indicates_MSB_sign_bit_wrong), // OPTIONAL + .dataa (data_in[lpm_width-1:0]), + .datab (data_pl_mi_in[lpm_width-1:0]), + .cin (add_1_if_HIGH_sub_1_if_LOW), // OPTIONAL + .add_sub (add_if_HIGH_must_set_HIGH_if_using_lpm_direction), // OPTIONAL + .clock (clock_if_pipelined), // OPTIONAL + .clken (clock_enable_HIGH_if_pipelined), // OPTIONAL + .aclr (async_clear_if_pipelined) // OPTIONAL +); + +lpm_compare +#( 1, // lpm_width (width of input vector) + "UNSIGNED", // lpm_representation, optional, {UNSIGNED, SIGNED} + 0 // lpm_pipeline, optional, {0, 1} + ) lpm_compare_example ( + .agb (a_greater_than_b), + .ageb (a_greater_or_equil_to_b), + .aeb (a_equil_to_b), + .aleb (a_less_or_equil_to_b), + .alb (a_less_than_b), + .aneb (a_not_equil_b), + .dataa (data_in_a[lpm_width-1:0]), + .datab (data_in_a[lpm_width-1:0]), + .clock (clock_if_pipelined), // OPTIONAL + .clken (clock_enable_HIGH_if_pipelined), // OPTIONAL + .aclr (async_clear_if_pipelined) // OPTIONAL +); + +module lpm_mult ( +#( 1, // lpm_widtha (width of input vector) + 1, // lpm_widthb (width of input vector) + 1, // lpm_widths (width of partial sum vector) + 1, // lpm_widthp (width of product vector) + "UNSIGNED", // lpm_representation, optional, {UNSIGNED, SIGNED} + 0 // lpm_pipeline, optional, {0, 1} + ) lpm_mult_example ( + .result (data_out[lpm_widthp-1:0]), + .sum (partial_sum_in[lpm_widths-1:0]), // OPTIONAL + .dataa (multiplicand_a_in[lpm_widtha-1:0]), + .datab (multiplicand_b_in[lpm_widthb-1:0]), + .clock (clock_if_pipelined), // OPTIONAL + .clken (clock_enable_HIGH_if_pipelined), // OPTIONAL + .aclr (async_clear_if_pipelined) // OPTIONAL +); + +lpm_divide +#( 1, // lpm_widthn (width of numerator) + 1, // lpm_widthn (width of denominator) + "UNSIGNED", // lpm_nrepresentation, optional, {UNSIGNED, SIGNED} + "UNSIGNED", // lpm_drepresentation, optional, {UNSIGNED, SIGNED} + 0 // lpm_pipeline, optional, {0, 1} + ) lpm_divide_example ( + .quotient (data_out[lpm_widthn-1:0]), // CHOICE + .remain (data_out[lpm_widthd-1:0]), // CHOICE + .numer (data_out[lpm_widthn-1:0]), + .denom (data_out[lpm_widthd-1:0]), + .clock (clock_if_pipelined), // OPTIONAL + .clken (clock_enable_HIGH_if_pipelined), // OPTIONAL + .aclr (async_clear_if_pipelined) // OPTIONAL +); + +lpm_abs +#( 1 // lpm_width (width of input) + ) lpm_abs_example ( + .result (data_out[lpm_width-1:0]), + .overflow (overflow_because_negative_number_was_max), // OPTIONAL + .data (data_in[lpm_width-1:0]) +); + +module lpm_counter ( +#( 1, // lpm_width (width of input) + 0, // lpm_modulus (max count plus 1) + "UNUSED", // lpm_direction, optional, {UNUSED, UP, DOWN} + "UNUSED", // lpm_avalue, value to load if ASET active + "UNUSED", // lpm_svalue, value to load if SSET active + "UNUSED", // lpm_pvalue, value to load at powerup + "lpm_counter", // lpm_type, optional, must be "lpm_counter if lpm_hint used + "UNUSED" // lpm_hint, optional, {UNSIGNED, SIGNED, BCD, GRAY_CODE, JOHNSON, LFSR} + ) lpm_counter_example ( + .cout (max_value_reached), // CHOICE + .q (counter_out[lpm_width-1:0]), // CHOICE + .data (sync_data_in[lpm_width-1:0]), // OPTIONAL + .sload (load_counter_with_data_next_clock), // OPTIONAL + .sset (set_counter_to_max_or_lpm_svalue_next_clock), // OPTIONAL + .sclr (clear_counter_next_clock), // OPTIONAL + .cnt_en (enable_counting_when_HIGH), // OPTIONAL + .cin (carry_in_to_enable_counter), // OPTIONAL + .updown (inc_if_HIGH_must_set_LOW_if_using_lpm_direction), // OPTIONAL + .clock (clock_if_pipelined), + .clk_en (enable_all_sync_activity_when_HIGH), // OPTIONAL + .aload (async_load_counter_with_data), // OPTIONAL + .aset (async_set_counter_to_max_or_lpm_avalue), // OPTIONAL + .aclr (async_clear_if_pipelined) // OPTIONAL +); +*/ + +//------------------------------------------------------------------------ +// LPM Synthesizable Models +//------------------------------------------------------------------------ +// Version 1.5 (lpm 220) Date 12/17/99 +// +// Modified LPM_ADD_SUB and LPM_MULT to accomodate LPM_WIDTH = 1. +// Default values for LPM_WIDTH* are changed back to 1. +// Added LPM_HINT to LPM_DIVIDE. +// Rewritten LPM_FIFO_DC to output correctly. +// Modified LPM_FIFO to output 0s before first read, output correct +// values after aclr and sclr, and output LPM_NUMWORDS mod +// exp(2, LPM_WIDTHU) when FIFO is full. +// +//------------------------------------------------------------------------ +// Version 1.4.1 (lpm 220) Date 10/29/99 +// +// Default values for LPM_WIDTH* of LPM_ADD_SUB and LPM_MULT are changed +// from 1 to 2. +// +//------------------------------------------------------------------------ +// Version 1.4 (lpm 220) Date 10/18/99 +// +// Default values for each optional inputs for ALL modules are added. +// Some LPM_PVALUE implementations were missing, and now implemented. +// +//------------------------------------------------------------------------ +// Version 1.3 (lpm 220) Date 06/23/99 +// +// Corrected LPM_FIFO and LPM_FIFO_DC cout and empty/full flags. +// Implemented LPM_COUNTER cin/cout, and LPM_MODULUS is now working. +// +//------------------------------------------------------------------------ +// Version 1.2 (lpm 220) Date 06/16/99 +// +// Added LPM_RAM_DP, LPM_RAM_DQ, LPM_IO, LPM_ROM, LPM_FIFO, LPM_FIFO_DC. +// Parameters and ports are added/discarded according to the spec. +// +//------------------------------------------------------------------------ +// Version 1.1 (lpm 220) Date 02/05/99 +// +// Added LPM_DIVIDE module. +// +//------------------------------------------------------------------------ +// Version 1.0 Date 07/09/97 +// +//------------------------------------------------------------------------ +// Excluded Functions: +// +// LPM_FSM and LPM_TTABLE. +// +//------------------------------------------------------------------------ +// Assumptions: +// +// 1. LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, and LPM_NUMWORDS, +// LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE default value is +// string UNUSED. +// +//------------------------------------------------------------------------ +// Verilog Language Issues: +// +// Two dimensional ports are not supported. Modules with two dimensional +// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH) +// bits wide. +// +//------------------------------------------------------------------------ +// Synthesis Issues: +// +// 1. LPM_COUNTER +// +// Currently synthesis tools do not allow mixing of level and edge +// sensetive signals. To overcome that problem the "data" signal is +// removed from the clock always block of lpm_counter, however the +// synthesis result is accurate. For correct simulation add the "data" +// pin to the sensetivity list as follows: +// +// always @(posedge clock or posedge aclr or posedge aset or +// posedge aload or data) +//------------------------------------------------------------------------ + +module lpm_add_sub ( result, cout, overflow, + add_sub, cin, dataa, datab, clock, clken, aclr ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_width = 1; + parameter lpm_direction = "UNUSED"; + parameter lpm_representation = "UNSIGNED"; + parameter lpm_pipeline = 0; + parameter lpm_type = "lpm_add_sub"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + input [lpm_width-1:0] dataa, datab; + input add_sub, cin; + input clock; + input clken; + input aclr; + output [lpm_width-1:0] result; + output cout, overflow; + + reg [lpm_width-1:0] tmp_result; + reg [lpm_width-1:0] tmp_result2 [lpm_pipeline:0]; + reg [lpm_pipeline:0] tmp_cout2; + reg [lpm_pipeline:0] tmp_overflow2; + reg tmp_cout; + reg tmp_overflow; + reg [lpm_width-1:0] tmp_a, tmp_b; + integer i, j, k, n; + integer dataa_int, datab_int, result_int, compare, borrow; + + tri0 aclr; + tri0 clock; + tri1 clken; + tri0 cin; + tri1 add_sub; + + buf (i_aclr, aclr); + buf (i_clock, clock); + buf (i_clken, clken); + buf (i_cin, cin); + buf (i_add_sub, add_sub); + + + always @(i_cin or dataa or datab or i_add_sub) + begin + borrow = i_cin ? 0 : 1; + // cout is the same for both signed and unsign representation. + if (lpm_direction == "ADD" || i_add_sub == 1) + begin + {tmp_cout,tmp_result} = dataa + datab + i_cin; + tmp_overflow = tmp_cout; + end + else if (lpm_direction == "SUB" || i_add_sub == 0) + begin + // subtraction + {tmp_overflow, tmp_result} = dataa - datab - borrow; + tmp_cout = (dataa >= (datab+borrow))?1:0; + end + + if (lpm_representation == "SIGNED") + begin + // convert to negative integer + if (dataa[lpm_width-1] == 1) + begin + for (j = 0; j < lpm_width; j = j + 1) + tmp_a[j] = dataa[j] ^ 1; + dataa_int = (tmp_a) * (-1) - 1; + end + else + dataa_int = dataa; + + // convert to negative integer + if (datab[lpm_width-1] == 1) + begin + for (k = 0; k < lpm_width; k = k + 1) + tmp_b[k] = datab[k] ^ 1; + datab_int = (tmp_b) * (-1) - 1; + end + else + datab_int = datab; + + // perform the addtion or subtraction operation + if (lpm_direction == "ADD" || i_add_sub == 1) + result_int = dataa_int + datab_int + i_cin; + else if (lpm_direction == "SUB" || i_add_sub == 0) + result_int = dataa_int - datab_int - borrow; + tmp_result = result_int; + + // set the overflow + compare = 1 << (lpm_width -1); + if ((result_int > (compare - 1)) || (result_int < (-1)*(compare))) + tmp_overflow = 1; + else + tmp_overflow = 0; + end + end + + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) + begin + for (i = 0; i <= lpm_pipeline; i = i + 1) + begin + tmp_result2[i] = 'b0; + tmp_cout2[i] = 1'b0; + tmp_overflow2[i] = 1'b0; + end + end + else if (i_clken == 1) + begin + tmp_result2[lpm_pipeline] = tmp_result; + tmp_cout2[lpm_pipeline] = tmp_cout; + tmp_overflow2[lpm_pipeline] = tmp_overflow; + for (n = 0; n < lpm_pipeline; n = n + 1) + begin + tmp_result2[n] = tmp_result2[n+1]; + tmp_cout2[n] = tmp_cout2[n+1]; + tmp_overflow2[n] = tmp_overflow2[n+1]; + end + end + end + + + assign result = (lpm_pipeline >0) ? tmp_result2[0]:tmp_result; + assign cout = (lpm_pipeline >0) ? tmp_cout2[0] : tmp_cout; + assign overflow = (lpm_pipeline >0) ? tmp_overflow2[0] : tmp_overflow; + +// Check for previous Parameter declaration order +initial if ((lpm_width === "lpm_add_sub") || (lpm_type !== "lpm_add_sub")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_add_sub + +//------------------------------------------------------------------------ + +module lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, + clock, clken, aclr ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_width = 1; + parameter lpm_representation = "UNSIGNED"; + parameter lpm_pipeline = 0; + parameter lpm_type = "lpm_compare"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + input [lpm_width-1:0] dataa, datab; + input clock; + input clken; + input aclr; + output alb, aeb, agb, aleb, aneb, ageb; + + reg tmp_alb, tmp_aeb, tmp_agb; + reg tmp_aleb, tmp_aneb, tmp_ageb; + reg [lpm_pipeline:0] tmp_alb2, tmp_aeb2, tmp_agb2; + reg [lpm_pipeline:0] tmp_aleb2, tmp_aneb2, tmp_ageb2; + reg [lpm_width-1:0] a_int; + integer i, j, k, l, m, n, o, p, u, dataa_int, datab_int; + + tri0 aclr; + tri0 clock; + tri1 clken; + + buf (i_aclr, aclr); + buf (i_clock, clock); + buf (i_clken, clken); + + + always @(dataa or datab) + begin + if (lpm_representation == "UNSIGNED") + begin + dataa_int = dataa[lpm_width-1:0]; + datab_int = datab[lpm_width-1:0]; + end + else if (lpm_representation == "SIGNED") + begin + // convert to negative integer + if (dataa[lpm_width-1] == 1) + begin + for (j = 0; j < lpm_width; j = j + 1) + a_int[j] = dataa[j] ^ 1; + dataa_int = (a_int) * (-1) - 1; + end + else + dataa_int = dataa; + + // convert to negative integer + if (datab[lpm_width-1] == 1) + begin + for (j = 0; j < lpm_width; j = j + 1) + a_int[j] = datab[j] ^ 1; + datab_int = (a_int) * (-1) - 1; + end + else + datab_int = datab; + end + + tmp_alb = (dataa_int < datab_int); + tmp_aeb = (dataa_int == datab_int); + tmp_agb = (dataa_int > datab_int); + tmp_aleb = (dataa_int <= datab_int); + tmp_aneb = (dataa_int != datab_int); + tmp_ageb = (dataa_int >= datab_int); + end + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) + begin + for (u = 0; u <= lpm_pipeline; u = u +1) + begin + tmp_aeb2[u] = 'b0; + tmp_agb2[u] = 'b0; + tmp_alb2[u] = 'b0; + tmp_aleb2[u] = 'b0; + tmp_aneb2[u] = 'b0; + tmp_ageb2[u] = 'b0; + end + end + else if (i_clken == 1) + begin + // Assign results to registers + tmp_alb2[lpm_pipeline] = tmp_alb; + tmp_aeb2[lpm_pipeline] = tmp_aeb; + tmp_agb2[lpm_pipeline] = tmp_agb; + tmp_aleb2[lpm_pipeline] = tmp_aleb; + tmp_aneb2[lpm_pipeline] = tmp_aneb; + tmp_ageb2[lpm_pipeline] = tmp_ageb; + + for (k = 0; k < lpm_pipeline; k = k +1) + tmp_alb2[k] = tmp_alb2[k+1]; + for (l = 0; l < lpm_pipeline; l = l +1) + tmp_aeb2[l] = tmp_aeb2[l+1]; + for (m = 0; m < lpm_pipeline; m = m +1) + tmp_agb2[m] = tmp_agb2[m+1]; + for (n = 0; n < lpm_pipeline; n = n +1) + tmp_aleb2[n] = tmp_aleb2[n+1]; + for (o = 0; o < lpm_pipeline; o = o +1) + tmp_aneb2[o] = tmp_aneb2[o+1]; + for (p = 0; p < lpm_pipeline; p = p +1) + tmp_ageb2[p] = tmp_ageb2[p+1]; + end + end + + assign alb = (lpm_pipeline > 0) ? tmp_alb2[0] : tmp_alb; + assign aeb = (lpm_pipeline > 0) ? tmp_aeb2[0] : tmp_aeb; + assign agb = (lpm_pipeline > 0) ? tmp_agb2[0] : tmp_agb; + assign aleb = (lpm_pipeline > 0) ? tmp_aleb2[0] : tmp_aleb; + assign aneb = (lpm_pipeline > 0) ? tmp_aneb2[0] : tmp_aneb; + assign ageb = (lpm_pipeline > 0) ? tmp_ageb2[0] : tmp_ageb; + +// Check for previous Parameter declaration order +initial if ((lpm_width === "lpm_compare") || (lpm_type !== "lpm_compare")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_compare + +//------------------------------------------------------------------------ + +module lpm_mult ( result, dataa, datab, sum, clock, clken, aclr ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_widtha = 1; + parameter lpm_widthb = 1; + parameter lpm_widths = 1; + parameter lpm_widthp = 1; + parameter lpm_representation = "UNSIGNED"; + parameter lpm_pipeline = 0; + parameter lpm_type = "lpm_mult"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + input clock; + input clken; + input aclr; + input [lpm_widtha-1:0] dataa; + input [lpm_widthb-1:0] datab; + input [lpm_widths-1:0] sum; + output [lpm_widthp-1:0] result; + + // inernal reg + reg [lpm_widthp-1:0] tmp_result; + reg [lpm_widthp-1:0] tmp_result2 [lpm_pipeline:0]; + reg [lpm_widtha-1:0] a_int; + reg [lpm_widthb-1:0] b_int; + reg [lpm_widths-1:0] s_int; + reg [lpm_widthp-1:0] p_reg; + integer p_int; + integer i, j, k, m, n, p, maxs_mn; + integer int_dataa, int_datab, int_sum, int_result; + + tri0 aclr; + tri0 clock; + tri1 clken; + + buf (i_aclr, aclr); + buf (i_clock, clock); + buf (i_clken, clken); + + + always @(dataa or datab or sum) + begin + if (lpm_representation == "UNSIGNED") + begin + int_dataa = dataa; + int_datab = datab; + int_sum = sum; + end + else if (lpm_representation == "SIGNED") + begin + // convert signed dataa + if (dataa[lpm_widtha-1] == 1) + begin + for (i = 0; i < lpm_widtha; i = i + 1) + a_int[i] = dataa[i] ^ 1; + int_dataa = (a_int) * (-1) - 1; + end + else + int_dataa = dataa; + + // convert signed datab + if (datab[lpm_widthb-1] == 1) + begin + for (j = 0; j < lpm_widthb; j = j + 1) + b_int[j] = datab[j] ^ 1; + int_datab = (b_int) * (-1) - 1; + end + else + int_datab = datab; + + // convert signed sum + if (sum[lpm_widths-1] == 1) + begin + for (k = 0; k < lpm_widths; k = k + 1) + s_int[k] = sum[k] ^ 1; + int_sum = (s_int) * (-1) - 1; + end + else + int_sum = sum; + end + else + begin + int_dataa = {lpm_widtha{1'bx}}; + int_datab = {lpm_widthb{1'bx}}; + int_sum = {lpm_widths{1'bx}}; + end + + p_int = int_dataa * int_datab + int_sum; + maxs_mn = ((lpm_widtha+lpm_widthb)>lpm_widths)?lpm_widtha+lpm_widthb:lpm_widths; + if (lpm_widthp >= maxs_mn) + tmp_result = p_int; + else + begin + p_reg = p_int; + for (m = 0; m < lpm_widthp; m = m + 1) + tmp_result[lpm_widthp-1-m] = p_reg[maxs_mn-1-m]; + end + end + + always @(posedge i_clock or posedge i_aclr) + begin + if (i_aclr) + begin + for (p = 0; p <= lpm_pipeline; p = p + 1) + tmp_result2[p] = 'b0; + end + else if (i_clken == 1) + begin :syn_block + tmp_result2[lpm_pipeline] = tmp_result; + for (n = 0; n < lpm_pipeline; n = n +1) + tmp_result2[n] = tmp_result2[n+1]; + end + end + + assign result = (lpm_pipeline > 0) ? tmp_result2[0] : tmp_result; + +// Check for previous Parameter declaration order +initial if ((lpm_widtha === "lpm_mult") || (lpm_type !== "lpm_mult")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_mult + +//------------------------------------------------------------------------ + +module lpm_divide ( quotient,remain, numer, denom, clock, clken, aclr ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_widthn = 1; + parameter lpm_widthd = 1; + //parameter lpm_widthq = 1; + //parameter lpm_widthr = 1; + parameter lpm_nrepresentation = "UNSIGNED"; + parameter lpm_drepresentation = "UNSIGNED"; + parameter lpm_pipeline = 0; + parameter lpm_type = "lpm_divide"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + input clock; + input clken; + input aclr; + input [lpm_widthn-1:0] numer; + input [lpm_widthd-1:0] denom; + output [lpm_widthn-1:0] quotient; + output [lpm_widthd-1:0] remain; + + // inernal reg + reg [lpm_widthn-1:0] tmp_quotient [lpm_pipeline:0]; + reg [lpm_widthd-1:0] tmp_remain [lpm_pipeline:0]; + reg [lpm_widthn-1:0] ONES, ZEROS, UNKNOWN, HiZ; + reg [lpm_widthd-1:0] DZEROS, DUNKNOWN; + reg [lpm_widthn-1:0] NUNKNOWN; + reg [lpm_widthd-1:0] RZEROS ; + integer i; + integer int_numer, int_denom, int_quotient, int_remain; + + tri0 aclr; + tri0 clock; + tri1 clken; + + buf (i_aclr, aclr); + buf (i_clock, clock); + buf (i_clken, clken); + + + initial + begin + + // check if lpm_widthn > 0 + if (lpm_widthn <= 0) + $display("%t: Error! LPM_WIDTHN must be greater than 0.\n", $time); + // check if lpm_widthd > 0 + if (lpm_widthd <= 0) + $display("%t: Error! LPM_WIDTHD must be greater than 0.\n", $time); + // check if lpm_widthn > 0 + //if (lpm_widthq <= 0) + // $display("%t: Error! LPM_WIDTHQ must be greater than 0.\n", $time); + // check if lpm_widthR > 0 + //if (lpm_widthr <= 0) + // $display("%t: Error! LPM_WIDTHR must be greater than 0.\n", $time); + // check for valid lpm_nrep value + if ((lpm_nrepresentation !== "SIGNED") && (lpm_nrepresentation !== "UNSIGNED")) + $display("%t: Error! LPM_NREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".", $time); + + // check for valid lpm_drep value + if ((lpm_drepresentation !== "SIGNED") && (lpm_drepresentation !== "UNSIGNED")) + $display("%t: Error! LPM_DREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".", $time); + + // check if lpm_pipeline is > 1 and clock is not used + if ((lpm_pipeline >=1) && (clock === 1'bz)) + $display("%t: Error! The clock pin is requied if lpm_pipeline is used\n", $time); + else if ((lpm_pipeline == 0) && (clock !== 1'bz)) + $display("%t: Error! If the clock pin is used, lpm_pipeline must be greater than 0.\n", $time); + + for (i=0; i < lpm_widthn; i=i+1) + begin + ONES[i] = 1'b1; + ZEROS[i] = 1'b0; + UNKNOWN[i] = 1'bx; + HiZ[i] = 1'bz; + end + + for (i=0; i < lpm_widthd; i=i+1) + DUNKNOWN[i] = 1'bx; + + for (i=0; i < lpm_widthn; i=i+1) + NUNKNOWN[i] = 1'bx; + + for (i=0; i < lpm_widthd; i=i+1) + RZEROS[i] = 1'b0; + + end + + always @(numer or denom) + begin + if (lpm_nrepresentation == "UNSIGNED") + int_numer = numer; + else if (lpm_nrepresentation == "SIGNED") + begin + // convert signed numer + if (numer[lpm_widthn-1] == 1) + begin + int_numer = 0; + for (i = 0; i < lpm_widthn - 1; i = i + 1) + int_numer[i] = numer[i] ^ 1; + int_numer = -(int_numer + 1); + end + else + int_numer = numer; + end + else + int_numer = NUNKNOWN; + + if (lpm_drepresentation == "UNSIGNED") + int_denom = denom; + else if (lpm_drepresentation == "SIGNED") + begin + // convert signed denom + if (denom[lpm_widthd-1] == 1) + begin + int_denom = 0; + for (i = 0; i < lpm_widthd - 1; i = i + 1) + int_denom[i] = denom[i] ^ 1; + int_denom = -(int_denom + 1); + end + else + int_denom = denom; + end + else + int_denom = DUNKNOWN; + + int_quotient = int_numer / int_denom; + int_remain = int_numer % int_denom; + + tmp_quotient[lpm_pipeline] = int_quotient; + tmp_remain[lpm_pipeline] = int_remain; + end + + always @(posedge i_clock or i_aclr) + begin :syn_block + if (i_aclr) + begin + disable syn_block; + for (i = 0; i <= lpm_pipeline; i = i + 1) + tmp_quotient[i] = ZEROS; + tmp_remain[i] = RZEROS; + end + else if (i_clken) + for (i = 0; i < lpm_pipeline; i = i +1) + begin + tmp_quotient[i] = tmp_quotient[i+1]; + tmp_remain[i] = tmp_remain[i+1]; + end + end + + assign quotient = tmp_quotient[0]; + assign remain = tmp_remain[0]; + +// Check for previous Parameter declaration order +initial if ((lpm_widthn === "lpm_divide") || (lpm_type !== "lpm_divide")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_divide + +//------------------------------------------------------------------------ + +module lpm_abs ( result, overflow, data ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_width = 1; + parameter lpm_type = "lpm_abs"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + input [lpm_width-1:0] data; + output [lpm_width-1:0] result; + output overflow; + + reg [lpm_width-1:0] a_int; + reg [lpm_width-1:0] result; + reg overflow; + integer i; + + always @(data) + begin + overflow = 0; + if (data[lpm_width-1] == 1) + begin + for (i = 0; i < lpm_width; i = i + 1) + a_int[i] = data[i] ^ 1; + result = (a_int + 1); + overflow = (result == ( 1<<(lpm_width -1))); + end + else + result = data; + end + +// Check for previous Parameter declaration order +initial if ((lpm_width === "lpm_abs") || (lpm_type !== "lpm_abs")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_abs + +//------------------------------------------------------------------------ + +module lpm_counter ( q, data, clock, cin, cout,clk_en, cnt_en, updown, + aset, aclr, aload, sset, sclr, sload ); + +// NOTE: Parameters must be declared in the same order as the Properties +// are specified in the Cell Specification document. + parameter lpm_width = 1; + parameter lpm_modulus = 0; + parameter lpm_direction = "UNUSED"; + parameter lpm_avalue = "UNUSED"; + parameter lpm_svalue = "UNUSED"; + parameter lpm_pvalue = "UNUSED"; + parameter lpm_type = "lpm_counter"; + parameter lpm_hint = "UNUSED"; + parameter lpm_source_version = "lpm 220 version 1.6"; + + output [lpm_width-1:0] q; + //output [lpm_modulus-1:0] eq; + output cout; + input cin; + input [lpm_width-1:0] data; + input clock, clk_en, cnt_en, updown; + input aset, aclr, aload; + input sset, sclr, sload; + + reg [lpm_width-1:0] tmp_count; + reg tmp_updown; + integer tmp_modulus; + + tri1 clk_en; + tri1 cnt_en; + tri1 updown; + tri0 sload; + tri0 sset; + tri0 sclr; + tri0 aload; + tri0 aset; + tri0 aclr; + tri0 cin; + + buf (i_clk_en, clk_en); + buf (i_cnt_en, cnt_en); + buf (i_updown, updown); + buf (i_sload, sload); + buf (i_sset, sset); + buf (i_sclr, sclr); + buf (i_aload, aload); + buf (i_aset, aset); + buf (i_aclr, aclr); + buf (i_cin, cin); + + +//---------------------------------------------------------------// + function [lpm_width-1:0] NextBin; + input [lpm_width-1:0] count; + + //reg [lpm_width-1:0] re_start; + //reg [lpm_width-1:0] tmp_nextbin; + //integer up_limit; + + begin + if (tmp_updown == 1) + begin + if (i_cin == 1 && count == tmp_modulus-2) + NextBin = 0; + else + NextBin = (count >= tmp_modulus-1) ? i_cin : count+1+i_cin; + end + else + begin + if (i_cin == 1 && count == 1) + NextBin = tmp_modulus - 1; + else + NextBin = (count <= 0) ? tmp_modulus-1-i_cin : count-1-i_cin; + end + end + endfunction + +//---------------------------------------------------------------// +// function [(1< 1< 1<= tmp_modulus-1-i_cin) && tmp_updown) + || ((tmp_count <= i_cin) && !tmp_updown)) ? 1 : 0; + +// Check for previous Parameter declaration order +initial if ((lpm_width === "lpm_counter") || (lpm_type !== "lpm_counter")) + begin + $display ("LPM 220 Version 1.6 Parameter Order changed; update instantiation"); + $finish; + end +endmodule // lpm_counter Index: common/trunk/220_vhdl_usage.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: common/trunk/220_vhdl_usage.pdf =================================================================== --- common/trunk/220_vhdl_usage.pdf (nonexistent) +++ common/trunk/220_vhdl_usage.pdf (revision 48)

common/trunk/220_vhdl_usage.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: common/trunk/220_count4_example.v =================================================================== --- common/trunk/220_count4_example.v (nonexistent) +++ common/trunk/220_count4_example.v (revision 48) @@ -0,0 +1,35 @@ +//------------------------------------------------------------------------ +// Copyright (c) 1997 Altera Corporation, all right reserved +// +// This Verilog file may be copied and/or distributed at no cost as long as +// this copyright notice is retained. +// +//---------------------------------------------------------------- +// Four-bit Loadable Up-Down Counter with synchronous set, load and clear +//---------------------------------------------------------------- +// Version 1.0 Date 07/09/97 +//---------------------------------------------------------------- +// + +`include "210model.v" +module count4 (q, + data, clock, + clk_en, cnt_en, updown, + sset, sclr, sload) ; + + parameter lpm_width = 4 ; + + output [lpm_width-1:0] q ; + input [lpm_width-1:0] data ; + input clock, clk_en, cnt_en, updown ; + input sset, sclr, sload ; + + + lpm_counter U1 (.q(q), + .data(data), .clock(clock), + .clk_en(clk_en), .cnt_en(cnt_en), .updown(updown), + .sset(sset), .sclr(sclr), .sload(sload)) ; + + defparam U1.lpm_width=4; + +endmodule Index: common/trunk/crc32_lib.v =================================================================== --- common/trunk/crc32_lib.v (nonexistent) +++ common/trunk/crc32_lib.v (revision 48) @@ -0,0 +1,2324 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// crc_32_lib, consisting of: //// +//// crc_32_64_pipelined_2 //// +//// crc_32_32_pipelined_1 //// +//// crc_32_8_incremental_pipelined_1 //// +//// //// +//// This file is part of the general opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// Calculate CRC-32 checksums by applying 8, 16, 24, 32, or //// +//// 64 bits of new data per clock. //// +//// CRC-32 needs to start out with a value of all F's. //// +//// When CRC-32 is applied to a block which ends with the //// +//// CRC-32 of the previous data in the block, the resulting //// +//// CRC-32 checksum is always 32'hCBF43926. //// +//// //// +//// The verilog these routines is started from scratch. A new //// +//// user might want to look at a wonderful paper by Ross //// +//// Williams, which seems to be at //// +//// ftp.adelaide.edu.au:/pub/rocksoft/crc_v3.txt //// +//// Also see http://www.easics.be/webtools/crctool //// +//// //// +//// To Do: //// +//// None of the flop-to-flop routines have been checked! //// +//// Might make this handle different sizes. //// +//// Might put some real thought into minimizing things so that //// +//// a poor FPGA can reuse input terms to the max. //// +//// //// +//// Author(s): //// +//// - Anonymous //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Anonymous and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: crc32_lib.v,v 1.2 2001-09-07 11:38:25 bbeaver Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/09/07 11:32:02 Blue Beaver +// no message +// +// Revision 1.24 2001/09/07 11:28:49 Blue Beaver +// no message +// +// + +//=========================================================================== +// NOTE: I am greatly confused about the order in which the CRC should be +// sent over the wire to a remote machine. Bit 0 first? Bit 31 first? +// True or compliment values? The user has got to figure this out in +// order to interoperate with existing machines. +// +// NOTE: Bit order matters in this code, of course. The existing code on +// the net assumes that when you present a multi-bit word to a parallel +// CRC generator, the MSB corresponds to the earliest data to arrive +// across a serial interface. +// +// NOTE: The code also assumes that the data shifts into bit 0 of the shift +// register, and shifts out of bit 31. +// +// NOTE: The math for the CRC-32 is beyond me. +// +// NOTE: But they are pretty easy to use. +// You initialize a CRC to a special value to keep from missing +// initial 0 bytes. That is 32'hFFFFFFFF for CRC-32. +// You update a CRC as data comes in. +// You append the calculated CRC to the end of your message. +// You have to agree on logic sense and bit order with the +// receiver, or everything you send will seem wrong. +// The receiver calculates a CRC the same way, but receives a +// message longer than the one you sent, due to the added CRC. +// After the CRC is processed by the receiver, you either compare +// the calculated CRC with the sent one, or look for a magic +// final value which indicates that the message had no errors. +// +// NOTE: Looking on the web, one finds a nice tutorial by Cypress entitled +// "Parallel Cyclic Redundancy Check (CRC) for HOTLink(TM)". +// This reminds me of how I learned to do this from a wonderful +// CRC tutorial on the web, done by Ross N. Williams. +// +// NOTE: The CRC-32 polynomial is: +// X**0 + X**1 + X**2 + X**4 + X**5 + X**7 + X**8 + X**10 +// + X**11 + X**12 + X**16 + X**22 + X**23 + X**26 + X**32 +// You initialize it to the value 32'hFFFFFFFF +// You append it to the end of the message. +// The receiver sees the value 32'hC704DD7B when the message is +// received no errors. +// +// That means that each clock a new bit comes in, you have to shift +// all the 32 running state bits 1 bit higher and drop the MSB. +// PLUS you have to XOR in (new bit ^ MSB) to locations +// 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, and 26. +// +// That is simple but slow. If you keep track of the bits, you can +// see that it might be possible to apply 1 bit, shift it, apply +// another bit, shift THAT, and end up with a new formula of how +// to update the shift register based on applyig 1 bits at once. +// +// That is the general plan. Figure out how to apply several bits +// at a time. Write out the big formula, then simplify it if possible. +// Apply the bits, shift several bit locations at once, run faster. +// +// But what are the formulas? Good question. Use a computer to figure +// this out for you. And Williams wrote a program! +// +// NOTE: The idea is simple, so I may include a program to print out +// formulas at the end of this code. The module SHOULD be improved +// to group the terms into an XOR tree, with parantheses. That can +// be left for a new person. +// +// NOTE: ALL input data is latched in flops immediately. +// All outputs are already latched. So everything is flop-to-flop. +// This lets the module be synthesized and layed out independently +// of all other modules when trying to meet timing. +// This also lets the modules which calculate with more than 32 +// input bits per clock have an internal pipeline stage where +// the Data component of the new CRC is calculate. But be +// careful! An extra layer of pipelining changes when data +// becomes available. +// Might also make versions which let a non-F CRC be loaded. This +// would be useful if a CRC needed to be calculated incrementally, +// which is the case when calculating AAL-5 checksums, for instance. +// +// This code was developed using VeriLogger Pro, by Synapticad. +// Their support is greatly appreciated. +// +//=========================================================================== + +`timescale 1ns/1ps + +// Look up the CRC-32 polynomial on the web. +// The LSB corresponds to bit 0, the new input bit. +`define CRC 32'b0000_0100_1100_0001_0001_1101_1011_0111 +`define CHECK_VALUE 32'b1100_1011_1111_0100_0011_1001_0010_0110 +`define NUMBER_OF_BITS_IN_CRC_32 32 + +// Given a 64-bit aligned data stream, calculate the CRC-32 8 bytes at a time. +// Input data and the use_F indication are latched on input at clock 0. +// The CRC result is available after clock 2 (!) after the last data item is consumed. +// The indication that the CRC is correct is available after clock 3 (!) clocks after +// the last data item is consumed. +// If the data stream is not an exact multiple of 8 bytes long, the checksum +// calculated here must be incrementally updated for each byte beyond the +// multiple of 8. Use another module to do that. + +module crc_32_64_pipelined_2 ( + use_F_for_CRC, + data_in_64, + running_crc_2, + crc_correct_3, + clk +); + parameter NUMBER_OF_BITS_APPLIED = 64; // do NOT override + input use_F_for_CRC; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_64; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] running_crc_2; + output crc_correct_3; + input clk; + +// A pipelined version of the CRC_32 working on 64-bit operands. +// Latch all operands at Clock 0. +// Calculate the Data Dependency during Clock 1. +// Update the CRC during Clock 2. +// The CRC Correct signal comes out after Clock 3. + +// Latch all operands at Clock 0. + reg use_F_for_CRC_latched_0; + reg [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_64_latched_0; + + always @(posedge clk) + begin + use_F_for_CRC_latched_0 <= use_F_for_CRC; + data_in_64_latched_0[NUMBER_OF_BITS_APPLIED - 1 : 0] <= + data_in_64[NUMBER_OF_BITS_APPLIED - 1 : 0]; + end + +// Instantiate the Data part of the dependency. + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_part_1_out_0; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_part_2_out_0; + +crc_32_64_data_private crc_32_64_data_part ( + .data_in_64 (data_in_64_latched_0[NUMBER_OF_BITS_APPLIED - 1 : 0]), + .data_part_1_out (data_part_1_out_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_part_2_out (data_part_2_out_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + +// Calculate the Data Dependency during Clock 1. + reg use_F_for_CRC_prev_1; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_part_1_latched_1; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_part_2_latched_1; + + always @(posedge clk) + begin + use_F_for_CRC_prev_1 <= use_F_for_CRC_latched_0; + data_part_1_latched_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] <= + data_part_1_out_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_part_2_latched_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] <= + data_part_2_out_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + end + +// Update the CRC during Clock 2. + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_2; + + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] crc_part_1_out_1; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] crc_part_2_out_1; + +crc_32_64_crc_private crc_32_64_crc_part ( + .use_F_for_CRC (use_F_for_CRC_prev_1), + .present_crc (present_crc_2[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .crc_part_1_out (crc_part_1_out_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .crc_part_2_out (crc_part_2_out_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_depend_part_1 = + data_part_1_latched_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] + ^ data_part_2_latched_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; // source depth 2 gates + + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] first_crc_part_1 = + data_depend_part_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] + ^ crc_part_1_out_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; // source depth 4 gates + + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc_1 = + first_crc_part_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] + ^ crc_part_2_out_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; // source depth 5 gates + + always @(posedge clk) + begin + present_crc_2[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] <= + next_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + end + +// Assign separately so that flop outputs can be used in feedback. + assign running_crc_2[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_2[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + +// Watch to detect blocks which end with the correct CRC appended. + reg crc_correct_3; + + always @(posedge clk) + begin + crc_correct_3 <= (present_crc_2[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] == 32'hCBF43926); + end + +// synopsys translate_off +// Check the user didn't override anything + initial + begin + if (NUMBER_OF_BITS_APPLIED != 64) + begin + $display ("*** Exiting because %m crc_32_64_pipelined_2 Number of bits %d != 64", + NUMBER_OF_BITS_APPLIED); + $finish; + end + end +// synopsys translate_on +endmodule + +// Given a 32-bit aligned data stream, calculate the CRC-32 4 bytes at a time. +// Inout data and the use_F indication are latched on input at clock 0. +// The CRC result is available after clock 1 (!) after the last data item is consumed. +// The indication that the CRC is correct is available after clock 2 (!) clocks after +// the last data item is consumed. +// If the data stream is not an exact multiple of 4 bytes long, the checksum +// calculated here must be incrementally updated for each byte beyond the +// multiple of 4. Use another module to do that. + +module crc_32_32_pipelined_1 ( + use_F_for_CRC, + data_in_32, + running_crc_1, + crc_correct_2, + clk +); + parameter NUMBER_OF_BITS_APPLIED = 32; // do NOT override + input use_F_for_CRC; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_32; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] running_crc_1; + output crc_correct_2; + input clk; + +// A pipelined version of the CRC_32 working on 32-bit operands. +// Latch all operands at Clock 0. +// Update the CRC during Clock 1. +// The CRC Correct signal comes out after Clock 2. + +// Latch all operands at Clock 0. + reg use_F_for_CRC_latched_0; + reg [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_32_latched_0; + + always @(posedge clk) + begin + use_F_for_CRC_latched_0 <= use_F_for_CRC; + data_in_32_latched_0[NUMBER_OF_BITS_APPLIED - 1 : 0] <= + data_in_32[NUMBER_OF_BITS_APPLIED - 1 : 0]; + end + +// Update the CRC during Clock 1. + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_1; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc_0; + +crc_32_32_private crc_32_32_crc ( + .use_F_for_CRC (use_F_for_CRC_prev_1), + .present_crc (present_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_in_32 (data_in_32_latched_0[NUMBER_OF_BITS_APPLIED - 1 : 0]), + .next_crc (next_crc_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + + always @(posedge clk) + begin + present_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] <= + next_crc_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + end + +// Assign separately so that flop outputs can be used in feedback. + assign running_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + +// Watch to detect blocks which end with the correct CRC appended. + reg crc_correct_2; + + always @(posedge clk) + begin + crc_correct_2 <= (present_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] == 32'hCBF43926); + end + +// synopsys translate_off +// Check the user didn't override anything + initial + begin + if (NUMBER_OF_BITS_APPLIED != 32) + begin + $display ("*** Exiting because %m crc_32_32_pipelined_1 Number of bits %d != 32", + NUMBER_OF_BITS_APPLIED); + $finish; + end + end +// synopsys translate_on +endmodule + +// Given an 8-bit aligned data stream, calculate the CRC-32 1 byte at a time. +// Input data and the use_F indication are latched on input at clock 0. +// The CRC result is available after clock 1 (!) after the last data item is consumed. +// The indication that the CRC is correct is available after clock 2 (!) clocks after +// the last data item is consumed. +// This module can be given a starting CRC, and can incrementally calculate +// a new CRC-32 by applying 1 new data byte at a time. + +module crc_32_8_incremental_pipelined_1 ( + use_old_CRC, + old_crc, + use_F_for_CRC, + data_in_8, + running_crc_1, + crc_correct_2, + clk +); + parameter NUMBER_OF_BITS_APPLIED = 8; // do NOT override + input use_old_CRC; + input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] old_crc; + input use_F_for_CRC; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_8; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] running_crc_1; + output crc_correct_2; + input clk; + +// A pipelined version of the CRC_32 working on 32-bit operands. +// Latch all operands at Clock 0. +// Update the CRC during Clock 1. +// The CRC Correct signal comes out after Clock 2. + +// Latch all operands at Clock 0. + reg use_old_crc_latched_0; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] old_crc_latched_0; + reg use_F_for_CRC_latched_0; + reg [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_8_latched_0; + + always @(posedge clk) + begin + use_old_crc_latched_0 <= use_old_CRC; + old_crc_latched_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] <= + old_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + use_F_for_CRC_latched_0 <= use_F_for_CRC; + data_in_8_latched_0[NUMBER_OF_BITS_APPLIED - 1 : 0] <= + data_in_8[NUMBER_OF_BITS_APPLIED - 1 : 0]; + end + +// Update the CRC during Clock 1. + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_1; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_0 = use_old_crc_latched_0 + ? old_crc_latched_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] + : present_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc_0; + +crc_32_8_private crc_32_8_crc ( + .use_F_for_CRC (use_F_for_CRC_prev_1), + .present_crc (present_crc_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_in_8 (data_in_8_latched_0[NUMBER_OF_BITS_APPLIED - 1 : 0]), + .next_crc (next_crc_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + + always @(posedge clk) + begin + present_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] <= + next_crc_0[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + end + +// Assign separately so that flop outputs can be used in feedback. + assign running_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + +// Watch to detect blocks which end with the correct CRC appended. + reg crc_correct_2; + + always @(posedge clk) + begin + crc_correct_2 <= (present_crc_1[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] == 32'hCBF43926); + end + +// synopsys translate_off +// Check the user didn't override anything + initial + begin + if (NUMBER_OF_BITS_APPLIED != 8) + begin + $display ("*** Exiting because %m crc_32_8_pipelined_1 Number of bits %d != 8", + NUMBER_OF_BITS_APPLIED); + $finish; + end + end +// synopsys translate_on +endmodule + +// The private modules which have the real formulas in them: + +// Given a 32-bit CRC-32 running value, update it using 8 new bits of data. +// The way to make this fast is to find common sub-expressions. +// +// The user needs to supply external flops to make this work. + +module crc_32_8_private ( + use_F_for_CRC, + present_crc, + data_in_8, + next_crc +); + parameter NUMBER_OF_BITS_APPLIED = 8; + input use_F_for_CRC; + input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_8; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc; + + wire X7, X6, X5, X4, X3, X2, X1, X0; + assign {X7, X6, X5, X4, X3, X2, X1, X0} = data_in_8[NUMBER_OF_BITS_APPLIED - 1 : 0] + ^ ( present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : `NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED] + | {NUMBER_OF_BITS_APPLIED{use_F_for_CRC}}); + + wire C23, C22, C21, C20, C19, C18, C17, C16; + wire C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0; + assign {C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, + C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0} = + present_crc[`NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED - 1 : 0] + | {(`NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED){use_F_for_CRC}}; + + assign next_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + { C23 ^ X5 , + C22 ^ X4 ^ X7, + C21 ^ X3 ^ X6 ^ X7, + C20 ^ X2 ^ X5 ^ X6 , + C19 ^ X1 ^ X4 ^ X5 ^ X7, + C18 ^ X0 ^ X3 ^ X4 ^ X6 , + C17 ^ X2 ^ X3 , + C16 ^ X1 ^ X2 ^ X7, + C15 ^ X0 ^ X1 ^ X6 , + C14 ^ X0 , + C13 ^ X5 , + C12 ^ X4 , + C11 ^ X3 ^ X7, + C10 ^ X2 ^ X6 ^ X7, + C9 ^ X1 ^ X5 ^ X6 , + C8 ^ X0 ^ X4 ^ X5 , + C7 ^ X3 ^ X4 ^ X5 ^ X7, + C6 ^ X2 ^ X3 ^ X4 ^ X6 ^ X7, + C5 ^ X1 ^ X2 ^ X3 ^ X5 ^ X6 ^ X7, + C4 ^ X0 ^ X1 ^ X2 ^ X4 ^ X5 ^ X6 , + C3 ^ X0 ^ X1 ^ X3 ^ X4 , + C2 ^ X0 ^ X2 ^ X3 ^ X5 , + C1 ^ X1 ^ X2 ^ X4 ^ X5 , + C0 ^ X0 ^ X1 ^ X3 ^ X4 , + X0 ^ X2 ^ X3 ^ X5 ^ X7, + X1 ^ X2 ^ X4 ^ X5 ^ X6 ^ X7, + X0 ^ X1 ^ X3 ^ X4 ^ X5 ^ X6 ^ X7, + X0 ^ X2 ^ X3 ^ X4 ^ X6 , + X1 ^ X2 ^ X3 ^ X7, + X0 ^ X1 ^ X2 ^ X6 ^ X7, + X0 ^ X1 ^ X6 ^ X7, + X0 ^ X6 + }; +endmodule + +module crc_32_16_private ( + use_F_for_CRC, + present_crc, + data_in_16, + next_crc +); + parameter NUMBER_OF_BITS_APPLIED = 16; + input use_F_for_CRC; + input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_16; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc; + +/* State Variables depend on input bit number (bigger is earlier) : +{ +31 : C15 ^ X5 ^ X8 ^ X9 ^ X11 ^ X15, +30 : C14 ^ X4 ^ X7 ^ X8 ^ X10 ^ X14 , +29 : C13 ^ X3 ^ X6 ^ X7 ^ X9 ^ X13 , +28 : C12 ^ X2 ^ X5 ^ X6 ^ X8 ^ X12 , +27 : C11 ^ X1 ^ X4 ^ X5 ^ X7 ^ X11 , +26 : C10 ^ X0 ^ X3 ^ X4 ^ X6 ^ X10 , +25 : C9 ^ X2 ^ X3 ^ X8 ^ X11 ^ X15, +24 : C8 ^ X1 ^ X2 ^ X7 ^ X10 ^ X14 , +23 : C7 ^ X0 ^ X1 ^ X6 ^ X9 ^ X13 ^ X15, +22 : C6 ^ X0 ^ X12 ^ X9 ^ X14 ^ X11 , +21 : C5 ^ X5 ^ X9 ^ X13 ^ X10 , +20 : C4 ^ X4 ^ X8 ^ X12 ^ X9 , +19 : C3 ^ X3 ^ X7 ^ X8 ^ X11 ^ X15, +18 : C2 ^ X2 ^ X6 ^ X7 ^ X10 ^ X14 ^ X15, +17 : C1 ^ X1 ^ X5 ^ X6 ^ X9 ^ X13 ^ X14 , +16 : C0 ^ X0 ^ X4 ^ X5 ^ X8 ^ X12 ^ X13 , +15 : 0 ^ X3 ^ X4 ^ X5 ^ X7 ^ X8 ^ X12 ^ X9 ^ X15, +14 : 0 ^ X2 ^ X3 ^ X4 ^ X6 ^ X7 ^ X8 ^ X14 ^ X11 ^ X15, +13 : 0 ^ X1 ^ X2 ^ X3 ^ X5 ^ X6 ^ X7 ^ X13 ^ X10 ^ X14 , +12 : 0 ^ X0 ^ X1 ^ X2 ^ X4 ^ X5 ^ X6 ^ X12 ^ X9 ^ X13 ^ X15, +11 : 0 ^ X0 ^ X1 ^ X3 ^ X4 ^ X12 ^ X9 ^ X14 ^ X15, +10 : 0 ^ X0 ^ X2 ^ X3 ^ X5 ^ X9 ^ X13 ^ X14 , + 9 : 0 ^ X1 ^ X2 ^ X4 ^ X5 ^ X12 ^ X9 ^ X13 ^ X11 , + 8 : 0 ^ X0 ^ X1 ^ X3 ^ X4 ^ X8 ^ X12 ^ X10 ^ X11 , + 7 : 0 ^ X0 ^ X2 ^ X3 ^ X5 ^ X7 ^ X8 ^ X10 ^ X15, + 6 : 0 ^ X1 ^ X2 ^ X4 ^ X5 ^ X6 ^ X7 ^ X8 ^ X14 ^ X11 , + 5 : 0 ^ X0 ^ X1 ^ X3 ^ X4 ^ X5 ^ X6 ^ X7 ^ X13 ^ X10 , + 4 : 0 ^ X0 ^ X2 ^ X3 ^ X4 ^ X6 ^ X8 ^ X12 ^ X11 ^ X15, + 3 : 0 ^ X1 ^ X2 ^ X3 ^ X7 ^ X8 ^ X9 ^ X10 ^ X14 ^ X15, + 2 : 0 ^ X0 ^ X1 ^ X2 ^ X6 ^ X7 ^ X8 ^ X9 ^ X13 ^ X14 , + 1 : 0 ^ X0 ^ X1 ^ X6 ^ X7 ^ X12 ^ X9 ^ X13 ^ X11 , + 0 : 0 ^ X0 ^ X6 ^ X12 ^ X9 ^ X10 +} +*/ +// There are 2 obvious ways to implement these functions: +// 1) XOR the State bits with the Input bits, then calculate the XOR's +// 2) Independently calculate a result for Inputs and State variables, +// then XOR the results together. +// The second idea seems to take much more logic, but to have no benefit. + +// Single numbered terms are calculated in 1 XOR time. + wire X15, X14, X13, X12, X11, X10, X9, X8, X7, X6, X5, X4, X3, X2, X1, X0; + assign {X15, X14, X13, X12, X11, X10, X9, X8, X7, X6, X5, X4, X3, X2, X1, X0} = + data_in_16[NUMBER_OF_BITS_APPLIED - 1 : 0] + ^ ( present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : `NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED] + | {NUMBER_OF_BITS_APPLIED{use_F_for_CRC}}); + +// State Bits are shifted over by the width of the input, then XOR's into the X terms. + wire C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0; + assign {C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0} = + present_crc[`NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED - 1 : 0] + | {(`NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED){use_F_for_CRC}}; + +// Calculate higher_order terms, to make parity trees. +// 2_numbered terms are calculated in 1 XOR times. +// NOTE: In a Xilinx chip, it would be fine to constrain X0 and X0_1 to +// be calculated in the same CLB, and so on for all bits. + wire X0_1 = X0 ^ X1; wire X1_2 = X1 ^ X2; + wire X2_3 = X2 ^ X3; wire X3_4 = X3 ^ X4; + wire X4_5 = X4 ^ X5; wire X5_6 = X5 ^ X6; + wire X6_7 = X6 ^ X7; wire X7_8 = X7 ^ X8; +// Use odd-ordered XOR terms because it seems these might be useful + wire X8_12 = X8 ^ X12; wire X12_9 = X12 ^ X9; + wire X9_13 = X9 ^ X13; wire X13_10 = X13 ^ X10; + wire X10_14 = X10 ^ X14; wire X14_11 = X14 ^ X11; + wire X11_15 = X11 ^ X15; + +// Calculate terms which might have a single use. They are calculated here +// so that the parity trees can be balanced. + wire C15_5 = C15 ^ X5; wire C14_4 = C14 ^ X4; + wire C13_3 = C13 ^ X3; wire C12_2 = C12 ^ X2; + wire C11_1 = C11 ^ X1; wire C10_0 = C10 ^ X0; + wire C9_8 = C9 ^ X8; wire C8_7 = C8 ^ X7; + wire C7_6 = C7 ^ X6; wire C6_0 = C6 ^ X0; + wire C5_5 = C5 ^ X5; wire C4_4 = C4 ^ X4; + wire C3_3 = C3 ^ X3; wire C2_2 = C2 ^ X2; + wire C1_1 = C1 ^ X1; wire C0_0 = C0 ^ X0; +// Some of these could be matched with other terms to share 1 input in a CLB. + wire X0_5 = X0 ^ X5; wire X0_6 = X0 ^ X6; + wire X2_6 = X2 ^ X6; wire X2_8 = X2 ^ X8; + wire X3_7 = X3 ^ X7; wire X3_9 = X3 ^ X9; + wire X4_8 = X4 ^ X8; + wire X5_15 = X5 ^ X15; + wire X6_10 = X6 ^ X10; + wire X7_11 = X7 ^ X11; + wire X8_9 = X8 ^ X9; + wire X10_11 = X10 ^ X11; wire X10_15 = X10 ^ X15; + wire X13_11 = X13 ^ X11; wire X13_15 = X13 ^ X15; + wire X14_15 = X14 ^ X15; + +// NOTE: 5 terms can be implemented in a CLB, as long as the other Flop +// doesn't use logic. This would be perfect if the data_in_16 +// was registered as an input to the module in that CLB. + assign next_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + { (C15_5 ^ X8_9) ^ X11_15, + (C14_4 ^ X7_8) ^ X10_14, + (C13_3 ^ X6_7) ^ X9_13, + (C12_2 ^ X5_6) ^ X8_12, + (C11_1 ^ X4_5) ^ X7_11, + (C10_0 ^ X3_4) ^ X6_10, + (C9_8 ^ X2_3) ^ X11_15, + (C8_7 ^ X1_2) ^ X10_14, + (C7_6 ^ X0_1) ^ (X9_13 ^ X15), + (C6_0 ^ X12_9) ^ X14_11, + (C5_5 ^ X9_13) ^ X10, + (C4_4 ^ X8_12) ^ X9, + (C3_3 ^ X7_8) ^ X11_15, + (C2_2 ^ X6_7) ^ (X14_15 ^ X10), + (C1_1 ^ X5_6) ^ (X9_13 ^ X14), + (C0_0 ^ X4_5) ^ (X8_12 ^ X13), + (X3_4 ^ X5_15) ^ (X7_8 ^ X12_9), + ((X2_3 ^ X4_8) ^ (X6_7 ^ X14_15)) ^ X11, + ((X1_2 ^ X3_7) ^ (X5_6 ^ X13_10)) ^ X14, + ((X0_1 ^ X2_6) ^ (X4_5 ^ X12_9)) ^ X13_15, + (X0_1 ^ X3_4) ^ (X12_9 ^ X14_15), + (X0_5 ^ X2_3) ^ (X9_13 ^ X14), + (X1_2 ^ X4_5) ^ (X12_9 ^ X13_11), + (X0_1 ^ X3_4) ^ (X8_12 ^ X10_11), + (X0_5 ^ X2_3) ^ (X7_8 ^ X10_15), + ((X1_2 ^ X4_5) ^ (X6_7 ^ X14_11)) ^ X8, + ((X0_1 ^ X3_4) ^ (X5_6 ^ X13_10)) ^ X7, + ((X0_6 ^ X2_3) ^ (X8_12 ^ X11_15)) ^ X4, + ((X1_2 ^ X3_9) ^ (X7_8 ^ X10_14)) ^ X15, + ((X0_1 ^ X2_8) ^ (X6_7 ^ X9_13)) ^ X14, + (X0_1 ^ X6_7) ^ (X12_9 ^ X13_11), + (X0_6 ^ X12_9) ^ X10 + }; +endmodule + +module crc_32_24_private ( + use_F_for_CRC, + present_crc, + data_in_24, + next_crc +); + parameter NUMBER_OF_BITS_APPLIED = 24; + input use_F_for_CRC; + input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_24; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc; + +/* State Variables depend on input bit number (bigger is earlier) : +{ +C7 ^ X5 ^ X8 ^ X9 ^ X11 ^ X15 ^ X23, +C6 ^ X4 ^ X7 ^ X8 ^ X10 ^ X14 ^ X22 ^ X23, +C5 ^ X3 ^ X6 ^ X7 ^ X9 ^ X13 ^ X21 ^ X22 ^ X23, +C4 ^ X2 ^ X5 ^ X6 ^ X8 ^ X12 ^ X20 ^ X21 ^ X22 , +C3 ^ X1 ^ X4 ^ X5 ^ X7 ^ X11 ^ X19 ^ X20 ^ X21 ^ X23, +C2 ^ X0 ^ X3 ^ X4 ^ X6 ^ X10 ^ X18 ^ X19 ^ X20 ^ X22 ^ X23, +C1 ^ X2 ^ X3 ^ X8 ^ X11 ^ X15 ^ X17 ^ X18 ^ X19 ^ X21 ^ X22 , +C0 ^ X1 ^ X2 ^ X7 ^ X10 ^ X14 ^ X16 ^ X17 ^ X18 ^ X20 ^ X21 , + 0 ^ X0 ^ X1 ^ X6 ^ X9 ^ X13 ^ X15 ^ X16 ^ X17 ^ X19 ^ X20 , + 0 ^ X0 ^ X12 ^ X9 ^ X14 ^ X11 ^ X16 ^ X18 ^ X19 ^ X23, + 0 ^ X5 ^ X9 ^ X13 ^ X10 ^ X17 ^ X18 ^ X22 , + 0 ^ X4 ^ X8 ^ X12 ^ X9 ^ X16 ^ X17 ^ X21 ^ X23, + 0 ^ X3 ^ X7 ^ X8 ^ X11 ^ X15 ^ X16 ^ X20 ^ X22 , + 0 ^ X2 ^ X6 ^ X7 ^ X10 ^ X14 ^ X15 ^ X19 ^ X21 ^ X23, + 0 ^ X1 ^ X5 ^ X6 ^ X9 ^ X13 ^ X14 ^ X18 ^ X20 ^ X22 ^ X23, + 0 ^ X0 ^ X4 ^ X5 ^ X8 ^ X12 ^ X13 ^ X17 ^ X19 ^ X21 ^ X22 , + 0 ^ X3 ^ X4 ^ X5 ^ X7 ^ X8 ^ X12 ^ X9 ^ X15 ^ X16 ^ X18 ^ X20 ^ X21 , + 0 ^ X2 ^ X3 ^ X4 ^ X6 ^ X7 ^ X8 ^ X14 ^ X11 ^ X15 ^ X17 ^ X19 ^ X20 ^ X23, + 0 ^ X1 ^ X2 ^ X3 ^ X5 ^ X6 ^ X7 ^ X13 ^ X10 ^ X14 ^ X16 ^ X18 ^ X19 ^ X22 , + 0 ^ X0 ^ X1 ^ X2 ^ X4 ^ X5 ^ X6 ^ X12 ^ X9 ^ X13 ^ X15 ^ X17 ^ X18 ^ X21 , + 0 ^ X0 ^ X1 ^ X3 ^ X4 ^ X12 ^ X9 ^ X14 ^ X15 ^ X16 ^ X17 ^ X20 , + 0 ^ X0 ^ X2 ^ X3 ^ X5 ^ X9 ^ X13 ^ X14 ^ X16 ^ X19 , + 0 ^ X1 ^ X2 ^ X4 ^ X5 ^ X12 ^ X9 ^ X13 ^ X11 ^ X18 ^ X23, + 0 ^ X0 ^ X1 ^ X3 ^ X4 ^ X8 ^ X12 ^ X10 ^ X11 ^ X17 ^ X22 ^ X23, + 0 ^ X0 ^ X2 ^ X3 ^ X5 ^ X7 ^ X8 ^ X10 ^ X15 ^ X16 ^ X21 ^ X22 ^ X23, + 0 ^ X1 ^ X2 ^ X4 ^ X5 ^ X6 ^ X7 ^ X8 ^ X14 ^ X11 ^ X20 ^ X21 ^ X22 , + 0 ^ X0 ^ X1 ^ X3 ^ X4 ^ X5 ^ X6 ^ X7 ^ X13 ^ X10 ^ X19 ^ X20 ^ X21 , + 0 ^ X0 ^ X2 ^ X3 ^ X4 ^ X6 ^ X8 ^ X12 ^ X11 ^ X15 ^ X18 ^ X19 ^ X20 , + 0 ^ X1 ^ X2 ^ X3 ^ X7 ^ X8 ^ X9 ^ X10 ^ X14 ^ X15 ^ X17 ^ X18 ^ X19 , + 0 ^ X0 ^ X1 ^ X2 ^ X6 ^ X7 ^ X8 ^ X9 ^ X13 ^ X14 ^ X16 ^ X17 ^ X18 , + 0 ^ X0 ^ X1 ^ X6 ^ X7 ^ X12 ^ X9 ^ X13 ^ X11 ^ X16 ^ X17 , + 0 ^ X0 ^ X6 ^ X12 ^ X9 ^ X10 ^ X16 +} +*/ +// There are 2 obvious ways to implement these functions: +// 1) XOR the State bits with the Input bits, then calculate the XOR's +// 2) Independently calculate a result for Inputs and State variables, +// then XOR the results together. +// The second idea seems to take much more logic, but to have no benefit. + +// Single numbered terms are calculated in 1 XOR time. + wire X23, X22, X21, X20, X19, X18, X17, X16; + wire X15, X14, X13, X12, X11, X10, X9, X8, X7, X6, X5, X4, X3, X2, X1, X0; + assign {X23, X22, X21, X20, X19, X18, X17, X16, X15, X14, X13, X12, + X11, X10, X9, X8, X7, X6, X5, X4, X3, X2, X1, X0} = + data_in_24[NUMBER_OF_BITS_APPLIED - 1 : 0] + ^ ( present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : `NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED] + | {NUMBER_OF_BITS_APPLIED{use_F_for_CRC}}); + +// State Bits are shifted over by the width of the input, then XOR's into the X terms. + wire C7, C6, C5, C4, C3, C2, C1, C0; + assign {C7, C6, C5, C4, C3, C2, C1, C0} = + present_crc[`NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED - 1 : 0] + | {(`NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED){use_F_for_CRC}}; + +// Calculate higher_order terms, to make parity trees. +// 2_numbered terms are calculated in 1 XOR times. +// NOTE: In a Xilinx chip, it would be fine to constrain X0 and X0_1 to +// be calculated in the same CLB, and so on for all bits. + wire X0_1 = X0 ^ X1; wire X1_2 = X1 ^ X2; + wire X2_3 = X2 ^ X3; wire X3_4 = X3 ^ X4; + wire X4_5 = X4 ^ X5; wire X5_6 = X5 ^ X6; + wire X6_7 = X6 ^ X7; wire X7_8 = X7 ^ X8; +// Use odd-ordered XOR terms because it seems these might be useful + wire X8_12 = X8 ^ X12; wire X12_9 = X12 ^ X9; + wire X9_13 = X9 ^ X13; wire X13_10 = X13 ^ X10; + wire X10_14 = X10 ^ X14; wire X14_11 = X14 ^ X11; + wire X11_15 = X11 ^ X15; +// back to simple ordering + wire X15_16 = X15 ^ X16; + wire X16_17 = X16 ^ X17; wire X17_18 = X17 ^ X18; + wire X18_19 = X18 ^ X19; wire X19_20 = X19 ^ X20; + wire X20_21 = X20 ^ X21; wire X21_22 = X21 ^ X22; + wire X22_23 = X22 ^ X23; + +// Calculate terms which might have a single use. They are calculated here +// so that the parity trees can be balanced. + wire C7_5 = C7 ^ X5; wire C6_4 = C6 ^ X4; + wire C5_3 = C5 ^ X3; wire C4_2 = C4 ^ X2; + wire C3_1 = C3 ^ X1; wire C2_0 = C2 ^ X0; + wire C1_8 = C1 ^ X8; wire C0_7 = C0 ^ X7; +// Some of these could be matched with other terms to share 1 input in a CLB. + wire X8_9 = X8 ^ X9; wire X7_11 = X7 ^ X11; + wire X6_10 = X6 ^ X10; wire X21_23 = X21 ^ X23; + wire X6_17 = X6 ^ X17; wire X0_16 = X0 ^ X16; + wire X5_10 = X5 ^ X10; wire X4_9 = X4 ^ X9; + wire X3_16 = X3 ^ X16; wire X20_22 = X20 ^ X22; + wire X15_19 = X15 ^ X19; wire X1_9 = X1 ^ X9; + wire X13_14 = X13 ^ X14; wire X18_20 = X18 ^ X20; + wire X0_8 = X0 ^ X8; wire X12_13 = X12 ^ X13; + wire X17_19 = X17 ^ X19; wire X5_18 = X5 ^ X18; + wire X4_8 = X4 ^ X8; wire X15_17 = X15 ^ X17; + wire X3_7 = X3 ^ X7; wire X2_6 = X2 ^ X6; + wire X14_17 = X14 ^ X17; wire X0_5 = X0 ^ X5; + wire X14_16 = X14 ^ X16; wire X13_15 = X13 ^ X15; + wire X0_4 = X0 ^ X4; wire X0_6 = X0 ^ X6; + wire X3_9 = X3 ^ X9; wire X2_8 = X2 ^ X8; + wire X13_11 = X13 ^ X11; wire X16_23 = X16 ^ X23; + wire X10_11 = X10 ^ X11; wire X10_15 = X10 ^ X15; + wire X8_22 = X8 ^ X22; wire X14_18 = X14 ^ X18; + wire X6_20 = X6 ^ X20; wire X7_21 = X7 ^ X21; + +// NOTE: 5 terms can be implemented in a CLB, as long as the other Flop +// doesn't use logic. This would be perfect if the data_in_24 +// was registered as an input to the module in that CLB. + assign next_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + { (C7_5 ^ X8_9) ^ (X11_15 ^ X23), + (C6_4 ^ X7_8) ^ (X10_14 ^ X22_23), + ((C5_3 ^ X6_7) ^ (X9_13 ^ X21_22)) ^ X23, + ((C4_2 ^ X5_6) ^ (X8_12 ^ X20_21)) ^ X22, + ((C3_1 ^ X4_5) ^ (X7_11 ^ X19_20)) ^ X21_23, + ((C2_0 ^ X3_4) ^ (X6_10 ^ X18_19)) ^ (X20 ^ X22_23), + ((C1_8 ^ X2_3) ^ (X11_15 ^ X17_18)) ^ (X19 ^ X21_22), + ((C0_7 ^ X1_2) ^ (X10_14 ^ X16_17)) ^ (X18 ^ X20_21), + ((X0_1 ^ X6_17) ^ (X9_13 ^ X15_16)) ^ X19_20, + ((X0_16 ^ X12_9) ^ (X14_11 ^ X18_19)) ^ X23, + (X5_10 ^ X9_13) ^ (X17_18 ^ X22), + (X4_9 ^ X8_12) ^ (X16_17 ^ X21_23), + (X3_16 ^ X7_8) ^ (X11_15 ^ X20_22), + ((X2 ^ X6_7) ^ (X10_14 ^ X15_19)) ^ X21_23, + ((X1_9 ^ X5_6) ^ (X13_14 ^ X18_20)) ^ X22_23, + ((X0_8 ^ X4_5) ^ (X12_13 ^ X17_19)) ^ X21_22, + ((X3_4 ^ X5_18) ^ (X7_8 ^ X12_9)) ^ (X15_16 ^ X20_21), + ((X2_3 ^ X4_8) ^ (X6_7 ^ X14_11)) ^ ((X15_17 ^ X19_20) ^ X23), + ((X1_2 ^ X3_7) ^ (X5_6 ^ X13_10)) ^ ((X14_16 ^ X18_19) ^ X22), + ((X0_1 ^ X2_6) ^ (X4_5 ^ X12_9)) ^ ((X13_15 ^ X17_18) ^ X21), + ((X0_1 ^ X3_4) ^ (X12_9 ^ X14_17)) ^ (X15_16 ^ X20), + ((X0_5 ^ X2_3) ^ (X9_13 ^ X14)) ^ (X16 ^ X19), + ((X1_2 ^ X4_5) ^ (X12_9 ^ X13_11)) ^ (X18 ^ X23), + ((X0_1 ^ X3_4) ^ (X8_12 ^ X10_11)) ^ (X17 ^ X22_23), + ((X0_5 ^ X2_3) ^ (X7_8 ^ X10_15)) ^ (X16_23 ^ X21_22), + ((X1_2 ^ X4_5) ^ (X6_7 ^ X8_22)) ^ (X14_11 ^ X20_21), + ((X0_1 ^ X3_4) ^ (X5_6 ^ X7_21)) ^ (X13_10 ^ X19_20), + ((X0_4 ^ X2_3) ^ (X6_20 ^ X8_12)) ^ (X11_15 ^ X18_19), + ((X1_2 ^ X3_9) ^ (X7_8 ^ X10_14)) ^ (X15_19 ^ X17_18), + ((X0_1 ^ X2_8) ^ (X6_7 ^ X9_13)) ^ (X14_18 ^ X16_17), + ((X0_1 ^ X6_7) ^ (X12_9 ^ X13_11)) ^ X16_17, + (X0_6 ^ X12_9) ^ (X10 ^ X16) + }; +endmodule + +module crc_32_32_private ( + use_F_for_CRC, + present_crc, + data_in_32, + next_crc +); + parameter NUMBER_OF_BITS_APPLIED = 32; + input use_F_for_CRC; + input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_32; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc; + +/* State Variables depend on input bit number (bigger is earlier) : +{ + ^ 5 ^ 8 ^ 9 ^ 11 ^ 15 ^ 23 ^ 24 ^ 25 ^ 27 ^ 28 ^ 29 ^ 30 ^ 31, + ^ 4 ^ 7 ^ 8 ^ 10 ^ 14 ^ 22 ^ 23 ^ 24 ^ 26 ^ 27 ^ 28 ^ 29 ^ 30 , + ^ 3 ^ 6 ^ 7 ^ 9 ^ 13 ^ 21 ^ 22 ^ 23 ^ 25 ^ 26 ^ 27 ^ 28 ^ 29 ^ 31, + ^ 2 ^ 5 ^ 6 ^ 8 ^ 12 ^ 20 ^ 21 ^ 22 ^ 24 ^ 25 ^ 26 ^ 27 ^ 28 ^ 30 , + ^ 1 ^ 4 ^ 5 ^ 7 ^ 11 ^ 19 ^ 20 ^ 21 ^ 23 ^ 24 ^ 25 ^ 26 ^ 27 ^ 29 , +0 ^ 3 ^ 4 ^ 6 ^ 10 ^ 18 ^ 19 ^ 20 ^ 22 ^ 23 ^ 24 ^ 25 ^ 26 ^ 28 ^ 31, + ^ 2 ^ 3 ^ 8 ^ 11 ^ 15 ^ 17 ^ 18 ^ 19 ^ 21 ^ 22 ^ 28 ^ 29 ^ 31, + ^ 1 ^ 2 ^ 7 ^ 10 ^ 14 ^ 16 ^ 17 ^ 18 ^ 20 ^ 21 ^ 27 ^ 28 ^ 30 , +0 ^ 1 ^ 6 ^ 9 ^ 13 ^ 15 ^ 16 ^ 17 ^ 19 ^ 20 ^ 26 ^ 27 ^ 29 ^ 31, +0 ^ 9 ^ 11 ^ 12 ^ 14 ^ 16 ^ 18 ^ 19 ^ 23 ^ 24 ^ 26 ^ 27 ^ 29 ^ 31, + ^ 5 ^ 9 ^ 10 ^ 13 ^ 17 ^ 18 ^ 22 ^ 24 ^ 26 ^ 27 ^ 29 ^ 31, + ^ 4 ^ 8 ^ 9 ^ 12 ^ 16 ^ 17 ^ 21 ^ 23 ^ 25 ^ 26 ^ 28 ^ 30 , + ^ 3 ^ 7 ^ 8 ^ 11 ^ 15 ^ 16 ^ 20 ^ 22 ^ 24 ^ 25 ^ 27 ^ 29 , + ^ 2 ^ 6 ^ 7 ^ 10 ^ 14 ^ 15 ^ 19 ^ 21 ^ 23 ^ 24 ^ 26 ^ 28 ^ 31, + ^ 1 ^ 5 ^ 6 ^ 9 ^ 13 ^ 14 ^ 18 ^ 20 ^ 22 ^ 23 ^ 25 ^ 27 ^ 30 ^ 31, +0 ^ 4 ^ 5 ^ 8 ^ 12 ^ 13 ^ 17 ^ 19 ^ 21 ^ 22 ^ 24 ^ 26 ^ 29 ^ 30 , + ^ 3 ^ 4 ^ 5 ^ 7 ^ 8 ^ 9 ^ 12 ^ 15 ^ 16 ^ 18 ^ 20 ^ 21 ^ 24 ^ 27 ^ 30 , + ^ 2 ^ 3 ^ 4 ^ 6 ^ 7 ^ 8 ^ 11 ^ 14 ^ 15 ^ 17 ^ 19 ^ 20 ^ 23 ^ 26 ^ 29 , + ^ 1 ^ 2 ^ 3 ^ 5 ^ 6 ^ 7 ^ 10 ^ 13 ^ 14 ^ 16 ^ 18 ^ 19 ^ 22 ^ 25 ^ 28 ^ 31, +0 ^ 1 ^ 2 ^ 4 ^ 5 ^ 6 ^ 9 ^ 12 ^ 13 ^ 15 ^ 17 ^ 18 ^ 21 ^ 24 ^ 27 ^ 30 ^ 31, +0 ^ 1 ^ 3 ^ 4 ^ 9 ^ 12 ^ 14 ^ 15 ^ 16 ^ 17 ^ 20 ^ 24 ^ 25 ^ 26 ^ 27 ^ 28 ^ 31, +0 ^ 2 ^ 3 ^ 5 ^ 9 ^ 13 ^ 14 ^ 16 ^ 19 ^ 26 ^ 28 ^ 29 ^ 31, + ^ 1 ^ 2 ^ 4 ^ 5 ^ 9 ^ 11 ^ 12 ^ 13 ^ 18 ^ 23 ^ 24 ^ 29 , +0 ^ 1 ^ 3 ^ 4 ^ 8 ^ 10 ^ 11 ^ 12 ^ 17 ^ 22 ^ 23 ^ 28 ^ 31, +0 ^ 2 ^ 3 ^ 5 ^ 7 ^ 8 ^ 10 ^ 15 ^ 16 ^ 21 ^ 22 ^ 23 ^ 24 ^ 25 ^ 28 ^ 29 , + ^ 1 ^ 2 ^ 4 ^ 5 ^ 6 ^ 7 ^ 8 ^ 11 ^ 14 ^ 20 ^ 21 ^ 22 ^ 25 ^ 29 ^ 30 , +0 ^ 1 ^ 3 ^ 4 ^ 5 ^ 6 ^ 7 ^ 10 ^ 13 ^ 19 ^ 20 ^ 21 ^ 24 ^ 28 ^ 29 , +0 ^ 2 ^ 3 ^ 4 ^ 6 ^ 8 ^ 11 ^ 12 ^ 15 ^ 18 ^ 19 ^ 20 ^ 24 ^ 25 ^ 29 ^ 30 ^ 31, + ^ 1 ^ 2 ^ 3 ^ 7 ^ 8 ^ 9 ^ 10 ^ 14 ^ 15 ^ 17 ^ 18 ^ 19 ^ 25 ^ 27 ^ 31, +0 ^ 1 ^ 2 ^ 6 ^ 7 ^ 8 ^ 9 ^ 13 ^ 14 ^ 16 ^ 17 ^ 18 ^ 24 ^ 26 ^ 30 ^ 31, +0 ^ 1 ^ 6 ^ 7 ^ 9 ^ 11 ^ 12 ^ 13 ^ 16 ^ 17 ^ 24 ^ 27 ^ 28 , +0 ^ 6 ^ 9 ^ 10 ^ 12 ^ 16 ^ 24 ^ 25 ^ 26 ^ 28 ^ 29 ^ 30 ^ 31 +} +*/ +// There are 2 obvious ways to implement these functions: +// 1) XOR the State bits with the Input bits, then calculate the XOR's +// 2) Independently calculate a result for Inputs and State variables, +// then XOR the results together. +// The second idea seems to take much more logic, but to have no benefit. + + wire X31, X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20; + wire X19, X18, X17, X16, X15, X14, X13, X12, X11, X10, X9, X8; + wire X7, X6, X5, X4, X3, X2, X1, X0; + assign {X31, X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, + X19, X18, X17, X16, X15, X14, X13, X12, X11, X10, X9, X8, + X7, X6, X5, X4, X3, X2, X1, X0} = + data_in_32[NUMBER_OF_BITS_APPLIED - 1 : 0] + ^ ( present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : `NUMBER_OF_BITS_IN_CRC_32 - NUMBER_OF_BITS_APPLIED] + | {NUMBER_OF_BITS_APPLIED{use_F_for_CRC}}); + +// Calculate higher_order terms, to make parity trees. +// NOTE: In a Xilinx chip, it would be fine to constrain X0 and X0_1 to +// be calculated in the same CLB, and so on for all bits. + wire X0_1 = X0 ^ X1; wire X1_2 = X1 ^ X2; + wire X2_3 = X2 ^ X3; wire X3_4 = X3 ^ X4; + wire X4_5 = X4 ^ X5; wire X5_6 = X5 ^ X6; + wire X6_7 = X6 ^ X7; wire X7_8 = X7 ^ X8; +// Use odd-ordered XOR terms because it seems these might be useful + wire X8_12 = X8 ^ X12; wire X12_9 = X12 ^ X9; + wire X9_13 = X9 ^ X13; wire X13_10 = X13 ^ X10; + wire X10_14 = X10 ^ X14; wire X14_11 = X14 ^ X11; + wire X11_15 = X11 ^ X15; +// back to simple ordering + wire X15_16 = X15 ^ X16; + wire X16_17 = X16 ^ X17; wire X17_18 = X17 ^ X18; + wire X18_19 = X18 ^ X19; wire X19_20 = X19 ^ X20; + wire X20_21 = X20 ^ X21; wire X21_22 = X21 ^ X22; + wire X22_23 = X22 ^ X23; wire X23_24 = X23 ^ X24; + wire X24_25 = X24 ^ X25; wire X25_26 = X25 ^ X26; + wire X26_27 = X26 ^ X27; wire X27_28 = X27 ^ X28; + wire X28_29 = X28 ^ X29; wire X29_30 = X29 ^ X30; + wire X30_31 = X30 ^ X31; + +// Calculate terms which might have a single use. They are calculated here +// so that the parity trees can be balanced. + wire X8_9 = X8 ^ X9; wire X29_31 = X29 ^ X31; + wire X28_30 = X28 ^ X30; wire X28_31 = X28 ^ X31; + wire X27_29 = X27 ^ X29; wire X4_6 = X4 ^ X6; + wire X7_11 = X7 ^ X11; wire X6_10 = X6 ^ X10; + wire X22_24 = X22 ^ X24; wire X21_23 = X21 ^ X23; + wire X20_22 = X20 ^ X22; wire X19_21 = X19 ^ X21; + wire X18_20 = X18 ^ X20; wire X17_19 = X17 ^ X19; + wire X24_27 = X24 ^ X27; wire X23_26 = X23 ^ X26; + wire X22_25 = X22 ^ X25; wire X21_24 = X21 ^ X24; + + wire X20_26 = X20 ^ X26; wire X25_27 = X25 ^ X27; + wire X24_26 = X24 ^ X26; wire X18_30 = X18 ^ X30; + wire X15_17 = X15 ^ X17; wire X14_16 = X14 ^ X16; + wire X13_15 = X13 ^ X15; wire X13_11 = X13 ^ X11; + wire X10_11 = X10 ^ X11; wire X10_15 = X10 ^ X15; + wire X3_5 = X3 ^ X5; wire X2_4 = X2 ^ X4; + wire X3_9 = X3 ^ X9; wire X0_5 = X0 ^ X5; + wire X17_20 = X17 ^ X20; wire X16_19 = X16 ^ X19; + wire X16_21 = X16 ^ X21; wire X15_19 = X15 ^ X19; + wire X27_31 = X27 ^ X31; wire X20_31 = X20 ^ X31; + wire X2_8 = X2 ^ X8; + wire X14_18 = X14 ^ X18; + wire X0_6 = X0 ^ X6; + wire X10_16 = X10 ^ X16; + + assign next_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + {((X5 ^ X8_9) ^ (X11_15 ^ X23_24)) ^ ((X25 ^ X27_28) ^ (X29_30 ^ X31)), + ((X4 ^ X7_8) ^ (X10_14 ^ X22_23)) ^ ((X24 ^ X26_27) ^ (X28_29 ^ X30)), + ((X3 ^ X6_7) ^ (X9_13 ^ X21_22)) ^ ((X23 ^ X25_26) ^ (X27_28 ^ X29_31)), + ((X2 ^ X5_6) ^ (X8_12 ^ X20_21)) ^ ((X22 ^ X24_25) ^ (X26_27 ^ X28_30)), + ((X1 ^ X4_5) ^ (X7_11 ^ X19_20)) ^ ((X21 ^ X23_24) ^ (X25_26 ^ X27_29)), + ((X0 ^ X3_4) ^ (X6_10 ^ X18_19)) ^ ((X20_26 ^ X22_23) ^ (X24_25 ^ X28_31)), + ((X2_3 ^ X8) ^ (X11_15 ^ X17_18)) ^ ((X19 ^ X21_22) ^ (X28_29 ^ X31)), + ((X1_2 ^ X7) ^ (X10_14 ^ X16_17)) ^ ((X18 ^ X20_21) ^ (X27_28 ^ X30)), + ((X0_1 ^ X6) ^ (X9_13 ^ X15_16)) ^ ((X17 ^ X19_20) ^ (X26_27 ^ X29_31)), + ((X0 ^ X12_9) ^ (X14_11 ^ X16)) ^ ((X18_19 ^ X23_24) ^ (X26_27 ^ X29_31)), + ((X5 ^ X9_13) ^ (X10 ^ X17_18)) ^ ((X22_24 ^ X26_27) ^ (X29_31)), + ((X4 ^ X8_12) ^ (X9 ^ X16_17)) ^ ((X21_23 ^ X25_26) ^ (X28_30)), + ((X3 ^ X7_8) ^ (X11_15 ^ X16)) ^ ((X20_22 ^ X24_25) ^ (X27_29)), + ((X2 ^ X6_7) ^ (X10_14 ^ X15)) ^ ((X19_21 ^ X23_24) ^ (X26 ^ X28_31)), + ((X1 ^ X5_6) ^ (X9_13 ^ X14)) ^ ((X18_20 ^ X22_23) ^ (X25_27 ^ X30_31)), + ((X0 ^ X4_5) ^ (X8_12 ^ X13)) ^ ((X17_19 ^ X21_22) ^ (X24_26 ^ X29_30)), + ((X3_4 ^ X5) ^ (X7_8 ^ X12_9)) ^ ((X15_16 ^ X18_30) ^ (X20_21 ^ X24_27)), + ((X2_3 ^ X4_6) ^ (X7_8 ^ X14_11)) ^ ((X15_17 ^ X19_20) ^ (X23_26 ^ X29)), + ((X1_2 ^ X3_5) ^ (X6_7 ^ X13_10)) ^ ((X14_16 ^ X18_19) ^ (X22_25 ^ X28_31)), + ((X0_1 ^ X2_4) ^ (X5_6 ^ X12_9)) ^ ((X13_15 ^ X17_18) ^ (X21_24 ^ X27)) ^ X30_31, + ((X0_1 ^ X3_4) ^ (X12_9 ^ X14)) ^ ((X15_16 ^ X17_20) ^ (X24_25 ^ X26_27)) ^ X28_31, + ((X0_5 ^ X2_3) ^ (X9_13 ^ X14)) ^ ((X16_19 ^ X26) ^ (X28_29 ^ X31)), + ((X1_2 ^ X4_5) ^ (X12_9 ^ X13_11)) ^ ((X18 ^ X23_24) ^ (X29)), + ((X0_1 ^ X3_4) ^ (X8_12 ^ X10_11)) ^ ((X17 ^ X22_23) ^ (X28_31)), + ((X0_5 ^ X2_3) ^ (X7_8 ^ X10_15)) ^ ((X16_21 ^ X22_23) ^ (X24_25 ^ X28_29)), + ((X1_2 ^ X4_5) ^ (X6_7 ^ X8)) ^ ((X14_11 ^ X20_21) ^ (X22_25 ^ X29_30)), + ((X0_1 ^ X3_4) ^ (X5_6 ^ X7)) ^ ((X13_10 ^ X19_20) ^ (X21_24 ^ X28_29)), + ((X0 ^ X2_3) ^ (X4_6 ^ X8_12)) ^ ((X11_15 ^ X18_19) ^ (X20_31 ^ X24_25)) ^ X29_30, + ((X1_2 ^ X3_9) ^ (X7_8 ^ X10_14)) ^ ((X15_19 ^ X17_18) ^ (X25 ^ X27_31)), + ((X0_1 ^ X2_8) ^ (X6_7 ^ X9_13)) ^ ((X14_18 ^ X16_17) ^ (X24_26 ^ X30_31)), + ((X0_1 ^ X6_7) ^ (X12_9 ^ X13_11)) ^ ((X16_17 ^ X24) ^ (X27_28)), + ((X0_6 ^ X12_9) ^ (X10_16 ^ X24_25)) ^ ((X26 ^ X28_29) ^ (X30_31)) + }; +endmodule + +// Calculate the Data dependent part of the CRC-32 function with 64 inputs here in +// a separate module so that the user can pipeline this one clock earlier. This +// MIGHT mean that the whole thing can run faster. If not, use as a function! +module crc_32_64_data_private ( + data_in_64, + data_part_1_out, data_part_2_out +); + parameter NUMBER_OF_BITS_APPLIED = 64; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_64; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_part_1_out; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_part_2_out; + +/* +// After looking at this, I am getting the feeling that the layout of the circuit would +// be the best if more complicated terms were collected from adjacent simple terms. +// For instance, the first line might use a term X5^X8, then another X9^X11 +// +// Data Input dependencies +{ +X5 ^X8^X9 ^X11 ^X15 ^X23^X24^X25 ^X27^X28^X29^X30^X31 ^X33 ^X36 ^X43^X44 ^X46^X47 ^X49 ^X52^X53^X54 ^X57 ^X59^X60 ^X62, +X4 ^X7^X8 ^X10 ^X14 ^X22^X23^X24 ^X26^X27^X28^X29^X30 ^X32 ^X35 ^X42^X43 ^X45^X46 ^X48 ^X51^X52^X53 ^X56 ^X58^X59 ^X61 ^X63, +X3 ^X6^X7 ^X9 ^X13 ^X21^X22^X23 ^X25^X26^X27^X28^X29 ^X31 ^X34 ^X41^X42 ^X44^X45 ^X47 ^X50^X51^X52 ^X55 ^X57^X58 ^X60 ^X62^X63, +X2 ^X5^X6 ^X8 ^X12 ^X20^X21^X22 ^X24^X25^X26^X27^X28 ^X30 ^X33 ^X40^X41 ^X43^X44 ^X46 ^X49^X50^X51 ^X54 ^X56^X57 ^X59 ^X61^X62^X63, +X1 ^X4^X5 ^X7 ^X11 ^X19^X20^X21 ^X23^X24^X25^X26^X27 ^X29 ^X32 ^X39^X40 ^X42^X43 ^X45 ^X48^X49^X50 ^X53 ^X55^X56 ^X58 ^X60^X61^X62^X63, +X0 ^X3^X4 ^X6 ^X10 ^X18^X19^X20 ^X22^X23^X24^X25^X26 ^X28 ^X31 ^X38^X39 ^X41^X42 ^X44 ^X47^X48^X49 ^X52 ^X54^X55 ^X57 ^X59^X60^X61^X62, +X2^X3 ^X8 ^X11 ^X15 ^X17^X18^X19 ^X21^X22 ^X28^X29 ^X31 ^X33 ^X36^X37^X38 ^X40^X41 ^X44 ^X48^X49 ^X51^X52 ^X56^X57^X58 ^X61^X62, +X1^X2 ^X7 ^X10 ^X14 ^X16^X17^X18 ^X20^X21 ^X27^X28 ^X30 ^X32 ^X35^X36^X37 ^X39^X40 ^X43 ^X47^X48 ^X50^X51 ^X55^X56^X57 ^X60^X61 ^X63, +X0^X1 ^X6 ^X9 ^X13 ^X15^X16^X17 ^X19^X20 ^X26^X27 ^X29 ^X31 ^X34^X35^X36 ^X38^X39 ^X42 ^X46^X47 ^X49^X50 ^X54^X55^X56 ^X59^X60 ^X62, +X0 ^X9 ^X11^X12 ^X14 ^X16 ^X18^X19 ^X23^X24 ^X26^X27 ^X29 ^X31 ^X34^X35^X36^X37^X38 ^X41 ^X43^X44^X45 ^X47^X48 ^X52 ^X55 ^X57^X58 ^X60^X61^X62, +X5 ^X9^X10 ^X13 ^X17^X18 ^X22 ^X24 ^X26^X27 ^X29 ^X31 ^X34^X35 ^X37 ^X40 ^X42 ^X49 ^X51^X52^X53 ^X56 ^X61^X62, +X4 ^X8^X9 ^X12 ^X16^X17 ^X21 ^X23 ^X25^X26 ^X28 ^X30 ^X33^X34 ^X36 ^X39 ^X41 ^X48 ^X50^X51^X52 ^X55 ^X60^X61, +X3 ^X7^X8 ^X11 ^X15^X16 ^X20 ^X22 ^X24^X25 ^X27 ^X29 ^X32^X33 ^X35 ^X38 ^X40 ^X47 ^X49^X50^X51 ^X54 ^X59^X60, +X2 ^X6^X7 ^X10 ^X14^X15 ^X19 ^X21 ^X23^X24 ^X26 ^X28 ^X31^X32 ^X34 ^X37 ^X39 ^X46 ^X48^X49^X50 ^X53 ^X58^X59, +X1 ^X5^X6 ^X9 ^X13^X14 ^X18 ^X20 ^X22^X23 ^X25 ^X27 ^X30^X31 ^X33 ^X36 ^X38 ^X45 ^X47^X48^X49 ^X52 ^X57^X58, +X0 ^X4^X5 ^X8 ^X12^X13 ^X17 ^X19 ^X21^X22 ^X24 ^X26 ^X29^X30 ^X32 ^X35 ^X37 ^X44 ^X46^X47^X48 ^X51 ^X56^X57, +X3^X4^X5 ^X7^X8^X9 ^X12 ^X15^X16 ^X18 ^X20^X21 ^X24 ^X27 ^X30 ^X33^X34 ^X44^X45 ^X49^X50 ^X52^X53^X54^X55^X56^X57 ^X59^X60 ^X62, +X2^X3^X4 ^X6^X7^X8 ^X11 ^X14^X15 ^X17 ^X19^X20 ^X23 ^X26 ^X29 ^X32^X33 ^X43^X44 ^X48^X49 ^X51^X52^X53^X54^X55^X56 ^X58^X59 ^X61 ^X63, +X1^X2^X3 ^X5^X6^X7 ^X10 ^X13^X14 ^X16 ^X18^X19 ^X22 ^X25 ^X28 ^X31^X32 ^X42^X43 ^X47^X48 ^X50^X51^X52^X53^X54^X55 ^X57^X58 ^X60 ^X62, +X0^X1^X2 ^X4^X5^X6 ^X9 ^X12^X13 ^X15 ^X17^X18 ^X21 ^X24 ^X27 ^X30^X31 ^X41^X42 ^X46^X47 ^X49^X50^X51^X52^X53^X54 ^X56^X57 ^X59 ^X61 ^X63, +X0^X1 ^X3^X4 ^X9 ^X12 ^X14^X15^X16^X17 ^X20 ^X24^X25^X26^X27^X28 ^X31 ^X33 ^X36 ^X40^X41 ^X43^X44^X45 ^X47^X48 ^X50^X51 ^X54^X55^X56^X57^X58^X59, +X0 ^X2^X3 ^X5 ^X9 ^X13^X14 ^X16 ^X19 ^X26 ^X28^X29 ^X31^X32^X33 ^X35^X36 ^X39^X40 ^X42 ^X50 ^X52 ^X55^X56 ^X58^X59^X60 ^X62^X63, +X1^X2 ^X4^X5 ^X9 ^X11^X12^X13 ^X18 ^X23^X24 ^X29 ^X32^X33^X34^X35^X36 ^X38^X39 ^X41 ^X43^X44 ^X46^X47 ^X51^X52^X53 ^X55 ^X58 ^X60^X61, +X0^X1 ^X3^X4 ^X8 ^X10^X11^X12 ^X17 ^X22^X23 ^X28 ^X31^X32^X33^X34^X35 ^X37^X38 ^X40 ^X42^X43 ^X45^X46 ^X50^X51^X52 ^X54 ^X57 ^X59^X60 ^X63, +X0 ^X2^X3 ^X5 ^X7^X8 ^X10 ^X15^X16 ^X21^X22^X23^X24^X25 ^X28^X29 ^X32 ^X34 ^X37 ^X39 ^X41^X42^X43 ^X45^X46^X47 ^X50^X51^X52 ^X54 ^X56^X57^X58 ^X60, +X1^X2 ^X4^X5^X6^X7^X8 ^X11 ^X14 ^X20^X21^X22 ^X25 ^X29^X30 ^X38 ^X40^X41^X42^X43 ^X45 ^X47 ^X50^X51^X52 ^X54^X55^X56 ^X60 ^X62, +X0^X1 ^X3^X4^X5^X6^X7 ^X10 ^X13 ^X19^X20^X21 ^X24 ^X28^X29 ^X37 ^X39^X40^X41^X42 ^X44 ^X46 ^X49^X50^X51 ^X53^X54^X55 ^X59 ^X61 ^X63, +X0 ^X2^X3^X4 ^X6 ^X8 ^X11^X12 ^X15 ^X18^X19^X20 ^X24^X25 ^X29^X30^X31 ^X33 ^X38^X39^X40^X41 ^X44^X45^X46^X47^X48 ^X50 ^X57^X58^X59 ^X63, +X1^X2^X3 ^X7^X8^X9^X10 ^X14^X15 ^X17^X18^X19 ^X25 ^X27 ^X31^X32^X33 ^X36^X37^X38^X39^X40 ^X45 ^X52^X53^X54 ^X56 ^X58^X59^X60, +X0^X1^X2 ^X6^X7^X8^X9 ^X13^X14 ^X16^X17^X18 ^X24 ^X26 ^X30^X31^X32 ^X35^X36^X37^X38^X39 ^X44 ^X51^X52^X53 ^X55 ^X57^X58^X59, +X0^X1 ^X6^X7 ^X9 ^X11^X12^X13 ^X16^X17 ^X24 ^X27^X28 ^X33^X34^X35 ^X37^X38 ^X44 ^X46^X47 ^X49^X50^X51 ^X53 ^X56 ^X58^X59^X60 ^X62^X63, +X0 ^X6 ^X9^X10 ^X12 ^X16 ^X24^X25^X26 ^X28^X29^X30^X31^X32 ^X34 ^X37 ^X44^X45 ^X47^X48 ^X50 ^X53^X54^X55 ^X58 ^X60^X61 ^X63 +} +*/ +// Data terms depend ONLY on data in. + wire D63, D62, D61, D60, D59, D58, D57, D56, D55, D54, D53, D52; + wire D51, D50, D49, D48, D47, D46, D45, D44, D43, D42, D41, D40; + wire D39, D38, D37, D36, D35, D34, D33, D32; + wire D31, D30, D29, D28, D27, D26, D25, D24, D23, D22, D21, D20; + wire D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8; + wire D7, D6, D5, D4, D3, D2, D1, D0; + assign {D63, D62, D61, D60, D59, D58, D57, D56, D55, D54, D53, D52, + D51, D50, D49, D48, D47, D46, D45, D44, D43, D42, D41, D40, + D39, D38, D37, D36, D35, D34, D33, D32, + D31, D30, D29, D28, D27, D26, D25, D24, D23, D22, D21, D20, + D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, + D7, D6, D5, D4, D3, D2, D1, D0} = + data_in_64[63 : 0]; + +// Calculate higher_order terms, to make parity trees. +// NOTE: In a Xilinx chip, it would be fine to constrain D0 and D0_1 to +// be calculated in the same CLB, and so on for all bits. + wire D0_1 = D0 ^ D1; wire D1_2 = D1 ^ D2; + wire D2_3 = D2 ^ D3; wire D3_4 = D3 ^ D4; + wire D4_5 = D4 ^ D5; wire D5_6 = D5 ^ D6; + wire D6_7 = D6 ^ D7; wire D7_8 = D7 ^ D8; + wire D8_9 = D8 ^ D9; wire D9_10 = D9 ^ D10; + wire D10_11 = D10 ^ D11; wire D11_12 = D11 ^ D12; + wire D12_13 = D12 ^ D13; wire D13_14 = D13 ^ D14; + wire D14_15 = D14 ^ D15; wire D15_16 = D15 ^ D16; + wire D16_17 = D16 ^ D17; wire D17_18 = D17 ^ D18; + wire D18_19 = D18 ^ D19; wire D19_20 = D19 ^ D20; + wire D20_21 = D20 ^ D21; wire D21_22 = D21 ^ D22; + wire D22_23 = D22 ^ D23; wire D23_24 = D23 ^ D24; + wire D24_25 = D24 ^ D25; wire D25_26 = D25 ^ D26; + wire D26_27 = D26 ^ D27; wire D27_28 = D27 ^ D28; + wire D28_29 = D28 ^ D29; wire D29_30 = D29 ^ D30; + wire D30_31 = D30 ^ D31; wire D31_32 = D31 ^ D32; + wire D32_33 = D32 ^ D33; wire D33_34 = D33 ^ D34; + wire D34_35 = D34 ^ D35; wire D35_36 = D35 ^ D36; + wire D36_37 = D36 ^ D37; wire D37_38 = D37 ^ D38; + wire D38_39 = D38 ^ D39; wire D39_40 = D39 ^ D40; + wire D40_41 = D40 ^ D41; wire D41_42 = D41 ^ D42; + wire D42_43 = D42 ^ D43; wire D43_44 = D43 ^ D44; + wire D44_45 = D44 ^ D45; wire D45_46 = D45 ^ D46; + wire D46_47 = D46 ^ D47; wire D47_48 = D47 ^ D48; + wire D48_49 = D48 ^ D49; wire D49_50 = D49 ^ D50; + wire D50_51 = D50 ^ D51; wire D51_52 = D51 ^ D52; + wire D52_53 = D52 ^ D53; wire D53_54 = D53 ^ D54; + wire D54_55 = D54 ^ D55; wire D55_56 = D55 ^ D56; + wire D56_57 = D56 ^ D57; wire D57_58 = D57 ^ D58; + wire D58_59 = D58 ^ D59; wire D59_60 = D59 ^ D60; + wire D60_61 = D60 ^ D61; wire D61_62 = D61 ^ D62; + wire D62_63 = D62 ^ D63; + +// Calculate terms which might have a single use. They are calculated here +// so that the parity trees can be balanced. + + wire D5_11 = D5 ^ D11; wire D15_23 = D15 ^ D23; + wire D4_10 = D4 ^ D10; wire D14_22 = D14 ^ D22; + wire D3_9 = D3 ^ D9; wire D13_21 = D13 ^ D21; + wire D2_8 = D2 ^ D8; wire D12_20 = D12 ^ D20; + wire D1_7 = D1 ^ D7; wire D11_19 = D11 ^ D19; + wire D0_6 = D0 ^ D6; wire D10_18 = D10 ^ D18; + wire D8_11 = D8 ^ D11; wire D15_17 = D15 ^ D17; + wire D7_10 = D7 ^ D10; wire D14_16 = D14 ^ D16; + wire D6_9 = D6 ^ D9; wire D13_15 = D13 ^ D15; + wire D0_9 = D0 ^ D9; + wire D5_13 = D5 ^ D13; wire D22_24 = D22 ^ D24; + wire D4_12 = D4 ^ D12; wire D21_23 = D21 ^ D23; + wire D3_11 = D3 ^ D11; wire D20_22 = D20 ^ D22; + wire D2_10 = D2 ^ D10; wire D19_21 = D19 ^ D21; + wire D1_9 = D1 ^ D9; wire D18_20 = D18 ^ D20; + wire D0_8 = D0 ^ D8; wire D17_19 = D17 ^ D19; + wire D5_7 = D5 ^ D7; wire D12_18 = D12 ^ D18; + wire D4_6 = D4 ^ D6; wire D11_17 = D11 ^ D17; + wire D3_5 = D3 ^ D5; wire D10_16 = D10 ^ D16; + wire D2_4 = D2 ^ D4; wire D9_15 = D9 ^ D15; + wire D29_31 = D29 ^ D31; wire D37_40 = D37 ^ D40; + wire D28_30 = D28 ^ D30; wire D36_39 = D36 ^ D39; + wire D27_29 = D27 ^ D29; wire D35_38 = D35 ^ D38; + wire D26_28 = D26 ^ D28; wire D34_37 = D34 ^ D37; + wire D25_27 = D25 ^ D27; wire D33_36 = D33 ^ D36; + wire D24_26 = D24 ^ D26; wire D32_35 = D32 ^ D35; + wire D31_33 = D31 ^ D33; wire D30_32 = D30 ^ D32; + wire D36_49 = D36 ^ D49; wire D54_57 = D54 ^ D57; + wire D35_48 = D35 ^ D48; wire D53_56 = D53 ^ D56; + wire D34_47 = D34 ^ D47; wire D52_55 = D52 ^ D55; + wire D33_46 = D33 ^ D46; wire D51_54 = D51 ^ D54; + wire D32_45 = D32 ^ D45; wire D50_53 = D50 ^ D53; + wire D31_44 = D31 ^ D44; wire D49_52 = D49 ^ D52; + wire D38_44 = D38 ^ D44; wire D37_43 = D37 ^ D43; + wire D36_42 = D36 ^ D42; wire D38_41 = D38 ^ D41; + wire D59_61 = D59 ^ D61; wire D61_63 = D61 ^ D63; + wire D58_60 = D58 ^ D60; wire D57_59 = D57 ^ D59; + wire D57_63 = D57 ^ D63; wire D56_62 = D56 ^ D62; + wire D45_52 = D45 ^ D52; wire D55_60 = D55 ^ D60; + wire D42_49 = D42 ^ D49; wire D41_48 = D41 ^ D48; + wire D40_47 = D40 ^ D47; wire D39_46 = D39 ^ D46; + wire D38_45 = D38 ^ D45; + wire D37_44 = D37 ^ D44; wire D48_51 = D48 ^ D51; + wire D24_27 = D24 ^ D27; wire D30_52 = D30 ^ D52; + wire D23_26 = D23 ^ D26; wire D29_51 = D29 ^ D51; + wire D22_25 = D22 ^ D25; wire D28_50 = D28 ^ D50; + wire D21_24 = D21 ^ D24; wire D27_49 = D27 ^ D49; + wire D57_62 = D57 ^ D62; wire D56_61 = D56 ^ D61; + wire D54_59 = D54 ^ D59; + wire D9_12 = D9 ^ D12; wire D20_24 = D20 ^ D24; + wire D36_43 = D36 ^ D43; + wire D0_5 = D0 ^ D5; wire D9_16 = D9 ^ D16; + wire D19_26 = D19 ^ D26; wire D33_42 = D33 ^ D42; + wire D50_52 = D50 ^ D52; + wire D9_11 = D9 ^ D11; wire D18_29 = D18 ^ D29; + wire D36_41 = D36 ^ D41; + wire D53_55 = D53 ^ D55; + wire D8_10 = D8 ^ D10; wire D17_28 = D17 ^ D28; + wire D35_40 = D35 ^ D40; wire D52_54 = D52 ^ D54; + wire D10_21 = D10 ^ D21; wire D32_34 = D32 ^ D34; + wire D37_39 = D37 ^ D39; wire D43_45 = D43 ^ D45; + wire D14_20 = D14 ^ D20; wire D25_38 = D25 ^ D38; + wire D45_47 = D45 ^ D47; wire D60_62 = D60 ^ D62; + wire D13_19 = D13 ^ D19; + wire D24_37 = D24 ^ D37; wire D44_46 = D44 ^ D46; + wire D51_53 = D51 ^ D53; + wire D0_2 = D0 ^ D2; wire D6_8 = D6 ^ D8; + wire D15_18 = D15 ^ D18; + wire D48_50 = D48 ^ D50; wire D59_63 = D59 ^ D63; + wire D3_17 = D3 ^ D17; wire D56_58 = D56 ^ D58; + wire D2_16 = D2 ^ D16; wire D44_51 = D44 ^ D51; + wire D55_57 = D55 ^ D57; + wire D24_33 = D24 ^ D33; wire D44_49 = D44 ^ D49; + wire D12_16 = D12 ^ D16; wire D58_63 = D58 ^ D63; + + +// Need to distribute this logic so that it can be fast. The user can +// use 1 or 2 outputs, just so long as their XOR is the final value. + + assign data_part_1_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = // first half of each formula + { (((D5_11 ^ D8_9) ^ (D15_23 ^D24_25)) ^ ((D27_28 ^D29_30) ^ (D31_33 ^D36_49))), + (((D4_10 ^ D7_8) ^ (D14_22 ^D23_24)) ^ ((D26_27 ^D28_29) ^ (D30_32 ^D35_48))), + (((D3_9 ^ D6_7) ^ (D13_21 ^D22_23)) ^ ((D25_26 ^D27_28) ^ (D29_31 ^D34_47))), + (((D2_8 ^ D5_6) ^ (D12_20 ^D21_22)) ^ ((D24_25 ^D26_27) ^ (D28_30 ^D33_46))), + (((D1_7 ^ D4_5) ^ (D11_19 ^D20_21)) ^ ((D23_24 ^D25_26) ^ (D27_29 ^D32_45))), + (((D0_6 ^ D3_4) ^ (D10_18 ^D19_20)) ^ ((D22_23 ^D24_25) ^ (D26_28 ^D31_44))), + (((D2_3 ^ D8_11) ^ (D15_17 ^D18_19)) ^ ((D21_22 ^D28_29) ^ (D31_33 ^D36_37))), + (((D1_2 ^ D7_10) ^ (D14_16 ^D17_18)) ^ ((D20_21 ^D27_28) ^ (D30_32 ^D35_36))), + (((D0_1 ^ D6_9) ^ (D13_15 ^D16_17)) ^ ((D19_20 ^D26_27) ^ (D29_31 ^D34_35))), + (((D0_9 ^ D11_12) ^ (D14_16 ^D18_19)) ^ ((D23_24 ^D26_27) ^ (D29_31 ^D34_35))), + (((D5_13 ^ D9_10) ^ (D17_18 ^D22_24)) ^ ((D26_27 ^D29_31) ^ (D34_35 ^D37_40))), + (((D4_12 ^ D8_9) ^ (D16_17 ^D21_23)) ^ ((D25_26 ^D28_30) ^ (D33_34 ^D36_39))), + (((D3_11 ^ D7_8) ^ (D15_16 ^D20_22)) ^ ((D24_25 ^D27_29) ^ (D32_33 ^D35_38))), + (((D2_10 ^ D6_7) ^ (D14_15 ^D19_21)) ^ ((D23_24 ^D26_28) ^ (D31_32 ^D34_37))), + (((D1_9 ^ D5_6) ^ (D13_14 ^D18_20)) ^ ((D22_23 ^D25_27) ^ (D30_31 ^D33_36))), + (((D0_8 ^ D4_5) ^ (D12_13 ^D17_19)) ^ ((D21_22 ^D24_26) ^ (D29_30 ^D32_35))), + (((D3_4 ^ D5_7) ^ (D8_9 ^D12_18)) ^ ((D15_16 ^D20_21) ^ (D24_27 ^D30_52))), + (((D2_3 ^ D4_6) ^ (D7_8 ^D11_17)) ^ ((D14_15 ^D19_20) ^ (D23_26 ^D29_51))), + (((D1_2 ^ D3_5) ^ (D6_7 ^D10_16)) ^ ((D13_14 ^D18_19) ^ (D22_25 ^D28_50))), + (((D0_1 ^ D2_4) ^ (D5_6 ^D9_15)) ^ ((D12_13 ^D17_18) ^ (D21_24 ^D27_49))), + (((D0_1 ^ D3_4) ^ (D9_12 ^D14_15)) ^ ((D16_17 ^D20_24) ^ (D25_26 ^D27_28))), + (((D0_5 ^ D2_3) ^ (D9_16 ^D13_14)) ^ ((D19_26 ^D28_29) ^ (D31_32 ^D33_42))), + (((D1_2 ^ D4_5) ^ (D9_11 ^D12_13)) ^ ((D18_29 ^D23_24) ^ (D32_33 ^D34_35))), + (((D0_1 ^ D3_4) ^ (D8_10 ^D11_12)) ^ ((D17_28 ^D22_23) ^ (D31_32 ^D33_34))), + (((D0_5 ^ D2_3) ^ (D7_8 ^D10_21)) ^ ((D15_16 ^D22_23) ^ (D24_25 ^D28_29))), + (((D1_2 ^ D4_5) ^ (D6_7 ^D8_11)) ^ ((D14_20 ^D21_22) ^ (D25_38 ^D29_30))), + (((D0_1 ^ D3_4) ^ (D5_6 ^D7_10)) ^ ((D13_19 ^D20_21) ^ (D24_37 ^D28_29))), + (((D0_2 ^ D3_4) ^ (D6_8 ^D11_12)) ^ ((D15_18 ^D19_20) ^ (D24_25 ^D29_30))), + (((D1_2 ^ D3_17) ^ (D7_8 ^D9_10)) ^ ((D14_15 ^D18_19) ^ (D25_27 ^D31_32))), + (((D0_1 ^ D2_16) ^ (D6_7 ^D8_9)) ^ ((D13_14 ^D17_18) ^ (D24_26 ^D30_31))), + (((D0_1 ^ D6_7) ^ (D9_11 ^D12_13)) ^ ((D16_17 ^D24_33) ^ (D27_28 ^D34_35))), + (((D0_6 ^ D9_10) ^ (D12_16 ^D24_25)) ^ ((D26_28 ^D29_30) ^ (D31_32 ^D34_37))) + }; + + assign data_part_2_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + { (((D43_44 ^ D46_47) ^ (D52_53 ^ D54_57)) ^ ((D59_60 ^ D62))), + (((D42_43 ^ D45_46) ^ (D51_52 ^ D53_56)) ^ ((D58_59 ^ D61_63))), + (((D41_42 ^ D44_45) ^ (D50_51 ^ D52_55)) ^ ((D57_58 ^ D60) ^ D62_63)), + (((D40_41 ^ D43_44) ^ (D49_50 ^ D51_54)) ^ ((D56_57 ^ D59_61) ^ D62_63)), + (((D39_40 ^ D42_43) ^ (D48_49 ^ D50_53)) ^ ((D55_56 ^ D58_60) ^ (D61_62 ^ D63))), + (((D38_39 ^ D41_42) ^ (D47_48 ^ D49_52)) ^ ((D54_55 ^ D57_59) ^ (D60_61 ^ D62))), + (((D38_44 ^ D40_41) ^ (D48_49 ^ D51_52)) ^ ((D56_57 ^ D58) ^ D61_62)), + (((D37_43 ^ D39_40) ^ (D47_48 ^ D50_51)) ^ ((D55_56 ^ D57_63) ^ D60_61)), + (((D36_42 ^ D38_39) ^ (D46_47 ^ D49_50)) ^ ((D54_55 ^ D56_62) ^ D59_60)), + (((D36_37 ^ D38_41) ^ (D43_44 ^ D45_52)) ^ ((D47_48 ^ D55_60) ^ (D57_58 ^ D61_62))), + (((D42_49 ^ D51_52) ^ (D53_56 ^ D61_62))), + (((D41_48 ^ D50_51) ^ (D52_55 ^ D60_61))), + (((D40_47 ^ D49_50) ^ (D51_54 ^ D59_60))), + (((D39_46 ^ D48_49) ^ (D50_53 ^ D58_59))), + (((D38_45 ^ D47_48) ^ (D49_52 ^ D57_58))), + (((D37_44 ^ D46_47) ^ (D48_51 ^ D56_57))), + (((D33_34 ^ D44_45) ^ (D49_50 ^ D53_54)) ^ ((D55_56 ^ D57_62) ^ D59_60)), + (((D32_33 ^ D43_44) ^ (D48_49 ^ D52_53)) ^ ((D54_55 ^ D56_61) ^ (D58_59 ^ D63))), + (((D31_32 ^ D42_43) ^ (D47_48 ^ D51_52)) ^ ((D53_54 ^ D55_60) ^ (D57_58 ^ D62))), + (((D30_31 ^ D41_42) ^ (D46_47 ^ D50_51)) ^ ((D52_53 ^ D54_59) ^ (D56_57 ^ D61_63))), + (((D31_33 ^ D36_43) ^ (D40_41 ^ D44_45)) ^ ((D47_48 ^ D50_51) ^ (D54_55 ^ D56_57))) ^ D58_59, + (((D35_36 ^ D39_40) ^ (D50_52 ^ D55_56)) ^ ((D58_59 ^ D60) ^ D62_63)), + (((D36_41 ^ D38_39) ^ (D43_44 ^ D46_47)) ^ ((D51_52 ^ D53_55) ^ (D58 ^ D60_61))), + (((D35_40 ^ D37_38) ^ (D42_43 ^ D45_46)) ^ ((D50_51 ^ D52_54) ^ (D57_63 ^ D59_60))), + (((D32_34 ^ D37_39) ^ (D41_42 ^ D43_45)) ^ ((D46_47 ^ D50_51) ^ (D52_54 ^ D56_57))) ^ D58_60, + (((D40_41 ^ D42_43) ^ (D45_47 ^ D50_51)) ^ ((D52_54 ^ D55_56) ^ D60_62)), + (((D39_40 ^ D41_42) ^ (D44_46 ^ D49_50)) ^ ((D51_53 ^ D54_55) ^ (D59 ^ D61_63))), + (((D31_33 ^ D38_39) ^ (D40_41 ^ D44_45)) ^ ((D46_47 ^ D48_50) ^ (D57_58 ^ D59_63))), + (((D33_36 ^ D37_38) ^ (D39_40 ^ D45_52)) ^ ((D53_54 ^ D56_58) ^ D59_60)), + (((D32_35 ^ D36_37) ^ (D38_39 ^ D44_51)) ^ ((D52_53 ^ D55_57) ^ D58_59)), + (((D37_38 ^ D44_49) ^ (D46_47 ^ D50_51)) ^ ((D53_56 ^ D58_59) ^ (D60 ^ D62_63))), + (((D44_45 ^ D47_48) ^ (D50_53 ^ D54_55)) ^ ((D58_63 ^ D60_61))) + }; +endmodule + +module crc_32_64_crc_private ( + use_F_for_CRC, + present_crc, + crc_part_1_out, crc_part_2_out +); + input use_F_for_CRC; + input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] crc_part_1_out; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] crc_part_2_out; + +/* +// CRC input dependencies +{ +C1 ^C4 ^C11^C12 ^C14^C15 ^C17 ^C20^C21^C22 ^C25 ^C27^C28 ^C30, +C0 ^C3 ^C10^C11 ^C13^C14 ^C16 ^C19^C20^C21 ^C24 ^C26^C27 ^C29 ^C31, +C2 ^C9^C10 ^C12^C13 ^C15 ^C18^C19^C20 ^C23 ^C25^C26 ^C28 ^C30^C31, +C1 ^C8^C9 ^C11^C12 ^C14 ^C17^C18^C19 ^C22 ^C24^C25 ^C27 ^C29^C30^C31, +C0 ^C7^C8 ^C10^C11 ^C13 ^C16^C17^C18 ^C21 ^C23^C24 ^C26 ^C28^C29^C30^C31, +C6^C7 ^C9^C10 ^C12 ^C15^C16^C17 ^C20 ^C22^C23 ^C25 ^C27^C28^C29^C30, +C1 ^C4^C5^C6 ^C8^C9 ^C12 ^C16^C17 ^C19^C20 ^C24^C25^C26 ^C29^C30, +C0 ^C3^C4^C5 ^C7^C8 ^C11 ^C15^C16 ^C18^C19 ^C23^C24^C25 ^C28^C29 ^C31, +C2^C3^C4 ^C6^C7 ^C10 ^C14^C15 ^C17^C18 ^C22^C23^C24 ^C27^C28 ^C30, +C2^C3^C4^C5^C6 ^C9 ^C11^C12^C13 ^C15^C16 ^C20 ^C23 ^C25^C26 ^C28^C29^C30, +C2^C3 ^C5 ^C8 ^C10 ^C17 ^C19^C20^C21 ^C24 ^C29^C30, +C1^C2 ^C4 ^C7 ^C9 ^C16 ^C18^C19^C20 ^C23 ^C28^C29, +C0^C1 ^C3 ^C6 ^C8 ^C15 ^C17^C18^C19 ^C22 ^C27^C28, +C0 ^C2 ^C5 ^C7 ^C14 ^C16^C17^C18 ^C21 ^C26^C27, +C1 ^C4 ^C6 ^C13 ^C15^C16^C17 ^C20 ^C25^C26, +C0 ^C3 ^C5 ^C12 ^C14^C15^C16 ^C19 ^C24^C25, +C1^C2 ^C12^C13 ^C17^C18 ^C20^C21^C22^C23^C24^C25 ^C27^C28 ^C30, +C0^C1 ^C11^C12 ^C16^C17 ^C19^C20^C21^C22^C23^C24 ^C26^C27 ^C29 ^C31, +C0 ^C10^C11 ^C15^C16 ^C18^C19^C20^C21^C22^C23 ^C25^C26 ^C28 ^C30, +C9^C10 ^C14^C15 ^C17^C18^C19^C20^C21^C22 ^C24^C25 ^C27 ^C29 ^C31, +C1 ^C4 ^C8^C9 ^C11^C12^C13 ^C15^C16 ^C18^C19 ^C22^C23^C24^C25^C26^C27, +C0^C1 ^C3^C4 ^C7^C8 ^C10 ^C18 ^C20 ^C23^C24 ^C26^C27^C28 ^C30^C31, +C0^C1^C2^C3^C4 ^C6^C7 ^C9 ^C11^C12 ^C14^C15 ^C19^C20^C21 ^C23 ^C26 ^C28^C29, +C0^C1^C2^C3 ^C5^C6 ^C8 ^C10^C11 ^C13^C14 ^C18^C19^C20 ^C22 ^C25 ^C27^C28 ^C31, +C0 ^C2 ^C5 ^C7 ^C9^C10^C11 ^C13^C14^C15 ^C18^C19^C20 ^C22 ^C24^C25^C26 ^C28, +C6 ^C8^C9^C10^C11 ^C13 ^C15 ^C18^C19^C20 ^C22^C23^C24 ^C28 ^C30, +C5 ^C7^C8^C9^C10 ^C12 ^C14 ^C17^C18^C19 ^C21^C22^C23 ^C27 ^C29 ^C31, +C1 ^C6^C7^C8^C9 ^C12^C13^C14^C15^C16 ^C18 ^C25^C26^C27 ^C31, +C0^C1 ^C4^C5^C6^C7^C8 ^C13 ^C20^C21^C22 ^C24 ^C26^C27^C28, +C0 ^C3^C4^C5^C6^C7 ^C12 ^C19^C20^C21 ^C23 ^C25^C26^C27, +C1^C2^C3 ^C5^C6 ^C12 ^C14^C15 ^C17^C18^C19 ^C21 ^C24 ^C26^C27^C28 ^C30^C31, +C0 ^C2 ^C5 ^C12^C13 ^C15^C16 ^C18 ^C21^C22^C23 ^C26 ^C28^C29 ^C31 +} + */ +// CRC terms depend ONLY on CRC data from the previous clock + wire C31, C30, C29, C28, C27, C26, C25, C24, C23, C22, C21, C20, C19, C18, C17; + wire C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0; + assign {C31, C30, C29, C28, C27, C26, C25, C24, + C23, C22, C21, C20, C19, C18, C17, C16, C15, C14, C13, C12, + C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0} = + present_crc[`NUMBER_OF_BITS_IN_CRC_32- 1 : 0] + | {`NUMBER_OF_BITS_IN_CRC_32{use_F_for_CRC}}; + + wire C0_1 = C0 ^ C1; wire C1_2 = C1 ^ C2; + wire C2_3 = C2 ^ C3; wire C3_4 = C3 ^ C4; + wire C4_5 = C4 ^ C5; wire C5_6 = C5 ^ C6; + wire C6_7 = C6 ^ C7; wire C7_8 = C7 ^ C8; + wire C8_9 = C8 ^ C9; wire C9_10 = C9 ^ C10; + wire C10_11 = C10 ^ C11; wire C11_12 = C11 ^ C12; + wire C12_13 = C12 ^ C13; wire C13_14 = C13 ^ C14; + wire C14_15 = C14 ^ C15; wire C15_16 = C15 ^ C16; + wire C16_17 = C16 ^ C17; wire C17_18 = C17 ^ C18; + wire C18_19 = C18 ^ C19; wire C19_20 = C19 ^ C20; + wire C20_21 = C20 ^ C21; wire C21_22 = C21 ^ C22; + wire C22_23 = C22 ^ C23; wire C23_24 = C23 ^ C24; + wire C24_25 = C24 ^ C25; wire C25_26 = C25 ^ C26; + wire C26_27 = C26 ^ C27; wire C27_28 = C27 ^ C28; + wire C28_29 = C28 ^ C29; wire C29_30 = C29 ^ C30; + wire C30_31 = C30 ^ C31; + +// Calculate terms which might have a single use. They are calculated here +// so that the parity trees can be balanced. + wire C1_4 = C1 ^ C4; wire C0_3 = C0 ^ C3; + wire C0_2 = C0 ^ C2; wire C5_7 = C5 ^ C7; + wire C17_20 = C17 ^ C20; wire C25_30 = C25 ^ C30; + wire C16_19 = C16 ^ C19; wire C24_31 = C24 ^ C31; + wire C2_15 = C2 ^ C15; wire C18_23 = C18 ^ C23; + wire C1_14 = C1 ^ C14; wire C17_22 = C17 ^ C22; + wire C0_13 = C0 ^ C13; wire C16_21 = C16 ^ C21; + wire C27_29 = C27 ^ C29; wire C12_15 = C12 ^ C15; + wire C20_25 = C20 ^ C25; wire C12_24 = C12 ^ C24; + wire C11_23 = C11 ^ C23; wire C4_10 = C4 ^ C10; + wire C24_30 = C24 ^ C30; wire C6_9 = C6 ^ C9; + wire C13_20 = C13 ^ C20; wire C23_28 = C23 ^ C28; + wire C5_8 = C5 ^ C8; wire C10_17 = C10 ^ C17; + wire C21_24 = C21 ^ C24; wire C4_7 = C4 ^ C7; + wire C9_16 = C9 ^ C16; wire C20_23 = C20 ^ C23; + wire C3_6 = C3 ^ C6; wire C8_15 = C8 ^ C15; + wire C19_22 = C19 ^ C22; wire C14_16 = C14 ^ C16; + wire C6_13 = C6 ^ C13; wire C15_20 = C15 ^ C20; + wire C5_12 = C5 ^ C12; wire C14_19 = C14 ^ C19; + wire C29_31 = C29 ^ C31; wire C28_30 = C28 ^ C30; + wire C10_18 = C10 ^ C18; wire C20_26 = C20 ^ C26; + wire C4_9 = C4 ^ C9; wire C21_23 = C21 ^ C23; + wire C8_18 = C8 ^ C18; wire C22_25 = C22 ^ C25; + wire C11_13 = C11 ^ C13; wire C20_22 = C20 ^ C22; + wire C26_28 = C26 ^ C28; wire C15_18 = C15 ^ C18; + wire C14_17 = C14 ^ C17; wire C23_27 = C23 ^ C27; + wire C1_12 = C1 ^ C12; wire C18_25 = C18 ^ C25; + wire C8_13 = C8 ^ C13; wire C22_24 = C22 ^ C24; + wire C12_19 = C12 ^ C19; wire C23_25 = C23 ^ C25; + wire C3_12 = C3 ^ C12; wire C19_21 = C19 ^ C21; + wire C24_26 = C24 ^ C26; wire C5_18 = C5 ^ C18; + wire C23_26 = C23 ^ C26; + + assign crc_part_1_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + { + (C1_4 ^ C11_12) ^ (C14_15 ^ C17_20), + (C0_3 ^ C10_11) ^ (C13_14 ^ C16_19), + (C2_15 ^ C9_10) ^ (C12_13 ^ C18_23), + (C1_14 ^ C8_9) ^ (C11_12 ^ C17_22), + (C0_13 ^ C7_8) ^ (C10_11 ^ C16_21), + (C6_7 ^ C9_10) ^ (C12_15 ^ C16_17), + (C1_4 ^ C5_6) ^ (C8_9 ^ C12_24), + (C0_3 ^ C4_5) ^ (C7_8 ^ C11_23), + (C2_3 ^ C4_10) ^ (C6_7 ^ C14_15), + (C2_3 ^ C4_5) ^ (C6_9 ^ C11_12), + (C2_3 ^ C5_8) ^ (C10_17 ^ C19_20), + (C1_2 ^ C4_7) ^ (C9_16 ^ C18_19), + (C0_1 ^ C3_6) ^ (C8_15 ^ C17_18), + (C0_2 ^ C5_7) ^ (C14_16 ^ C17_18), + (C1_4 ^ C6_13) ^ (C15_20 ^ C16_17), + (C0_3 ^ C5_12) ^ (C14_19 ^ C15_16), + (C1_2 ^ C12_13) ^ (C17_18 ^ C20_21), + (C0_1 ^ C11_12) ^ (C16_17 ^ C19_20), + (C0 ^ C10_11) ^ (C15_16 ^ C18_19), + (C9_10 ^ C14_15) ^ (C17_18 ^ C19_20), + (C1_4 ^ C8_9) ^ (C11_12 ^ C13), + (C0_1 ^ C3_4) ^ (C7_8 ^ C10_18), + (C0_1 ^ C2_3) ^ (C4_9 ^ C6_7), + (C0_1 ^ C2_3) ^ (C5_6 ^ C8_18), + (C0_2 ^ C5_7) ^ (C9_10 ^ C11_13), + (C6_13 ^ C8_9) ^ (C10_11 ^ C15_18), + (C5_12 ^ C7_8) ^ (C9_10 ^ C14_17), + (C1_12 ^ C6_7) ^ (C8_9 ^ C13_14), + (C0_1 ^ C4_5) ^ (C6_7 ^ C8_13), + (C0_3 ^ C4_5) ^ (C6_7 ^ C12_19), + (C1_2 ^ C3_12) ^ (C5_6 ^ C14_15), + (C0_2 ^ C5_18) ^ (C12_13 ^ C15_16) + }; + + assign crc_part_2_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + { + (C21_22 ^ C25_30) ^ (C27_28 ), + (C20_21 ^ C24_31) ^ (C26_27 ^ C29 ), + (C19_20 ^ C25_26) ^ (C28 ^ C30_31), + (C18_19 ^ C24_25) ^ (C27_29 ^ C30_31), + (C17_18 ^ C23_24) ^ (C26 ^ C28_29) ^ (C30_31), + (C20_25 ^ C22_23) ^ (C27_28 ^ C29_30), + (C16_17 ^ C19_20) ^ (C25_26 ^ C29_30), + (C15_16 ^ C18_19) ^ (C24_25 ^ C28_29) ^ (C31), + (C17_18 ^ C22_23) ^ (C24_30 ^ C27_28), + (C13_20 ^ C15_16) ^ (C23_28 ^ C25_26) ^ (C29_30), + (C21_24 ^ C29_30), + (C20_23 ^ C28_29), + (C19_22 ^ C27_28), + (C21 ^ C26_27), + (C25_26), + (C24_25), + (C22_23 ^ C24_25) ^ (C27_28 ^ C30), + (C21_22 ^ C23_24) ^ (C26_27 ^ C29_31), + (C20_21 ^ C22_23) ^ (C25_26 ^ C28_30), + (C21_22 ^ C24_25) ^ (C27 ^ C29_31), + (C15_16 ^ C18_19) ^ (C22_23 ^ C24_25) ^ (C26_27), + (C20_26 ^ C23_24) ^ (C27_28 ^ C30_31), + (C11_12 ^ C14_15) ^ (C19_20 ^ C21_23) ^ (C26 ^ C28_29), + (C10_11 ^ C13_14) ^ (C19_20 ^ C22_25) ^ (C27_28 ^ C31), + (C14_15 ^ C18_19) ^ (C20_22 ^ C24_25) ^ (C26_28), + (C19_20 ^ C22_23) ^ (C24 ^ C28_30), + (C18_19 ^ C21_22) ^ (C23_27 ^ C29_31), + (C15_16 ^ C18_25) ^ (C26_27 ^ C31), + (C20_21 ^ C22_24) ^ (C26_27 ^ C28), + (C20_21 ^ C23_25) ^ (C26_27), + (C17_18 ^ C19_21) ^ (C24_26 ^ C27_28) ^ (C30_31), + (C21_22 ^ C23_26) ^ (C28_29 ^ C31) + }; +endmodule + +module crc_32_64_private ( + use_F_for_CRC, + present_crc, + data_in_64, + next_crc +); + parameter NUMBER_OF_BITS_APPLIED = 64; + input use_F_for_CRC; + input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc; + input [NUMBER_OF_BITS_APPLIED - 1 : 0] data_in_64; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc; + +// There are 2 obvious ways to implement these functions: +// 1) XOR the State bits with the Input bits, then calculate the XOR's +// 2) Independently calculate a result for Inputs and State variables, +// then XOR the results together. +// Once the applied data width > CRC size, it seems best to use the second technique. +// The formulas for each output term are seen to have a large number of +// terms depending on input data, and a smaller number of terms dependent +// on the initial value of the CRC. +// Calculate the Data component of the dependency. This can be done in +// a pipelined fashion, since it doesn't matter how long it takes. +// Calculate the CRC component of the dependency. Each clock this must +// be XOR'd with the correctly time-aligned Data component, and the +// results must be put back in the running CRC latches. +// It looks like 64 bits per clock may be FASTER than 32 bits per clock, +// because the Data dependency can be done in several clocks. + +// Instantiate the Data part of the dependency. + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_part_1_out; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_part_2_out; + +crc_32_64_data_private crc_32_64_data_part ( + .data_in_64 (data_in_64[NUMBER_OF_BITS_APPLIED - 1 : 0]), + .data_part_1_out (data_part_1_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_part_2_out (data_part_2_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] data_depend_part = + data_part_1_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] + ^ data_part_2_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + +// Instantiate the CRC part of the dependency. + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] crc_part_1_out; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] crc_part_2_out; + +crc_32_64_crc_private crc_32_64_crc_part ( + .use_F_for_CRC (use_F_for_CRC), + .present_crc (present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .crc_part_1_out (crc_part_1_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .crc_part_2_out (crc_part_2_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] first_part = + data_depend_part[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] + ^ crc_part_1_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; // source depth 4 gates + + assign next_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + first_part[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] + ^ crc_part_2_out[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; // source depth 5 gates +endmodule + + `define COMPARE_PARALLEL_VERSIONS_AGAINST_SERIAL_VERSION_FOR_DEBUG +`ifdef COMPARE_PARALLEL_VERSIONS_AGAINST_SERIAL_VERSION_FOR_DEBUG +// a slow one to make sure I did things right. +module crc_32_1_bit_at_a_time ( + use_F_for_CRC, + present_crc, + data_in_1, + next_crc +); + input use_F_for_CRC; + input [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc; + input data_in_1; + output [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc; + + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] resettable_crc; + assign resettable_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + {`NUMBER_OF_BITS_IN_CRC_32{use_F_for_CRC}} + | present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + + wire xor_value = data_in_1 ^ resettable_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1]; + + assign next_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = xor_value + ? {resettable_crc[`NUMBER_OF_BITS_IN_CRC_32 - 2 : 0], 1'b0} ^ `CRC + : {resettable_crc[`NUMBER_OF_BITS_IN_CRC_32 - 2 : 0], 1'b0}; +endmodule + +module test_crc_1 (); + + integer i, j; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc; + reg use_F_for_CRC; + reg [7:0] data_in_8; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_8; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc_8; + reg [15:0] data_in_16; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_16; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc_16; + reg [23:0] data_in_24; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_24; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc_24; + reg [31:0] data_in_32; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_32; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc_32; + reg [63:0] data_in_64; + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] present_crc_64; + wire [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] next_crc_64; + + +// Assign data_in_8 before invoking. This consumes data MSB first +task apply_1_8_to_crc; + integer j; + begin + #0 ; + present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + next_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + for (j = 0; j < 8; j = j + 1) // apply data bit at a time + begin + #0 ; + present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + next_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_8[7:0] = {data_in_8[6:0], 1'b0}; // Shift byte out MSB first + use_F_for_CRC = 1'b0; + end + end +endtask + +task apply_16_to_crc; + integer j; + begin + #0 ; + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = // remember: apply 16 bits + next_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + use_F_for_CRC = 1'b0; + end +endtask + +task apply_24_to_crc; + integer j; + begin + #0 ; + present_crc_24[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = // remember: apply 24 bits + next_crc_24[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + use_F_for_CRC = 1'b0; + end +endtask + +task apply_32_to_crc; + integer j; + begin + #0 ; + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = // remember: apply 32 bits + next_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + use_F_for_CRC = 1'b0; + end +endtask + +task apply_64_to_crc; + integer j; + begin + #0 ; + present_crc_64[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = // remember: apply 64 bits + next_crc_64[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + use_F_for_CRC = 1'b0; + end +endtask + + initial + begin + #10; + $display ("running serial version of code against parallel versions"); + use_F_for_CRC = 1'b1; + for (i = 0; i < 43; i = i + 1) + begin + data_in_8[7:0] = 8'h00; + apply_1_8_to_crc; + end + data_in_8[7:0] = 8'h28; + apply_1_8_to_crc; + if (~present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'h864D7F99) + $display ("*** 1-bit after 40 bytes of 1'b0, I want 32'h864D7F99, I get 32\`h%x", + ~present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + if (~present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'h864D7F99) + $display ("*** 8-bit after 40 bytes of 1'b0, I want 32'h864D7F99, I get 32\`h%x", + ~present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_8[7:0] = 8'h86; + apply_1_8_to_crc; + data_in_8[7:0] = 8'h4D; + apply_1_8_to_crc; + data_in_8[7:0] = 8'h7F; + apply_1_8_to_crc; + data_in_8[7:0] = 8'h99; + apply_1_8_to_crc; +// The receiver sees the value 32'hC704DD7B when the message is +// received no errors. Bit reversed, that is 32'hDEBB20E3. + if (present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 1-bit 0's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + if (present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 8-bit 0's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + data_in_16[15:0] = 16'h0000; + for (i = 0; i < 21; i = i + 1) + begin + apply_16_to_crc; + end + data_in_16[15:0] = 16'h0028; + apply_16_to_crc; + if (~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'h864D7F99) + $display ("*** 16-bit after 40 bytes of 1'b0, I want 32'h864D7F99, I get 32\`h%x", + ~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_16[15:0] = 16'h864D; + apply_16_to_crc; + data_in_16[15:0] = 16'h7F99; + apply_16_to_crc; + if (present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 16-bit 0's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + data_in_24[23:0] = 24'h000000; + for (i = 0; i < 14; i = i + 1) + begin + apply_24_to_crc; + end + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_24[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_16[15:0] = 16'h0028; + apply_16_to_crc; + if (~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'h864D7F99) + $display ("*** 24-bit after 40 bytes of 1'b0, I want 32'h864D7F99, I get 32\`h%x", + ~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_16[15:0] = 16'h864D; + apply_16_to_crc; + data_in_16[15:0] = 16'h7F99; + apply_16_to_crc; + if (present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 24-bit 0's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + data_in_32[31:0] = 32'h00000000; + for (i = 0; i < 10; i = i + 1) + begin + apply_32_to_crc; + end + data_in_32[31:0] = 32'h00000028; + apply_32_to_crc; + if (~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'h864D7F99) + $display ("*** 32-bit after 40 bytes of 1'b0, I want 32'h864D7F99, I get 32\`h%x", + ~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_32[31:0] = 32'h864D7F99; + apply_32_to_crc; + if (present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 32-bit 0's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + +// NOTE: WORKING: add 48 + + use_F_for_CRC = 1'b1; + data_in_64[63:0] = 64'h00000000_00000000; + for (i = 0; i < 5; i = i + 1) + begin + apply_64_to_crc; + end + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_64[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_32[31:0] = 32'h00000028; + apply_32_to_crc; + if (~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'h864D7F99) + $display ("*** 64-bit after 40 bytes of 1'b0, I want 32'h864D7F99, I get 32\`h%x", + ~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_32[31:0] = 32'h864D7F99; + apply_32_to_crc; + if (present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 64-bit 0's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + + use_F_for_CRC = 1'b1; + for (i = 0; i < 40; i = i + 1) + begin + data_in_8[7:0] = 8'hFF; + apply_1_8_to_crc; + end + for (i = 0; i < 3; i = i + 1) + begin + data_in_8[7:0] = 8'h00; + apply_1_8_to_crc; + end + data_in_8[7:0] = 8'h28; + apply_1_8_to_crc; + if (~present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC55E457A) + $display ("*** 1-bit after 40 bytes of 1'b1, I want 32'hC55E457A, I get 32\`h%x", + ~present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + if (~present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC55E457A) + $display ("*** 8-bit after 40 bytes of 1'b1, I want 32'hC55E457A, I get 32\`h%x", + ~present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_8[7:0] = 8'hC5; + apply_1_8_to_crc; + data_in_8[7:0] = 8'h5E; + apply_1_8_to_crc; + data_in_8[7:0] = 8'h45; + apply_1_8_to_crc; + data_in_8[7:0] = 8'h7A; + apply_1_8_to_crc; + if (present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 1-bit 1's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + if (present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 8-bit 1's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + data_in_16[15:0] = 16'hFFFF; + for (i = 0; i < 20; i = i + 1) + begin + apply_16_to_crc; + end + data_in_16[15:0] = 16'h0000; + apply_16_to_crc; + data_in_16[15:0] = 16'h0028; + apply_16_to_crc; + if (~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC55E457A) + $display ("*** 16-bit after 40 bytes of 1'b1, I want 32'hC55E457A, I get 32\`h%x", + ~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_16[15:0] = 16'hC55E; + apply_16_to_crc; + data_in_16[15:0] = 16'h457A; + apply_16_to_crc; + if (present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 16-bit 1's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + data_in_24[23:0] = 24'hFFFFFF; + for (i = 0; i < 13; i = i + 1) + begin + apply_24_to_crc; + end + present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_24[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_8[7:0] = 8'hFF; + apply_1_8_to_crc; + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_16[15:0] = 16'h0000; + apply_16_to_crc; + data_in_16[15:0] = 16'h0028; + apply_16_to_crc; + if (~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC55E457A) + $display ("*** 24-bit after 40 bytes of 1'b1, I want 32'hC55E457A, I get 32\`h%x", + ~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_16[15:0] = 16'hC55E; + apply_16_to_crc; + data_in_16[15:0] = 16'h457A; + apply_16_to_crc; + if (present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 24-bit 1's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + data_in_32[31:0] = 32'hFFFFFFFF; + for (i = 0; i < 10; i = i + 1) + begin + apply_32_to_crc; + end + data_in_32[31:0] = 32'h00000028; + apply_32_to_crc; + if (~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC55E457A) + $display ("*** 32-bit after 40 bytes of 1'b1, I want 32'hC55E457A, I get 32\`h%x", + ~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_32[31:0] = 32'hC55E457A; + apply_32_to_crc; + if (present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 32-bit 1's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + +// NOTE: WORKING: add 48 + + use_F_for_CRC = 1'b1; + data_in_64[63:0] = 64'hFFFFFFFF_FFFFFFFF; + for (i = 0; i < 5; i = i + 1) + begin + apply_64_to_crc; + end + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_64[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_32[31:0] = 32'h00000028; + apply_32_to_crc; + if (~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC55E457A) + $display ("*** 64-bit after 40 bytes of 1'b1, I want 32'hC55E457A, I get 32\`h%x", + ~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_32[31:0] = 32'hC55E457A; + apply_32_to_crc; + if (present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 64-bit 1's after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + + use_F_for_CRC = 1'b1; + for (i = 0; i < 40; i = i + 1) + begin + data_in_8[7:0] = i + 1; + apply_1_8_to_crc; + end + for (i = 0; i < 3; i = i + 1) + begin + data_in_8[7:0] = 8'h00; + apply_1_8_to_crc; + end + data_in_8[7:0] = 8'h28; + apply_1_8_to_crc; + if (~present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hBF671ED0) + $display ("*** 1-bit after 40 bytes of i+1, I want 32'hBF671ED0, I get 32\`h%x", + ~present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + if (~present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hBF671ED0) + $display ("*** 8-bit after 40 bytes of i+1, I want 32'hBF671ED0, I get 32\`h%x", + ~present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_8[7:0] = 8'hBF; + apply_1_8_to_crc; + data_in_8[7:0] = 8'h67; + apply_1_8_to_crc; + data_in_8[7:0] = 8'h1E; + apply_1_8_to_crc; + data_in_8[7:0] = 8'hD0; + apply_1_8_to_crc; + if (present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 1-bit i+1 after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + if (present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 8-bit i+1 after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + for (i = 0; i < 20; i = i + 1) + begin + data_in_16[15:0] = (((2 * i) + 1) << 8) | ((2 * i) + 2); + apply_16_to_crc; + end + data_in_16[15:0] = 16'h0000; + apply_16_to_crc; + data_in_16[15:0] = 16'h0028; + apply_16_to_crc; + if (~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hBF671ED0) + $display ("*** 16-bit after 40 bytes of i+1, I want 32'hBF671ED0, I get 32\`h%x", + ~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_16[15:0] = 16'hBF67; + apply_16_to_crc; + data_in_16[15:0] = 16'h1ED0; + apply_16_to_crc; + if (present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 16-bit i+1 after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + for (i = 0; i < 13; i = i + 1) + begin + data_in_24[23:0] = (((3 * i) + 1) << 16) | (((3 * i) + 2) << 8) | ((3 * i) + 3); + apply_24_to_crc; + end + present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_24[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_8[7:0] = 8'h28; + apply_1_8_to_crc; + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_16[15:0] = 16'h0000; + apply_16_to_crc; + data_in_16[15:0] = 16'h0028; + apply_16_to_crc; + if (~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hBF671ED0) + $display ("*** 24-bit after 40 bytes of i+1, I want 32'hBF671ED0, I get 32\`h%x", + ~present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_16[15:0] = 16'hBF67; + apply_16_to_crc; + data_in_16[15:0] = 16'h1ED0; + apply_16_to_crc; + if (present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 24-bit i+1 after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + use_F_for_CRC = 1'b1; + for (i = 0; i < 10; i = i + 1) + begin + data_in_32[31:0] = (((4 * i) + 1) << 24) | (((4 * i) + 2) << 16) + | (((4 * i) + 3) << 8) | ((4 * i) + 4); + apply_32_to_crc; + end + data_in_32[31:0] = 32'h00000028; + apply_32_to_crc; + if (~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hBF671ED0) + $display ("*** 32-bit after 40 bytes of i+1, I want 32'hBF671ED0, I get 32\`h%x", + ~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_32[31:0] = 32'hBF671ED0; + apply_32_to_crc; + if (present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 32-bit i+1 after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + +// NOTE: WORKING: add 48 + + use_F_for_CRC = 1'b1; + for (i = 0; i < 5; i = i + 1) + begin + data_in_64[63:0] = (((8 * i) + 1) << 56) | (((8 * i) + 2) << 48) + | (((8 * i) + 3) << 40) | (((8 * i) + 4) << 32) + | (((8 * i) + 5) << 24) | (((8 * i) + 6) << 16) + | (((8 * i) + 7) << 8) | ((8 * i) + 8); + apply_64_to_crc; + end + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = + present_crc_64[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]; + data_in_32[31:0] = 32'h00000028; + apply_32_to_crc; + if (~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hBF671ED0) + $display ("*** 64-bit after 40 bytes of i+1, I want 32'hBF671ED0, I get 32\`h%x", + ~present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + data_in_32[31:0] = 32'hBF671ED0; + apply_32_to_crc; + if (present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] !== 32'hC704DD7B) + $display ("*** 64-bit i+1 after running CRC through, I want 32'hC704DD7B, I get 32\`h%x", + present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); + + end + +crc_32_1_bit_at_a_time test_1_bit ( + .use_F_for_CRC (use_F_for_CRC), + .present_crc (present_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_in_1 (data_in_8[7]), + .next_crc (next_crc[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + +crc_32_8_private test_8_bit ( + .use_F_for_CRC (use_F_for_CRC), + .present_crc (present_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_in_8 (data_in_8[7:0]), + .next_crc (next_crc_8[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + +crc_32_16_private test_16_bit ( + .use_F_for_CRC (use_F_for_CRC), + .present_crc (present_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_in_16 (data_in_16[15:0]), + .next_crc (next_crc_16[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + +crc_32_24_private test_24_bit ( + .use_F_for_CRC (use_F_for_CRC), + .present_crc (present_crc_24[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_in_24 (data_in_24[23:0]), + .next_crc (next_crc_24[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + +crc_32_32_private test_32_bit ( + .use_F_for_CRC (use_F_for_CRC), + .present_crc (present_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_in_32 (data_in_32[31:0]), + .next_crc (next_crc_32[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + +crc_32_64_private test_64_bit ( + .use_F_for_CRC (use_F_for_CRC), + .present_crc (present_crc_64[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]), + .data_in_64 (data_in_64[63:0]), + .next_crc (next_crc_64[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]) +); + +// Angie Tso's CRC-32 Test Cases +// tsoa@ttc.com +// Angie Tso +// Telecommunications Techniques Corp. E-mail: tsoa@ttc.com +// 20400 Observation Drive, Voice : 301-353-1550 ext.4061 +// Germantown, MD 20876-4023 Fax : 301-353-1536 Mail Stop O +// +// Angie posted the following on the cell-relay list Mon, 24 Oct 1994 18:33:11 GMT=20 +// -------------------------------------------------------------------------------- +// +// Here are the examples of valid AAL-5 CS-PDU in I.363: +// (There are three examples in I.363) +// +// 40 Octets filled with "0" +// CPCS-UU = 0, CPI = 0, Length = 40, CRC-32 = 864d7f99 +// char pkt_data[48]={0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +// 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +// 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +// 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +// 0x00,0x00,0x00,0x28,0x86,0x4d,0x7f,0x99}; +// +// 40 Octets filled with "1" +// CPCS-UU = 0, CPI = 0, Length = 40, CRC-32 = c55e457a +// char pkt_data[48]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, +// 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, +// 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, +// 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, +// 0x00,0x00,0x00,0x28,0xc5,0x5e,0x45,0x7a}; +// +// 40 Octets counting: 1 to 40 +// CPCS-UU = 0, CPI = 0, Length = 40, CRC-32 = bf671ed0 +// char pkt_data[48]={0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a, +// 0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14, +// 0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e, +// 0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, +// 0x00,0x00,0x00,0x28,0xbf,0x67,0x1e,0xd0}; +// +// Here is one out of my calculation for your reference: +// +// 40 Octets counting: 1 to 40 +// CPCS-UU = 11, CPI = 22, CRC-32 = acba602a +// char pkt_data[48]={0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a, +// 0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14, +// 0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e, +// 0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, +// 0x11,0x22,0x00,0x28,0xac,0xba,0x60,0x2a}; + +endmodule +`endif // COMPARE_PARALLEL_VERSIONS_AGAINST_SERIAL_VERSION_FOR_DEBUG + +// `define CALCULATE_FUNCTIONAL_DEPENDENCE_ON_INPUT_AND_STATE +`ifdef CALCULATE_FUNCTIONAL_DEPENDENCE_ON_INPUT_AND_STATE + +// Try to make a program which will generate formulas for how to do CRC-32 +// several bits at a time. +// The idea is to get a single-bit implementation which works. (!) +// Then apply an initial value for state and an input data stream. +// The initial value will have a single bit set, and the data stream +// will have a single 1-bit followed by 0 bits. +// Grind the state machine forward the desired number of bits N, and +// look at the stored state. Each place in the shift register where +// there is a 1'b1, that is a bit which is sensitive to the input +// or state bit in a parallel implementation N bits wide. + +module print_out_formulas (); + + parameter NUM_BITS_TO_DO_IN_PARALLEL = 8'h40; + + reg [`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] running_state; + reg [63:0] input_vector; + reg xor_value; + integer i, j, remaining_length; + + reg [2047:0] corner_turner; // 32 bits * 64 shifts + + initial + begin + $display ("Calculating functional dependence on input bits, for %d bits. Rightmost bit is State Bit 0.", + NUM_BITS_TO_DO_IN_PARALLEL); + for (i = 0; i < NUM_BITS_TO_DO_IN_PARALLEL; i = i + 1) + begin + running_state = {`NUMBER_OF_BITS_IN_CRC_32{1'b0}}; + input_vector = 64'h80000000_00000000; // MSB first for this program + for (j = 0; j < i + 1; j = j + 1) + begin + xor_value = input_vector[63] ^ running_state[`NUMBER_OF_BITS_IN_CRC_32 - 1]; + running_state[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0] = xor_value + ? {running_state[`NUMBER_OF_BITS_IN_CRC_32 - 2 : 0], 1'b0} ^ `CRC + : {running_state[`NUMBER_OF_BITS_IN_CRC_32 - 2 : 0], 1'b0}; + input_vector[63 : 0] = + {input_vector[62 : 0], 1'b0}; + end + $display ("input bit number (bigger is earlier) %d, dependence %b", + i, running_state[`NUMBER_OF_BITS_IN_CRC_32 - 1 : 0]); +// First entry, which gets shifted the most in corner_turner, is the last bit loaded + corner_turner[2047:0] = {corner_turner[2047 - `NUMBER_OF_BITS_IN_CRC_32 : 0], + running_state[`NUMBER_OF_BITS_IN_CRC_32 - 1:0]}; + end + +// Plan: reverse the order bits are reported in +// Add C23 terms to first 24 terms +// Insert ^ X + +// Count out formulas in the opposite order, write out valid formulas. + $display ("When the amount of data applied to the CRC is less than the length of the CRC itself,"); + $display (" the Most Significant CRC_LEN - CRC_WIDTH terms are of the form data_in[N] ^ State[N]."); + $display ("The next CRC_WIDTH terms are NOT dependent on the CRC values, except in so much as"); + $display (" they depend on CSR bits because of X = D ^ C terms."); + $display ("State Variables depend on input bit number (bigger is earlier) :"); +// try to read out formulas by sweeping a 1-bit through the corner_turner array. + $display ("{"); + for (i = `NUMBER_OF_BITS_IN_CRC_32 - 1; i >= NUM_BITS_TO_DO_IN_PARALLEL; i = i - 1) + begin // Bits which depend on shifted state bits directly + $write ("%d : C%0d ", i, i - NUM_BITS_TO_DO_IN_PARALLEL); + for (j = 0; j < NUM_BITS_TO_DO_IN_PARALLEL; j = j + 1) + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + $write (",\n"); + end + + if (NUM_BITS_TO_DO_IN_PARALLEL <= `NUMBER_OF_BITS_IN_CRC_32) + begin + remaining_length = NUM_BITS_TO_DO_IN_PARALLEL - 1; + end + else + begin + remaining_length = `NUMBER_OF_BITS_IN_CRC_32 - 1; + end + for (i = remaining_length; i >= 0; i = i - 1) + begin // bits which only depend on shifted XOR'd bits + $write ("%d : 0 ", i); + for (j = 0; j < NUM_BITS_TO_DO_IN_PARALLEL; j = j + 1) + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + if (i != 0) $write (",\n"); else $write ("\n"); + end + $display ("}"); + +// Write out bits in a different order, to make it easier to group terms. + if (NUM_BITS_TO_DO_IN_PARALLEL >= 16) + begin + $display ("{"); + for (i = `NUMBER_OF_BITS_IN_CRC_32 - 1; i >= NUM_BITS_TO_DO_IN_PARALLEL; i = i - 1) + begin // Bits which depend on shifted state bits directly + $write ("%d : C%0d ", i, i - NUM_BITS_TO_DO_IN_PARALLEL); + for (j = 0; j <= 8; j = j + 1) + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 12; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 9; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 13; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 10; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 14; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 11; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 15; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + for (j = 16; j < NUM_BITS_TO_DO_IN_PARALLEL; j = j + 1) + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + $write (",\n"); + end + + if (NUM_BITS_TO_DO_IN_PARALLEL <= `NUMBER_OF_BITS_IN_CRC_32) + begin + remaining_length = NUM_BITS_TO_DO_IN_PARALLEL - 1; + end + else + begin + remaining_length = `NUMBER_OF_BITS_IN_CRC_32 - 1; + end + for (i = remaining_length; i >= 0; i = i - 1) + begin // bits which only depend on shifted XOR'd bits + $write ("%d : 0 ", i); + for (j = 0; j <= 8; j = j + 1) + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 12; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 9; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 13; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 10; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 14; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 11; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + j = 15; + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + for (j = 16; j < NUM_BITS_TO_DO_IN_PARALLEL; j = j + 1) + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ X%0d", j[5:0]); + else if (j >= 10) $write (" "); else $write (" "); + end + if (i != 0) $write (",\n"); else $write ("\n"); + end + $display ("}"); + end // if width >= 16 + + if (NUM_BITS_TO_DO_IN_PARALLEL <= `NUMBER_OF_BITS_IN_CRC_32) + begin + $display ("Since the number of data bits applied is <= number of CRC bits, each"); + $display (" X term in these formulas corresponds to X = Data_In ^ State"); + end + else + begin + $display ("The number of bits being applied to the CRC is greater than the number of"); + $display (" bits in the CRC. Each X term in these formulas corersponds to a Data_In bit."); + $display ("If the shift distance was small, the original CRC bits would be XOR'd with"); + $display (" the new data. In this case, the shift distance per clock is large, so the"); + $display (" dependence on the original CRC bits has to be handled carefully."); + $display ("Here is the plan: Calculate the contribution due to the incoming data based"); + $display (" on the formulas produced for a particular shift distance."); + $display ("Separately, calculate the data dependence due to the present CRC."); + $display ("This is accomplished by using the HIGH numbered terms discovered when tracking"); + $display (" data dependencies. For instance, if the shift distance is"); + $display (" 64 and the CRC is 32 bits wide, the top 32 X terms of each of the formulas"); + $display (" is re-interpreted as C (state) terms."); + $display ("The terms depending on X63 : X32 are re-interpred to be terms depending on"); + $display (" CSR bits 31 : 0 correspondingly"); + $display ("{"); + for (i = `NUMBER_OF_BITS_IN_CRC_32 - 1; i >= 0; i = i - 1) + begin // Bits which depend on shifted state bits directly + $write ("%d : ", i); + for (j = `NUMBER_OF_BITS_IN_CRC_32; + j < NUM_BITS_TO_DO_IN_PARALLEL +`NUMBER_OF_BITS_IN_CRC_32; + j = j + 1) + begin + if (corner_turner[(NUM_BITS_TO_DO_IN_PARALLEL-j-1)*`NUMBER_OF_BITS_IN_CRC_32 + i] + != 1'b0) + $write (" ^ C%0d", j[5:0] - `NUMBER_OF_BITS_IN_CRC_32); + else if (j >= 10) $write (" "); else $write (" "); + end + if (i != 0) $write (",\n"); else $write ("\n"); + end + $display ("}"); + end + end +endmodule +`endif // CALCULATE_FUNCTIONAL_DEPENDENCE_ON_INPUT_AND_STATE + Index: common/trunk/plesiochronous_fifo.v =================================================================== --- common/trunk/plesiochronous_fifo.v (nonexistent) +++ common/trunk/plesiochronous_fifo.v (revision 48) @@ -0,0 +1,800 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// plesiochronous_fifo #(N, N, N, N, N) //// +//// //// +//// This file is part of the general opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// An example of a plesiochronous FIFO between 2 clock domains //// +//// //// +//// To Do: //// +//// nothing pending //// +//// //// +//// Author(s): //// +//// - Anonymous //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Anonymous and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: plesiochronous_fifo.v,v 1.3 2001-09-03 13:26:38 bbeaver Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/09/03 13:31:00 Blue Beaver +// no message +// +// Revision 1.1 2001/09/03 12:51:43 Blue Beaver +// no message +// +// Revision 1.5 2001/09/03 12:50:38 Blue Beaver +// no message +// +// + +////////////////////////////////////////////////////////////////////// +// +// Web definition of Plesiochronous: +// "Signals which are arbitrarily close in frequency to some defined precision. +// They are not sourced from the same clock and so, over the long term, will +// be skewed from each other. Their relative closeness of frequency allows a +// switch to cross connect, switch, or in some way process them. That same +// inaccuracy of timing will force a switch, over time, to repeat or delete +// frames (called frame slips) in order to handle buffer underflow or overflow." +// +// Summary: Make a FIFO which is used to cross between 2 Pleasiochronous +// clock domains. +// This code assumes that latency does not matter. +// This code assumes that the FIFO is being used for packet IO. +// This code REQUIRES that the reader of the FIFO reads an entire +// packet in back-to-back clocks, with no dead cycles. +// This code REQUIRES that the writer of the FIFO leaves dead cycles +// between packets when writing the FIFO, so that it does not overflow. +// +// NOTE: This FIFO REQUIRES that the Sender ALWAYS sends a full packet into +// the FIFO on adjacent Sender-side clocks. NO WAIT STATES except at +// packet boundries. The Sender promises this to the Receiver. +// +// NOTE: This FIFO REQUIRES that the Receiver ALWAYS receives a full packet +// out of the FIFO as soon as it gets an indication that the FIFO +// is half full. NO WAIT STATES. The Receiver promises this to +// the Sender. +// +// NOTE: The Read side has to capture the Read Data IMMEDIATELY. It must +// wrap read_fifo_half_full back directly to read_consume, and must +// capture and use the data it captures the first clock read_consume +// is asserted. read_consume means data valid to the receiver logic. +// +// NOTE: A plesiochronous system is one in which the different clock domains +// are running at different frequencies, but the designer knows how +// far apart the system frequencies are worst case. The designer +// can use this knowledge to make the system seem fully synchronous. +// +// NOTE: The system does NOT need to have the same frequencies for both the +// reader and the writer, if the widths of the interfaces are different. +// For instance, assume that the sender runs at N MHz with an M bit +// interface. The receiver might run at N/2 MHz with a 2*M bit +// interface. +// As long as there are bounds on the variations of the sender's N MHz +// clock and the receiver's N/2 MHz clock, the system can be +// considered to be plesiochronous. +// +// NOTE: The idea: The Sender writes data into the FIFO. Every so often, +// BUT ONLY AT A PACKET BOUNDRY, the sender intentionally does not +// write to the FIFO for 1 clock. +// The Receiver watches the FIFO. The receiver does not START reading +// from the FIFO until the FIFO becomes half full. Once it starts +// reading, it removes an entire packet from the FIFO all at once. +// The Sender can be sure that it will not overrun the FIFO, because +// it knows that the Receiver is emptying it. Even if the Sender is +// filling faster than the Receiver is emptying, the bounded +// difference in frequencies lets the Sender know that it cannot +// fill up the FIFO before it skips a write. +// The skipped write cycle keeps the Sender from over-filling the +// FIFO in the long run. +// The Receiver knows that it can receive an entire packet from the +// FIFO without emptying it. Even if the Receiver is emptying the +// FIFO faster than the Sender is filling it, the bounded +// difference in frequencies lets the Receiver know that it cannot +// empty the FIFO before it finishes reading a full packet. +// As soon as the Receiver finishes reading a packet, it waits until +// the FIFO gets at least half full again. The wait may be for +// more than 1 clock. The waits until the FIFO is half full keeps +// the Receiver from emptying the FIFO inthe ling run. +// +// NOTE: You have to tell the FIFO the paramaters of the clocks and packets +// you are designing for. This lets the FIFO calculate whether it +// can safely meet the design goals. +// +// NOTE: In this case, the FIFO is ALWAYS 6 elements deep. There are 6 entries +// instead of 4 to handle cases I can't imagine involving clock jitter. +// +// NOTE: This module instantiates synchronizer_flop.v, available at +// www.opencores.com/ +// +// This code was developed using VeriLogger Pro, by Synapticad. +// Their support is greatly appreciated. +// +//=========================================================================== + +`timescale 1ns/1ps + +module plesiochronous_fifo ( + reset_flags_async, + write_clk, + write_submit, + write_data, + read_clk, read_sync_clk, + read_fifo_half_full, + read_consume, + read_data +); + +// These parameters MUST be set where the module is instantiated. + parameter TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION = 0; // typically 100 + parameter RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION = 0; // typically 100 + parameter NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET = 0; // might be 256, for instance + parameter TRANSMIT_FIFO_WIDTH = 0; // MUST be the same as RECEIVE_FIFO_WIDTH now + parameter RECEIVE_FIFO_WIDTH = 0; + + input reset_flags_async; + input write_clk; + input write_submit; + input [TRANSMIT_FIFO_WIDTH - 1 : 0] write_data; + input read_clk, read_sync_clk; // The read_sync_clock is the SAME as the read_clk + output read_fifo_half_full; + input read_consume; + output [RECEIVE_FIFO_WIDTH - 1 : 0] read_data; + +// Calculate paramaters based on the main parameters set by the user. + parameter WORSE_CASE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION = + RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION + + TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION; + + parameter TRANSMIT_CLOCK_DIVIDED_BY_RECEIVE_CLOCK_RATIO = + TRANSMIT_FIFO_WIDTH/RECEIVE_FIFO_WIDTH; // must be 1 now + + parameter TRANSMIT_FIFO_CLOCK_SLIP_DEPTH = + 1000000/WORSE_CASE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION; + +function [2:0] grey_code_counter_inc; + input [2:0] grey_code_counter_in; + begin + case (grey_code_counter_in[2:0]) + 3'b000: grey_code_counter_inc[2:0] = 3'b001; + 3'b001: grey_code_counter_inc[2:0] = 3'b011; + 3'b011: grey_code_counter_inc[2:0] = 3'b010; + 3'b010: grey_code_counter_inc[2:0] = 3'b110; + 3'b110: grey_code_counter_inc[2:0] = 3'b111; + 3'b111: grey_code_counter_inc[2:0] = 3'b101; + 3'b101: grey_code_counter_inc[2:0] = 3'b100; + 3'b100: grey_code_counter_inc[2:0] = 3'b000; + default: + begin + grey_code_counter_inc[2:0] = 3'b000; +// synopsys translate_off + if ($time > 0) + begin + $display ("*** %m grey code in to inc has invalid value %h, at %t", + grey_code_counter_in[2:0], $time); + end + else ; // be quiet linterizer +// synopsys translate_off + end + endcase + end +endfunction + +function [2:0] grey_to_binary_3; + input [2:0] grey_code_counter_in; + begin + case (grey_code_counter_in[2:0]) + 3'b000: grey_to_binary_3[2:0] = 3'b000; + 3'b001: grey_to_binary_3[2:0] = 3'b001; + 3'b011: grey_to_binary_3[2:0] = 3'b010; + 3'b010: grey_to_binary_3[2:0] = 3'b011; + 3'b110: grey_to_binary_3[2:0] = 3'b100; + 3'b111: grey_to_binary_3[2:0] = 3'b101; + 3'b101: grey_to_binary_3[2:0] = 3'b110; + 3'b100: grey_to_binary_3[2:0] = 3'b111; + default: + begin + grey_to_binary_3[2:0] = 3'b000; +// synopsys translate_off + if ($time > 0) + begin + $display ("*** %m grey code in to binary has invalid value %h, at %t", + grey_to_binary_3[2:0], $time); + end + else ; // be quiet linterizer +// synopsys translate_off + end + endcase + end +endfunction + +// Write-side FIFO counters + reg [2:0] write_pointer_grey_W; // counts 0, 1, 3, 2, 6, 7, 5, 4, 0, 1, ... + reg [2:0] write_pointer_physical; // counts 0, 1, 2, 3, 4, 0, 1, ... + + always @(posedge write_clk or posedge reset_flags_async) + begin + if (reset_flags_async == 1'b1) + begin + write_pointer_grey_W[2:0] <= 3'h0; + write_pointer_physical[2:0] <= 3'h0; + end + else + begin + if (write_submit == 1'b1) + begin + write_pointer_grey_W[2:0] <= grey_code_counter_inc (write_pointer_grey_W[2:0]); + write_pointer_physical[2:0] <= (write_pointer_physical[2:0] >= 3'h5) + ? 3'h0 + : write_pointer_physical[2:0] + 3'h1; + end + else + begin + write_pointer_grey_W[2:0] <= write_pointer_grey_W[2:0]; + write_pointer_physical[2:0] <= write_pointer_physical[2:0]; + end + end + end + +// Read-side FIFO counters + reg [2:0] read_pointer_grey; // counts 0, 1, 3, 2, 6, 7, 5, 4, 0, 1, ... + reg [2:0] read_pointer_physical; // counts 0, 1, 2, 3, 4, 0, 1, ... + + always @(posedge read_clk or posedge reset_flags_async) + begin + if (reset_flags_async == 1'b1) + begin + read_pointer_grey[2:0] <= 3'h0; + read_pointer_physical[2:0] <= 3'h0; + end + else + begin + if (read_consume == 1'b1) + begin + read_pointer_grey[2:0] <= grey_code_counter_inc (read_pointer_grey[2:0]); + read_pointer_physical[2:0] <= (read_pointer_physical[2:0] >= 3'h5) + ? 3'h0 + : read_pointer_physical[2:0] + 3'h1; + end + else + begin + read_pointer_grey[2:0] <= read_pointer_grey[2:0]; + read_pointer_physical[2:0] <= read_pointer_physical[2:0]; + end + end + end + +// NOTE: Very unusual FIFO. It needs to synchronize the Write Pointer into +// the Read clock domain, but does NOT need to synchronize the Read +// Pointer into the Write clock domain. The Writer KNOWS that it +// can always safely write. This is guaranteed by the Read side +// behavior. That Read side is GUARANTEED to always be reading. + + wire [2:0] write_pointer_grey_sync_R; + +synchronizer_flop sync_write_grey_0 ( + .data_in (write_pointer_grey_W[0]), + .clk_out (read_sync_clk), + .sync_data_out (write_pointer_grey_sync_R[0]), + .async_reset (reset_flags_async) +); + +synchronizer_flop sync_write_grey_1 ( + .data_in (write_pointer_grey_W[1]), + .clk_out (read_sync_clk), + .sync_data_out (write_pointer_grey_sync_R[1]), + .async_reset (reset_flags_async) +); + +synchronizer_flop sync_write_grey_2 ( + .data_in (write_pointer_grey_W[2]), + .clk_out (read_sync_clk), + .sync_data_out (write_pointer_grey_sync_R[2]), + .async_reset (reset_flags_async) +); + +// Calculate how much stuff is stored in the FIFO. This can be +// done by comparing the Read and Write Grey Code Counters. +// They start out the same. The Write side gets ahead of +// the read side, until the read side starts unloading. +// If the write side stops writing, they can get to be the +// same again. +// These counters wrap. In the case that the Write Counter is +// greater than than the Read Counter, the amount of stuff +// in the FIFO is write pointer - read pointer; +// In the case that the Write Counter is less than the Read +// Counter, the amount of stuff in the FIFO is 8 + difference. +// BUT only the bottom 3 bits matter! That seems to mean +// that you can simply subtract and look at the bottom 3 bits. + + wire [2:0] write_pointer_binary_R = + grey_to_binary_3 (write_pointer_grey_sync_R[2:0]); + + wire [2:0] read_pointer_binary = + grey_to_binary_3 (read_pointer_grey[2:0]); + + wire [2:0] number_of_elements_in_fifo = + write_pointer_binary_R[2:0] - read_pointer_binary[2:0]; + +// Tell the Receiver to go when there are 2 or more elements in this 5 element FIFO. + assign read_fifo_half_full = number_of_elements_in_fifo[2:0] >= 3'h3; + +// FIFO storage + reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_0; + reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_1; + reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_2; + reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_3; + reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_4; + reg [TRANSMIT_FIFO_WIDTH - 1 : 0] fifo_5; + + always @(posedge write_clk) + begin + fifo_0[TRANSMIT_FIFO_WIDTH - 1 : 0] = + (write_submit & (write_pointer_physical[2:0] == 3'h0)) + ? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0] + : fifo_0[TRANSMIT_FIFO_WIDTH - 1 : 0]; + fifo_1[TRANSMIT_FIFO_WIDTH - 1 : 0] = + (write_submit & (write_pointer_physical[2:0] == 3'h1)) + ? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0] + : fifo_1[TRANSMIT_FIFO_WIDTH - 1 : 0]; + fifo_2[TRANSMIT_FIFO_WIDTH - 1 : 0] = + (write_submit & (write_pointer_physical[2:0] == 3'h2)) + ? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0] + : fifo_2[TRANSMIT_FIFO_WIDTH - 1 : 0]; + fifo_3[TRANSMIT_FIFO_WIDTH - 1 : 0] = + (write_submit & (write_pointer_physical[2:0] == 3'h3)) + ? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0] + : fifo_3[TRANSMIT_FIFO_WIDTH - 1 : 0]; + fifo_4[TRANSMIT_FIFO_WIDTH - 1 : 0] = + (write_submit & (write_pointer_physical[2:0] == 3'h4)) + ? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0] + : fifo_4[TRANSMIT_FIFO_WIDTH - 1 : 0]; + fifo_5[TRANSMIT_FIFO_WIDTH - 1 : 0] = + (write_submit & (write_pointer_physical[2:0] == 3'h5)) + ? write_data[TRANSMIT_FIFO_WIDTH - 1 : 0] + : fifo_5[TRANSMIT_FIFO_WIDTH - 1 : 0]; + end + +// Read port to FIFO + assign read_data = ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h0}} + & fifo_0[TRANSMIT_FIFO_WIDTH - 1 : 0]) + | ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h1}} + & fifo_1[TRANSMIT_FIFO_WIDTH - 1 : 0]) + | ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h2}} + & fifo_2[TRANSMIT_FIFO_WIDTH - 1 : 0]) + | ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h3}} + & fifo_3[TRANSMIT_FIFO_WIDTH - 1 : 0]) + | ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h4}} + & fifo_4[TRANSMIT_FIFO_WIDTH - 1 : 0]) + | ({RECEIVE_FIFO_WIDTH{read_pointer_physical[2:0] == 3'h5}} + & fifo_5[TRANSMIT_FIFO_WIDTH - 1 : 0]); + +// synopsys translate_off +// ASSUMING that the clock period is 10 nSec, look to make sure data is valid long +// enough to get through the read MUX. At least 1 write clock period! + reg written_0, written_1, written_2, written_3, written_4, written_5; + reg valid_0, valid_1, valid_2, valid_3, valid_4, valid_5; + initial + begin + written_0 = 1'b0; + written_1 = 1'b0; + written_2 = 1'b0; + written_3 = 1'b0; + written_4 = 1'b0; + written_5 = 1'b0; + end + always @(posedge write_clk) + begin + written_0 <= (write_submit & (write_pointer_physical[2:0] == 3'h0)) ^ written_0; // only change when written + valid_0 <= written_0; + written_1 <= (write_submit & (write_pointer_physical[2:0] == 3'h1)) ^ written_1; + valid_1 <= written_1; + written_2 <= (write_submit & (write_pointer_physical[2:0] == 3'h2)) ^ written_2; + valid_2 <= written_2; + written_3 <= (write_submit & (write_pointer_physical[2:0] == 3'h3)) ^ written_3; + valid_3 <= written_3; + written_4 <= (write_submit & (write_pointer_physical[2:0] == 3'h4)) ^ written_4; + valid_4 <= written_4; + written_5 <= (write_submit & (write_pointer_physical[2:0] == 3'h5)) ^ written_5; + valid_5 <= written_5; + end + always @(posedge read_clk) + begin + if (read_consume & (read_pointer_physical[2:0] == 3'h0) & (written_0 ^ valid_0)) + $display ("*** read data 0 not valid for full read clock at %t", $time); + if (read_consume & (read_pointer_physical[2:0] == 3'h1) & (written_1 ^ valid_1)) + $display ("*** read data 1 not valid for full read clock at %t", $time); + if (read_consume & (read_pointer_physical[2:0] == 3'h2) & (written_2 ^ valid_2)) + $display ("*** read data 2 not valid for full read clock at %t", $time); + if (read_consume & (read_pointer_physical[2:0] == 3'h3) & (written_3 ^ valid_3)) + $display ("*** read data 3 not valid for full read clock at %t", $time); + if (read_consume & (read_pointer_physical[2:0] == 3'h4) & (written_4 ^ valid_4)) + $display ("*** read data 4 not valid for full read clock at %t", $time); + if (read_consume & (read_pointer_physical[2:0] == 3'h5) & (written_5 ^ valid_5)) + $display ("*** read data 5 not valid for full read clock at %t", $time); + end + +// Check that there is never more than 5 words in this FIFO. I know, that +// means there only needs to be 5 sets of flops! +// Remember that there MIGHT be more data in the FIFO than the receive side +// thinks, because the Write Pointer might not have been incremented. Also, +// due to jitter, the Write side might get 2 writes (!) in between any 2 +// adjacent Read side clocks. This MIGHT mean that the data can go from +// having 3 entry in it to having 5 entries. Then, as the write clock +// contiues to run fast, the FIFO might work up to having 6 full entries. +// The other excuse I can have to having the extra set of flops is that it +// makes it clear that hold times are met, even when a write happens at +// the exact same time as the read which frees up the 5th entry. +// I feel much more confident with a 6th available entry. + + always @(posedge read_clk) + begin + if (number_of_elements_in_fifo[2:0] >= 3'h6) + $display ("*** %m fatal plesiochronous FIFO got too much data in it at %t", $time); + end +// synopsys translate_on + +// synopsys translate_off + initial + begin + if (TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION <= 0) + begin + $display ("*** Exiting because %m TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION %d <= 0", + TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION); + $finish; + end + if (RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION <= 0) + begin + $display ("*** Exiting because %m RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION %d <= 0", + RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION); + $finish; + end + if (NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET <= 0) + begin + $display ("*** Exiting because %m NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET %d <= 0", + NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET); + $finish; + end + if (TRANSMIT_FIFO_WIDTH <= 0) + begin + $display ("*** Exiting because %m TRANSMIT_FIFO_WIDTH %d <= 0", + TRANSMIT_FIFO_WIDTH); + $finish; + end + if (RECEIVE_FIFO_WIDTH <= 0) + begin + $display ("*** Exiting because %m RECEIVE_FIFO_WIDTH %d <= 0", + RECEIVE_FIFO_WIDTH); + $finish; + end +// NOTE: WORKING: Remove this restriction when this becomes able to write +// data with a different width than the read data port is. +// This will require the clocks to run at the ratio set by +// the rations of the FIFO port widths! + if (TRANSMIT_FIFO_WIDTH != RECEIVE_FIFO_WIDTH) + begin + $display ("*** Exiting because %m TRANSMIT_FIFO_WIDTH != RECEIVE_FIFO_WIDTH %d <= 0", + TRANSMIT_FIFO_WIDTH, RECEIVE_FIFO_WIDTH); + $finish; + end + +// The Sender needs to know that it will not overrun the FIFO even if it is running +// faster than the Receiver. It needs to make careful calculations to make sure +// this is true. +// It knows that the Receiver won't start unloading until it thinks the FIFO is +// at least 1/2 full. But when is the latest this can happen? +// The latest is when the Sender writes word 0, then word 1, BUT the indication +// that word 1 is available does not get latched by the receiver until the +// NEXT clock. At that time, the Sender writes entry 2. +// The Receiver unloads data from word 0 at the same time the sender writes word 3. +// So the FIFO has valid data in locations 1, 2, and 3. +// The FIFO has 3 valid words in it at the start. +// If the Sender writes faster than the Receiver reads, the FIFO can work up to +// having 4 words of valid data in it. +// +// The Receiver needs to know that it will not run out of data if it unloads +// faster than the Sender sends. How can it check this? +// The earliest the Receiver can know that data is available is if the Sender +// writes word 0, the word 1, and the Receiver hears about the data available +// instantly. Then, the Sender writes word 2 while the receiver unloads word 0. +// So the FIFO has valid data in locations 1 and 2. +// The FIFO has 2 words of data in it at the start. +// If the Receiver reads faster than the Sender writes, the FIFO can work down to +// having 1 word of valid data in it. +// +// Having 4 words max and 1 word min are fine constraints on the FIFO's behavior. +// To meet the constraints, the Sender and Receiver clocks must not vary too far +// from one-another. If they got too far apart, too much data would be either +// read or written throught the FIFO. + +// Calculate the maximum clock difference possible. +// NOTE: This calculation will have to take into account different port widths +// with corresponding different port clocks, if and when this is improved to +// allow port size changes across the FIFO. + + if (TRANSMIT_FIFO_CLOCK_SLIP_DEPTH < NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET) + begin + $display ("*** Exiting because %m TRANSMIT_FIFO_CLOCK_SLIP_DEPTH %d < NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET %d", + TRANSMIT_FIFO_CLOCK_SLIP_DEPTH, NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET); + $finish; + end + end +// synopsys translate_on +endmodule + +// `define TEST_PLESIOCHRONOUS_FIFO +`ifdef TEST_PLESIOCHRONOUS_FIFO +module test_plesiochronous_fifo; +// Plan: do a bunch of packets when the Write Clock is faster than the Read Clock +// Then do a bunch of packets when the Read Clock is faster than the Write Clock +// +// Experiment with small clock deltas to change event ordering. +// Print out at run time when the receiver is slipping clocks +// Check that data is strictly incrementing; no drops or repeats + real transmit_clock_period, receive_clock_period; + real transmit_clock_delta, receive_clock_delta; + integer packet_length; + integer packets_to_send; + integer i, j, k, l; + + reg reset_flags_async; + reg write_clk; + reg write_submit; + reg [31:0] write_data; + reg read_clk; + wire read_fifo_half_full; + reg read_consume; + reg [31:0] expected_read_data; + wire [31:0] read_data; + +task read_one_item; + begin + #0; + read_clk = 1'b1; + #receive_clock_period; + read_clk = 1'b0; + #receive_clock_period; + end +endtask + +task write_one_item; + begin + #0; + write_clk = 1'b1; + #transmit_clock_period; + write_clk = 1'b0; + #transmit_clock_period; + end +endtask + +task send_and_check; + begin + fork // Write Clock faster than Read Clock + begin // transmit activity + write_clk = 1'b0; + reset_flags_async = 1'b1; + # 10; + reset_flags_async = 1'b0; + # 10; + # transmit_clock_delta; + write_data[31:0] = 32'h00000000; + for (i = 0; i < packets_to_send; i = i + 1) + begin + write_submit = 1'b1; + for (j = 0; j < packet_length; j = j + 1) + begin + write_data[31:0] = write_data[31:0] + 32'h00000001; + write_one_item; // send 1 data item; + end + write_submit = 1'b0; + write_one_item; // skip a write; + end + end + + begin // receive activity + read_clk = 1'b0; + # 10; + # 10; + # receive_clock_delta; + expected_read_data[31:0] = 32'h00000001; + for (k = 0; k < packets_to_send; k = k + 1) + begin + read_consume = 1'b0; + if (k == 0) // wait for the first one + begin + while (read_fifo_half_full == 1'b0) + begin + read_one_item; // snooze + end + end + else // all subsequent ones should be back-to-back. + begin + if (read_fifo_half_full == 1'b1) + begin + $display ("Reading with 0 delay"); + end + else + begin + read_one_item; // snooze + if (read_fifo_half_full == 1'b1) + begin + $display ("Reading with 1 delay"); + end + else + begin + read_one_item; // snooze + if (read_fifo_half_full == 1'b1) + begin + $display ("Reading with 2 delay"); + end + else + begin + read_one_item; // snooze + if (read_fifo_half_full == 1'b1) + begin + $display ("Reading with 3 delay"); + end + else + begin + $display ("*** Data didn't become available!"); + end + end + end + end + end + read_consume = 1'b1; // this is a combinational copy of read_fifo_half_full! + for (l = 0; l < packet_length; l = l + 1) + begin + if (expected_read_data[31:0] !== read_data[31:0]) + begin + $display ("*** Data wasn't as expected! %h %h", + read_data[31:0], expected_read_data[31:0]); + end + read_one_item; + expected_read_data[31:0] = expected_read_data[31:0] + 32'h0000001; + end + end + end + join + end +endtask + + real normal_clk, fast_clk, slow_clk; + +initial + begin + packet_length = 20; // needed if each clock varies <= 25000 parts per million + packets_to_send = 200; + normal_clk = 5.0; + fast_clk = normal_clk * 0.976; // FAILS if 9.75, 1.025 !?! + slow_clk = normal_clk * 1.024; + + $display ("Same Frequency, no offset"); + transmit_clock_period = normal_clk; + receive_clock_period = normal_clk; + transmit_clock_delta = 0.000; + receive_clock_delta = 0.000; + + send_and_check; + + $display ("Same Frequency, Transmit late"); + transmit_clock_period = normal_clk; + receive_clock_period = normal_clk; + transmit_clock_delta = 0.001; + receive_clock_delta = 0.000; + + send_and_check; + + $display ("Same Frequency, Receive late"); + transmit_clock_period = normal_clk; + receive_clock_period = normal_clk; + transmit_clock_delta = 0.000; + receive_clock_delta = 0.001; + + send_and_check; + + + $display ("Transmit Fast, no offset"); + transmit_clock_period = fast_clk; + receive_clock_period = slow_clk; + transmit_clock_delta = 0.000; + receive_clock_delta = 0.000; + + send_and_check; + + $display ("Transmit Fast, Transmit late"); + transmit_clock_period = fast_clk; + receive_clock_period = slow_clk; + transmit_clock_delta = 0.001; + receive_clock_delta = 0.000; + + send_and_check; + + $display ("Transmit Fast, Receive late"); + transmit_clock_period = fast_clk; + receive_clock_period = slow_clk; + transmit_clock_delta = 0.000; + receive_clock_delta = 0.001; + + send_and_check; + + + $display ("Receive Fast, no offset"); + transmit_clock_period = slow_clk; + receive_clock_period = fast_clk; + transmit_clock_delta = 0.000; + receive_clock_delta = 0.000; + + send_and_check; + + $display ("Receive Fast, Transmit late"); + transmit_clock_period = slow_clk; + receive_clock_period = fast_clk; + transmit_clock_delta = 0.001; + receive_clock_delta = 0.000; + + send_and_check; + + $display ("Receive Fast, Receive late"); + transmit_clock_period = slow_clk; + receive_clock_period = fast_clk; + transmit_clock_delta = 0.000; + receive_clock_delta = 0.001; + + send_and_check; + + end + + +// Instantiation parameters are in order: +// TRANSMIT_CLOCK_UNCERTAINTY_PARTS_PER_MILLION +// RECEIVE_CLOCK_UNCERTAINTY_PARTS_PER_MILLION +// NUMBER_OF_TRANSMIT_CLOCKS_PER_PACKET +// TRANSMIT_FIFO_WIDTH +// RECEIVE_FIFO_WIDTH + +plesiochronous_fifo #(25000, 25000, 20, 32, 32) test_fifo ( + .reset_flags_async (reset_flags_async), + .write_clk (write_clk), + .write_submit (write_submit), + .write_data (write_data[31:0]), + .read_clk (read_clk), + .read_sync_clk (read_clk), + .read_fifo_half_full (read_fifo_half_full), + .read_consume (read_consume), + .read_data (read_data[31:0]) +); +`endif // TEST_PLESIOCHRONOUS_FIFO +endmodule + + Index: common/trunk/synchronizer_flop.v =================================================================== --- common/trunk/synchronizer_flop.v (nonexistent) +++ common/trunk/synchronizer_flop.v (revision 48) @@ -0,0 +1,104 @@ +//=========================================================================== +// $Id: synchronizer_flop.v,v 1.4 2001-09-03 13:18:30 bbeaver Exp $ +// +////////////////////////////////////////////////////////////////////// +//// //// +//// synchronizer_flop //// +//// //// +//// This file is part of the general opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// Make a rising-edge triggered flop with async reset with a //// +//// distinguished name so that it can be replaced with a flop //// +//// which does not make X's during simulation. //// +//// //// +//// This flop should be used instead of a regular flop for ALL //// +//// cross-clock-domain flops. Manually instantiating this //// +//// flop for all signals which must NEVER go to 1'bX during //// +//// simulation will make it possible for the user to //// +//// substitute a simulation model which does NOT have setup //// +//// and hold checks. //// +//// //// +//// If a target device library has a component which is //// +//// especially well suited to perform this function, it should //// +//// be instantiated by name in this file. Otherwise, the //// +//// behaviorial version of this module will be used. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - anynomous //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/09/03 11:16:00 Blue Beaver +// no message +// +// Revision 1.1.1.1 2001/09/03 10:24:58 bbeaver +// no message +// +// Revision 1.1 2001/09/02 11:32:03 Blue Beaver +// no message +// +// + +`timescale 1ns/1ps + +// If the vendor has a flop which is particularly good at settling out of +// metastability, it should be used here. +module synchronizer_flop ( + data_in, clk_out, sync_data_out, async_reset +); + input data_in; + input clk_out; + output sync_data_out; + input async_reset; + + reg sync_data_out; + + always @(posedge clk_out or posedge async_reset) + begin + if (async_reset == 1'b1) + begin + sync_data_out <= 1'b0; + end + else + begin +// In gate-level simulation, must only go to 1'bX if the input is 1'bX or 1'bZ. +// This should NEVER go to 1'bX due to setup or hold violations. + sync_data_out <= data_in; + end + end +endmodule + Index: common/trunk/hamming_ecc_64.v =================================================================== --- common/trunk/hamming_ecc_64.v (nonexistent) +++ common/trunk/hamming_ecc_64.v (revision 48) @@ -0,0 +1,792 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// hamming_ecc_64 //// +//// //// +//// hamming_ecc_generate_word_with_check_bits_64 //// +//// hamming_ecc_check_and_correct_64 //// +//// //// +//// This file is part of the general opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// Using Hamming style functions, calculate 72 bits from 64 to //// +//// make a value which can be corrected back to the original //// +//// 64 bits of valid data if a single bit error is applied to //// +//// the 72 bits. //// +//// //// +//// To Do: //// +//// nothing pending //// +//// //// +//// Author(s): //// +//// - Anonymous //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Anonymous and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: hamming_ecc_64.v,v 1.1 2001-09-03 13:18:30 bbeaver Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/09/03 13:22:46 Blue Beaver +// no message +// +// + +//=========================================================================== +// +// NOTE: The plan seems to be the following: +// Assign a binary Bit Address to each bit. +// Calculate ECC check bits by XOR'ing the bits together which +// correspond to 1's in each bit's Bit Address; +// (For instance, ECC Check Digit bit 0 XORs together Data_In[1], +// Data_In[3], and so on.) +// You need 7 bits to have enough addresses for all 64 single-bit +// errors, plus the value which covers the case of no errors. +// +// NOTE: But wait, there's more! What if a check bit fails? +// The trick is to have the failing check digit call ITSELF out. +// To achieve this, you have to distribute the check bits +// so that they have nice binary Bit Addresses. +// +// NOTE: There is even more. Every single bit error results in a word +// with wrong parity. But what if 2 bits flip? The parity goes +// back to the original. You can add a parity bit to everything, +// and if the check bits say there is an error but the parity is +// correct that means that 2 bits are wrong. +// The parity bit becomes the 8th bit of the ECC check bits. +// +// NOTE: The web pages discussing this seem to put the parity bit as bit 1 +// in the check bit calculation, the LSB check bit as bit 2, the +// next check bit as bit 4, and so on. +// +// NOTE: Since the parity bit is used to calculate the LSB of the +// check bits, and since it is the XOR of all bits, you have +// to calculate the XOR of the bits you least expect to calculate +// the low-order check bit. The ones with "0" as the LSB of their +// bit address, not "1". +// +// This code was developed using VeriLogger Pro, by Synapticad. +// Their support is greatly appreciated. +// +//=========================================================================== + +`timescale 1ns/1ps + +// Given 64 bits, calculate 7 bits of ECC check bits and 1 bit of parity. +// NOTE: Why a module and not a function? No idea. + +module hamming_ecc_calculate_check_bits_private ( + data_in, + check_bits_out, + par_if_inserting_check_bits_out +); + + parameter NUM_DATA_BITS = 64; // do not override in the instantiation. + parameter NUM_CHECK_BITS = 8; + + input [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] data_in; + output [NUM_CHECK_BITS - 1 : 0] check_bits_out; + output par_if_inserting_check_bits_out; + +// LSB of Check Bits depends on every other input bit. + wire parity_1_3_5_7 = data_in[1] ^ data_in[3] ^ data_in[5] ^ data_in[7]; + wire parity_9_11_13_15 = data_in[9] ^ data_in[11] ^ data_in[13] ^ data_in[15]; + wire parity_17_19_21_23 = data_in[17] ^ data_in[19] ^ data_in[21] ^ data_in[23]; + wire parity_25_27_29_31 = data_in[25] ^ data_in[27] ^ data_in[29] ^ data_in[31]; + wire parity_33_35_37_39 = data_in[33] ^ data_in[35] ^ data_in[37] ^ data_in[39]; + wire parity_41_43_45_47 = data_in[41] ^ data_in[43] ^ data_in[45] ^ data_in[47]; + wire parity_49_51_53_55 = data_in[49] ^ data_in[51] ^ data_in[53] ^ data_in[55]; + wire parity_57_59_61_63 = data_in[57] ^ data_in[59] ^ data_in[61] ^ data_in[63]; + wire parity_65_67_69_71 = data_in[65] ^ data_in[67] ^ data_in[69] ^ data_in[71]; + + wire parity_1_3_5_7_9_11_13_15_17_19_21_23 = + parity_1_3_5_7 ^ parity_9_11_13_15 ^ parity_17_19_21_23; + wire parity_25_27_29_31_33_35_37_39_41_43_45_47 = + parity_25_27_29_31 ^ parity_33_35_37_39 ^ parity_41_43_45_47; + wire parity_49_51_53_55_57_59_61_63_65_67_69_71 = + parity_49_51_53_55 ^ parity_57_59_61_63 ^ parity_65_67_69_71; + + assign check_bits_out[0] = parity_1_3_5_7_9_11_13_15_17_19_21_23 + ^ parity_25_27_29_31_33_35_37_39_41_43_45_47 + ^ parity_49_51_53_55_57_59_61_63_65_67_69_71; + +// second bit depends 2 out of 4 bits + wire parity_2_3_6_7 = data_in[2] ^ data_in[3] ^ data_in[6] ^ data_in[7]; + wire parity_10_11_14_15 = data_in[10] ^ data_in[11] ^ data_in[14] ^ data_in[15]; + wire parity_18_19_22_23 = data_in[18] ^ data_in[19] ^ data_in[22] ^ data_in[23]; + wire parity_26_27_30_31 = data_in[26] ^ data_in[27] ^ data_in[30] ^ data_in[31]; + wire parity_34_35_38_39 = data_in[34] ^ data_in[35] ^ data_in[38] ^ data_in[39]; + wire parity_42_43_46_47 = data_in[42] ^ data_in[43] ^ data_in[46] ^ data_in[47]; + wire parity_50_51_54_55 = data_in[50] ^ data_in[51] ^ data_in[54] ^ data_in[55]; + wire parity_58_59_62_63 = data_in[58] ^ data_in[59] ^ data_in[62] ^ data_in[63]; + wire parity_66_67_70_71 = data_in[66] ^ data_in[67] ^ data_in[70] ^ data_in[71]; + + wire parity_2_3_6_7_10_11_14_15_18_19_22_23 = + parity_2_3_6_7 ^ parity_10_11_14_15 ^ parity_18_19_22_23; + wire parity_26_27_30_31_34_35_38_39_42_43_46_47 = + parity_26_27_30_31 ^ parity_34_35_38_39 ^ parity_42_43_46_47; + wire parity_50_51_54_55_58_59_62_63_66_67_70_71 = + parity_50_51_54_55 ^ parity_58_59_62_63 ^ parity_66_67_70_71; + + assign check_bits_out[1] = parity_2_3_6_7_10_11_14_15_18_19_22_23 + ^ parity_26_27_30_31_34_35_38_39_42_43_46_47 + ^ parity_50_51_54_55_58_59_62_63_66_67_70_71; + +// Higher-numbered bits depend on groups of 4 adjacent input bits. + wire parity_0_3 = ^data_in[3:0]; // XOR reduction + wire parity_4_7 = ^data_in[7:4]; // XOR reduction + wire parity_8_11 = ^data_in[11:8]; // XOR reduction + wire parity_12_15 = ^data_in[15:12]; // XOR reduction + wire parity_16_19 = ^data_in[19:16]; // XOR reduction + wire parity_20_23 = ^data_in[23:20]; // XOR reduction + wire parity_24_27 = ^data_in[27:24]; // XOR reduction + wire parity_28_31 = ^data_in[31:28]; // XOR reduction + wire parity_32_35 = ^data_in[35:32]; // XOR reduction + wire parity_36_39 = ^data_in[39:36]; // XOR reduction + wire parity_40_43 = ^data_in[43:40]; // XOR reduction + wire parity_44_47 = ^data_in[47:44]; // XOR reduction + wire parity_48_51 = ^data_in[51:48]; // XOR reduction + wire parity_52_55 = ^data_in[55:52]; // XOR reduction + wire parity_56_59 = ^data_in[59:56]; // XOR reduction + wire parity_60_63 = ^data_in[63:60]; // XOR reduction + wire parity_64_67 = ^data_in[67:64]; // XOR reduction + wire parity_68_71 = ^data_in[71:68]; // XOR reduction + + wire parity_4_7_12_15_20_23 = parity_4_7 ^ parity_12_15 ^ parity_20_23; + wire parity_28_31_36_39_44_47 = parity_28_31 ^ parity_36_39 ^ parity_44_47; + wire parity_52_55_60_63_68_71 = parity_52_55 ^ parity_60_63 ^ parity_68_71; + + assign check_bits_out[2] = parity_4_7_12_15_20_23 + ^ parity_28_31_36_39_44_47 + ^ parity_52_55_60_63_68_71; + + wire parity_8_11_12_15_24_27 = parity_8_11 ^ parity_12_15 ^ parity_24_27; + wire parity_28_31_40_43_44_47 = parity_28_31 ^ parity_40_43 ^ parity_44_47; + wire parity_56_59_60_63 = parity_56_59 ^ parity_60_63; + + assign check_bits_out[3] = parity_8_11_12_15_24_27 + ^ parity_28_31_40_43_44_47 + ^ parity_56_59_60_63; + + wire parity_16_19_20_23_24_27 = parity_16_19 ^ parity_20_23 ^ parity_24_27; + wire parity_28_31_48_51_52_55 = parity_28_31 ^ parity_48_51 ^ parity_52_55; + + assign check_bits_out[4] = parity_16_19_20_23_24_27 + ^ parity_28_31_48_51_52_55 + ^ parity_56_59_60_63; + + wire parity_32_35_36_39_40_43 = parity_32_35 ^ parity_36_39 ^ parity_40_43; + wire parity_44_47_48_51_52_55 = parity_44_47 ^ parity_48_51 ^ parity_52_55; + + wire parity_second_quarter = parity_32_35_36_39_40_43 + ^ parity_44_47_48_51_52_55 + ^ parity_56_59_60_63; + + assign check_bits_out[5] = parity_second_quarter; + + wire parity_third_quarter = parity_64_67 ^ parity_68_71; + + assign check_bits_out[6] = parity_third_quarter; + +// NOTE: In the generate case, the Check Bit inputs to this function come in +// as all 0's. The generator wants to calculate parity across all bits, +// including Check Bits! +// The slow, inexpensive way to do this is to calculate the odd parity of +// the data including 0's for Check Bits, then XOR that with all of +// the check bits to get the actual word checksum. +// A faster way to do this is to calculate the final checksum directly. +// This starts out by XOR'ing all the Data Bits together. BUT notice +// that the ECC bits contain XOR's of bits in the data. If you +// XOR the Check Bits with the XOR of the Data Bits, some of the +// dependencies on certain data bits go away! +// This function therefore only bothers to calculate the XOR of the bits +// which are not rendered don't cares by the XORing of the check bits. + + wire parity_0_3_5_6 = data_in[0] ^ data_in[3] ^ data_in[5] ^ data_in[6]; + wire parity_9_10_12_15 = data_in[9] ^ data_in[10] ^ data_in[12] ^ data_in[15]; + wire parity_17_18_20_23 = data_in[17] ^ data_in[18] ^ data_in[20] ^ data_in[23]; + wire parity_24_27_29_30 = data_in[24] ^ data_in[27] ^ data_in[29] ^ data_in[30]; + wire parity_33_34_36_39 = data_in[33] ^ data_in[34] ^ data_in[36] ^ data_in[39]; + wire parity_40_43_45_46 = data_in[40] ^ data_in[43] ^ data_in[45] ^ data_in[46]; + wire parity_48_51_53_54 = data_in[48] ^ data_in[51] ^ data_in[53] ^ data_in[54]; + wire parity_57_58_60_63 = data_in[57] ^ data_in[58] ^ data_in[60] ^ data_in[63]; + wire parity_65_66_68_71 = data_in[65] ^ data_in[66] ^ data_in[68] ^ data_in[71]; + + wire parity_0_3_5_6_9_10_12_15_17_18_20_23 = + parity_0_3_5_6 ^ parity_9_10_12_15 ^ parity_17_18_20_23; + wire parity_24_27_29_30_33_34_36_39_40_43_45_46 = + parity_24_27_29_30 ^ parity_33_34_36_39 ^ parity_40_43_45_46; + wire parity_48_51_53_54_57_58_60_63 = + parity_48_51_53_54 ^ parity_57_58_60_63 ^ parity_65_66_68_71; + + assign par_if_inserting_check_bits_out = + parity_0_3_5_6_9_10_12_15_17_18_20_23 + ^ parity_24_27_29_30_33_34_36_39_40_43_45_46 + ^ parity_48_51_53_54_57_58_60_63; + +// The module which checks ECC values actually has to look at all the data. +// Reuse calculations which have already been done. + + wire parity_0_3_8_11_16_19 = parity_0_3 ^ parity_8_11 ^ parity_16_19; + wire parity_24_27_28_31 = parity_24_27 ^ parity_28_31; + + wire parity_first_quarter = parity_0_3_8_11_16_19 + ^ parity_4_7_12_15_20_23 + ^ parity_24_27_28_31; + + assign check_bits_out[7] = parity_first_quarter + ^ parity_second_quarter + ^ parity_third_quarter; +endmodule + +// Given a 64-bit word (with no errors), calculate the 72-bit word which +// will be stored to allow ECC to recover the original 64 bits in case of +// a single bit error. + +module hamming_ecc_generate_word_with_check_bits_64 ( + data_in, + data_plus_ecc_out, + clk +); + + parameter NUM_DATA_BITS = 64; // do not override in the instantiation. + parameter NUM_CHECK_BITS = 8; + + input [NUM_DATA_BITS - 1 : 0] data_in; + output [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] data_plus_ecc_out; + input clk; + + wire [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] input_vector = + {data_in[63:57], 1'b0, // check digit 6, bit 64 + data_in[56:26], 1'b0, // check digit 5, bit 32 + data_in[25:11], 1'b0, // check digit 4, bit 16 + data_in[10:4], 1'b0, // check digit 3, bit 8 + data_in[3:1], 1'b0, // check digit 2, bit 4 + data_in[0], 1'b0, // check digit 1, bit 2 + 1'b0, 1'b1}; // check digit 0, bit 0 == 1 says odd parity + + wire [NUM_CHECK_BITS - 1 : 0] check_bits_out; + wire par_if_inserting_check_bits_out; + +hamming_ecc_calculate_check_bits_private generate_ecc_bits ( + .data_in (input_vector[NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0]), + .check_bits_out (check_bits_out[NUM_CHECK_BITS - 1 : 0]), + .par_if_inserting_check_bits_out (par_if_inserting_check_bits_out) +); + +// Insert check bits into their nice power-of-2 locations, so they can call +// themselves out if they read in error. + wire [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] reordered_data_plus_ecc = + {data_in[63:57], check_bits_out[6], // check digit 6, bit 64 + data_in[56:26], check_bits_out[5], // check digit 5, bit 32 + data_in[25:11], check_bits_out[4], // check digit 4, bit 16 + data_in[10:4], check_bits_out[3], // check digit 3, bit 8 + data_in[3:1], check_bits_out[2], // check digit 2, bit 4 + data_in[0], check_bits_out[1], // check digit 1, bit 2 + check_bits_out[0], // check digit 0, bit 1 + par_if_inserting_check_bits_out}; // odd parity, bit 0 + + reg [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] data_plus_ecc_out; + + always @(posedge clk) + begin + data_plus_ecc_out[NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] <= + reordered_data_plus_ecc[NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0]; + end +endmodule + +// Given 64 bits, plus 7 bits of ECC check bits and 1 bit of parity, +// discover if the data is correct. +// If 1 bit is wrong, correct it and report the problem. +// If 2 bits are wrong, report the problem. +// If an unexpected bit error position comes out, report that as an error. +// If more than 2 bits are wrong, you are hosed. Most are not detected. +// +// The error_addressvalue is encoded. It means this: +// Error Value 0: no error +// Error Value 1: check bit 0 is wrong +// Error Value 2: check bit 1 is wrong +// Error Value 3: data bit 0 is wrong +// Error Value 4: check bit 2 is wrong +// Error Values 7:5: data bits 3:1 are wrong +// Error Value 8: check bit 3 is wrong +// Error Values 15:9: data bits 10:4 are wrong +// Error Value 16: check bit 4 is wrong +// Error Values 31:17: data bits 25:11 are wrong +// Error Value 32: check bit 5 is wrong +// Error Values 63:32: data bits 56:26 are wrong +// Error Value 64: check bit 6 is wrong +// Error Values 71:65: data bits 63:57 are wrong +// Error Value 72: check bit 7 is wrong + +module hamming_ecc_check_and_correct_64 ( + data_plus_ecc_in, + corrected_data_out, + corrected_check_bits_out, + single_bit_error_corrected, + double_bit_error_detected, + error_address, + clk +); + + parameter NUM_DATA_BITS = 64; // do not override in the instantiation. + parameter NUM_CHECK_BITS = 8; + + input [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] data_plus_ecc_in; + + output [NUM_DATA_BITS - 1 : 0] corrected_data_out; + output [NUM_CHECK_BITS - 1 : 0] corrected_check_bits_out; + + output single_bit_error_corrected; + output double_bit_error_detected; + + output [6:0] error_address; + + input clk; + +// If there is an error, the XOR of the calculated and stored Check Bits +// gives the address of the failing bit. +// The calculate_check_bits module, when applied to a word containing check bits, +// will do the XOR automatically. The output is the address of the failing bit. + wire [NUM_CHECK_BITS - 1 : 0] check_bits; + wire par_if_inserting_check_bits_out; // ignore + +hamming_ecc_calculate_check_bits_private check_ecc_bits ( + .data_in (data_plus_ecc_in[NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0]), + .check_bits_out (check_bits[NUM_CHECK_BITS - 1 : 0]), + .par_if_inserting_check_bits_out (par_if_inserting_check_bits_out) +); + + wire parity_error_detected = ~check_bits[7]; // If data was Odd Parity, return 1'b1; + + wire parity_bit_wrong = (check_bits[6:0] == 7'h00) & parity_error_detected; + + wire correction_needed = (check_bits[6:0] != 7'h00) // non-zero means correct! + | parity_bit_wrong; + + wire unexpected_error_address = (check_bits[6:0] >= 8'h48); // >= 72 + +// If there is an error, need to make a mask to XOR with the data in order to +// get the corrected data back. +// Verilogger seems to be in a core-dumping mood with a straight-forward shift. +// Doing things manually will result in better logic, anyway. + wire [1:0] mask_0 = check_bits[0] ? 2'b10 : 2'b01; + wire [3:0] mask_1 = check_bits[1] + ? {mask_0[1:0], 2'b00} + : {2'b00, mask_0[1:0]}; + wire [7:0] mask_2 = check_bits[2] + ? {mask_1[3:0], 4'h0} + : {4'h0, mask_1[3:0]}; + wire [15:0] mask_3 = check_bits[3] + ? {mask_2[7:0], 8'h00} + : {8'h00, mask_2[7:0]}; + wire [31:0] mask_4 = check_bits[4] + ? {mask_3[15:0], 16'h0000} + : {16'h0000, mask_3[15:0]}; + wire [63:0] mask_5 = check_bits[5] + ? {mask_4[31:0], 32'h00000000} + : {32'h00000000, mask_4[31:0]}; + wire [71:0] mask_6 = check_bits[6] + ? {mask_5[7:0], 64'h00000000_00000000} + : {8'h00, mask_5[63:0]}; + + wire [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] error_corrected_data = + data_plus_ecc_in[NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] + ^ {mask_6[71:1], parity_bit_wrong}; + + wire [NUM_DATA_BITS - 1 : 0] reordered_corrected_data = + {error_corrected_data[71:65], + error_corrected_data[63:33], + error_corrected_data[31:17], + error_corrected_data[15:9], + error_corrected_data[7:5], + error_corrected_data[3]}; + + wire [NUM_CHECK_BITS - 1 : 0] reordered_corrected_check_bits = + {error_corrected_data[0], + error_corrected_data[64], + error_corrected_data[32], + error_corrected_data[16], + error_corrected_data[8], + error_corrected_data[4], + error_corrected_data[2], + error_corrected_data[1]}; + + reg [NUM_DATA_BITS - 1 : 0] corrected_data_out; + reg [NUM_CHECK_BITS - 1 : 0] corrected_check_bits_out; + reg single_bit_error_corrected; + reg double_bit_error_detected; + reg [6:0] error_address; + + always @(posedge clk) + begin + corrected_data_out[NUM_DATA_BITS - 1 : 0] <= + reordered_corrected_data[NUM_DATA_BITS - 1 : 0]; + corrected_check_bits_out[NUM_CHECK_BITS - 1 : 0] <= + reordered_corrected_check_bits[NUM_CHECK_BITS - 1 : 0]; + single_bit_error_corrected <= correction_needed & parity_error_detected; + double_bit_error_detected <= (correction_needed & ~parity_error_detected) + | unexpected_error_address; + error_address[6:0] <= parity_bit_wrong + ? 8'h48 // 72 + : check_bits[6:0]; + end +endmodule + +// `define TEST_HAMMING_ECC_CODE +`ifdef TEST_HAMMING_ECC_CODE +module test_ecc (); + + parameter NUM_DATA_BITS = 64; // do not override in the instantiation. + parameter NUM_CHECK_BITS = 8; + + reg clk; + reg [NUM_DATA_BITS - 1 : 0] data_in; + wire [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] data_plus_ecc_out; + wire [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] data_plus_ecc_in; + reg [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] force_error; + wire [NUM_DATA_BITS - 1 : 0] corrected_data_out; + wire [NUM_CHECK_BITS - 1 : 0] corrected_check_bits_out; + wire single_bit_error_corrected; + wire double_bit_error_detected; + wire [6:0] error_address; + + reg [NUM_DATA_BITS - 1 : 0] data_pattern; + reg [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] error_mask_1; + reg [NUM_DATA_BITS + NUM_CHECK_BITS - 1 : 0] error_mask_2; + integer cnt; + +task make_clk; + begin + # 1; + clk = 1'b1; + # 2; + clk = 1'b0; + # 1; + end +endtask + + wire [NUM_CHECK_BITS - 1 : 0] original_check_bits = + {data_plus_ecc_out[0], + data_plus_ecc_out[64], + data_plus_ecc_out[32], + data_plus_ecc_out[16], + data_plus_ecc_out[8], + data_plus_ecc_out[4], + data_plus_ecc_out[2], + data_plus_ecc_out[1]}; + + initial + begin + clk = 1'b0; + + $display ("Walking a 1"); +// need to check that walking 1 bit goes through correctly. + for (data_pattern = 64'h00000000_00000001; + data_pattern != 64'h0; + data_pattern = data_pattern << 1) + begin + data_in = data_pattern; + force_error = 72'h00_00000000_00000000; + make_clk; + make_clk; + if (data_in !== corrected_data_out) + $display ("*** Data In != Data Out %x %x", data_in, corrected_data_out); + if (original_check_bits !== corrected_check_bits_out) + $display ("*** Check Bits In != Check Bits Out %x %x", original_check_bits, corrected_check_bits_out); + if (single_bit_error_corrected !== 1'b0) + $display ("*** Unexpected Single Bit Error Detected %x %x %x", + single_bit_error_corrected, data_pattern, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b0) + $display ("*** Unexpected Double Bit Error Detected %x %x %x", + double_bit_error_detected, data_pattern, data_plus_ecc_in); + end + + $display ("Walking a 0"); +// need to check that walking 0 bit goes through correctly. + for (data_pattern = 64'h00000000_00000001; + data_pattern != 64'h0; + data_pattern = data_pattern << 1) + begin + data_in = ~data_pattern; + force_error = 72'h00_00000000_00000000; + make_clk; + make_clk; + if (corrected_data_out !== data_in) + $display ("*** Data In != Data Out %x %x", data_in, corrected_data_out); + if (original_check_bits !== corrected_check_bits_out) + $display ("*** Check Bits In != Check Bits Out %x %x", original_check_bits, corrected_check_bits_out); + if (single_bit_error_corrected !== 1'b0) + $display ("*** Unexpected Single Bit Error Detected %x %x %x", + single_bit_error_corrected, data_pattern, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b0) + $display ("*** Unexpected Double Bit Error Detected %x %x %x", + double_bit_error_detected, data_pattern, data_plus_ecc_in); + end + + $display ("Sending Random Data"); +// need to check that walking 0 bit goes through correctly. + for (cnt = 0; cnt < 1000; cnt = cnt + 1) + begin + data_in = {$random, $random}; + force_error = 72'h00_00000000_00000000; + make_clk; + make_clk; + if (corrected_data_out !== data_in) + $display ("*** Data In != Data Out %x %x", data_in, corrected_data_out); + if (original_check_bits !== corrected_check_bits_out) + $display ("*** Check Bits In != Check Bits Out %x %x", original_check_bits, corrected_check_bits_out); + if (single_bit_error_corrected !== 1'b0) + $display ("*** Unexpected Single Bit Error Detected %x %x %x", + single_bit_error_corrected, data_pattern, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b0) + $display ("*** Unexpected Double Bit Error Detected %x %x %x", + double_bit_error_detected, data_pattern, data_plus_ecc_in); + end + + $display ("Making 0 go to 1, even parity, error check"); +// need to check that 1 bit which should be 0 is detected correctly, even parity. + for (error_mask_1 = 72'h00_00000000_00000001; + error_mask_1 != 72'h0; + error_mask_1 = error_mask_1 << 1) + begin + data_in = 64'h00000000_00000000; + force_error = error_mask_1; + make_clk; + make_clk; + if (corrected_data_out !== data_in) + $display ("*** Data In != Data Out %x %x", data_in, corrected_data_out); + if (original_check_bits !== corrected_check_bits_out) + $display ("*** Check Bits In != Check Bits Out %x %x", original_check_bits, corrected_check_bits_out); + if (single_bit_error_corrected !== 1'b1) + $display ("*** Expected Single Bit Error Missed %x %x %x", + single_bit_error_corrected, error_mask_1, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b0) + $display ("*** Unexpected Double Bit Error Detected %x %x %x", + double_bit_error_detected, error_mask_1, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Parity Error calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Bit 0 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h80_00000000_00000000) + & (error_address != 8'h47) ) + $display ("*** Bit 71 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + end + + $display ("Making 0 go to 1, odd parity, error check"); +// need to check that 1 bit which should be 0 is detected correctly, odd parity. + for (error_mask_1 = 72'h00_00000000_00000001; + error_mask_1 != 72'h0; + error_mask_1 = error_mask_1 << 1) + begin + data_in = 64'h10000000_00000000; + force_error = error_mask_1; + make_clk; + make_clk; + if (corrected_data_out !== data_in) + $display ("*** Data In != Data Out %x %x", data_in, corrected_data_out); + if (original_check_bits !== corrected_check_bits_out) + $display ("*** Check Bits In != Check Bits Out %x %x", original_check_bits, corrected_check_bits_out); + if (single_bit_error_corrected !== 1'b1) + $display ("*** Expected Single Bit Error Missed %x %x %x", + single_bit_error_corrected, error_mask_1, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b0) + $display ("*** Unexpected Double Bit Error Detected %x %x %x", + double_bit_error_detected, error_mask_1, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Parity Error calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Bit 0 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h80_00000000_00000000) + & (error_address != 8'h47) ) + $display ("*** Bit 71 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + end + + $display ("Making 1 go to 0, even parity, error check"); +// need to check that 0 bit which should be 1 is detected correctly, even parity. + for (error_mask_1 = 72'h00_00000000_00000001; + error_mask_1 != 72'h0; + error_mask_1 = error_mask_1 << 1) + begin + data_in = 64'hFFFFFFFF_FFFFFFFF; + force_error = error_mask_1; + make_clk; + make_clk; + if (corrected_data_out !== data_in) + $display ("*** Data In != Data Out %x %x", data_in, corrected_data_out); + if (original_check_bits !== corrected_check_bits_out) + $display ("*** Check Bits In != Check Bits Out %x %x", original_check_bits, corrected_check_bits_out); + if (single_bit_error_corrected !== 1'b1) + $display ("*** Expected Single Bit Error Missed %x %x %x", + single_bit_error_corrected, error_mask_1, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b0) + $display ("*** Unexpected Double Bit Error Detected %x %x %x", + double_bit_error_detected, error_mask_1, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Parity Error calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Bit 0 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h80_00000000_00000000) + & (error_address != 8'h47) ) + $display ("*** Bit 71 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + end + + $display ("Making 1 go to 0, odd parity, error check"); +// need to check that 0 bit which should be 1 is detected correctly, odd parity. + for (error_mask_1 = 72'h00_00000000_00000001; + error_mask_1 != 72'h0; + error_mask_1 = error_mask_1 << 1) + begin + data_in = 64'hFFFFFFFF_FFFFFFFE; + force_error = error_mask_1; + make_clk; + make_clk; + if (corrected_data_out !== data_in) + $display ("*** Data In != Data Out %x %x", data_in, corrected_data_out); + if (original_check_bits !== corrected_check_bits_out) + $display ("*** Check Bits In != Check Bits Out %x %x", original_check_bits, corrected_check_bits_out); + if (single_bit_error_corrected !== 1'b1) + $display ("*** Expected Single Bit Error Missed %x %x %x", + single_bit_error_corrected, error_mask_1, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b0) + $display ("*** Unexpected Double Bit Error Detected %x %x %x", + double_bit_error_detected, error_mask_1, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Parity Error calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Bit 0 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h80_00000000_00000000) + & (error_address != 8'h47) ) + $display ("*** Bit 71 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + end + + $display ("Walking error, random data, error check"); +// need to check that 0 bit which should be 1 is detected correctly, odd parity. + for (error_mask_1 = 72'h00_00000000_00000001; + error_mask_1 != 72'h0; + error_mask_1 = error_mask_1 << 1) + begin + for (cnt = 0; cnt < 25; cnt = cnt + 1) + begin + data_in = {$random, $random}; + force_error = error_mask_1; + make_clk; + make_clk; + if (corrected_data_out !== data_in) + $display ("*** Data In != Data Out %x %x", data_in, corrected_data_out); + if (original_check_bits !== corrected_check_bits_out) + $display ("*** Check Bits In != Check Bits Out %x %x", original_check_bits, corrected_check_bits_out); + if (single_bit_error_corrected !== 1'b1) + $display ("*** Expected Single Bit Error Missed %x %x %x", + single_bit_error_corrected, error_mask_1, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b0) + $display ("*** Unexpected Double Bit Error Detected %x %x %x", + double_bit_error_detected, error_mask_1, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Parity Error calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h00_00000000_00000001) + & (error_address != 8'h48) ) + $display ("*** Bit 0 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + if ( (error_mask_1 == 72'h80_00000000_00000000) + & (error_address != 8'h47) ) + $display ("*** Bit 71 calls out wrong bit offset %x %x", + error_address, data_plus_ecc_in); + end + end + + $display ("testing 2-bit errors, random data, error check"); +// need to check 2 bit errors detected. + for (error_mask_1 = 72'h00_00000000_00000001; + error_mask_1 != 72'h80_00000000_00000000; + error_mask_1 = error_mask_1 << 1) + begin + for (error_mask_2 = error_mask_1 << 1; + error_mask_2 != 72'h0; + error_mask_2 = error_mask_2 << 1) + begin + if (error_mask_1 != error_mask_2) + begin + data_in = {$random, $random}; + force_error = error_mask_1 | error_mask_2; + make_clk; + make_clk; + if (single_bit_error_corrected !== 1'b0) + $display ("*** Unexpected Single Bit Error Detected %x %x %x", + single_bit_error_corrected, error_mask_1, data_plus_ecc_in); + if (double_bit_error_detected !== 1'b1) + $display ("*** Expected Double Bit Error Missed %x %x %x", + double_bit_error_detected, error_mask_1, data_plus_ecc_in); + end + end + end + end + +hamming_ecc_generate_word_with_check_bits_64 generate ( + .data_in (data_in), + .data_plus_ecc_out (data_plus_ecc_out), + .clk (clk) +); + + assign data_plus_ecc_in[71:0] = data_plus_ecc_out ^ force_error; + +hamming_ecc_check_and_correct_64 check_and_correct ( + .data_plus_ecc_in (data_plus_ecc_in), + .corrected_data_out (corrected_data_out), + .corrected_check_bits_out (corrected_check_bits_out), + .single_bit_error_corrected (single_bit_error_corrected), + .double_bit_error_detected (double_bit_error_detected), + .error_address (error_address), + .clk (clk) +); + +endmodule +`endif // TEST_HAMMING_ECC_CODE + Index: common/trunk/Readme =================================================================== --- common/trunk/Readme (nonexistent) +++ common/trunk/Readme (revision 48) @@ -0,0 +1,49 @@ +// This directory contains files which are too small to be projects in themselves. +// +// Examples of such files might be: +// prototype copyright files +// parameterizable cell libraries +// files which implement some interesting low-level function +// files which are used as components in several projects +// +// Each file should be self-documenting so that a quick glance would serve +// to explain what it is and why it is here. +// +// As a courtesy, each file could also have a small entry here to make it +// easy to browse the directory looking for interesting stuff. +// +// "opencores_copyright.v" is an example of a copyright file one might +// include to control the use and abuse of a file stored in this web site. +// +// "synchronizer_flop.v" is a behaviorial description of a 1-bit flop. +// It should be manually instantiated in EACH AND EVERY MODULE which +// uses a flop to synchronize a signal from one clock domain to another. +// In real use, the user of this file will generate a simulation module +// which will behave like a normal flop when presented with 1, 0, X, or Z. +// This special-purpose module will NOT have setup and hold tests. It will +// NOT convert a valid value into an X due to setup timing being violated. +// This module makes it possible to simulate gate-level netlists with +// multiple clock domains without fear of making inappropriate X's. +// +// "grey_to_binary.v" is an example of code which takes a binary number +// and converts it to grey code, and vice versa. +// This module has a parameter which describes how wide the operands +// are. +// This module does not use for-loops to generate the functions. Instead, +// it manually does the translation for widths up to 16 bits. +// If the user wants fewer bits, the synthesis tool removes the extra. +// +// "plesiochronous_fifo.v" is an example of a FIFO which transfers packets +// between two clock domains. +// The clocks are REQUIRED to be close to one-another in frequency. +// The Writer is REQUIRED to skip writes every so often, to make sure that +// the FIFO doesn't overflow. +// This file instantiates the synchronizer_flop mentioned above. +// +// "hamming_ecc_64.v" is an example of how to use 8 bits of redundant data to +// correct single-bit errors and detect double-bit errors in 64 bits of data. +// There are probably better ways to reorder the terms to reduce loads, and +// to change the formulas to detect a larger percentage of likely errors. +// + + Index: common/trunk/opencores_copyright.v =================================================================== --- common/trunk/opencores_copyright.v (nonexistent) +++ common/trunk/opencores_copyright.v (revision 48) @@ -0,0 +1,50 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// YOUR MODULE OR FILE NAME HERE //// +//// //// +//// This file is part of the YOUR PROJECT NAME opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// YOUR MODULE DESCRIPTION //// +//// //// +//// To Do: //// +//// YOUR STATE HERE //// +//// //// +//// Author(s): //// +//// - YOUR NAME HERE //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 YOUR NAME HERE and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// \$Id\$ TAKE OUT THE \'s and this comment in order to get this to work +// +// CVS Revision History +// +// \$Log\$ TAKE OUT THE \'s and this comment in order to get this to work +// +