URL
https://opencores.org/ocsvn/m1_core/m1_core/trunk
Subversion Repositories m1_core
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- This comparison shows the changes necessary to convert path
/
- from Rev 47 to Rev 48
- ↔ Reverse comparison
Rev 47 → Rev 48
/trunk/hdl/rtl/m1_core/m1_alu.v
8,40 → 8,47
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// Combinational ALU with 32-bit operands |
module m1_alu( |
input[31:0] a_i, // Operands A |
input[31:0] b_i, // Operands B |
input[31:0] a_i, // Operand A |
input[31:0] b_i, // Operand B |
input[4:0] func_i, // Function to be performed |
input signed_i, // Operation is signed |
output reg[31:0] result_o, // Result |
output carry_o // Carry bit |
output reg[32:0] result_o // 33-bit result (uppermost bit is the carry) |
); |
|
// Carry is currently unused |
assign carry_o = 0; |
|
// ALU Logic |
always @(a_i or b_i or func_i or signed_i) begin |
case(func_i) |
`ALU_OP_SLL: result_o = a_i << b_i[4:0]; |
`ALU_OP_SRL: result_o = a_i >> b_i[4:0]; |
`ALU_OP_SRA: result_o = {{32{a_i[31]}}, a_i } >> b_i[4:0]; |
`ALU_OP_ADD: result_o = a_i + b_i; |
`ALU_OP_SUB: result_o = a_i - b_i; |
`ALU_OP_AND: result_o = a_i & b_i; |
`ALU_OP_OR: result_o = a_i | b_i; |
`ALU_OP_XOR: result_o = a_i ^ b_i; |
`ALU_OP_NOR: result_o = ~(a_i | b_i); |
`ALU_OP_SEQ: result_o = (a_i == b_i) ? 32'b1 : 32'b0; |
`ALU_OP_SNE: result_o = (a_i != b_i) ? 32'b1 : 32'b0; |
`ALU_OP_SLT: if(signed_i) result_o = ({~a_i[31],a_i[30:0]} < {~b_i[31],b_i[30:0]}) ? 32'b1 : 32'b0; |
else result_o = a_i < b_i; |
`ALU_OP_SLE: if ((a_i[31] == 1'b1) || (a_i == 32'b0)) result_o = 32'b1; |
else result_o = 32'b0; |
`ALU_OP_SGT: if ((a_i[31] == 1'b0) && (a_i != 32'b0)) result_o = 32'b1; |
else result_o = 32'b0; |
`ALU_OP_SGE: if(signed_i) result_o = ({~a_i[31],a_i[30:0]} >= {~b_i[31],b_i[30:0]}) ? 32'b1 : 32'b0; |
else result_o = a_i >= b_i; |
default: result_o = 32'b0; |
|
// Shift instructions |
`ALU_OP_SLL: result_o = {1'b0, a_i << b_i[4:0]}; |
`ALU_OP_SRL: result_o = {1'b0, a_i >> b_i[4:0]}; |
`ALU_OP_SRA: result_o = {1'b0, {{32{a_i[31]}}, a_i } >> b_i[4:0]}; |
|
// Arithmetical instructions |
`ALU_OP_ADD: if(signed_i) result_o = a_i + b_i; // Result may include a carry bit |
else result_o = {1'b0, a_i + b_i}; |
`ALU_OP_SUB: if(signed_i) result_o = a_i - b_i; // Result may include a carry bit |
else result_o = {1'b0, a_i - b_i}; |
|
// Logical instructions |
`ALU_OP_AND: result_o = {1'b0, a_i & b_i}; |
`ALU_OP_OR: result_o = {1'b0, a_i | b_i}; |
`ALU_OP_XOR: result_o = {1'b0, a_i ^ b_i}; |
`ALU_OP_NOR: result_o = {1'b0, ~(a_i | b_i)}; |
|
// Conditional instructions |
`ALU_OP_SEQ: result_o = (a_i == b_i) ? 33'b1 : 33'b0; |
`ALU_OP_SNE: result_o = (a_i != b_i) ? 33'b1 : 33'b0; |
`ALU_OP_SLT: if(signed_i) result_o = ({~a_i[31],a_i[30:0]} < {~b_i[31],b_i[30:0]}) ? 33'b1 : 33'b0; |
else result_o = (a_i < b_i) ? 33'b1 : 33'b0; |
`ALU_OP_SLE: if(signed_i) result_o = ({~a_i[31],a_i[30:0]} <= {~b_i[31],b_i[30:0]}) ? 33'b1 : 33'b0; |
else result_o = (a_i <= b_i) ? 33'b1 : 33'b0; |
`ALU_OP_SGT: if(signed_i) result_o = ({~a_i[31],a_i[30:0]} > {~b_i[31],b_i[30:0]}) ? 33'b1 : 33'b0; |
else result_o = (a_i > b_i) ? 33'b1 : 33'b0; |
`ALU_OP_SGE: if(signed_i) result_o = ({~a_i[31],a_i[30:0]} >= {~b_i[31],b_i[30:0]}) ? 33'b1 : 33'b0; |
else result_o = (a_i >= b_i) ? 33'b1 : 33'b0; |
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default: result_o = 33'b0; |
endcase |
end |
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/trunk/hdl/rtl/m1_core/m1_cpu.v
16,8 → 16,7
output[31:0] alu_b_o, // ALU Operand B |
output[4:0] alu_func_o, // ALU Function |
output alu_signed_o, // ALU operation is Signed |
input[31:0] alu_result_i, // ALU Result |
input alu_carry_i, // ALU Carry |
input[32:0] alu_result_i, // ALU Result with Carry |
|
// Multiplier |
output reg mul_req_o, // Multiplier Request |
92,6 → 91,7
reg[31:0] ex_mem_addr, ex_mem_addrnext; |
reg[31:0] ex_mem_addrbranch, ex_mem_addrjump, ex_mem_addrjr; |
reg[63:0] ex_mem_aluout; // ALU result |
reg ex_mem_carry; // ALU carry |
reg ex_mem_branch, ex_mem_jump, ex_mem_jr, ex_mem_linked; |
reg ex_mem_mult, ex_mem_div; |
reg ex_mem_load,ex_mem_store; |
1766,7 → 1766,10
// Choose the output from ALU, Multiplier or Divider |
if(id_ex_mult) ex_mem_aluout <= mul_product_i; |
else if(id_ex_div) ex_mem_aluout <= { div_remainder_i, div_quotient_i }; |
else ex_mem_aluout <= alu_result_i; |
else begin |
ex_mem_aluout <= {32'b0, alu_result_i[31:0]}; |
ex_mem_carry <= alu_result_i[32]; |
end |
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if(id_ex_store) begin |
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/trunk/hdl/rtl/m1_core/m1_core.v
32,8 → 32,7
wire[31:0] alu_b; |
wire[4:0] alu_func; |
wire alu_signed; |
wire[31:0] alu_result; |
wire alu_carry; |
wire[32:0] alu_result; |
|
// Multiplier |
wire mul_req; |
85,7 → 84,6
.alu_func_o(alu_func), |
.alu_signed_o(alu_signed), |
.alu_result_i(alu_result), |
.alu_carry_i(alu_carry), |
|
// Multiplier |
.mul_req_o(mul_req), |
127,8 → 125,7
.b_i(alu_b), |
.func_i(alu_func), |
.signed_i(alu_signed), |
.result_o(alu_result), |
.carry_o(alu_carry) |
.result_o(alu_result) |
); |
|
// Multiplier |