URL
https://opencores.org/ocsvn/m32632/m32632/trunk
Subversion Repositories m32632
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 48 to Rev 49
- ↔ Reverse comparison
Rev 48 → Rev 49
/m32632/trunk/rtl/DCACHE.v
4,14 → 4,15
// http://opencores.org/project,m32632 |
// |
// Filename: DCACHE.v |
// Version: 3.0 Cache Interface reworked |
// History: 2.1 bug fix of November 2016 |
// Version: 3.2 bug fix |
// History: 3.0 Cache Interface reworked |
// 2.1 bug fix of November 2016 |
// 2.0 50 MHz release of 14 August 2016 |
// 1.1 bug fix of 7 October 2015 |
// 1.0 first release of 30 Mai 2015 |
// Date: 2 December 2018 |
// Date: 17 January 2021 |
// |
// Copyright (C) 2018 Udo Moeller |
// Copyright (C) 2021 Udo Moeller |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
171,6 → 172,7
wire PKEEP; |
wire XADDR2; |
wire [28:12] TAGDAT; |
wire clr_up; |
|
// +++++++++++++++++++ Memories ++++++++++++++++++++ |
|
277,9 → 279,14
(PD_MUX ? PTE_DAT[15:0] : WRDATA[15:0])}; |
AUX_ALT <= DFF_QWEXT | IO_RD; |
DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1]; |
VADR_R <= VADR; |
VADR_R[23:0] <= VADR[23:0]; |
end |
|
assign clr_up = ~(DRAMSZ == 3'd0); |
always @(posedge BCLK or negedge clr_up) |
if (!clr_up) VADR_R[31:24] <= 8'd0; |
else VADR_R[31:24] <= VADR[31:24]; |
|
always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q; |
|
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++ |
/m32632/trunk/rtl/DECODER.v
4,12 → 4,13
// http://opencores.org/project,m32632 |
// |
// Filename: DECODER.v |
// Version: 3.0 |
// History: 2.0 of 11 August 2016 |
// Version: 3.2 bug fix |
// History: 3.0 of 2 December 2018 |
// 2.0 of 11 August 2016 |
// 1.0 first release of 30 Mai 2015 |
// Date: 2 December 2018 |
// Date: 17 January 2021 |
// |
// Copyright (C) 2018 Udo Moeller |
// Copyright (C) 2021 Udo Moeller |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
571,7 → 572,7
always @(posedge BCLK) ldpc_phase <= (phase_reg == 8'h3E) // PC load at CXP/Traps , all one clock cycle guaranted |
| (phase_reg == 8'h43) // PC load at RXP |
| ((phase_reg == 8'h49) & reti_flag) // PC load at RETI |
| (phase_reg == 8'h4E) // PC load at RETT |
| ((phase_reg == 8'h4E) & next) // PC load at RETT - here not one clock cycle guaranted |
| (phase_reg == 8'h66) // PC load at JUMP/JSR/CASE |
| (phase_reg == 8'h7B); // PC load at DE = Direct Exception |
|
/m32632/trunk/rtl/ICACHE.v
4,15 → 4,14
// http://opencores.org/project,m32632 |
// |
// Filename: ICACHE.v |
// Project: M32632 |
// Version: 3.1 bug fix of 25 February 2019 |
// History: 3.0 Cache Interface reworked |
// Version: 3.2 bug fix |
// History: 3.1 bug fix of 25 February 2019 |
// 3.0 Cache Interface reworked |
// 2.0 50 MHz release of 14 August 2016 |
// 1.0 first release of 30 Mai 2015 |
// Author: Udo Moeller |
// Date: 8 July 2017 |
// Date: 17 January 2021 |
// |
// Copyright (C) 2019 Udo Moeller |
// Copyright (C) 2021 Udo Moeller |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
149,6 → 148,7
wire RMW; |
wire [31:0] CAP_Q; |
wire [28:12] TAGDAT; |
wire clr_up; |
|
// +++++++++++++++++++ Memories ++++++++++++++++++++ |
|
221,8 → 221,13
assign VADR[31:12] = IVAR_MUX ? VADR_D : VADR_I[31:12]; |
assign VADR[11:0] = VADR_I[11:0]; |
|
always @(posedge BCLK) VADR_R <= VADR; |
always @(posedge BCLK) VADR_R[23:0] <= VADR[23:0]; |
|
assign clr_up = ~(DRAMSZ == 3'd0); |
always @(posedge BCLK or negedge clr_up) |
if (!clr_up) VADR_R[31:24] <= 8'd0; |
else VADR_R[31:24] <= VADR[31:24]; |
|
always @(posedge BCLK) DFF_IRD_REG <= IO_RD; |
|
always @(posedge BCLK) DFF_HDFF1 <= IO_READY; |