URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
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- This comparison shows the changes necessary to convert path
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- from Rev 483 to Rev 484
- ↔ Reverse comparison
Rev 483 → Rev 484
/openrisc/trunk/orpsocv2/doc/orpsoc.texi
434,10 → 434,15
@item SIMULATOR |
Specify simulator to use. Default is Icarus Verilog, can be set to @code{modelsim} to use Mentor Graphics' Modelsim. No others are supported right now. |
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@item MGC_NO_VOPT |
When using Modelsim (specifying @code{SIMULATOR=modelsim}), if the version does not include the individual @code{vopt} executable, specify @code{MGC_NO_VOPT=1} when compiling. |
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@end table |
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@node Reference Design Cycle Accurate |
@subsection Cycle Accurate |
@cindex cycle accurate simulation of reference design |
/openrisc/trunk/orpsocv2/sim/bin/Makefile
174,9 → 174,32
# If VCD dump is desired, tell Modelsim not to optimise |
# away everything. |
ifeq ($(VCD), 1) |
#VOPT_ARGS=-voptargs="+acc=rnp" |
# If certain versions of modelsim don't have the vopt executable, define |
# MGC_NO_VOPT=1 when running. |
ifeq ($(MGC_NO_VOPT), 1) |
MGC_VSIM_ARGS +=-voptargs="+acc=rnp" |
MGC_VOPT_CMD=echo |
MGC_VSIM_TGT=orpsoc_testbench |
else |
VOPT_ARGS=+acc=rnpqv |
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb |
MGC_VSIM_TGT=tb |
endif |
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else |
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ifeq ($(MGC_NO_VOPT), 1) |
MGC_VSIM_ARGS += -vopt |
MGC_VOPT_CMD=echo |
MGC_VSIM_TGT=orpsoc_testbench |
else |
VOPT_ARGS=+acc=rnpqv |
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb |
MGC_VSIM_TGT=tb |
endif |
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endif |
# VSIM commands |
# Suppressed warnings - 3009: Failed to open $readmemh() file |
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale |
183,7 → 206,7
# directive in effect, but previous modules do. |
# Suppressed warnings - 8598: Non-positive replication multiplier inside |
# concat. Replication will be ignored |
MGC_VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \ |
MGC_VSIM_ARGS += -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \ |
-do "set StdArithNoWarnings 1; run -all; exit" |
# Options required when VPI option used |
ifeq ($(VPI), 1) |
321,9 → 344,9
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(MGC_VPI_LIB) work |
$(Q)echo; echo "\t### Compiling testbench ###"; echo |
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $< |
$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb |
$(Q)$(MGC_VOPT_CMD) |
$(Q)echo; echo "\t### Launching simulation ###"; echo |
$(Q)vsim $(MGC_VSIM_ARGS) tb |
$(Q)vsim $(VOPT_ARGS) $(MGC_VSIM_ARGS) $(MGC_VSIM_TGT) |
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# |
# Icarus Verilog simulator build and run rules |