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URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

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Rev 49 → Rev 50

/turbo8051/trunk/rtl/lib/wb_rd_mem2mem.v
42,7 → 42,18
//////////////////////////////////////////////////////////////////////
 
/**********************************************
Web-bone , Read from Wishbone Memory and Write to internal Memory
Web-bone , Read from Wishbone Memory and Write to internal Memory
 
This block handles following task
1. Check the Descriptor Q for not empty
2. If the Descriptor Q is not empty, the read the 32 bit descriptor
3. The 32 bit descriptor holds following information
[11:0] - Packet Length
[25:12] - MSB [15:2] of Packet Start Location
[31:26] - Packet Status
4. Based on the Packet Length, Read the data from external Data memory
and write it to Internal Memory
 
**********************************************/
 
module wb_rd_mem2mem (
50,13 → 61,12
rst_n ,
clk ,
 
// descriptor handshake
cfg_desc_baddr ,
desc_q_empty ,
 
// Master Interface Signal
mem_req ,
mem_txfr ,
mem_ack ,
mem_taddr ,
mem_addr ,
mem_full ,
mem_afull ,
mem_wr ,
85,8 → 95,10
// State Machine Parameter
//--------------------
 
parameter IDLE = 0;
parameter TXFR = 1;
parameter IDLE = 0;
parameter DESC_RD = 1;
parameter DATA_WAIT = 2;
parameter TXFR = 3;
 
 
//-------------------------------------------
103,19 → 115,21
// to restart. Furthermore, all internal self-starting state
// machines will be forced into an initial state.
 
//---------------------------------
// Descriptor Interface
//---------------------------------
input [15:6] cfg_desc_baddr ; // descriptor Base Address
input desc_q_empty ;
 
//------------------------------------------
// Stanard Memory Interface
//------------------------------------------
input mem_req ;
input [15:0] mem_txfr ;
output mem_ack ;
 
input [TAR_WD-1:0] mem_taddr ; // target address
input [15:0] mem_addr ; // memory address
input mem_full ; // memory full
input mem_afull ; // memory afull
output mem_wr ; // memory read
output [7:0] mem_din ; // memory read data
output mem_wr ; // memory Write
output [8:0] mem_din ; // memory read data
 
//------------------------------------------
// External Memory WB Interface
185,7 → 199,7
// Register Declration
//----------------------------------------
 
reg state ;
reg [1:0] state ;
reg [15:0] cnt ;
reg [TAR_WD-1:0] wbo_taddr ;
reg [ADR_WD-1:0] wbo_addr ;
193,17 → 207,21
reg wbo_we ;
reg [BE_WD-1:0] wbo_be ;
reg wbo_cyc ;
reg mem_ack ;
reg [15:0] mem_addr ;
 
wire mem_wr = wbo_ack;
wire mem_wr = (state == TXFR) ? wbo_ack: 1'b0 ;
 
// Generate Next Address, to fix the read to address inc issue
wire [15:0] taddr = mem_addr+1;
 
wire [7:0] mem_din = (mem_addr[1:0] == 2'b00) ? wbo_dout[7:0] :
(mem_addr[1:0] == 2'b01) ? wbo_dout[15:8] :
(mem_addr[1:0] == 2'b10) ? wbo_dout[23:16] : wbo_dout[31:24] ;
assign mem_din[7:0] = (mem_addr[1:0] == 2'b00) ? wbo_dout[7:0] :
(mem_addr[1:0] == 2'b01) ? wbo_dout[15:8] :
(mem_addr[1:0] == 2'b10) ? wbo_dout[23:16] : wbo_dout[31:24] ;
 
assign mem_din[8] = (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
 
reg [3:0] desc_ptr;
 
always @(negedge rst_n or posedge clk) begin
if(rst_n == 0) begin
state <= IDLE;
213,39 → 231,67
wbo_we <= 0;
wbo_be <= 0;
wbo_cyc <= 0;
mem_ack <= 0;
desc_ptr <= 0;
mem_addr <= 0;
end
else begin
case(state)
IDLE: begin
if(mem_req && !mem_full) begin
cnt <= mem_txfr;
wbo_taddr <= mem_taddr;
wbo_addr <= mem_addr[14:2];
wbo_stb <= 1'b1;
wbo_we <= 1'b0;
wbo_be <= 1 << mem_addr[1:0];
wbo_cyc <= 1'b1;
mem_ack <= 1;
state <= TXFR;
// Check for Descriptor Q not empty
if(!desc_q_empty) begin
wbo_taddr <= mem_taddr;
wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]};
wbo_be <= 4'hF;
wbo_we <= 1'b0;
wbo_stb <= 1'b1;
wbo_cyc <= 1;
state <= DESC_RD;
desc_ptr <= desc_ptr+1;
end
end
DESC_RD: begin
// wait for web-bone ack
if(wbo_ack) begin
wbo_cyc <= 1'b0;
wbo_stb <= 1'b0;
state <= IDLE;
cnt <= wbo_dout[11:0];
mem_addr <= {wbo_dout[27:12],2'b0};
state <= DATA_WAIT;
end
end
 
DATA_WAIT: begin
// check for internal memory not full and initiate
// the transfer
if(!mem_full) begin
wbo_taddr <= mem_taddr;
wbo_addr <= mem_addr[14:2];
wbo_stb <= 1'b1;
wbo_we <= 1'b0;
wbo_be <= 4'hF;
wbo_cyc <= 1'b1;
state <= TXFR;
end
end
TXFR: begin
mem_ack <= 0;
if(wbo_ack) begin
cnt <= cnt-1;
wbo_addr <= taddr[14:2];
wbo_be <= 1 << taddr[1:0];
mem_addr <= mem_addr+1;
cnt <= cnt-1;
wbo_addr <= taddr[14:2];
wbo_be <= 4'hF;
if(cnt == 1) begin
wbo_stb <= 1'b0;
wbo_cyc <= 1'b0;
state <= IDLE;
end
else if(mem_afull) begin
else if(mem_afull) begin // to handle the interburst fifo full case
wbo_cyc <= 1'b0;
wbo_stb <= 1'b0;
end
end else if(!mem_full) begin
wbo_stb <= 1'b1;
end else if(!mem_full) begin // to handle interbust fifo full cases
wbo_cyc <= 1'b1;
wbo_stb <= 1'b1;
end
end
endcase
/turbo8051/trunk/rtl/lib/wb_wr_mem2mem.v
58,6 → 58,14
mem_aempty ,
mem_rd ,
mem_dout ,
mem_eop ,
 
cfg_desc_baddr ,
desc_req ,
desc_ack ,
desc_disccard ,
desc_data ,
 
// Slave Interface Signal
wbo_din ,
79,8 → 87,10
parameter TAR_WD = 4; // Target Width
 
// State Machine
parameter IDLE = 0;
parameter XFR = 1;
parameter IDLE = 2'h0;
parameter XFR = 2'h1;
parameter DESC_WAIT = 2'h2;
parameter DESC_XFR = 2'h3;
 
input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
// for the internal logic within the WISHBONE interconnect.
101,7 → 111,17
input mem_aempty; // memory empty
output mem_rd; // memory read
input [7:0] mem_dout; // memory read data
input mem_eop; // Last Transfer indication
 
//----------------------------------------
// Discriptor defination
//----------------------------------------
input desc_req; // descriptor request
output desc_ack; // descriptor ack
input desc_disccard;// descriptor discard
input [15:6] cfg_desc_baddr; // descriptor memory base address
input [31:0] desc_data; // descriptor data
 
//------------------------------------------
// External Memory WB Interface
//------------------------------------------
177,11 → 197,13
reg [BE_WD-1:0] wbo_be ;
reg wbo_cyc ;
reg [D_WD-1:0] wbo_din ;
reg state ;
reg [1:0] state ;
 
reg mem_rd ;
reg mem_rd ;
reg [3:0] desc_ptr ; // descriptor pointer, in 32 bit mode
reg mem_eop_l ; // delayed eop signal
reg desc_ack ; // delayed eop signal
 
 
always @(negedge rst_n or posedge clk) begin
if(rst_n == 0) begin
wbo_taddr <= 0;
192,11 → 214,15
wbo_cyc <= 0;
wbo_din <= 0;
mem_rd <= 0;
desc_ptr <= 0;
mem_eop_l <= 0;
desc_ack <= 0;
state <= IDLE;
end
else begin
case(state)
IDLE: begin
desc_ack <= 0;
if(!mem_empty) begin
wbo_taddr <= mem_taddr;
wbo_addr <= mem_addr[14:2];
205,6 → 231,7
wbo_be <= 1 << mem_addr[1:0];
wbo_cyc <= 1;
wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
mem_eop_l <= mem_eop;
mem_rd <= 1;
state <= XFR;
end
211,10 → 238,14
end
XFR: begin
if(wbo_ack) begin
mem_eop_l <= mem_eop;
wbo_addr <= mem_addr[14:2];
wbo_be <= 1 << mem_addr[1:0];
wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
if(mem_aempty || mem_empty) begin
if(mem_eop_l) begin
state <= DESC_WAIT;
end
else if(mem_aempty || mem_empty) begin
wbo_stb <= 1'b0;
wbo_cyc <= 0;
state <= IDLE;
225,6 → 256,33
mem_rd <= 0;
end
end
DESC_WAIT: begin
if(desc_req) begin
desc_ack <= 1;
if(desc_disccard) begin // if the Desc is discarded
state <= IDLE;
end
else begin
wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]}; // Each Transfer is 32bit
wbo_be <= 4'hF;
wbo_din <= desc_data;
wbo_we <= 1'b1;
wbo_stb <= 1'b1;
wbo_cyc <= 1;
state <= DESC_XFR;
desc_ptr <= desc_ptr+1;
end
end
end
DESC_XFR: begin
desc_ack <= 0;
if(wbo_ack) begin
wbo_stb <= 1'b0;
wbo_cyc <= 1'b0;
state <= IDLE;
end
end
 
endcase
end
end
/turbo8051/trunk/rtl/lib/g_dpath_ctrl.v
41,23 → 41,31
//// ////
//////////////////////////////////////////////////////////////////////
 
module dpath_ctrl (
module g_dpath_ctrl (
rst_n ,
clk ,
 
rx_buf_base_addr ,
tx_buf_base_addr ,
 
// gmac core to memory write interface
g_rx_mem_rd ,
g_rx_mem_eop ,
g_rx_mem_addr ,
g_rx_block_rxrd ,
 
// Memory to gmac core interface
g_tx_mem_wr ,
g_tx_mem_eop ,
g_tx_mem_addr ,
g_tx_mem_req ,
g_tx_mem_req_length ,
g_tx_mem_ack
// descr handshake
g_rx_desc_req ,
g_rx_desc_discard ,
g_rx_desc_data ,
g_rx_desc_ack ,
 
g_rx_pkt_done ,
g_rx_pkt_len ,
g_rx_pkt_status ,
g_rx_pkt_drop
 
 
);
 
 
64,68 → 72,91
input rst_n ;
input clk ;
 
input [3:0] rx_buf_base_addr ; // 8K Rx Base Address
input [3:0] tx_buf_base_addr ; // 8K tx Base Address
 
// gmac core to memory write interface
input g_rx_mem_rd ;
input g_rx_mem_eop ;
output [15:0] g_rx_mem_addr ;
output g_rx_block_rxrd ; // Block Rx Read between EOP and PktDone
 
// Memory to gmac core interface
input g_tx_mem_wr ;
output g_tx_mem_eop ;
output [15:0] g_tx_mem_addr ;
input g_rx_pkt_done ; // End of current Packet
input [11:0] g_rx_pkt_len ; // Packet Length
input [15:0] g_rx_pkt_status ; // Packet Status
input g_rx_pkt_drop ; // Packet drop and rewind the pointer
 
output g_tx_mem_req ;
output [15:0] g_tx_mem_req_length ;
input g_tx_mem_ack ;
 
//-----------------------------------
// Descriptor handshake
//----------------------------------
output g_rx_desc_req ; // rx desc request
output g_rx_desc_discard ; // rx desc discard indication
output [31:0] g_rx_desc_data ; // rx desc data
input g_rx_desc_ack ; // rx desc ack
 
reg [15:0] g_rx_mem_addr ;
reg [15:0] g_tx_mem_addr ;
reg [15:0] g_tx_mem_req_length ;
reg [15:0] rx_plen ;
reg [15:0] tx_plen ;
reg g_tx_mem_req ;
 
wire g_tx_mem_eop = ((tx_plen +1) == g_tx_mem_req_length) ? 1'b1 : 1'b0;
reg g_rx_desc_req ;
reg g_rx_desc_discard ; // rx desc discard indication
reg [31:0] g_rx_desc_data ; // rx desc data
 
reg [11:0] g_rx_mem_addr_int ;
 
wire [15:0] g_rx_mem_addr = {rx_buf_base_addr,g_rx_mem_addr_int[11:0]};
 
 
reg bStartFlag; // Indicate a SOP transaction, used for registering Start Address
reg g_rx_block_rxrd; // Block Rx Read at the end of EOP and Enable on Packet Done
reg [11:0] g_rx_saddr;
always @(negedge rst_n or posedge clk) begin
if(rst_n == 0) begin
g_rx_mem_addr <= 0;
g_tx_mem_addr <= 0;
rx_plen <= 0;
tx_plen <= 0;
g_rx_mem_addr_int <= 0;
bStartFlag <= 1;
g_rx_block_rxrd <= 0;
g_rx_saddr <= 0;
g_rx_desc_discard <= 0;
g_rx_desc_data <= 0;
g_rx_desc_req <= 0;
end
else begin
if(bStartFlag && g_rx_mem_rd) begin
g_rx_saddr <= g_rx_mem_addr_int[11:0];
bStartFlag <= 0;
end else if (g_rx_mem_rd && g_rx_mem_eop) begin
bStartFlag <= 1;
end
 
if(g_rx_mem_rd && g_rx_mem_eop)
g_rx_block_rxrd <= 1;
else if(g_rx_pkt_done)
g_rx_block_rxrd <= 0;
 
//-----------------------------
// Finding the Frame Size
//----------------------------
if(g_rx_mem_rd) begin
g_rx_mem_addr <= g_rx_mem_addr+1;
if(g_rx_mem_eop) rx_plen <= 0;
else rx_plen <= rx_plen +1;
if(g_rx_pkt_done && g_rx_pkt_drop) begin
g_rx_mem_addr_int <= g_rx_saddr;
end else if(g_rx_mem_rd && g_rx_mem_eop) begin
// Realign to 32 bit boundary and add one free space at eop
g_rx_mem_addr_int <= g_rx_mem_addr_int+4-g_rx_mem_addr_int[1:0];
end else if(g_rx_mem_rd ) begin
g_rx_mem_addr_int <= g_rx_mem_addr_int+1;
end
//------------------------
// Generate Tx Request at last transfer of RX Req
//------------------------
//
if(g_rx_mem_eop && g_rx_mem_rd) begin
g_tx_mem_req_length <= rx_plen+1;
g_tx_mem_req <= 1;
end else if (g_tx_mem_ack) begin
g_tx_mem_req <= 0;
// Descriptor Request Generation
if(g_rx_pkt_done) begin
g_rx_desc_req <= 1;
if(g_rx_pkt_drop) begin
g_rx_desc_discard <= 1;
end else begin
g_rx_desc_discard <= 0;
g_rx_desc_data <= {g_rx_pkt_status[5:0],rx_buf_base_addr[3:0],
g_rx_saddr[11:2],g_rx_pkt_len[11:0]};
end
end
 
//------------------------
// Generate of EOP for TX Interface at last transfer
//-------------------------
if(g_tx_mem_wr) begin
g_tx_mem_addr <= g_tx_mem_addr+1;
if(g_tx_mem_req_length == (tx_plen +1)) begin
tx_plen <= 0;
end else begin
tx_plen <= tx_plen +1;
end
else if (g_rx_desc_ack) begin
g_rx_desc_req <= 0;
g_rx_desc_discard <= 0;
end
end
end
/turbo8051/trunk/rtl/lib/stat_counter.v
61,7 → 61,8
sys_clk,
s_reset_n,
count_trigger,
count_inc,
count_dec,
reg_sel,
reg_wr_data,
79,7 → 80,8
// ------------------- Clock and Reset Signals ------------------------
input sys_clk;
input s_reset_n;
input count_trigger;
input count_inc; // Counter Increment
input count_dec; // counter decrement, assuption does not under flow
input reg_sel;
input reg_wr;
input [CWD-1:0] reg_wr_data;
103,14 → 105,20
reg_trig_cntr <= reg_wr_data;
end
else begin
if (count_trigger)
if (count_inc && count_dec)
reg_trig_cntr <= reg_trig_cntr;
else if (count_inc)
reg_trig_cntr <= reg_trig_cntr + 1'b1;
else if (count_dec)
reg_trig_cntr <= reg_trig_cntr - 1'b1;
else
reg_trig_cntr <= reg_trig_cntr;
end
end
end
assign cntr_intr = ((reg_trig_cntr + 1) == 'h0 && count_trigger) ;
end
// only increment overflow is assumed
// decrement underflow is not handled
assign cntr_intr = ((reg_trig_cntr + 1) == 'h0 && count_inc) ;
 
assign cntrout = reg_trig_cntr;
 
/turbo8051/trunk/rtl/gmac/mac/g_mac_core.v
104,8 → 104,21
// configuration output
cf_mac_sa,
cfg_ip_sa,
cfg_mac_filter
cfg_mac_filter,
rx_buf_base_addr,
tx_buf_base_addr,
 
rx_buf_qbase_addr,
tx_buf_qbase_addr,
 
tx_qcnt_inc,
tx_qcnt_dec,
tx_qcnt,
 
rx_qcnt_inc,
rx_qcnt_dec,
rx_qcnt
 
);
parameter mac_mdio_en = 1'b1;
191,6 → 204,20
output [47:0] cf_mac_sa;
output [31:0] cfg_ip_sa;
output [31:0] cfg_mac_filter;
output [3:0] rx_buf_base_addr;
output [3:0] tx_buf_base_addr;
 
output [9:0] rx_buf_qbase_addr; // Rx Q Base Address
output [9:0] tx_buf_qbase_addr; // Tx Q Base Address
 
input tx_qcnt_inc;
input tx_qcnt_dec;
output [3:0] tx_qcnt;
 
input rx_qcnt_inc;
input rx_qcnt_dec;
output [3:0] rx_qcnt;
 
//-----------------------------------------------------------------------
// RX-Clock Domain Status Signal
//-----------------------------------------------------------------------
517,7 → 544,23
.cf2md_regad (cf2md_regad),
.cf2md_phyad (cf2md_phyad),
.cf2md_op (cf2md_op),
.cf2md_go (cf2md_go)
.cf2md_go (cf2md_go),
 
.rx_buf_base_addr (rx_buf_base_addr),
.tx_buf_base_addr (tx_buf_base_addr),
 
.rx_buf_qbase_addr (rx_buf_qbase_addr),
.tx_buf_qbase_addr (tx_buf_qbase_addr),
 
.tx_qcnt_inc (tx_qcnt_inc),
.tx_qcnt_dec (tx_qcnt_dec),
.tx_qcnt (tx_qcnt),
 
.rx_qcnt_inc (rx_qcnt_inc),
.rx_qcnt_dec (rx_qcnt_dec),
.rx_qcnt (rx_qcnt)
 
 
);
 
g_mii_intf u_mii_intf(
/turbo8051/trunk/rtl/gmac/mac/g_cfg_mgmt.v
110,7 → 110,22
cf2md_regad,
cf2md_phyad,
cf2md_op,
cf2md_go);
cf2md_go,
 
rx_buf_base_addr,
tx_buf_base_addr,
rx_buf_qbase_addr,
tx_buf_qbase_addr,
 
tx_qcnt_inc,
tx_qcnt_dec,
tx_qcnt,
 
rx_qcnt_inc,
rx_qcnt_dec,
rx_qcnt
 
);
parameter mac_mdio_en = 1'b1;
 
119,63 → 134,76
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input reg_cs ;
input reg_wr ;
input [3:0] reg_addr ;
input [31:0] reg_wdata ;
input [3:0] reg_be ;
input reg_cs ;
input reg_wr ;
input [3:0] reg_addr ;
input [31:0] reg_wdata ;
input [3:0] reg_be ;
// Outputs
output [31:0] reg_rdata ;
output reg_ack ;
output [31:0] reg_rdata ;
output reg_ack ;
 
input rx_sts_vld ; // rx status valid indication, sync w.r.t app clk
input [7:0] rx_sts ; // rx status bits
input rx_sts_vld ; // rx status valid indication, sync w.r.t app clk
input [7:0] rx_sts ; // rx status bits
 
input tx_sts_vld ; // tx status valid indication, sync w.r.t app clk
input tx_sts ; // tx status bits
input tx_sts_vld ; // tx status valid indication, sync w.r.t app clk
input tx_sts ; // tx status bits
 
//List of Inputs
 
input app_clk ;
input app_reset_n ;
input md2cf_cmd_done ; // Read/Write MDIO completed
input md2cf_status ; // MDIO transfer error
input [15:0] md2cf_data ; // Data from PHY for a
// mdio read access
input app_clk ;
input app_reset_n ;
input md2cf_cmd_done ; // Read/Write MDIO completed
input md2cf_status ; // MDIO transfer error
input [15:0] md2cf_data ; // Data from PHY for a
// mdio read access
//List of Outputs
output cf2mi_rmii_en ; // Working in RMII when set to 1
output cf_mac_mode ; // mac mode set this to 1 for 100Mbs/10Mbs
output cf_chk_rx_dfl ; // Check for RX Deferal
output cf2mi_rmii_en ; // Working in RMII when set to 1
output cf_mac_mode ; // mac mode set this to 1 for 100Mbs/10Mbs
output cf_chk_rx_dfl ; // Check for RX Deferal
output [47:0] cf_mac_sa ;
output [31:0] cfg_ip_sa ;
output [31:0] cfg_mac_filter ;
output cf2tx_ch_en ; //enable the TX channel
output cf_silent_mode ; //PHY Inactive
output [7:0] cf2df_dfl_single ; //number of clk ticks for dfl
output [7:0] cf2df_dfl_single_rx ; //number of clk ticks for dfl
output cf2tx_ch_en ; //enable the TX channel
output cf_silent_mode ; //PHY Inactive
output [7:0] cf2df_dfl_single ; //number of clk ticks for dfl
output [7:0] cf2df_dfl_single_rx ; //number of clk ticks for dfl
output cf2tx_pad_enable ; //enable padding, < 64 bytes
output cf2tx_append_fcs; //append CRC for TX frames
output cf2rx_ch_en; //Enable RX channel
output cf2rx_strp_pad_en; //strip the padded bytes on RX frame
output cf2rx_snd_crc; //send FCS to application, else strip
//the FCS before sending to application
output cf2mi_loopback_en; // TX to RX loop back enable
output cf2rx_runt_pkt_en; //don't throw packets less than 64 bytes
output [15:0] cf2md_datain;
output [4:0] cf2md_regad;
output [4:0] cf2md_phyad;
output cf2md_op;
output cf2md_go;
output cf2tx_pad_enable ; //enable padding, < 64 bytes
output cf2tx_append_fcs ; //append CRC for TX frames
output cf2rx_ch_en ; //Enable RX channel
output cf2rx_strp_pad_en ; //strip the padded bytes on RX frame
output cf2rx_snd_crc ; //send FCS to application, else strip
//the FCS before sending to application
output cf2mi_loopback_en ; // TX to RX loop back enable
output cf2rx_runt_pkt_en ; //don't throw packets less than 64 bytes
output [15:0] cf2md_datain ;
output [4:0] cf2md_regad ;
output [4:0] cf2md_phyad ;
output cf2md_op ;
output cf2md_go ;
 
output [15:0] cf2rx_max_pkt_sz; //max rx packet size
output cf2tx_force_bad_fcs; //force bad fcs on tx
output [15:0] cf2rx_max_pkt_sz ; //max rx packet size
output cf2tx_force_bad_fcs ; //force bad fcs on tx
 
output cfg_uni_mac_mode_change_i;
 
output [3:0] rx_buf_base_addr; // Rx Data Buffer Base Address
output [3:0] tx_buf_base_addr; // Tx Data Buffer Base Address
output [9:0] rx_buf_qbase_addr; // Rx Q Base Address
output [9:0] tx_buf_qbase_addr; // Tx Q Base Address
 
input tx_qcnt_inc;
input tx_qcnt_dec;
output [3:0] tx_qcnt;
 
input rx_qcnt_inc;
input rx_qcnt_dec;
output [3:0] rx_qcnt;
 
// Wire assignments for output signals
wire [15:0] cf2md_datain;
198,8 → 226,7
// Wire and Reg assignments for local signals
reg int_md2cf_status;
wire [7:0] mac_mode_out;
wire [7:0] tx_cntrl_out_1, rx_cntrl_out_1;
wire [7:0] tx_cntrl_out_2, rx_cntrl_out_2;
wire [7:0] mac_cntrl_out_1, mac_cntrl_out_2;
wire [7:0] dfl_params_rx_out;
wire [7:0] dfl_params1_out;
wire [7:0] slottime_out_1;
370,65 → 397,66
// BIT[7] = Force TX FCS Error
 
generic_register #(8,0 ) tx_cntrl_reg_1 (
generic_register #(8,0 ) u_mac_cntrl_reg_1 (
.we ({8{sw_wr_en_0 &
wr_be[0] }} ),
.data_in (reg_wdata[7:0] ),
wr_be[0] }}),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (tx_cntrl_out_1[7:0] )
.data_out (mac_cntrl_out_1[7:0] )
);
 
generic_register #(8,0 ) tx_cntrl_reg_2 (
generic_register #(8,0 ) u_mac_cntrl_reg_2 (
.we ({8{sw_wr_en_0 &
wr_be[1] }} ),
.data_in (reg_wdata[15:8] ),
wr_be[1]}} ),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (tx_cntrl_out_2[7:0] )
.data_out (mac_cntrl_out_2[7:0] )
);
assign cf2tx_ch_en = tx_cntrl_out_1[0];
assign cf2tx_pad_enable = tx_cntrl_out_1[3];
assign cf2tx_append_fcs = tx_cntrl_out_1[4];
assign cf2tx_force_bad_fcs = tx_cntrl_out_1[7];
 
assign reg_0[15:0] = {tx_cntrl_out_2,tx_cntrl_out_1};
generic_register #(8,0 ) u_mac_cntrl_reg_3 (
.we ({8{sw_wr_en_0 & wr_be[2] }}),
.data_in (reg_wdata[3:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out ({tx_buf_base_addr[3:0],
rx_buf_base_addr[3:0]} )
);
 
//=========================================================================//
// RX_CNTRL_REGISTER 1 : Address Value 04H
 
// TX Control Register
assign cf2tx_ch_en = mac_cntrl_out_1[0];
assign cf2tx_pad_enable = mac_cntrl_out_1[3];
assign cf2tx_append_fcs = mac_cntrl_out_1[4];
assign cf2tx_force_bad_fcs = mac_cntrl_out_1[7];
 
// RX_CNTRL_REGISTER
// BIT[0] = Receive Channel Enable
// BIT[1] = Strip Padding from the Receive data
// BIT[2] = Send CRC along with data to the host
// BIT[4] = Check RX Deferral
// BIT[5] = Receive Address Check Enable
// BIT[6] = Receive Runt Packet
// BIT[7] = Broad Cast Rx Disable
// BIT[31:8] = Reserved
generic_register #(8,0 ) rx_cntrl_reg_1 (
.we ({8{sw_wr_en_1 &
wr_be[0] }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (rx_cntrl_out_1[7:0] )
);
assign cf2rx_ch_en = mac_cntrl_out_2[0];
assign cf2rx_strp_pad_en = mac_cntrl_out_2[1];
assign cf2rx_snd_crc = mac_cntrl_out_2[2];
assign cf_chk_rx_dfl = mac_cntrl_out_2[4];
assign cf2rx_runt_pkt_en = mac_cntrl_out_2[6];
 
assign cf2rx_ch_en = rx_cntrl_out_1[0];
assign cf2rx_strp_pad_en = rx_cntrl_out_1[1];
assign cf2rx_snd_crc = rx_cntrl_out_1[2];
assign cf_chk_rx_dfl = rx_cntrl_out_1[4];
assign cf2rx_runt_pkt_en = rx_cntrl_out_1[6];
assign reg_0[23:0] = {tx_buf_base_addr[3:0],
rx_buf_base_addr[3:0],
mac_cntrl_out_2[7:0],
mac_cntrl_out_1[7:0]};
 
 
assign reg_1[7:0] = {rx_cntrl_out_1};
//========================================================================//
// reg1 free
//========================================================================//
//TRANSMIT DEFFERAL CONTROL REGISTER: Address value 08H
//BIT[7:0] = Defferal TX
//BIT[15:8] = Defferal RX
435,8 → 463,8
 
generic_register #(8,0 ) dfl_params1_en_reg (
.we ({8{sw_wr_en_2 &
wr_be[0] }} ),
.data_in (reg_wdata[7:0] ),
wr_be[0] }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
449,7 → 477,7
generic_register #(8,0 ) dfl_params_rx_en_reg (
.we ({8{sw_wr_en_2 &
wr_be[1] }} ),
.data_in (reg_wdata[15:8] ),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
473,7 → 501,7
generic_register #(8,0 ) mac_mode_reg (
.we ({8{sw_wr_en_3 & wr_be[0]}}),
.data_in (reg_wdata[7:0] ),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
499,8 → 527,8
 
generic_register #(8,0 ) mdio_cmd_reg_1 (
.we ({8{sw_wr_en_4 &
wr_be[0] }} ),
.data_in (reg_wdata[7:0] ),
wr_be[0]}} ),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
510,8 → 538,8
 
generic_register #(8,0 ) mdio_cmd_reg_2 (
.we ({8{sw_wr_en_4 &
wr_be[1] }} ),
.data_in (reg_wdata[15:8] ),
wr_be[1]}} ),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
521,8 → 549,8
 
generic_register #(8,0 ) mdio_cmd_reg_3 (
.we ({8{sw_wr_en_4 &
wr_be[2] }} ),
.data_in (reg_wdata[23:16] ),
wr_be[2]}} ),
.data_in (reg_wdata[23:16] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
538,8 → 566,8
 
generic_register #(7,0 ) mdio_cmd_reg_4 (
.we ({7{sw_wr_en_4 &
wr_be[3] }} ),
.data_in (reg_wdata[30:24] ),
wr_be[3]}} ),
.data_in (reg_wdata[30:24] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
549,8 → 577,8
 
req_register #(0 ) u_mdio_req (
.cpu_we ({sw_wr_en_4 &
wr_be[3] } ),
.cpu_req (reg_wdata[31] ),
wr_be[3] } ),
.cpu_req (reg_wdata[31] ),
.hware_ack (mdio_cmd_done_sync ),
.reset_n (app_reset_n ),
.clk (app_clk ),
692,9 → 720,56
assign reg_8[15:0] = cf2rx_max_pkt_sz[15:0];
 
 
assign reg_9 = 0; // free
//========================================================================//
//MAC max packet size Register 20
 
generic_register #(2,0 ) m_rx_qbase_addr_1 (
.we ({8{sw_wr_en_9 & wr_be[0] }}),
.data_in (reg_wdata[7:6] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (rx_buf_qbase_addr[1:0] )
);
 
generic_register #(8,0 ) m_rx_qbase_addr_2 (
.we ({8{sw_wr_en_9 & wr_be[1] }}),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (rx_buf_qbase_addr[9:2] )
);
 
 
generic_register #(2,0 ) m_tx_qbase_addr_1 (
.we ({8{sw_wr_en_9 & wr_be[2] }}),
.data_in (reg_wdata[23:22] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (tx_buf_qbase_addr[1:0] )
);
 
generic_register #(8,0 ) m_tx_qbase_addr_2 (
.we ({8{sw_wr_en_9 & wr_be[3] }}),
.data_in (reg_wdata[31:24] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (tx_buf_qbase_addr[9:2] )
);
 
 
assign reg_9[15:0] = {rx_buf_qbase_addr[9:0],6'h0};
assign reg_9[31:16] = {tx_buf_qbase_addr[9:0],6'h0};
 
 
 
//-----------------------------------------------------------------------
// RX-Clock Static Counter Status Signal
//-----------------------------------------------------------------------
709,7 → 784,8
. sys_clk (app_clk ),
. s_reset_n (app_reset_n ),
. count_trigger (rx_good_frm_trig),
. count_inc (rx_good_frm_trig),
. count_dec (1'b0 ),
. reg_sel (sw_wr_en_10 ),
. reg_wr_data (reg_wdata[15:0] ),
724,14 → 800,15
. sys_clk (app_clk ),
. s_reset_n (app_reset_n ),
. count_trigger (rx_bad_frm_trig ),
. count_inc (rx_bad_frm_trig ),
. count_dec (1'b0 ),
. reg_sel (sw_wr_en_11 ),
. reg_wr_data (reg_wdata[15:0] ),
. reg_sel (sw_wr_en_10 ),
. reg_wr_data (reg_wdata[31:16] ),
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
 
. cntr_intr ( ),
. cntrout (reg_11[15:0] )
. cntrout (reg_10[31:16] )
);
 
 
742,18 → 819,54
. sys_clk (app_clk ),
. s_reset_n (app_reset_n ),
. count_trigger (tx_good_frm_trig ),
. count_inc (tx_good_frm_trig ),
. count_dec (1'b0 ),
. reg_sel (sw_wr_en_12 ),
. reg_sel (sw_wr_en_11 ),
. reg_wr_data (reg_wdata[15:0] ),
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
 
. cntr_intr ( ),
. cntrout (reg_12[15:0] )
. cntrout (reg_11[15:0] )
);
 
// reg_13 is free
// reg_12 & reg_13 is free
 
stat_counter #(4) u_rx_qcnt (
// Clock and Reset Signals
. sys_clk (app_clk ),
. s_reset_n (app_reset_n ),
. count_inc (rx_qcnt_inc ),
. count_dec (rx_qcnt_dec ),
. reg_sel (sw_wr_en_12 ),
. reg_wr_data (reg_wdata[3:0] ),
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
 
. cntr_intr ( ),
. cntrout (rx_qcnt )
);
 
stat_counter #(4) u_tx_qcnt (
// Clock and Reset Signals
. sys_clk (app_clk ),
. s_reset_n (app_reset_n ),
. count_inc (tx_qcnt_inc ),
. count_dec (tx_qcnt_dec ),
. reg_sel (sw_wr_en_12 ),
. reg_wr_data (reg_wdata[11:8] ),
. reg_wr (wr_be[2] ), // Byte write not supported for cntr
 
. cntr_intr ( ),
. cntrout (tx_qcnt )
);
 
assign reg_12[7:0] = {4'h0,rx_qcnt[3:0]};
assign reg_12[15:8] = {4'h0,tx_qcnt[3:0]};
 
generic_intr_stat_reg #(9) u_intr_stat (
//inputs
. clk (app_clk ),
/turbo8051/trunk/rtl/gmac/top/g_mac_top.v
59,6 → 59,7
// Application RX FIFO Interface
app_txfifo_wren_i,
app_txfifo_wrdata_i,
app_txfifo_addr,
app_txfifo_full_o,
app_txfifo_afull_o,
app_txfifo_space_o,
69,7 → 70,13
app_rxfifo_aempty_o,
app_rxfifo_cnt_o,
app_rxfifo_rdata_o,
app_rxfifo_addr,
 
app_rx_desc_req ,
app_rx_desc_ack ,
app_rx_desc_discard ,
app_rx_desc_data ,
 
// Conntrol Bus Sync with Application Clock
reg_cs,
reg_wr,
101,7 → 108,20
mdio_clk,
mdio_in,
mdio_out_en,
mdio_out
mdio_out,
 
// QCounter
rx_buf_qbase_addr,
tx_buf_qbase_addr,
 
tx_qcnt_inc,
tx_qcnt_dec,
rx_qcnt_inc,
rx_qcnt_dec,
 
tx_qcnt,
rx_qcnt
 
);
 
parameter W = 8'd9;
135,6 → 155,8
// Application RX FIFO Interface
input app_txfifo_wren_i;
input [8:0] app_txfifo_wrdata_i;
output [15:0] app_txfifo_addr;
 
output app_txfifo_full_o;
output app_txfifo_afull_o;
output [AW:0] app_txfifo_space_o;
145,7 → 167,14
output app_rxfifo_aempty_o;
output [AW:0] app_rxfifo_cnt_o;
output [8:0] app_rxfifo_rdata_o;
output [15:0] app_rxfifo_addr;
 
// descriptor interface
output app_rx_desc_req ; // descriptor request
input app_rx_desc_ack ; // descriptor ack
output app_rx_desc_discard ; // descriptor discard
output [31:0] app_rx_desc_data ; // descriptor data
 
// Conntrol Bus Sync with Application Clock
//---------------------------------
// Reg Bus Interface Signal
186,6 → 215,20
output mdio_out_en;
output mdio_out;
 
//--------------------------------------
// QCounter, Better to move to seperate global reg block
//-------------------------------------
output [9:0] rx_buf_qbase_addr; // Rx QBase Address
output [9:0] tx_buf_qbase_addr; // TX QBase Address
 
input tx_qcnt_inc; // Tx QCounter Increment indication
input tx_qcnt_dec; // Tx QCounter Decrement indication
input rx_qcnt_inc; // Rx QCounter Increment indication
input rx_qcnt_dec; // Rx QCounter Decrement indication
 
output [3:0] tx_qcnt ;
output [3:0] rx_qcnt ;
 
//---------------------
// RX FIFO Interface Signal
wire clr_rx_error_from_rx_fsm_o;
211,14 → 254,49
wire [47:0] cf_mac_sa;
wire [31:0] cfg_ip_sa;
wire [31:0] cfg_mac_filter;
wire [3:0] tx_buf_base_addr;
wire [3:0] rx_buf_base_addr;
wire [11:0] g_rx_pkt_len;
wire [15:0] pkt_status;
wire app_rxfifo_empty;
wire g_rx_block_rxrd;
 
assign app_rxfifo_empty_o = app_rxfifo_empty | g_rx_block_rxrd;
g_dpath_ctrl m_g_dpath_ctrl (
.rst_n ( s_reset_n ),
.clk ( app_clk ),
 
.rx_buf_base_addr (rx_buf_base_addr ),
.tx_buf_base_addr (tx_buf_base_addr ),
 
// gmac core to memory write interface
.g_rx_mem_rd ( app_rxfifo_rden_i ),
.g_rx_mem_eop ( app_rxfifo_rdata_o[8] ),
.g_rx_mem_addr ( app_rxfifo_addr ),
.g_rx_block_rxrd ( g_rx_block_rxrd ),
 
// descr handshake
.g_rx_desc_req (app_rx_desc_req ),
.g_rx_desc_discard (app_rx_desc_discard ),
.g_rx_desc_data (app_rx_desc_data ),
.g_rx_desc_ack (app_rx_desc_ack ),
 
 
.g_rx_pkt_done (g_rx_pkt_done ),
.g_rx_pkt_len (g_rx_pkt_len ),
.g_rx_pkt_status (g_rx_pkt_status ),
.g_rx_pkt_drop (g_rx_pkt_drop )
 
 
);
 
 
g_eth_parser u_eth_parser (
.s_reset_n (app_reset_n),
.app_clk (app_clk),
 
// Configuration
.cfg_filters (cfg_filters),
.cfg_filters (cfg_mac_filter),
.cfg_mac_sa (cf_mac_sa),
.cfg_ip_sa (cfg_ip_sa),
 
228,10 → 306,10
.data (app_rxfifo_rdata_o[7:0]),
// output status
.pkt_done (),
.pkt_len (),
.pkt_status (),
.pkt_drop_ind (),
.pkt_done (g_rx_pkt_done ),
.pkt_len (g_rx_pkt_len ),
.pkt_status (g_rx_pkt_status ),
.pkt_drop_ind (g_rx_pkt_drop ),
.pkt_drop_reason ()
);
 
302,8 → 380,22
 
.cf_mac_sa (cf_mac_sa),
.cfg_ip_sa (cfg_ip_sa),
.cfg_mac_filter (cfg_mac_filter)
.cfg_mac_filter (cfg_mac_filter),
 
.rx_buf_base_addr (rx_buf_base_addr),
.tx_buf_base_addr (tx_buf_base_addr),
 
.rx_buf_qbase_addr (rx_buf_qbase_addr),
.tx_buf_qbase_addr (tx_buf_qbase_addr),
 
.tx_qcnt_inc (tx_qcnt_inc),
.tx_qcnt_dec (tx_qcnt_dec),
.tx_qcnt (tx_qcnt),
 
.rx_qcnt_inc (rx_qcnt_inc),
.rx_qcnt_dec (rx_qcnt_dec),
.rx_qcnt (rx_qcnt)
 
);
 
assign tx_fifo_rdy = (tx_fifo_aval > 8) ; // Dinesh-A Change it to config
338,7 → 430,7
.rd_clk (app_clk),
.rd_reset_n (app_reset_n),
.rd_en (app_rxfifo_rden_i),
.empty (app_rxfifo_empty_o), // sync'ed to rd_clk
.empty (app_rxfifo_empty), // sync'ed to rd_clk
.aempty (app_rxfifo_aempty_o), // sync'ed to rd_clk
.rd_total_aval (app_rxfifo_cnt_o),
.rd_data (app_rxfifo_rdata_o)
/turbo8051/trunk/rtl/gmac/ctrl/eth_parser.v
101,7 → 101,7
//-----------------------------
output [11:0] pkt_len; // Packet Length
output pkt_done; // Packet Processing done indication
output [6:0] pkt_status; // packet processing status
output [15:0] pkt_status; // packet processing status
// [1:0] - MAC-DA
// 2'b00 - Broadcast frame
// 2'b01 - Multicast frame
133,12 → 133,15
reg [11:0] bcnt ; // Byte counter
reg [11:0] pkt_len ; // packet length
reg pkt_done ; // packet complete indication + Packet Status Valid
reg pkt_drop_ind ;
 
 
always @(s_reset_n or posedge app_clk) begin
if(s_reset_n == 1'b0) begin
bcnt <= 0;
pkt_len <= 0;
pkt_done <= 0;
bcnt <= 0;
pkt_len <= 0;
pkt_done <= 0;
pkt_drop_ind <= 0;
end
else begin
if(dval) begin
168,7 → 171,7
reg udpf ; // frame is udp
reg ip_sa_match ; // ip4 sa matches to local IP Address
reg ip_da_match ; // ip4 da matches to local IP Address
reg[6:0] pkt_status ; // Packet Status
reg[15:0] pkt_status ; // Packet Status
 
always @(s_reset_n or posedge app_clk) begin
if(s_reset_n == 1'b0) begin
/turbo8051/trunk/rtl/core/core.v
68,6 → 68,7
wb_xram_ack ,
wb_xram_err ,
wb_xram_wr ,
wb_xram_be ,
wb_xram_rdata ,
wb_xram_wdata ,
163,8 → 164,9
input wb_xram_ack ; // data-ram acknowlage
output wb_xram_err ; // data-ram error
output wb_xram_wr ; // data-ram error
input [7:0] wb_xram_rdata ; // ram data input
output [7:0] wb_xram_wdata ; // ram data input
output [3:0] wb_xram_be ; // Byte enable
input [31:0] wb_xram_rdata ; // ram data input
output [31:0] wb_xram_wdata ; // ram data input
 
output wb_xram_stb ; // data-ram strobe
output wb_xram_cyc ; // data-ram cycle
184,6 → 186,7
// MAC Related wire Decleration
//-----------------------------
wire [8:0] app_rxfifo_rddata_o ;
wire [31:0] app_rx_desc_data ;
wire mdio_out_en ;
wire mdio_out ;
wire gen_resetn ;
214,8 → 217,6
wire [31:0] reg_spi_rdata ;
wire reg_spi_ack ;
 
wire [31:0] wb_xram_wdata ; // ram data input
 
wire [3:0] wb_xrom_be ;
wire [3:0] wb_xram_be ;
 
247,8 → 248,11
wire [8:0] app_txfifo_wrdata_i;
wire [15:0] app_txfifo_addr;
wire [15:0] app_rxfifo_addr;
wire [15:0] app_txfifo_req_len;
wire [3:0] tx_qcnt ;
wire [3:0] rx_qcnt ;
 
wire tx_q_empty = (tx_qcnt == 0);
wire rx_q_empty = (rx_qcnt == 0);
 
assign reg_rdata = (reg_mac_ack) ? reg_mac_rdata :
(reg_uart_ack) ? reg_uart_rdata :
260,13 → 264,20
assign reset_out_n = gen_resetn;
 
 
assign wb_xram_adr[15] = 0;
assign wb_xram_adr[1:0] = (wb_xram_be == 4'b0001) ? 2'b00 :
(wb_xram_be == 4'b0010) ? 2'b01 :
(wb_xram_be == 4'b0100) ? 2'b10 : 2'b11 ;
 
assign wb_xram_adr[15] = 0;
assign wb_xram_adr[1:0] = 2'b00;
assign wb_xrom_adr[15:13] = 0;
 
wire [9:0] cfg_tx_buf_qbase_addr;
wire [9:0] cfg_rx_buf_qbase_addr;
 
// QCounter Inc/dec generation
 
wire tx_qcnt_inc = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack;
wire tx_qcnt_dec = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack;
wire rx_qcnt_inc = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack;
wire rx_qcnt_dec = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack;
 
//-------------------------------------------
// clock-gen instantiation
//-------------------------------------------
376,10 → 387,7
reg_mac_rdata,
reg_uart_rdata,
reg_spi_rdata,
{wb_xram_rdata,
wb_xram_rdata,
wb_xram_rdata,
wb_xram_rdata},
{wb_xram_rdata},
wb_xrom_rdata
}),
.wbd_adr_slave ({reg_mac_addr,
448,78 → 456,77
// Application RX FIFO Interface
.app_txfifo_wren_i (app_txfifo_wren_i ),
.app_txfifo_wrdata_i (app_txfifo_wrdata_i ),
.app_txfifo_addr (app_txfifo_addr ),
.app_txfifo_full_o (app_txfifo_full_o ),
.app_txfifo_afull_o (app_txfifo_afull_o ),
.app_txfifo_space_o ( ),
.app_txfifo_space_o ( ),
 
// Application TX FIFO Interface
.app_rxfifo_rden_i (app_rxfifo_rden_i ),
.app_rxfifo_empty_o (app_rxfifo_empty_o ),
.app_rxfifo_aempty_o (app_rxfifo_aempty_o ),
.app_rxfifo_cnt_o ( ),
.app_rxfifo_rdata_o (app_rxfifo_rddata_o ),
.app_rxfifo_empty_o (app_rxfifo_empty_o ),
.app_rxfifo_aempty_o (app_rxfifo_aempty_o ),
.app_rxfifo_cnt_o ( ),
.app_rxfifo_rdata_o (app_rxfifo_rddata_o ),
.app_rxfifo_addr (app_rxfifo_addr ),
 
.app_rx_desc_req (app_rx_desc_req ),
.app_rx_desc_ack (app_rx_desc_ack ),
.app_rx_desc_discard (app_rx_desc_discard ),
.app_rx_desc_data (app_rx_desc_data ),
 
// Line Side Interface TX Path
.phy_tx_en (phy_tx_en ),
.phy_tx_er ( ),
.phy_txd (phy_txd ),
.phy_tx_clk (phy_tx_clk ),
.phy_tx_en (phy_tx_en ),
.phy_tx_er ( ),
.phy_txd (phy_txd ),
.phy_tx_clk (phy_tx_clk ),
 
// Line Side Interface RX Path
.phy_rx_clk (phy_rx_clk ),
.phy_rx_er (1'b0 ),
.phy_rx_dv (phy_rx_dv ),
.phy_rxd (phy_rxd ),
.phy_crs (1'b0 ),
.phy_rx_clk (phy_rx_clk ),
.phy_rx_er (1'b0 ),
.phy_rx_dv (phy_rx_dv ),
.phy_rxd (phy_rxd ),
.phy_crs (1'b0 ),
 
//MDIO interface
.mdio_clk (MDC ),
.mdio_in (MDIO ),
.mdio_out_en (mdio_out_en ),
.mdio_out (mdio_out )
);
.mdio_clk (MDC ),
.mdio_in (MDIO ),
.mdio_out_en (mdio_out_en ),
.mdio_out (mdio_out ),
 
// QCounter
.rx_buf_qbase_addr (cfg_rx_buf_qbase_addr),
.tx_buf_qbase_addr (cfg_tx_buf_qbase_addr),
 
assign MDIO = (mdio_out_en) ? mdio_out : 1'bz;
.tx_qcnt_inc (tx_qcnt_inc),
.tx_qcnt_dec (tx_qcnt_dec),
.rx_qcnt_inc (rx_qcnt_inc),
.rx_qcnt_dec (rx_qcnt_dec),
.tx_qcnt (tx_qcnt),
.rx_qcnt (rx_qcnt)
 
 
dpath_ctrl m_dpath_ctrl (
.rst_n ( gen_resetn ),
.clk ( app_clk ),
);
 
// gmac core to memory write interface
.g_rx_mem_rd ( app_rxfifo_rden_i ),
.g_rx_mem_eop ( app_rxfifo_rddata_o[8] ) ,
.g_rx_mem_addr ( app_rxfifo_addr ) ,
 
// Memory to gmac core interface
.g_tx_mem_wr ( app_txfifo_wren_i ),
.g_tx_mem_eop ( app_txfifo_wrdata_i[8] ),
.g_tx_mem_addr ( app_txfifo_addr ),
.g_tx_mem_req ( app_txfifo_req ),
.g_tx_mem_req_length ( app_txfifo_req_len ),
.g_tx_mem_ack ( app_txfifo_ack )
assign MDIO = (mdio_out_en) ? mdio_out : 1'bz;
 
);
 
 
wb_rd_mem2mem #(32,4,13,4) u_wb_gmac_tx (
 
.rst_n ( gen_resetn ),
.clk ( app_clk ),
.rst_n ( gen_resetn ),
.clk ( app_clk ),
 
// descriptor handshake
.cfg_desc_baddr (cfg_tx_buf_qbase_addr),
.desc_q_empty (tx_q_empty ),
 
// Master Interface Signal
.mem_req ( app_txfifo_req ),
.mem_txfr ( app_txfifo_req_len ) ,
.mem_ack ( app_txfifo_ack ),
.mem_taddr ( 1 ),
.mem_addr ( app_txfifo_addr ),
.mem_full (app_txfifo_full_o ),
.mem_afull (app_txfifo_afull_o ),
.mem_wr (app_txfifo_wren_i ),
.mem_din (app_txfifo_wrdata_i[7:0] ),
.mem_din (app_txfifo_wrdata_i ),
// Slave Interface Signal
.wbo_dout ( wbgt_dout ),
543,12 → 550,18
 
// Master Interface Signal
.mem_taddr ( 1 ),
.mem_addr ( app_rxfifo_addr ),
.mem_addr (app_rxfifo_addr ),
.mem_empty (app_rxfifo_empty_o ),
.mem_aempty (app_rxfifo_aempty_o ),
.mem_rd (app_rxfifo_rden_i ),
.mem_dout (app_rxfifo_rddata_o[7:0]),
.mem_eop (app_rxfifo_rddata_o[8]),
.cfg_desc_baddr (cfg_rx_buf_qbase_addr ),
.desc_req (app_rx_desc_req ),
.desc_ack (app_rx_desc_ack ),
.desc_disccard (app_rx_desc_discard ),
.desc_data (app_rx_desc_data ),
// Slave Interface Signal
.wbo_din ( wbgr_din ),
.wbo_taddr ( wbgr_taddr ),
/turbo8051/trunk/apps/webserver/enc28j60.c
144,7 → 144,7
// Function : enc28j60_mac_is_linked
// Description : return MAC link status.
//
//*******************************************************************************************
/*******************************************************************************************
/*
BYTE enc28j60_mac_is_linked(void)
{
/turbo8051/trunk/apps/webserver/main.c
112,167 → 112,6
}
//*****************************************************************************************
//
// Function : client_process
// Description : send temparature to web server, this option is disabled by default.
// YOU MUST install webserver and server script before enable this option,
// I recommented Apache webserver and PHP script.
// More detail about Apache and PHP installation please visit http://www.avrportal.com/
//
//*****************************************************************************************
void client_process ( void )
{
WORD dlength;
// you can change rx,tx buffer size in includes.h
BYTE rxtx_buffer[MAX_RXTX_BUFFER];
 
// wait for send temparature flag is set, this flag set by time_base function (menu.c)
if ( flag1.bits.send_temp == 0 )
return;
// AVR busy now and wait untill transfer data to web browser completed.
if ( flag1.bits.syn_is_received )
return;
// AVR sent temparature to web server but not found web server on port 80
//if ( flag1.bits.not_found_server )
// return;
// send SYN to initial connection
if ( flag1.bits.syn_is_sent == 0 )
{
// start arp
// server ip was not found on network
if ( arp_who_is ( rxtx_buffer, (BYTE*)&server_mac, (BYTE*)&server_ip ) == 0 )
{
flag1.bits.send_temp = 0;
return;
}
// send SYN packet to initial connection
tcp_send_packet (
rxtx_buffer,
80, // destination port
1200, // source port
TCP_FLAG_SYN_V, // flag
1, // (bool)maximum segment size
1, // (bool)clear sequence ack number
0, // 0=use old seq, seqack : 1=new seq,seqack no data : new seq,seqack with data
0, // tcp data length
(BYTE*)&server_mac, // server mac address
(BYTE*)&server_ip ); // server ip address
flag1.bits.syn_is_sent = 1;
}
// get new packet
dlength = enc28j60_packet_receive( (BYTE*)&rxtx_buffer, MAX_RXTX_BUFFER );
// no new packet incoming
if ( dlength == 0 )
{
// timeout occured, when SYN has been sent but no response from web server
// reset send_temp and syn_is_sent flags
if ( flag1.bits.send_temp_timeout )
{
flag1.bits.send_temp_timeout = 0;
flag1.bits.send_temp = 0;
flag1.bits.syn_is_sent = 0;
}
return;
}
// check ip packet send to avr or not?
// accept ip packet only
if ( ip_packet_is_ip ( (BYTE*)&rxtx_buffer ) == 0 )
{
return;
}
 
// check SYNACK flag, after AVR send SYN server response by send SYNACK to AVR
if ( rxtx_buffer [ TCP_FLAGS_P ] == ( TCP_FLAG_SYN_V | TCP_FLAG_ACK_V ) )
{
// send ACK to answer SYNACK
tcp_send_packet (
(BYTE*)&rxtx_buffer,
80, // destination port
1200, // source port
TCP_FLAG_ACK_V, // flag
0, // (bool)maximum segment size
0, // (bool)clear sequence ack number
1, // 0=use old seq, seqack : 1=new seq,seqack no data : >1 new seq,seqack with data
0, // tcp data length
(BYTE*)&server_mac, // server mac address
(BYTE*)&server_ip ); // server ip address
// setup http request to server
dlength = http_put_request( (BYTE*)&rxtx_buffer );
// send http request packet
// send packet with PSHACK
tcp_send_packet (
(BYTE*)&rxtx_buffer,
80, // destination port
1200, // source port
TCP_FLAG_ACK_V | TCP_FLAG_PSH_V, // flag
0, // (bool)maximum segment size
0, // (bool)clear sequence ack number
0, // 0=use old seq, seqack : 1=new seq,seqack no data : >1 new seq,seqack with data
dlength, // tcp data length
(BYTE*)&server_mac, // server mac address
(BYTE*)&server_ip ); // server ip address
return;
}
// after AVR send http request to server, server response by send data with PSHACK to AVR
// AVR answer by send ACK and FINACK to server
if ( rxtx_buffer [ TCP_FLAGS_P ] == (TCP_FLAG_ACK_V|TCP_FLAG_PSH_V) )
{
dlength = tcp_get_dlength( (BYTE*)&rxtx_buffer );
 
// send ACK to answer PSHACK from server
tcp_send_packet (
(BYTE*)&rxtx_buffer,
80, // destination port
1200, // source port
TCP_FLAG_ACK_V, // flag
0, // (bool)maximum segment size
0, // (bool)clear sequence ack number
dlength, // 0=use old seq, seqack : 1=new seq,seqack no data : >1 new seq,seqack with data
0, // tcp data length
(BYTE*)&server_mac, // server mac address
(BYTE*)&server_ip ); // server ip address
// send finack to disconnect from web server
tcp_send_packet (
(BYTE*)&rxtx_buffer,
80, // destination port
1200, // source port
TCP_FLAG_FIN_V|TCP_FLAG_ACK_V, // flag
0, // (bool)maximum segment size
0, // (bool)clear sequence ack number
0, // (bool)calculate new seq and seqack number
0, // tcp data length
(BYTE*)&server_mac, // server mac address
(BYTE*)&server_ip ); // server ip address
return;
//menu_flag.bits.send_temp = 0;
//send_syn = 0;
}
// answer FINACK from web server by send ACK to web server
if ( rxtx_buffer [ TCP_FLAGS_P ] == (TCP_FLAG_FIN_V|TCP_FLAG_ACK_V) )
{
// send ACK with seqack = 1
tcp_send_packet (
(BYTE*)&rxtx_buffer,
80, // destination port
1200, // source port
TCP_FLAG_ACK_V, // flag
0, // (bool)maximum segment size
0, // (bool)clear sequence ack number
1, // 0=use old seq, seqack : 1=new seq,seqack no data : >1 new seq,seqack with data
0, // tcp data length
(BYTE*)&server_mac, // server mac address
(BYTE*)&server_ip ); // server ip address
// temparature has been sent
// and wait for next schedule to send temparature
flag1.bits.send_temp = 0;
flag1.bits.syn_is_sent = 0;
}
}
//*****************************************************************************************
//
// Function : main
// Description : main program,
//
345,7 → 184,7
 
// send temparature to web server unsing http protocol
// disable by default.
client_process ();
//client_process ();
 
// lcd user interface menu
// setup IP address, countdown timer
/turbo8051/trunk/apps/webserver/Makefile
13,9 → 13,9
#main.rel: main.c
# sdcc $(SDCCFLAGS) -c $<
 
all: turbo8051.hex
all: main.hex
 
turbo8051.hex :: $(MODULES)
main.hex : $(MODULES)
sdcc $(SDCCFLAGS) $(ASLINKFLAGS) $(MODULES)
packihx main.ihx > turbo8051.hex
 
/turbo8051/trunk/verif/model/oc8051_xram.v
57,7 → 57,7
// synopsys translate_on
 
 
module oc8051_xram (clk, rst, wr, addr, data_in, data_out, ack, stb);
module oc8051_xram (clk, rst, wr, be, addr, data_in, data_out, ack, stb);
//
// external data ram for simulation. part of oc8051_tb
// it's tehnology dependent
75,13 → 75,14
 
 
input clk, wr, stb, rst;
input [7:0] data_in;
input [3:0] be; // byte enable
input [31:0] data_in;
input [15:0] addr;
output [7:0] data_out;
output [31:0] data_out;
output ack;
 
reg ackw, ackr;
reg [7:0] data_out;
reg [31:0] data_out;
reg [2:0] cnt;
 
//
99,7 → 100,10
if (rst)
ackw <= #1 1'b0;
else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
buff[addr] <= #1 data_in;
if(be[0]) buff[addr] <= #1 data_in[7:0];
if(be[1]) buff[addr+1] <= #1 data_in[15:8];
if(be[2]) buff[addr+2] <= #1 data_in[23:16];
if(be[3]) buff[addr+3] <= #1 data_in[31:24];
ackw <= #1 1'b1;
end else ackw <= #1 1'b0;
end
108,7 → 112,7
if (rst)
ackr <= #1 1'b0;
else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
data_out <= #1 buff[addr];
data_out <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
ackr <= #1 1'b1;
end else begin
ackr <= #1 1'b0;
/turbo8051/trunk/verif/defs/tb_defines.v
20,3 → 20,18
`define TB_AGENTS_GMAC `TB_TOP.u_tb_eth
`define TB_AGENTS_UART `TB_TOP.tb_uart
 
 
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0100 -- MAC core
// 4'b0011 -- UART
// 4'b0010 -- SPI core
// 4'b0001 -- External RAM
// 4'b0000 -- External ROM
//--------------------------------------------------------------
`define ADDR_SPACE_MAC 4'b0100
`define ADDR_SPACE_UART 4'b0011
`define ADDR_SPACE_SPI 4'b0010
`define ADDR_SPACE_RAM 4'b0001
`define ADDR_SPACE_ROM 4'b0000
 
/turbo8051/trunk/verif/run/filelist_rtl.f
20,6 → 20,7
$TURBO8051_PROJ/rtl/gmac/crc32/g_rx_crc32.v
$TURBO8051_PROJ/rtl/gmac/crc32/g_tx_crc32.v
$TURBO8051_PROJ/rtl/lib/async_fifo.v
$TURBO8051_PROJ/rtl/lib/g_dpath_ctrl.v
 
//-------------------------------------
// SPI File List
46,7 → 47,6
$TURBO8051_PROJ/rtl/lib/wb_crossbar.v
$TURBO8051_PROJ/rtl/lib/wb_rd_mem2mem.v
$TURBO8051_PROJ/rtl/lib/wb_wr_mem2mem.v
$TURBO8051_PROJ/rtl/lib/dpath_ctrl.v
 
 
//------------------------------------
/turbo8051/trunk/verif/tb/tb_top.v
47,19 → 47,6
 
module tb_top;
 
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0100 -- MAC core
// 4'b0011 -- UART
// 4'b0010 -- SPI core
// 4'b0001 -- External RAM
// 4'b0000 -- External ROM
//--------------------------------------------------------------
`define ADDR_SPACE_MAC 4'b0100
`define ADDR_SPACE_UART 4'b0011
`define ADDR_SPACE_SPI 4'b0010
`define ADDR_SPACE_RAM 4'b0001
`define ADDR_SPACE_ROM 4'b0000
 
reg reset_n;
reg reset;
164,8 → 151,9
wire wb_xram_ack ; // data-ram acknowlage
wire wb_xram_err ; // data-ram error
wire wb_xram_wr ; // data-ram error
wire [7:0] wb_xram_rdata ; // ram data input
wire [7:0] wb_xram_wdata ; // ram data input
wire [3:0] wb_xram_be ; // data-ram error
wire [31:0] wb_xram_rdata ; // ram data input
wire [31:0] wb_xram_wdata ; // ram data input
 
wire wb_xram_stb ; // data-ram strobe
wire wb_xram_cyc ; // data-ram cycle
236,6 → 224,7
.wb_xram_ack (wb_xram_ack ),
.wb_xram_err (wb_xram_err ),
.wb_xram_wr (wb_xram_wr ),
.wb_xram_be (wb_xram_be ),
.wb_xram_rdata (wb_xram_rdata ),
.wb_xram_wdata (wb_xram_wdata ),
268,6 → 257,7
.clk (app_clk ),
.rst (!reset_n ),
.wr (wb_xram_wr ),
.be (wb_xram_be ),
.addr (wb_xram_adr ),
.data_in (wb_xram_wdata ),
.data_out (wb_xram_rdata ),
/turbo8051/trunk/verif/tb/tb_tasks.v
6,7 → 6,7
end
 
task cpu_read;
input [2:0] block_id; // 1/2/3 --> mac/spi/uart
input [2:0] block_id;
input [15:0] address;
output [31:0] read_data;
begin
14,6 → 14,7
if(block_id == 1) reg_id = `ADDR_SPACE_MAC;
if(block_id == 2) reg_id = `ADDR_SPACE_SPI;
if(block_id == 3) reg_id = `ADDR_SPACE_UART;
if(block_id == 4) reg_id = `ADDR_SPACE_RAM;
reg_cs = 1;
reg_wr = 0;
reg_be = 4'hF;
42,9 → 43,9
reg_addr = address;
reg_wdata = write_data;
@(posedge reg_ack);
reg_wr = 0;
@(posedge app_clk);
reg_cs = 0;
reg_wr = 0;
end
endtask
 
/turbo8051/trunk/verif/testcase/gmac_test1.v
1,14 → 1,34
task gmac_test1;
reg [31:0] read_data;
reg [3:0] desc_ptr;
reg [9:0] desc_rx_qbase;
reg [9:0] desc_tx_qbase;
reg [7:0] iFrmCnt;
 
//--------------------------
// Data Memory MAP
//-------------------------
// 0x0000 to 0x0FFF - 4K - Processor Data Memory
// 0x1000 to 0x1FFF - 4K - Gmac Rx Data Memory
// 0x2000 to 0x2FFF - 4K - Reserved for Rx
// 0x3000 to 0x3FFF - 4K - Gmac Tx Data Memory
// 0x4000 to 0x4FFF - 4K - Reserved for Tx
// 0x7000 to 0x703F - 64 - Rx Descriptor
// 0x7040 to 0x707F - 64 - Tx Descripto
 
events_log = $fopen("../test_log_files/test1_events.log");
tb_top.u_tb_eth.event_file = events_log;
 
desc_ptr = 0;
desc_rx_qbase = 10'h1C0;
desc_tx_qbase = 10'h1C1;
iFrmCnt = 0;
tb_top.u_tb_eth.init_port(3'b1, 3'b1, 1'b1, 0);
 
tb_top.cpu_write('h1,8'h0,8'h01); // tx-control
tb_top.cpu_write('h1,8'h4,8'h65); // Rx control
tb_top.cpu_write('h1,8'h0,{4'h1,4'h1,8'h45,8'h01}); // tx/rx-control
tb_top.cpu_write('h1,8'h8,{16'h0,8'd22,8'd22}); // Tx/Rx IFG
tb_top.cpu_write('h1,8'h24,{desc_tx_qbase,desc_ptr,2'b00,
desc_rx_qbase,desc_ptr,2'b00}); // Tx/Rx Descriptor
 
tb_top.u_tb_eth.set_flow_type(0);//L2 unicast
tb_top.u_tb_eth.set_L2_frame_size(1, 64, 84, 1); //, 1, 17, 33, 49, 64
25,6 → 45,20
tb_top.u_tb_eth.wait_for_event(3, 0);
tb_top.u_tb_eth.wait_for_event(3, 0);
end
begin
while(iFrmCnt != 10) begin
tb_top.cpu_read('h1,8'h30,read_data); // Tx/Rx Counter
if(read_data[3:0] != 0) begin // Check the Rx Q Counter
// Read the Receive Descriptor
tb_top.cpu_read('h4,{desc_rx_qbase,desc_ptr},read_data);
// Write the Tx Descriptor
tb_top.cpu_write('h4,{desc_tx_qbase,desc_ptr},read_data);
desc_ptr = desc_ptr+1;
iFrmCnt = iFrmCnt+1;
end
#1000;
end
end
join
 
#100000;

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