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Rev 49 → Rev 50

/trunk/rtl/verilog/uart_regs.v
62,6 → 62,15
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.26 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
288,7 → 297,7
 
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate);
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
 
 
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
364,20 → 373,6
msi_reset <= #1 1; // reset bits in Modem Status Register
end
 
/*
// threi_clear signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
threi_clear <= #1 0;
else
if (!lsr[`UART_LS_TFE] && (tf_count==0)) // reset clear flag when tx fifo clears
threi_clear <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_II)
threi_clear <= #1 1;
end
*/
 
//
// WRITES AND RESETS //
486,7 → 481,7
// Line Status Register
 
// activation conditions
assign lsr0 = (rf_count==0 && fifo_write); // data in receiver fifo available set condition
assign lsr0 = (rf_count==0 && rf_push); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
553,8 → 548,6
 
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
wire tx_fifo_write;
assign tx_fifo_write = (wb_we_i && ~dlab && wb_addr_i==`UART_REG_TR);
 
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5_d <= #1 1;
562,7 → 555,7
 
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= #1 1;
else lsr5r <= #1 (tx_fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
 
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
573,7 → 566,7
 
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6r <= #1 1;
else lsr6r <= #1 (tx_fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
 
// lsr bit 7 (error in fifo)
reg lsr7_d;
/trunk/rtl/verilog/uart_top.v
64,6 → 64,15
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.15 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.14 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
160,6 → 169,7
wire [7:0] wb_dat8_o; // 8-bit internal data output
wire [31:0] wb_dat32_o; // debug interface 32-bit output
wire [3:0] wb_sel_i; // WISHBONE select signal
wire [uart_addr_width-1:0] wb_adr_int;
wire we_o; // Write enable for registers
wire re_o; // Read enable for registers
//
197,6 → 207,8
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
214,6 → 226,8
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
223,7 → 237,7
uart_regs regs(
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_addr_i( wb_adr_i ),
.wb_addr_i( wb_adr_int ),
.wb_dat_i( wb_dat8_i ),
.wb_dat_o( wb_dat8_o ),
.wb_we_i( we_o ),
260,7 → 274,7
// Inputs
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wb_adr_i[`UART_ADDR_WIDTH-1:0]),
.wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
.re_o (re_o),
.ier (ier[3:0]),
.iir (iir[3:0]),
/trunk/rtl/verilog/uart_receiver.v
63,6 → 63,15
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.17 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
136,7 → 145,7
`include "uart_defines.v"
 
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate);
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
 
input clk;
input wb_rst_i;
154,6 → 163,7
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push;
 
reg [3:0] rstate;
reg [3:0] rcounter16;
/trunk/rtl/verilog/uart_wb.v
64,6 → 64,15
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
102,10 → 111,11
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "uart_defines.v"
module uart_wb (clk, wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
we_o, re_o // Write and read enable output for the core
);
 
117,17 → 127,23
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line
 
`ifdef DATA_BUS_WIDTH_8
input [7:0] wb_dat_i; //input WISHBONE bus
output [7:0] wb_dat_o;
reg [7:0] wb_dat_o;
wire [7:0] wb_dat_i;
reg [7:0] wb_dat_is;
`else // for 32 data bus mode
input [31:0] wb_dat_i; //input WISHBONE bus
output [31:0] wb_dat_o;
reg [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
`endif
reg [31:0] wb_dat_is;
`endif // !`ifdef DATA_BUS_WIDTH_8
 
output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0] wb_dat8_i;
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
139,16 → 155,69
reg wb_ack_o;
reg [7:0] wb_dat8_i;
wire [7:0] wb_dat8_o;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
reg [`UART_ADDR_WIDTH-1:0] wb_adr_is;
reg wb_we_is;
reg wb_cyc_is;
reg wb_stb_is;
reg [3:0] wb_sel_is;
wire [3:0] wb_sel_i;
reg wb_ack; // wb_ack is sampled to make 2 clock wait state between transfers
reg wre ;// timing control signal for write or read enable
 
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
// wb_ack_o FSM
reg [1:0] wbstate;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_ack_o <= #1 1'b0;
else
wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
wbstate <= #1 0;
end else
case (wbstate)
0: begin
if (wb_stb_is & wb_cyc_is) begin
wre <= #1 0;
wbstate <= #1 1;
wb_ack_o <= #1 1;
end else begin
wre <= #1 1;
wb_ack_o <= #1 0;
end
end
1: begin
wb_ack_o <= #1 0;
wbstate <= #1 2;
wre <= #1 0;
end
2,3: begin
wb_ack_o <= #1 0;
wbstate <= #1 0;
wre <= #1 0;
end
endcase
 
assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers
assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
 
// Sample input signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_adr_is <= #1 0;
wb_we_is <= #1 0;
wb_cyc_is <= #1 0;
wb_stb_is <= #1 0;
wb_dat_is <= #1 0;
wb_sel_is <= #1 0;
end else begin
wb_adr_is <= #1 wb_adr_i;
wb_we_is <= #1 wb_we_i;
wb_cyc_is <= #1 wb_cyc_i;
wb_stb_is <= #1 wb_stb_i;
wb_dat_is <= #1 wb_dat_i;
wb_sel_is <= #1 wb_sel_i;
end
 
assign wb_adr_int = wb_adr_is;
 
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
156,8 → 225,8
else
wb_dat_o <= #1 wb_dat8_o;
 
always @(wb_dat_i)
wb_dat8_i = wb_dat_i;
always @(wb_dat_is)
wb_dat8_i = wb_dat_is;
 
`else // 32-bit bus
// put output to the correct byte in 32 bits using select line
165,7 → 234,7
if (wb_rst_i)
wb_dat_o <= #1 0;
else if (re_o)
case (wb_sel_i)
case (wb_sel_is)
4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
172,18 → 241,15
4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
default: wb_dat_o <= #1 0;
// later add here selects for 16 and 32 bits
endcase // case(wb_sel_i)
 
// handle input (this will add a little timing overhead on input but it should asynchronous
// or another one clock delay will be introduced)
always @(wb_sel_i or wb_dat_i)
case (wb_sel_i)
4'b0001 : wb_dat8_i = wb_dat_i[7:0];
4'b0010 : wb_dat8_i = wb_dat_i[15:8];
4'b0100 : wb_dat8_i = wb_dat_i[23:16];
4'b1000 : wb_dat8_i = wb_dat_i[31:24];
default : wb_dat8_i = wb_dat_i[7:0];
always @(wb_sel_is or wb_dat_is)
case (wb_sel_is)
4'b0001 : wb_dat8_i = wb_dat_is[7:0];
4'b0010 : wb_dat8_i = wb_dat_is[15:8];
4'b0100 : wb_dat8_i = wb_dat_is[23:16];
4'b1000 : wb_dat8_i = wb_dat_is[31:24];
default : wb_dat8_i = wb_dat_is[7:0];
endcase // case(wb_sel_i)
 
`endif // !`ifdef DATA_BUS_WIDTH_8
/trunk/sim/rtl_sim/bin/nc.scr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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