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/minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v
64,6 → 64,10
// Revision History |
// |
// |
// Revision 2.1 2009/08/23 16:41:00 fajardo |
// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY |
// This actually models appropriately the behavior of the FPGA internal RAMs |
// |
// Revision 2.0 2009/09/10 11:30:00 fajardo |
// Added tri-state buffering for altera output |
// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY |
209,7 → 213,7
// |
// RAM address register |
// |
always @(negedge clk or posedge rst) |
always @(posedge clk or posedge rst) |
if (rst) |
addr_reg <= #1 {aw{1'b0}}; |
else if (ce) |
218,7 → 222,7
// |
// RAM write |
// |
always @(negedge clk) |
always @(posedge clk) |
if (ce && we) |
mem[addr] <= #1 di; |
|
/minsoc/trunk/doc/minsoc.pdf
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/minsoc/trunk/doc/minsoc.odt
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