URL
https://opencores.org/ocsvn/salsa20/salsa20/trunk
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/salsa20/trunk/rtl/salsaa_mc.vhd
0,0 → 1,246
-- |
-- Copyright 2012 iQUBE research |
-- |
-- This file is part of Salsa20IpCore. |
-- |
-- Salsa20IpCore is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- Salsa20IpCore is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU Lesser General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with Salsa20IpCore. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- e-mail: lukasz.dzianach@iqube.es, info@iqube.es |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
|
entity salsaa_mc is |
port ( |
clk : in std_logic; |
reset : in std_logic; |
|
-- iface for user |
key : in std_logic_vector(255 downto 0); |
nonce : in std_logic_vector(63 downto 0); |
start : in std_logic; |
|
-- iface to salsaa_dm |
mc_data : out std_logic_vector(511 downto 0); |
mc_restart : in std_logic := '0'; |
mc_busy : out std_logic |
|
); |
end entity salsaa_mc; |
|
architecture rtl of salsaa_mc is |
|
type x_type is array(0 to 15) of std_logic_vector(31 downto 0); |
|
constant salsa_const_0 : std_logic_vector := x"61707865"; |
constant salsa_const_1 : std_logic_vector := x"3320646e"; |
constant salsa_const_2 : std_logic_vector := x"79622d32"; |
constant salsa_const_3 : std_logic_vector := x"6b206574"; |
|
constant st_rst : std_logic_vector := x"0"; |
constant st_read_in : std_logic_vector := x"1"; |
constant st_save_init : std_logic_vector := x"2"; |
constant st_perf_rnds : std_logic_vector := x"3"; |
constant st_sum_res : std_logic_vector := x"4"; |
constant st_calc_done : std_logic_vector := x"5"; |
|
constant max_calc_state : std_logic_vector (7 downto 0) := x"07"; |
constant max_rnds_state : std_logic_vector (7 downto 0) := x"09"; |
|
signal x : x_type; |
signal idx : std_logic_vector (63 downto 0); |
|
signal state : std_logic_vector (3 downto 0); |
signal calc_state : std_logic_vector (7 downto 0); |
signal rnds_state : std_logic_vector (7 downto 0); |
|
signal mc_data_buf : std_logic_vector(511 downto 0); |
|
begin |
|
mc_data <= mc_data_buf; |
|
main: process(clk) is |
begin |
if (clk'event and clk='1') then |
if (reset='1') then |
state <= st_rst; |
mc_busy <= '1'; |
else |
|
case state is |
|
when st_rst => |
if start = '1' then |
state <= st_read_in; |
end if; |
|
-- reseting the index (as new nonce can is being read) |
idx <= x"0000000000000000"; |
mc_busy <= '1'; |
|
when st_read_in => |
|
state <= st_save_init; |
|
mc_busy <= '1'; |
|
x(0) <= salsa_const_0; |
x(1) <= key(32 * 0 + 31 downto 32 * 0 + 0); |
x(2) <= key(32 * 1 + 31 downto 32 * 1 + 0); |
x(3) <= key(32 * 2 + 31 downto 32 * 2 + 0); |
x(4) <= key(32 * 3 + 31 downto 32 * 3 + 0); |
x(5) <= salsa_const_1; |
x(6) <= nonce(32 * 0 + 31 downto 32 * 0 + 0); |
x(7) <= nonce(32 * 1 + 31 downto 32 * 1 + 0); |
x(8) <= idx(32 * 0 + 31 downto 32 * 0 + 0); |
x(9) <= idx(32 * 1 + 31 downto 32 * 1 + 0); |
x(10) <= salsa_const_2; |
x(11) <= key(32 * 4 + 31 downto 32 * 4 + 0); |
x(12) <= key(32 * 5 + 31 downto 32 * 5 + 0); |
x(13) <= key(32 * 6 + 31 downto 32 * 6 + 0); |
x(14) <= key(32 * 7 + 31 downto 32 * 7 + 0); |
x(15) <= salsa_const_3; |
|
when st_save_init => |
|
-- prepare seq of runds |
state <= st_perf_rnds; |
calc_state <= x"00"; |
rnds_state <= x"00"; |
|
-- storing initial state of x |
mc_data_buf(32 * 00 + 31 downto 32 * 00 + 0) <= x(00); |
mc_data_buf(32 * 01 + 31 downto 32 * 01 + 0) <= x(01); |
mc_data_buf(32 * 02 + 31 downto 32 * 02 + 0) <= x(02); |
mc_data_buf(32 * 03 + 31 downto 32 * 03 + 0) <= x(03); |
mc_data_buf(32 * 04 + 31 downto 32 * 04 + 0) <= x(04); |
mc_data_buf(32 * 05 + 31 downto 32 * 05 + 0) <= x(05); |
mc_data_buf(32 * 06 + 31 downto 32 * 06 + 0) <= x(06); |
mc_data_buf(32 * 07 + 31 downto 32 * 07 + 0) <= x(07); |
mc_data_buf(32 * 08 + 31 downto 32 * 08 + 0) <= x(08); |
mc_data_buf(32 * 09 + 31 downto 32 * 09 + 0) <= x(09); |
mc_data_buf(32 * 10 + 31 downto 32 * 10 + 0) <= x(10); |
mc_data_buf(32 * 11 + 31 downto 32 * 11 + 0) <= x(11); |
mc_data_buf(32 * 12 + 31 downto 32 * 12 + 0) <= x(12); |
mc_data_buf(32 * 13 + 31 downto 32 * 13 + 0) <= x(13); |
mc_data_buf(32 * 14 + 31 downto 32 * 14 + 0) <= x(14); |
mc_data_buf(32 * 15 + 31 downto 32 * 15 + 0) <= x(15); |
|
when st_perf_rnds => |
calc_state <= calc_state + x"01"; |
if calc_state = max_calc_state then |
if rnds_state = max_rnds_state then |
state <= st_sum_res; |
else |
calc_state <= x"00"; |
rnds_state <= rnds_state + x"01"; |
end if; |
end if; |
|
-- processing goes here |
case calc_state is |
when x"00" => |
x(04) <= x(04) xor std_logic_vector( rotate_left(unsigned(x(12)+x(00)),7)); |
x(09) <= x(09) xor std_logic_vector( rotate_left(unsigned(x(01)+x(05)),7)); |
x(14) <= x(14) xor std_logic_vector( rotate_left(unsigned(x(06)+x(10)),7)); |
x(03) <= x(03) xor std_logic_vector( rotate_left(unsigned(x(11)+x(15)),7)); |
when x"01" => |
x(08) <= x(08) xor std_logic_vector( rotate_left(unsigned(x(00)+x(04)),9)); |
x(13) <= x(13) xor std_logic_vector( rotate_left(unsigned(x(05)+x(09)),9)); |
x(02) <= x(02) xor std_logic_vector( rotate_left(unsigned(x(10)+x(14)),9)); |
x(07) <= x(07) xor std_logic_vector( rotate_left(unsigned(x(15)+x(03)),9)); |
when x"02" => |
x(12) <= x(12) xor std_logic_vector( rotate_left(unsigned(x(04)+x(08)),13)); |
x(01) <= x(01) xor std_logic_vector( rotate_left(unsigned(x(09)+x(13)),13)); |
x(06) <= x(06) xor std_logic_vector( rotate_left(unsigned(x(14)+x(02)),13)); |
x(11) <= x(11) xor std_logic_vector( rotate_left(unsigned(x(03)+x(07)),13)); |
when x"03" => |
x(00) <= x(00) xor std_logic_vector( rotate_left(unsigned(x(08)+x(12)),18)); |
x(05) <= x(05) xor std_logic_vector( rotate_left(unsigned(x(13)+x(01)),18)); |
x(10) <= x(10) xor std_logic_vector( rotate_left(unsigned(x(02)+x(06)),18)); |
x(15) <= x(15) xor std_logic_vector( rotate_left(unsigned(x(07)+x(11)),18)); |
|
when x"04" => |
x(01) <= x(01) xor std_logic_vector( rotate_left(unsigned(x(03)+x(00)),07)); |
x(06) <= x(06) xor std_logic_vector( rotate_left(unsigned(x(04)+x(05)),07)); |
x(11) <= x(11) xor std_logic_vector( rotate_left(unsigned(x(09)+x(10)),07)); |
x(12) <= x(12) xor std_logic_vector( rotate_left(unsigned(x(14)+x(15)),07)); |
when x"05" => |
x(02) <= x(02) xor std_logic_vector( rotate_left(unsigned(x(00)+x(01)),09)); |
x(07) <= x(07) xor std_logic_vector( rotate_left(unsigned(x(05)+x(06)),09)); |
x(08) <= x(08) xor std_logic_vector( rotate_left(unsigned(x(10)+x(11)),09)); |
x(13) <= x(13) xor std_logic_vector( rotate_left(unsigned(x(15)+x(12)),09)); |
when x"06" => |
x(03) <= x(03) xor std_logic_vector( rotate_left(unsigned(x(01)+x(02)),13)); |
x(04) <= x(04) xor std_logic_vector( rotate_left(unsigned(x(06)+x(07)),13)); |
x(09) <= x(09) xor std_logic_vector( rotate_left(unsigned(x(11)+x(08)),13)); |
x(14) <= x(14) xor std_logic_vector( rotate_left(unsigned(x(12)+x(13)),13)); |
when x"07" => |
x(00) <= x(00) xor std_logic_vector( rotate_left(unsigned(x(02)+x(03)),18)); |
x(05) <= x(05) xor std_logic_vector( rotate_left(unsigned(x(07)+x(04)),18)); |
x(10) <= x(10) xor std_logic_vector( rotate_left(unsigned(x(08)+x(09)),18)); |
x(15) <= x(15) xor std_logic_vector( rotate_left(unsigned(x(13)+x(14)),18)); |
when others => |
null; |
end case; |
|
when st_sum_res => |
|
-- preparing index for the next random block reneration |
idx <= idx + x"0000000000000001"; |
|
mc_data_buf(32 * 00 + 31 downto 32 * 00 + 0) <= mc_data_buf(32 * 00 + 31 downto 32 * 00 + 0) + x(00); |
mc_data_buf(32 * 01 + 31 downto 32 * 01 + 0) <= mc_data_buf(32 * 01 + 31 downto 32 * 01 + 0) + x(01); |
mc_data_buf(32 * 02 + 31 downto 32 * 02 + 0) <= mc_data_buf(32 * 02 + 31 downto 32 * 02 + 0) + x(02); |
mc_data_buf(32 * 03 + 31 downto 32 * 03 + 0) <= mc_data_buf(32 * 03 + 31 downto 32 * 03 + 0) + x(03); |
mc_data_buf(32 * 04 + 31 downto 32 * 04 + 0) <= mc_data_buf(32 * 04 + 31 downto 32 * 04 + 0) + x(04); |
mc_data_buf(32 * 05 + 31 downto 32 * 05 + 0) <= mc_data_buf(32 * 05 + 31 downto 32 * 05 + 0) + x(05); |
mc_data_buf(32 * 06 + 31 downto 32 * 06 + 0) <= mc_data_buf(32 * 06 + 31 downto 32 * 06 + 0) + x(06); |
mc_data_buf(32 * 07 + 31 downto 32 * 07 + 0) <= mc_data_buf(32 * 07 + 31 downto 32 * 07 + 0) + x(07); |
mc_data_buf(32 * 08 + 31 downto 32 * 08 + 0) <= mc_data_buf(32 * 08 + 31 downto 32 * 08 + 0) + x(08); |
mc_data_buf(32 * 09 + 31 downto 32 * 09 + 0) <= mc_data_buf(32 * 09 + 31 downto 32 * 09 + 0) + x(09); |
mc_data_buf(32 * 10 + 31 downto 32 * 10 + 0) <= mc_data_buf(32 * 10 + 31 downto 32 * 10 + 0) + x(10); |
mc_data_buf(32 * 11 + 31 downto 32 * 11 + 0) <= mc_data_buf(32 * 11 + 31 downto 32 * 11 + 0) + x(11); |
mc_data_buf(32 * 12 + 31 downto 32 * 12 + 0) <= mc_data_buf(32 * 12 + 31 downto 32 * 12 + 0) + x(12); |
mc_data_buf(32 * 13 + 31 downto 32 * 13 + 0) <= mc_data_buf(32 * 13 + 31 downto 32 * 13 + 0) + x(13); |
mc_data_buf(32 * 14 + 31 downto 32 * 14 + 0) <= mc_data_buf(32 * 14 + 31 downto 32 * 14 + 0) + x(14); |
mc_data_buf(32 * 15 + 31 downto 32 * 15 + 0) <= mc_data_buf(32 * 15 + 31 downto 32 * 15 + 0) + x(15); |
|
mc_busy <= '0'; |
|
state <= st_calc_done; |
|
when st_calc_done => |
|
if mc_restart = '1' then |
-- new block requested with new input |
state <= st_read_in; |
end if; |
|
when others => |
null; |
|
end case; |
|
end if; |
end if; |
end process; |
|
end architecture rtl; |
|
/salsa20/trunk/rtl/salsaa.vhd
0,0 → 1,96
-- |
-- Copyright 2012 iQUBE research |
-- |
-- This file is part of Salsa20IpCore. |
-- |
-- Salsa20IpCore is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- Salsa20IpCore is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU Lesser General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with Salsa20IpCore. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- e-mail: lukasz.dzianach@iqube.es, info@iqube.es |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.NUMERIC_STD.all; |
|
|
entity salsaa is |
port ( |
clk : in std_logic; |
reset : in std_logic; |
|
key : in std_logic_vector(255 downto 0); |
nonce : in std_logic_vector(63 downto 0); |
start : in std_logic; |
|
data_valid : out std_logic; |
|
data : out std_logic_vector(31 downto 0); |
data_req : in std_logic |
|
); |
end entity salsaa; |
|
architecture rtl of salsaa is |
|
signal mc_data : std_logic_vector(511 downto 0); |
signal mc_restart : std_logic; |
signal mc_busy : std_logic; |
|
begin |
|
salsaa_dm_0: entity work.salsaa_dm |
port map( |
clk => clk, |
reset => reset, |
|
-- iface for user |
data => data, |
data_req => data_req, |
|
data_valid => data_valid, |
|
-- iface to salsaa_mc |
mc_data => mc_data, |
mc_restart => mc_restart, |
mc_busy => mc_busy |
); |
|
salsaa_mc_0: entity work.salsaa_mc |
port map( |
clk => clk, |
reset => reset, |
|
-- iface for user |
key => key, |
nonce => nonce, |
start => start, |
|
-- iface to salsaa_dc |
mc_data => mc_data, |
mc_restart => mc_restart, |
mc_busy => mc_busy |
); |
|
main: process(clk) is |
begin |
if (clk'event and clk='1') then |
if (reset='1') then |
else |
end if; |
end if; |
end process; |
|
|
end architecture rtl; |
/salsa20/trunk/rtl/salsaa_dm.vhd
0,0 → 1,263
-- |
-- Copyright 2012 iQUBE research |
-- |
-- This file is part of Salsa20IpCore. |
-- |
-- Salsa20IpCore is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- Salsa20IpCore is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU Lesser General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with Salsa20IpCore. If not, see <http://www.gnu.org/licenses/>. |
-- |
|
-- e-mail: lukasz.dzianach@iqube.es, info@iqube.es |
-- |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.NUMERIC_STD.all; |
|
|
entity salsaa_dm is |
port ( |
clk : in std_logic; |
reset : in std_logic; |
|
-- iface for user |
data : out std_logic_vector(31 downto 0); |
data_req : in std_logic; |
data_valid : out std_logic; |
|
-- iface to salsaa_mc |
mc_data : in std_logic_vector(511 downto 0); |
mc_restart : out std_logic; |
mc_busy : in std_logic |
|
); |
end entity salsaa_dm; |
|
architecture rtl of salsaa_dm is |
|
type reg_type is array(0 to 15) of std_logic_vector(31 downto 0); |
|
signal state : std_logic_vector (3 downto 0); |
signal reg : reg_type; |
signal reg_idx : std_logic_vector (3 downto 0); |
|
|
constant dm_rst : std_logic_vector := x"0"; |
constant dm_wmc_dr : std_logic_vector := x"1"; |
constant dm_wmc_ndr : std_logic_vector := x"2"; |
constant dm_idl : std_logic_vector := x"3"; |
constant dm_lmd : std_logic_vector := x"4"; |
constant dm_lmdps : std_logic_vector := x"5"; |
constant dm_ps : std_logic_vector := x"6"; |
|
constant max_reg_idx : std_logic_vector := x"f"; |
|
begin |
|
main: process(clk) is |
begin |
if (clk'event and clk='1') then |
if (reset='1') then |
state <= dm_rst; |
|
for Z in 0 to 15 |
loop |
--reg(Z) <= mc_data(32 * Z + 31 downto 32 * Z + 0); |
reg(Z) <= x"00000000"; |
end loop; |
|
data_valid <= '0'; |
data <= x"00000000"; |
reg_idx <= x"0"; |
|
else |
|
case state is |
|
when dm_rst => |
reg_idx <= x"0"; |
data_valid <= '0'; |
mc_restart <= '0'; |
|
if mc_busy = '0' and data_req = '1' then |
state <= dm_lmdps; |
elsif data_req = '1' then |
state <= dm_wmc_dr; |
elsif mc_busy = '0' then |
state <= dm_lmd; |
end if; |
|
when dm_lmdps => |
|
-- state to reg |
reg(00) <= mc_data(32 * 00 + 31 downto 32 * 00 + 0); |
reg(01) <= mc_data(32 * 01 + 31 downto 32 * 01 + 0); |
reg(02) <= mc_data(32 * 02 + 31 downto 32 * 02 + 0); |
reg(03) <= mc_data(32 * 03 + 31 downto 32 * 03 + 0); |
reg(04) <= mc_data(32 * 04 + 31 downto 32 * 04 + 0); |
reg(05) <= mc_data(32 * 05 + 31 downto 32 * 05 + 0); |
reg(06) <= mc_data(32 * 06 + 31 downto 32 * 06 + 0); |
reg(07) <= mc_data(32 * 07 + 31 downto 32 * 07 + 0); |
reg(08) <= mc_data(32 * 08 + 31 downto 32 * 08 + 0); |
reg(09) <= mc_data(32 * 09 + 31 downto 32 * 09 + 0); |
reg(10) <= mc_data(32 * 10 + 31 downto 32 * 10 + 0); |
reg(11) <= mc_data(32 * 11 + 31 downto 32 * 11 + 0); |
reg(12) <= mc_data(32 * 12 + 31 downto 32 * 12 + 0); |
reg(13) <= mc_data(32 * 13 + 31 downto 32 * 13 + 0); |
reg(14) <= mc_data(32 * 14 + 31 downto 32 * 14 + 0); |
reg(15) <= mc_data(32 * 15 + 31 downto 32 * 15 + 0); |
|
reg_idx <= reg_idx + x"1"; |
data_valid <= '1'; |
mc_restart <= '1'; |
data <= mc_data(32 * 00 + 31 downto 32 * 00 + 0); |
|
if data_req = '1' then |
state <= dm_ps; |
else |
state <= dm_idl; |
end if; |
|
when dm_lmd => |
|
-- state to reg |
reg(00) <= mc_data(32 * 00 + 31 downto 32 * 00 + 0); |
reg(01) <= mc_data(32 * 01 + 31 downto 32 * 01 + 0); |
reg(02) <= mc_data(32 * 02 + 31 downto 32 * 02 + 0); |
reg(03) <= mc_data(32 * 03 + 31 downto 32 * 03 + 0); |
reg(04) <= mc_data(32 * 04 + 31 downto 32 * 04 + 0); |
reg(05) <= mc_data(32 * 05 + 31 downto 32 * 05 + 0); |
reg(06) <= mc_data(32 * 06 + 31 downto 32 * 06 + 0); |
reg(07) <= mc_data(32 * 07 + 31 downto 32 * 07 + 0); |
reg(08) <= mc_data(32 * 08 + 31 downto 32 * 08 + 0); |
reg(09) <= mc_data(32 * 09 + 31 downto 32 * 09 + 0); |
reg(10) <= mc_data(32 * 10 + 31 downto 32 * 10 + 0); |
reg(11) <= mc_data(32 * 11 + 31 downto 32 * 11 + 0); |
reg(12) <= mc_data(32 * 12 + 31 downto 32 * 12 + 0); |
reg(13) <= mc_data(32 * 13 + 31 downto 32 * 13 + 0); |
reg(14) <= mc_data(32 * 14 + 31 downto 32 * 14 + 0); |
reg(15) <= mc_data(32 * 15 + 31 downto 32 * 15 + 0); |
|
reg_idx <= x"0"; |
data_valid <= '0'; |
mc_restart <= '1'; |
|
if data_req = '1' then |
state <= dm_ps; |
else |
state <= dm_idl; |
end if; |
|
when dm_ps => |
|
-- loading data to output |
data <= reg(to_integer(unsigned(reg_idx))); |
data_valid <= '1'; |
|
-- mc should not restart in this state |
mc_restart <= '0'; |
|
-- moving reg_idx |
if reg_idx = max_reg_idx then |
reg_idx <= x"0"; |
else |
reg_idx <= reg_idx + x"1"; |
end if; |
|
|
|
-- selecting next state |
if reg_idx = max_reg_idx then |
-- considering the situation when the last reg_idx |
if data_req = '0' and mc_busy = '0' then |
state <= dm_lmd; |
elsif data_req = '0' and mc_busy = '1' then |
state <= dm_wmc_ndr; |
elsif data_req = '1' and mc_busy = '0' then |
state <= dm_lmdps; |
elsif data_req = '1' and mc_busy = '1' then |
state <= dm_wmc_dr; |
end if; |
else |
-- considering typical situation |
if data_req = '1' then |
state <= dm_ps; |
elsif data_req = '0' then |
state <= dm_idl; |
end if; |
end if; |
|
when dm_idl => |
|
-- no valid data |
data_valid <= '0'; |
|
-- mc should not restart in this state |
mc_restart <= '0'; |
|
-- selecting next state CHECK THIS CODE |
if data_req = '1' then |
state <= dm_ps; |
elsif data_req = '0' then |
state <= dm_idl; |
end if; |
|
when dm_wmc_dr => |
|
-- no valid data |
data_valid <= '0'; |
|
-- mc should not restart in this state |
mc_restart <= '0'; |
|
-- sett to the beginning of data register |
reg_idx <= x"0"; |
|
-- selecting next state |
if mc_busy = '0' then |
state <= dm_lmdps; |
end if; |
|
when dm_wmc_ndr => |
|
-- no valid data |
data_valid <= '0'; |
|
-- mc should not restart in this state |
mc_restart <= '0'; |
|
-- set to the beginning of data register |
reg_idx <= x"0"; |
|
-- selecting next state |
if mc_busy = '0' and data_req = '0' then |
state <= dm_lmd; |
elsif mc_busy = '0' and data_req = '1' then |
state <= dm_lmdps; |
elsif mc_busy = '1' and data_req = '0' then |
state <= dm_wmc_ndr; |
elsif mc_busy = '1' and data_req = '1' then |
state <= dm_wmc_dr; |
end if; |
|
when others => |
null; |
|
end case; |
|
end if; |
end if; |
end process; |
|
end architecture rtl; |