URL
https://opencores.org/ocsvn/tinycpu/tinycpu/trunk
Subversion Repositories tinycpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/tinycpu/trunk/src/registerfile.vhd
1,3 → 1,7
--registerfile module |
--16 registers, dual port for both read and write |
--8 bit registers |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
/tinycpu/trunk/src/memory.vhd
1,3 → 1,10
--RAM module |
--4096*8 bit file |
--simultaneous write/read support |
--16 bit or 8 bit data bus |
--16 bit address bus |
--On Reset, will load a "default" RAM image |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use ieee.std_logic_arith.all; |
4,6 → 11,8
use IEEE.NUMERIC_STD.ALL; |
use ieee.std_logic_unsigned.all; |
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|
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entity memory is |
port( |
Address: in std_logic_vector(15 downto 0); --memory address |
30,10 → 39,10
if(addr>size-1) then |
addr:=0; |
end if; |
if(Reset ='1' and rising_edge(Clock)) then |
mem <= (others => "00000000"); |
elsif(Write='1' and Reset='0') then |
if(rising_edge(clock)) then |
if(rising_edge(Clock)) then |
if(Reset ='1') then |
mem <= (others => "00000000"); |
elsif( Write='1') then |
mem(conv_integer(addr)) <= DataIn(7 downto 0); |
if(UseTopBits='1') then |
mem(conv_integer(addr)+1) <= DataIn(15 downto 8); |