URL
https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk
Subversion Repositories 10_100m_ethernet-fifo_convertor
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Rev 5 → Rev 6
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/common.v
0,0 → 1,16
//author :gurenliang |
//Email: gurenliang@gmail.com |
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me. |
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//version 0.3, create this file to be a common included one for future use to config the IP core |
//This file used to define some macro-varibles which can be used by all other files |
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//NOTE!!! Olny one of the following two definitions can be open |
//`define frameIDfromRx //frameID comes from Rxmodule |
`define frameIDcount //frameID counts for itself by adding one every frame |
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`define Preamble 64'hd555_5555_5555_5555 |
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//The MAC address of this MAC IP core and the other terminal on the Ethernet, can be changed! |
`define MAC_ADD 48'h0100_0000_0000 //mac address: 0x00-00-00-00-00-01 |
`define PC_MAC_ADD 48'hffff_ffff_ffff //mac address of the other terminal |