OpenCores

trunk/vga_lcd/doc/src/vga_core_enh.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/vga_lcd/doc/vga_core.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/vga_lcd/doc/vga_core.pdf =================================================================== --- trunk/vga_lcd/doc/vga_core.pdf (revision 5) +++ trunk/vga_lcd/doc/vga_core.pdf (nonexistent)

trunk/vga_lcd/doc/vga_core.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/vga_lcd/sim/rtl_sim/bin/Makefile =================================================================== --- trunk/vga_lcd/sim/rtl_sim/bin/Makefile (revision 5) +++ trunk/vga_lcd/sim/rtl_sim/bin/Makefile (nonexistent) @@ -1,161 +0,0 @@ - -all: sim -SHELL = /bin/sh -#MS="-s" - -########################################################################## -# -# DUT Sources -# -########################################################################## -DUT_SRC_DIR=../../../rtl/verilog -_TARGETS_= $(DUT_SRC_DIR)/generic_dpram.v \ - $(DUT_SRC_DIR)/generic_spram.v \ - $(DUT_SRC_DIR)/csm_spram_bw.v \ - $(DUT_SRC_DIR)/vga_colproc.v \ - $(DUT_SRC_DIR)/vga_csm_pb.v \ - $(DUT_SRC_DIR)/vga_cur_cregs.v \ - $(DUT_SRC_DIR)/vga_curproc.v \ - $(DUT_SRC_DIR)/vga_enh_top.v \ - $(DUT_SRC_DIR)/vga_dvi_top.v \ - $(DUT_SRC_DIR)/vga_fifo.v \ - $(DUT_SRC_DIR)/vga_fifo_dc.v \ - $(DUT_SRC_DIR)/vga_pgen.v \ - $(DUT_SRC_DIR)/vga_tgen.v \ - $(DUT_SRC_DIR)/vga_vtim.v \ - $(DUT_SRC_DIR)/vga_wb_master.v \ - $(DUT_SRC_DIR)/vga_wb_slave.v - - -########################################################################## -# -# Test Bench Sources -# -########################################################################## -TB_SRC_DIR=../../../bench/verilog -_TB_= $(TB_SRC_DIR)/test_bench_top.v \ - $(TB_SRC_DIR)/wb_slv_model.v \ - $(TB_SRC_DIR)/wb_mast_model.v \ - $(TB_SRC_DIR)/sync_check.v \ - $(TB_SRC_DIR)/artsmcl18u_ram/art_hssp_512x24_bw_bist.v \ - $(TB_SRC_DIR)/artsmcl18u_ram/art_hsdp_128x24_bist.v \ - $(TB_SRC_DIR)/bist/rtl/verilog/bist_dp_top.v \ - $(TB_SRC_DIR)/bist/rtl/verilog/bist_sp_top.v \ - $(TB_SRC_DIR)/bist/rtl/verilog/bist_tp_top.v \ - $(TB_SRC_DIR)/bist/rtl/verilog/bist.v \ - $(TB_SRC_DIR)/artsmcl18u_ram/art_hssp_512x24_bw/art_hssp_512x24_bw.v \ - $(TB_SRC_DIR)/artsmcl18u_ram/art_hsdp_128x24/art_hsdp_128x24.v \ - $(TB_SRC_DIR)/wb_b3_check.v - -########################################################################## -# -# Misc Variables -# -########################################################################## - -_TOP_=test -INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/" -LOGF=-LOGFILE .nclog -NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT -UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v -GATE_NETLIST=../../../syn/out/vga_vga_and_clut_ps.v - -########################################################################## -# -# Make Targets -# -########################################################################## -simw: - @$(MAKE) -s sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES" - -ss: - signalscan -do waves/waves.do -waves waves/waves.trn & - -sim: - @echo "" - @echo "----- Running NCVLOG ... ----------" - @$(MAKE) $(MS) vlog \ - TARGETS="$(_TARGETS_)" \ - TB="$(_TB_)" \ - INCDIR=$(INCDIR) \ - WAVES="$(WAVES)" \ - TOP=$(_TOP_) - @echo "" - @echo "----- Running NCELAB ... ----------" - @$(MAKE) $(MS) elab \ - ACCESS="$(ACCESS)" TOP=$(_TOP_) - @echo "" - @echo "----- Running NCSIM ... ----------" - @$(MAKE) $(MS) ncsim \ - TOP=$(_TOP_) - @echo "" - - -gatew: - @$(MAKE) -s gate ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES" - -gate: - @echo "" - @echo "----- Running NCVLOG ... ----------" - $(MAKE)$(MS) vlog \ - TARGETS="$(UMC_LIB) $(GATE_NETLIST)" \ - TB="$(_TB_)" \ - INCDIR=$(INCDIR) \ - WAVES="$(WAVES)" - @echo "" - @echo "----- Running NCELAB ... ----------" - @$(MAKE) $(MS) elab \ - ACCESS="$(ACCESS)" TOP=$(_TOP_) - @echo "" - @echo "----- Running NCSIM ... ----------" - @$(MAKE) $(MS) ncsim TOP=$(_TOP_) - @echo "" - - -hal: - @echo "" - @echo "----- Running HAL ... ----------" - hal +incdir+$(DUT_SRC_DIR) \ - -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \ - "$(_TARGETS_)" - @echo "----- DONE ... ----------" - -clean: - rm -rf ./waves/*.dsn ./waves/*.trn \ - ncwork/worklib/* ncwork/count/* \ - ncwork/worklib/.i* ncwork/count/.i* - -########################################################################## -# -# NCVLOG -# -########################################################################## - -vlog: - ncvlog $(NCCOMMON) $(LOGF) \ - -WORK worklib $(WAVES) $(TARGETS) $(TB) $(INCDIR) - -########################################################################## -# -# NCELAB -# -########################################################################## - -elab: - ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \ - -WORK worklib $(ACCESS) \ - -NOTIMINGCHECKS \ - worklib.$(TOP) - -########################################################################## -# -# NCSIM -# -########################################################################## - -ncsim: - ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \ - -EXIT -ERRORMAX 10 worklib.$(TOP) - - - Index: trunk/vga_lcd/syn/bin/read.dc =================================================================== --- trunk/vga_lcd/syn/bin/read.dc (revision 5) +++ trunk/vga_lcd/syn/bin/read.dc (nonexistent) @@ -1,66 +0,0 @@ -############################################################################### -# -# Pre Synthesis Script -# -# This script only reads in the design and saves it in a DB file -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters -source ../bin/design_spec.dc - -# ============================================== -# Setup Libraries -source ../bin/lib_spec.dc - -# ============================================== -# Setup IO Files - -append log_file ../log/$active_design "_pre.log" -append pre_comp_db_file ../out/$design_name "_pre.db" - -sh rm -f $log_file - -# ============================================== -# Setup Misc Variables - -set hdlin_enable_vpp true ;# Important - this enables 'ifdefs - -# ============================================== -# Read Design - -echo "+++++++++ Analyzing all design files ..." >> $log_file - -foreach module $design_files { - echo "+++++++++ Reading: $module" >> $log_file - echo +++++++++ Reading: $module - set module_file_name "" - append module_file_name $module ".v" - analyze -f verilog $module_file_name >> $log_file - elaborate $module >> $log_file - } - -current_design $active_design - -echo "+++++++++ Linking Design ..." >> $log_file -link >> $log_file - -echo "+++++++++ Uniquifying Design ..." >> $log_file -uniquify >> $log_file - -echo "+++++++++ Checking Design ..." >> $log_file -check_design >> $log_file - -# ============================================== -# Save Design -echo "+++++++++ Saving Design ..." >> $log_file -write_file -hierarchy -format db -output $pre_comp_db_file - Index: trunk/vga_lcd/syn/bin/comp.dc =================================================================== --- trunk/vga_lcd/syn/bin/comp.dc (revision 5) +++ trunk/vga_lcd/syn/bin/comp.dc (nonexistent) @@ -1,134 +0,0 @@ -############################################################################### -# -# Actual Synthesis Script -# -# This script does the actual synthesis -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters -source ../bin/design_spec.dc - -# ============================================== -# Setup Libraries -source ../bin/lib_spec.dc - -# ============================================== -# Setup IO Files - -append log_file ../log/$active_design "_cmp.log" -append pre_comp_db_file ../out/$design_name "_pre.db" -append post_comp_db_file ../out/$design_name ".db" -append post_syn_verilog_file ../out/$design_name "_ps.v" -set junk_file /dev/null - -sh rm -f $log_file - -# ============================================== -# Setup Misc Variables - -set hdlin_enable_vpp true ;# Important - this enables 'ifdefs - -# ============================================== -# Read Design - -echo "+++++++++ Reading Design ..." >> $log_file -read_file $pre_comp_db_file >> $log_file - -# ============================================== -# Operating conditions - -echo "+++++++++ Setting up Operation Conditions ..." >> $log_file -current_design $design_name -set_operating_conditions WORST >> $log_file - -# Turn off automatic wire load selection, as this -# always (WHY ???) defaults to "zero_load" -#set auto_wire_load_selection false -#set_wire_load_mode enclosed >> $log_file -#set_wire_load_mode top >> $log_file -#set_wire_load_model -name suggested_40K >> $log_file - -# ============================================== -# Setup Clocks and Resets - -echo "+++++++++ Setting up Clocks ..." >> $log_file - -set_drive 0 wb_clk_i -set_drive 0 clk_pclk_i - -# !!! WISHBONE Clock !!! -set clock_period 5 -create_clock -period $clock_period wb_clk_i -set_clock_skew -uncertainty 0.1 wb_clk_i -set_clock_transition 0.5 wb_clk_i -set_dont_touch_network wb_clk_i - -# !!! Pixel Clock !!! -set clock_period2 20 -create_clock -period $clock_period2 clk_pclk_i -set_clock_skew -uncertainty 0.5 clk_pclk_i -set_clock_transition 0.9 clk_pclk_i -set_dont_touch_network clk_pclk_i - -# !!! Reset !!! -set_drive 0 wb_rst_i -set_dont_touch_network wb_rst_i -set_drive 0 rst_nreset_i -set_dont_touch_network rst_nreset_i - -# ============================================== -# Setup IOs - -echo "+++++++++ Setting up IOs ..." >> $log_file - -# Need to spell out external IOs - -set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file -set_load 0.2 [all_outputs] - -set_input_delay -max 2 -clock wb_clk_i [all_inputs] -set_output_delay -max 2 -clock wb_clk_i [all_outputs] - -set_input_delay -max 2 -clock clk_pclk_i [all_inputs] -set_output_delay -max 2 -clock clk_pclk_i [all_outputs] - -# ============================================== -# Setup Area Constrains -set_max_area 0.0 -set compile_sequential_area_recovery true - -# ============================================== -# Force Ultra -set_ultra_optimization -f - -# ============================================== -# Compile Design - -echo "+++++++++ Starting Compile ..." >> $log_file -#compile -map_effort low -area_effort low >> $log_file -compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file - -# ============================================== -# Write Out the optimized design - -echo "+++++++++ Saving Optimized Design ..." >> $log_file -write_file -hierarchy -format verilog -output $post_syn_verilog_file -write_file -hierarchy -format db -output $post_comp_db_file - -# ============================================== -# Create Some Basic Reports - -echo "+++++++++ Reporting Final Results ..." >> $log_file -report_timing -nworst 10 >> $log_file -report_area >> $log_file - - Index: trunk/vga_lcd/syn/bin/lib_spec.dc =================================================================== --- trunk/vga_lcd/syn/bin/lib_spec.dc (revision 5) +++ trunk/vga_lcd/syn/bin/lib_spec.dc (nonexistent) @@ -1,36 +0,0 @@ -############################################################################### -# -# Library Specification -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Libraries - -set search_path [list $search_path . \ - /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ - $hdl_src_dir] - -set snps [getenv "SYNOPSYS"] - -set synthetic_library "" -append synthetic_library $snps "/libraries/syn/dw01.sldb " -append synthetic_library $snps "/libraries/syn/dw02.sldb " -append synthetic_library $snps "/libraries/syn/dw03.sldb " -append synthetic_library $snps "/libraries/syn/dw04.sldb " -append synthetic_library $snps "/libraries/syn/dw05.sldb " -append synthetic_library $snps "/libraries/syn/dw06.sldb " -append synthetic_library $snps "/libraries/syn/dw07.sldb " - -set target_library { umcl18u250t2_typ.db } -set link_library "" -append link_library $target_library " " $synthetic_library -set symbol_library { umcl18u250t2.sdb } - Index: trunk/vga_lcd/syn/bin/design_spec.dc =================================================================== --- trunk/vga_lcd/syn/bin/design_spec.dc (revision 5) +++ trunk/vga_lcd/syn/bin/design_spec.dc (nonexistent) @@ -1,27 +0,0 @@ -############################################################################### -# -# Design Specification -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -############################################################################### - -# ============================================== -# Setup Design Parameters - -set design_files {ud_cnt ro_cnt vga_fifo_dc vga_fifo vga_colproc vga_vtim vga_pgen vga_wb_master vga_tgen vga_wb_slave vga_csm_pb vga_top vga_vga_and_clut} - - -set design_name vga_vga_and_clut -set active_design vga_vga_and_clut - -# Next Statement defines all clocks and resets in the design -set special_net {rst clk_i pclk} - -set hdl_src_dir ../../rtl/verilog/ - Index: trunk/vga_lcd/software/include/oc_vga_lcd.h =================================================================== --- trunk/vga_lcd/software/include/oc_vga_lcd.h (revision 5) +++ trunk/vga_lcd/software/include/oc_vga_lcd.h (nonexistent) @@ -1,123 +0,0 @@ -/* -///////////////////////////////////////////////////////////////////// -//// //// -//// Include file for OpenCores VGA/LCD Controller //// -//// //// -//// File : oc_vga_lcd.h //// -//// Function: c-include file //// -//// //// -//// Authors: Richard Herveille (richard@asics.ws) //// -//// www.opencores.org //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001 Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// -*/ - -/* - * Definitions for the Opencores VGA/LCD Controller Core - */ - -/* --- Register definitions --- */ - -/* ----- Read-write access */ - -#define OC_VGA_CTRL 0x000 /* Control register */ -#define OC_VGA_STAT 0x004 /* Status register */ -#define OC_VGA_HTIM 0x008 /* Horizontal Timing register */ -#define OC_VGA_VTIM 0x00c /* Vertical Timing register */ -#define OC_VGA_HVLEN 0x010 /* Horizontal/Vertical length register*/ -#define OC_VGA_VBARA 0x014 /* Video Base Address register A */ -#define OC_VGA_VBARB 0x018 /* Video Base Address register B */ - -/* ----- Bits definition */ - -/* ----- Control register */ - /* bits 31-16 are reserved */ -#define OC_VGA_BL (1<<15) /* Blank level bit: */ -#define OC_VGA_CSL (1<<14) /* Composite Sync. level bit */ -#define OC_VGA_VSL (1<<13) /* Vertical Sync. level bit */ -#define OC_VGA_HSL (1<<12) /* Horizontal Sync. level bit */ - /* 0 - Positive */ - /* 1 - Negative */ -#define OC_VGA_PC (1<<11) /* Pseudo Color (only for 8bpp mode) */ - /* 0 - 8bpp gray scale */ - /* 1 - 8bpp pseudo color */ -#define OC_VGA_CD (1<< 9) /* Color Depth */ - /* 00 - 8bits per pixel */ - /* 01 - 16bits per pixel */ - /* 10 - 24bits per pixel */ - /* 11 - reserved */ -#define OC_VGA_VBL (1<< 7) /* Video burst length */ - /* 00 - 1 cycle */ - /* 01 - 2 cycle */ - /* 10 - 4 cycle */ - /* 11 - 8 cycle */ -#define OC_VGA_CBSWE (1<<6) /* CLUT Bank Switch Enable bit */ -#define OC_VGA_VBSWE (1<<5) /* Video Bank Switch Enable bit */ -#define OC_VGA_CBSIE (1<<4) /* CLUT Bank Switch Interrupt enable */ -#define OC_VGA_VBSIE (1<<3) /* Video Bank Switch Interrupt enable */ -#define OC_VGA_HIE (1<<2) /* Horizontal Interrupt enable */ -#define OC_VGA_VIE (1<<1) /* Vertical Interrupt enable */ -#define OC_VGA_VEN (1<<0) /* Video Enable bit */ - /* 1 - Enabled */ - /* 0 - Disabled */ - -/* ----- Status register */ - /* bits 31-18 are reserved */ -#define OC_VGA_ACMP (1<<17) /* Active CLUT Memory Page */ -#define OC_VGA_AVMP (1<<16) /* Active Video Memory Page */ - /* bits 15-8 are reserved */ -#define OC_VGA_CBSINT (1<<7) /* CLUT Bank Switch Interrupt pending */ -#define OC_VGA_VBSINT (1<<6) /* Bank Switch Interrupt pending */ -#define OC_VGA_HINT (1<<5) /* Horizontal Interrupt pending */ -#define OC_VGA_VINT (1<<4) /* Vertical Interrupt pending */ - /* bits 3-2 are reserved */ -#define OC_VGA_LUINT (1<<1) /* LineFIFO Underrun interrupt pending*/ -#define OC_VGA_SINT (1<<0) /* System Error Interrupt pending */ - - -/* ----- Horizontal/Vertical Timing registers */ - -#define OC_VGA_TSYNC (1<<24) /* Synchronization pulse width */ -#define OC_VGA_TGDEL (1<<16) /* Gate delay time */ -#define OC_VGA_TGATE (1<< 0) /* Gate time */ - - -/* ----- Horizontal and Vertcial Length registers */ - -#define OC_VGA_THLEN (1<<16) /* Horizontal length */ -#define OC_VGA_TVLEN (1<< 0) /* Vertical length */ - - -/* bit testing and setting macros */ - -#define OC_ISSET(reg,bitmask) ((reg)&(bitmask)) -#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask))) -#define OC_BITSET(reg,bitmask) ((reg)|(bitmask)) -#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask))) -#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask)) -#define OC_REGMOVE(reg,value) ((reg)=(value)) \ No newline at end of file

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