URL
https://opencores.org/ocsvn/aes_core/aes_core/trunk
Subversion Repositories aes_core
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- ↔ Reverse comparison
Rev 5 → Rev 6
/tags/start/bench/verilog/test_bench_top.v
File deleted
/tags/start/rtl/verilog/aes_inv_sbox.v
File deleted
/tags/start/rtl/verilog/aes_inv_cipher_top.v
File deleted
/tags/start/rtl/verilog/aes_sbox.v
File deleted
/tags/start/rtl/verilog/aes_cipher_top.v
File deleted
/tags/start/rtl/verilog/aes_key_expand_128.v
File deleted
/tags/start/rtl/verilog/aes_rcon.v
File deleted
/tags/start/doc/aes.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
tags/start/doc/aes.pdf
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
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Index: tags/start/vim_session.vim
===================================================================
--- tags/start/vim_session.vim (revision 5)
+++ tags/start/vim_session.vim (nonexistent)
@@ -1,243 +0,0 @@
-set nocompatible
-let s:cpo_save=&cpo
-set cpo&vim
-map!
-map!
-map!
-map!
-map!
-map!
-map!
-map!
-map!
-map!
-nnoremap 6_Paste "=@+.'xy'
-gPFx"_2x:echo
-map
-map
-map
-map
-map
-map
-map
-map
-map
-map
-let &cpo=s:cpo_save
-unlet s:cpo_save
-set background=dark
-set bufhidden=delete
-set buftype=nofile
-if &filetype != 'csh'
-set filetype=csh
-endif
-set guifont=-adobe-courier-medium-r-normal-*-*-120-*-*-m-*-iso8859-1
-set iminsert=0
-set imsearch=0
-set iskeyword=@,48-57,_,192-255,+,-,?
-set menuitems=50
-set mouse=a
-set noswapfile
-if &syntax != 'verilog'
-set syntax=verilog
-endif
-let s:so_save = &so | let s:siso_save = &siso | set so=0 siso=0
-let v:this_session=expand(":p")
-silent only
-cd ~/projects/aes_core
-set shortmess=aoO
-badd +1 rtl/verilog/aes_top.v
-badd +105 bench/verilog/test_bench_top.v
-badd +30 sim/rtl_sim/bin/Makefile
-badd +79 rtl/verilog/aes_key_expand_128.v
-badd +72 rtl/verilog/aes_key_expand_192.v
-badd +55 rtl/verilog/aes_key_expand_256.v
-badd +94 rtl/verilog/aes_rcon.v
-badd +80 rtl/verilog/aes_sbox.v
-badd +44 impl_results
-badd +1 rtl/verilog/aes_inv_cipher_top.v
-badd +471 rtl/verilog/aes_inv_sbox.v
-silent! argdel *
-set splitbelow splitright
-normal _|
-vsplit
-normal 1h
-normal w
-set nosplitbelow
-set nosplitright
-normal t
-set winheight=1 winwidth=1
-exe 'vert resize ' . ((&columns * 99 + 106) / 212)
-normal w
-exe 'vert resize ' . ((&columns * 112 + 106) / 212)
-normal w
-argglobal
-edit rtl/verilog/aes_sbox.v
-setlocal noautoindent
-setlocal autoread
-setlocal nobinary
-setlocal bufhidden=
-setlocal buflisted
-setlocal buftype=
-setlocal nocindent
-setlocal cinkeys=0{,0},0),:,0#,!^F,o,O,e
-setlocal cinoptions=
-setlocal cinwords=if,else,while,do,for,switch
-setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:-
-setlocal commentstring=/*%s*/
-setlocal complete=.,w,b,u,t,i
-setlocal define=
-setlocal dictionary=
-setlocal nodiff
-setlocal equalprg=
-setlocal errorformat=
-setlocal noexpandtab
-if &filetype != 'verilog'
-setlocal filetype=verilog
-endif
-setlocal foldcolumn=0
-setlocal foldenable
-setlocal foldexpr=0
-setlocal foldignore=#
-setlocal foldlevel=0
-setlocal foldmarker={{{,}}}
-setlocal foldmethod=manual
-setlocal foldminlines=1
-setlocal foldnestmax=20
-setlocal foldtext=foldtext()
-setlocal formatoptions=tcq
-setlocal grepprg=
-setlocal iminsert=0
-setlocal imsearch=0
-setlocal include=
-setlocal includeexpr=
-setlocal indentexpr=
-setlocal indentkeys=0{,0},:,0#,!^F,o,O,e
-setlocal noinfercase
-setlocal iskeyword=@,48-57,_,192-255,+,-,?
-setlocal keymap=
-setlocal nolinebreak
-setlocal nolisp
-setlocal nolist
-setlocal makeprg=
-setlocal matchpairs=(:),{:},[:]
-setlocal modeline
-setlocal modifiable
-setlocal nrformats=octal,hex
-setlocal nonumber
-setlocal path=
-setlocal nopreviewwindow
-setlocal noreadonly
-setlocal norightleft
-setlocal noscrollbind
-setlocal shiftwidth=8
-setlocal noshortname
-setlocal nosmartindent
-setlocal softtabstop=0
-setlocal suffixesadd=
-setlocal noswapfile
-if &syntax != 'verilog'
-setlocal syntax=verilog
-endif
-setlocal tabstop=8
-setlocal tags=
-setlocal textwidth=0
-setlocal thesaurus=
-setlocal wrap
-setlocal wrapmargin=0
-silent! normal zE
-let s:l = 65 - ((28 * winheight(0) + 34) / 69)
-if s:l < 1 | let s:l = 1 | endif
-exe s:l
-normal zt
-65
-normal 0
-normal w
-argglobal
-edit rtl/verilog/aes_inv_cipher_top.v
-setlocal noautoindent
-setlocal autoread
-setlocal nobinary
-setlocal bufhidden=
-setlocal buflisted
-setlocal buftype=
-setlocal nocindent
-setlocal cinkeys=0{,0},0),:,0#,!^F,o,O,e
-setlocal cinoptions=
-setlocal cinwords=if,else,while,do,for,switch
-setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:-
-setlocal commentstring=/*%s*/
-setlocal complete=.,w,b,u,t,i
-setlocal define=
-setlocal dictionary=
-setlocal nodiff
-setlocal equalprg=
-setlocal errorformat=
-setlocal noexpandtab
-if &filetype != 'verilog'
-setlocal filetype=verilog
-endif
-setlocal foldcolumn=0
-setlocal foldenable
-setlocal foldexpr=0
-setlocal foldignore=#
-setlocal foldlevel=0
-setlocal foldmarker={{{,}}}
-setlocal foldmethod=manual
-setlocal foldminlines=1
-setlocal foldnestmax=20
-setlocal foldtext=foldtext()
-setlocal formatoptions=tcq
-setlocal grepprg=
-setlocal iminsert=0
-setlocal imsearch=0
-setlocal include=
-setlocal includeexpr=
-setlocal indentexpr=
-setlocal indentkeys=0{,0},:,0#,!^F,o,O,e
-setlocal noinfercase
-setlocal iskeyword=@,48-57,_,192-255,+,-,?
-setlocal keymap=
-setlocal nolinebreak
-setlocal nolisp
-setlocal nolist
-setlocal makeprg=
-setlocal matchpairs=(:),{:},[:]
-setlocal modeline
-setlocal modifiable
-setlocal nrformats=octal,hex
-setlocal nonumber
-setlocal path=
-setlocal nopreviewwindow
-setlocal noreadonly
-setlocal norightleft
-setlocal noscrollbind
-setlocal shiftwidth=8
-setlocal noshortname
-setlocal nosmartindent
-setlocal softtabstop=0
-setlocal suffixesadd=
-setlocal noswapfile
-if &syntax != 'verilog'
-setlocal syntax=verilog
-endif
-setlocal tabstop=8
-setlocal tags=
-setlocal textwidth=0
-setlocal thesaurus=
-setlocal wrap
-setlocal wrapmargin=0
-silent! normal zE
-let s:l = 260 - ((19 * winheight(0) + 34) / 69)
-if s:l < 1 | let s:l = 1 | endif
-exe s:l
-normal zt
-260
-normal 09l
-normal w
-set winheight=1 winwidth=20 shortmess=filnxtToO
-let s:sx = expand(":p:r")."x.vim"
-if file_readable(s:sx)
- exe "source " . s:sx
-endif
-let &so = s:so_save | let &siso = s:siso_save
Index: tags/start/sim/rtl_sim/bin/Makefile
===================================================================
--- tags/start/sim/rtl_sim/bin/Makefile (revision 5)
+++ tags/start/sim/rtl_sim/bin/Makefile (nonexistent)
@@ -1,82 +0,0 @@
-
-all: sim
-SHELL = /bin/sh
-MS="-s"
-
-##########################################################################
-#
-# DUT Sources
-#
-##########################################################################
-DUT_SRC_DIR=../../../rtl/verilog
-_TARGETS_= $(DUT_SRC_DIR)/aes_sbox.v \
- $(DUT_SRC_DIR)/aes_rcon.v \
- $(DUT_SRC_DIR)/aes_key_expand_128.v \
- $(DUT_SRC_DIR)/aes_cipher_top.v \
- $(DUT_SRC_DIR)/aes_inv_sbox.v \
- $(DUT_SRC_DIR)/aes_inv_cipher_top.v
-
-
-##########################################################################
-#
-# Test Bench Sources
-#
-##########################################################################
-TB_SRC_DIR=../../../bench/verilog
-_TB_= $(TB_SRC_DIR)/test_bench_top.v
-
-##########################################################################
-#
-# Misc Variables
-#
-##########################################################################
-
-INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
-LOGF=-l .nclog
-UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
-GATE_NETLIST = ../../../syn/out/aes_cipher_top.v
-
-##########################################################################
-#
-# Make Targets
-#
-##########################################################################
-ss:
- signalscan -do waves/waves.do -waves waves/waves.trn &
-
-simw:
- @$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
-
-sim:
- ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
- $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
- +ncuid+`hostname`
-
-ivl:
- /usr/local/bin/iverilog -D RUDIS_TB $(_TARGETS_) $(_TB_) \
- -I ./$(DUT_SRC_DIR)/ -I ./$(TB_SRC_DIR)/ \
- $(WAVES) $(ACCESS) -s test
-
-gatew:
- @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
-
-gate:
- ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \
- $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \
- $(LOGF) +ncstatus +ncuid+`hostname`
-
-hal:
- @echo ""
- @echo "----- Running HAL ... ----------"
- @hal +incdir+$(DUT_SRC_DIR) -NOP -NOS \
- -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
- $(_TARGETS_)
- @echo "----- DONE ... ----------"
-
-clean:
- rm -rf ./waves/*.dsn ./waves/*.trn \
- ncwork/.inc* ncwork/inc* \
- ./verilog.* .nclog hal.log INCA_libs
-
-##########################################################################
-
tags/start/sim/rtl_sim/bin/Makefile
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/start/sim/rtl_sim/run/waves/waves.do
===================================================================
--- tags/start/sim/rtl_sim/run/waves/waves.do (revision 5)
+++ tags/start/sim/rtl_sim/run/waves/waves.do (nonexistent)
@@ -1,209 +0,0 @@
-// Signalscan Version 6.8b1
-
-
-define noactivityindicator
-define analog waveform lines
-define add variable default overlay off
-define waveform window analogheight 1
-define terminal automatic
-define buttons control \
- 1 opensimmulationfile \
- 2 executedofile \
- 3 designbrowser \
- 4 waveform \
- 5 source \
- 6 breakpoints \
- 7 definesourcessearchpath \
- 8 exit \
- 9 createbreakpoint \
- 10 creategroup \
- 11 createmarker \
- 12 closesimmulationfile \
- 13 renamesimmulationfile \
- 14 replacesimulationfiledata \
- 15 listopensimmulationfiles \
- 16 savedofile
-define buttons waveform \
- 1 replacesimulationfiledata \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 zoomin \
- 7 zoomout \
- 8 zoomoutfull \
- 9 expand \
- 10 createmarker \
- 11 designbrowser:1 \
- 12 savedofile \
- 13 variableradixoctal \
- 14 variableradixdecimal \
- 15 variableradixhexadecimal \
- 16 variableradixascii
-define buttons designbrowser \
- 1 undo \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 cdupscope \
- 7 getallvariables \
- 8 getdeepallvariables \
- 9 addvariables \
- 10 addvarsandclosewindow \
- 11 closewindow \
- 12 scopefiltermodule \
- 13 scopefiltertask \
- 14 scopefilterfunction \
- 15 scopefilterblock \
- 16 scopefilterprimitive
-define buttons event \
- 1 undo \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 move \
- 7 closewindow \
- 8 duplicate \
- 9 defineasrisingedge \
- 10 defineasfallingedge \
- 11 defineasanyedge \
- 12 variableradixbinary \
- 13 variableradixoctal \
- 14 variableradixdecimal \
- 15 variableradixhexadecimal \
- 16 variableradixascii
-define buttons source \
- 1 undo \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 createbreakpoint \
- 7 creategroup \
- 8 createmarker \
- 9 createevent \
- 10 createregisterpage \
- 11 closewindow \
- 12 opensimmulationfile \
- 13 closesimmulationfile \
- 14 renamesimmulationfile \
- 15 replacesimulationfiledata \
- 16 listopensimmulationfiles
-define buttons register \
- 1 undo \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 createregisterpage \
- 7 closewindow \
- 8 continuefor \
- 9 continueuntil \
- 10 continueforever \
- 11 stop \
- 12 previous \
- 13 next \
- 14 variableradixbinary \
- 15 variableradixhexadecimal \
- 16 variableradixascii
-define show related transactions
-define exit noprompt
-define event search direction forward
-define variable fullhierarchy
-define variable nofilenames
-define variable nofullpathfilenames
-include bookmark with filenames
-include scope history without filenames
-define waveform window listpane 7.95
-define waveform window namepane 33.97
-define multivalueindication
-define pattern curpos dot
-define pattern cursor1 dot
-define pattern cursor2 dot
-define pattern marker dot
-define print designer "Rudolf Usselmann"
-define print border
-define print color blackonwhite
-define print command "/usr/bin/lpr -P%P"
-define print printer lp
-define print size A4
-define print range visible
-define print variable visible
-define rise fall time low threshold percentage 10
-define rise fall time high threshold percentage 90
-define rise fall time low value 0
-define rise fall time high value 3.3
-define sendmail command "/usr/lib/sendmail"
-define sequence time width 30.00
-define snap
-
-define source noprompt
-define time units default
-define userdefinedbussymbol
-define user guide directory "/usr/local/designacc/signalscan-6.5s2/doc/html"
-define waveform window grid off
-define waveform window waveheight 14
-define waveform window wavespace 6
-define web browser command netscape
-define zoom outfull on initial add off
-add group \
- A \
- test.rst \
- test.clk \
- test.u0.ld \
- test.u0.ld_r \
- test.u0.key[127:0]'h \
- test.u0.text_in[127:0]'h \
- test.text_out[127:0]'h \
- test.u0.done \
- test.done2 \
- test.text_out2[127:0]'h \
- test.u0.w0[31:0]'h \
- test.u0.w1[31:0]'h \
- test.u0.w2[31:0]'h \
- test.u0.w3[31:0]'h \
- test.u0.sa00[7:0]'h \
- test.u0.sa01[7:0]'h \
- test.u0.sa02[7:0]'h \
- test.u0.sa03[7:0]'h \
- test.u0.sa10[7:0]'h \
- test.u0.sa11[7:0]'h \
- test.u0.sa12[7:0]'h \
- test.u0.sa13[7:0]'h \
- test.u0.sa20[7:0]'h \
- test.u0.sa21[7:0]'h \
- test.u0.sa22[7:0]'h \
- test.u0.sa23[7:0]'h \
- test.u0.sa30[7:0]'h \
- test.u0.sa31[7:0]'h \
- test.u0.sa32[7:0]'h \
- test.u0.sa33[7:0]'h \
- test.clk \
- test.u1.ld \
- test.u1.done \
- test.u1.w3[31:0]'h \
- test.u1.kdone \
- test.u1.kld \
- test.u1.text_in[127:0]'h \
- test.u1.text_in_r[127:0]'h \
- test.u1.text_out[127:0]'h \
- test.u1.kb_ld \
- test.u1.kcnt[3:0]'h \
- test.u1.dcnt[3:0]'h \
- test.u1.w0[31:0]'h \
- test.u1.w1[31:0]'h \
- test.u1.w2[31:0]'h \
- test.u1.w3[31:0]'h \
- test.u1.wk0[31:0]'h \
- test.u1.wk1[31:0]'h \
- test.u1.wk2[31:0]'h \
- test.u1.wk3[31:0]'h \
-
-
-deselect all
-create marker Marker1 0ns
-open window designbrowser 1 geometry 450 269 1020 752
-open window waveform 1 geometry 58 104 1540 838
-zoom at 0(0)ns 0.00803721 0.00000000
Index: tags/start/syn/bin/lib_spec.dc
===================================================================
--- tags/start/syn/bin/lib_spec.dc (revision 5)
+++ tags/start/syn/bin/lib_spec.dc (nonexistent)
@@ -1,43 +0,0 @@
-###############################################################################
-#
-# Library Specification
-#
-# Author: Rudolf Usselmann
-# rudi@asics.ws
-#
-# Revision:
-# 3/7/01 RU Initial Sript
-#
-#
-###############################################################################
-
-# ==============================================
-# Setup Libraries
-
-#tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
-#tools/dc_libraries/virtual_silicon/UMCL13L210D3_1.0/design_compiler/ \
-
-
-set search_path [list $search_path . \
- /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
- $hdl_src_dir]
-
-set snps [getenv "SYNOPSYS"]
-
-set synthetic_library ""
-append synthetic_library $snps "/libraries/syn/dw01.sldb "
-append synthetic_library $snps "/libraries/syn/dw02.sldb "
-append synthetic_library $snps "/libraries/syn/dw03.sldb "
-append synthetic_library $snps "/libraries/syn/dw04.sldb "
-append synthetic_library $snps "/libraries/syn/dw05.sldb "
-append synthetic_library $snps "/libraries/syn/dw06.sldb "
-append synthetic_library $snps "/libraries/syn/dw07.sldb "
-
-set target_library { umcl18u250t2_wc.db }
-#set target_library { umcl13l210t3_wc.db }
-
-set link_library ""
-append link_library $target_library " " $synthetic_library
-
-#set symbol_library { umcl13l210t3.sdb }
-
Index: tags/start/syn/bin/design_spec.dc
===================================================================
--- tags/start/syn/bin/design_spec.dc (revision 5)
+++ tags/start/syn/bin/design_spec.dc (nonexistent)
@@ -1,29 +0,0 @@
-###############################################################################
-#
-# Design Specification
-#
-# Author: Rudolf Usselmann
-# rudi@asics.ws
-#
-# Revision:
-# 3/7/01 RU Initial Sript
-#
-#
-###############################################################################
-
-# ==============================================
-# Setup Design Parameters
-
-set design_files {aes_rcon aes_sbox aes_key_expand_128 aes_cipher_top}
-set design_name aes_cipher_top
-set active_design aes_cipher_top
-
-#set design_files {aes_rcon aes_inv_sbox aes_key_expand_128 aes_inv_cipher_top}
-#set design_name aes_inv_cipher_top
-#set active_design aes_inv_cipher_top
-
-# Next Statement defines all clocks and resets in the design
-set special_net {clk}
-
-set hdl_src_dir ../../rtl/verilog/
-
Index: tags/start/syn/bin/read.dc
===================================================================
--- tags/start/syn/bin/read.dc (revision 5)
+++ tags/start/syn/bin/read.dc (nonexistent)
@@ -1,67 +0,0 @@
-###############################################################################
-#
-# Pre Synthesis Script
-#
-# This script only reads in the design and saves it in a DB file
-#
-# Author: Rudolf Usselmann
-# rudi@asics.ws
-#
-# Revision:
-# 3/7/01 RU Initial Sript
-#
-#
-###############################################################################
-
-# ==============================================
-# Setup Design Parameters
-source ../bin/design_spec.dc
-
-# ==============================================
-# Setup Libraries
-source ../bin/lib_spec.dc
-
-# ==============================================
-# Setup IO Files
-
-append log_file ../log/$active_design "_pre.log"
-append pre_comp_db_file ../out/$design_name "_pre.db"
-
-sh rm -f $log_file
-
-# ==============================================
-# Setup Misc Variables
-
-set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
-
-# ==============================================
-# Read Design
-
-echo "+++++++++ Analyzing all design files ..." >> $log_file
-
-foreach module $design_files {
- echo "+++++++++ Reading: $module" >> $log_file
- echo +++++++++ Reading: $module
- set module_file_name ""
- append module_file_name $module ".v"
- analyze -f verilog $module_file_name >> $log_file
- elaborate $module >> $log_file
- }
-
-current_design $active_design
-
-echo "+++++++++ Linking Design ..." >> $log_file
-link >> $log_file
-
-echo "+++++++++ Uniquifying Design ..." >> $log_file
-uniquify >> $log_file
-
-echo "+++++++++ Checking Design ..." >> $log_file
-check_design >> $log_file
-
-# ==============================================
-# Save Design
-echo "+++++++++ Saving Design ..." >> $log_file
-write_file -hierarchy -format db -output $pre_comp_db_file
-
-quit
Index: tags/start/syn/bin/comp.dc
===================================================================
--- tags/start/syn/bin/comp.dc (revision 5)
+++ tags/start/syn/bin/comp.dc (nonexistent)
@@ -1,142 +0,0 @@
-###############################################################################
-#
-# Actual Synthesis Script
-#
-# This script does the actual synthesis
-#
-# Author: Rudolf Usselmann
-# rudi@asics.ws
-#
-# Revision:
-# 3/7/01 RU Initial Sript
-#
-#
-###############################################################################
-
-# ==============================================
-# Setup Design Parameters
-source ../bin/design_spec.dc
-
-# ==============================================
-# Setup Libraries
-source ../bin/lib_spec.dc
-
-# ==============================================
-# Setup IO Files
-
-append log_file ../log/$active_design "_cmp.log"
-append pre_comp_db_file ../out/$design_name "_pre.db"
-append post_comp_db_file ../out/$design_name ".db"
-append post_syn_verilog_file ../out/$design_name "_ps.v"
-set junk_file /dev/null
-
-sh rm -f $log_file
-
-# ==============================================
-# Setup Misc Variables
-
-set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
-
-# ==============================================
-# Read Design
-
-echo "+++++++++ Reading Design ..." >> $log_file
-read_file $pre_comp_db_file >> $log_file
-
-# ==============================================
-# Operating conditions
-
-echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
-current_design $design_name
-set_operating_conditions WORST >> $log_file
-
-# ==============================================
-# Setup Clocks and Resets
-
-echo "+++++++++ Setting up Clocks ..." >> $log_file
-
-set_drive 0 [find port {clk}]
-
-# !!! Clock !!!
-set clock_period 2.5
-create_clock -period $clock_period clk
-set_clock_skew -uncertainty 0.1 clk
-set_clock_transition 0.2 clk
-set_dont_touch_network clk
-
-# ==============================================
-# Setup IOs
-
-echo "+++++++++ Setting up IOs ..." >> $log_file
-
-# Need to spell out external IOs
-
-set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
-set_load 0.2 [all_outputs]
-
-set_input_delay -max 1 -clock clk [all_inputs]
-set_output_delay -max 1 -clock clk [all_outputs]
-
-# ==============================================
-# Setup Area Constrains
-set_max_area 0.0
-
-# ==============================================
-# Force Ultra
-set_ultra_optimization -f
-set compile_new_optimization true
-
-# ==============================================
-# Compile Design
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Timing Loops Report +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-report_timing -loops -max_path 20 >> $log_file
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Starting Compile +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-
-set_wire_load_model -name suggested_160K [find design *]
-set_balance_registers true
-compile -boundary_optimization -ungroup_all
-optimize_registers -period 0
-compile -incremental_mapping -map_effort high -area_effort high -boundary_optimization -ungroup_all
-
-# ==============================================
-# Write Out the optimized design
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Saving Optimized Design +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-write_file -hierarchy -format verilog -output $post_syn_verilog_file
-write_file -hierarchy -format db -output $post_comp_db_file
-
-# ==============================================
-# Create Some Basic Reports
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Reporting Final Results +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-report_timing -path full_clock -nworst 10 -nets \
- -transition_time -capacitance -attributes \
- -sort_by slack >> $log_file
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Area Report +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-
-report_area >> $log_file
-quit
-
Index: trunk/bench/verilog/test_bench_top.v
===================================================================
--- trunk/bench/verilog/test_bench_top.v (revision 5)
+++ trunk/bench/verilog/test_bench_top.v (nonexistent)
@@ -1,467 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// AES Test Bench ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: test_bench_top.v,v 1.2 2002-11-12 16:10:12 rudi Exp $
-//
-// $Date: 2002-11-12 16:10:12 $
-// $Revision: 1.2 $
-// $Author: rudi $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-// Revision 1.1.1.1 2002/11/09 11:22:56 rudi
-// Initial Checkin
-//
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module test;
-
-reg clk;
-reg rst;
-
-reg [383:0] tv[512:0]; // Test vectors
-wire [383:0] tmp;
-reg kld;
-wire [127:0] key, plain, ciph;
-wire [127:0] text_in;
-wire [127:0] text_out;
-wire [127:0] text_out2;
-reg [127:0] text_exp;
-wire done, done2;
-integer n, error_cnt;
-
-initial
- begin
- $display("\n\n");
- $display("*****************************************************");
- $display("* AES Test bench ...");
- $display("*****************************************************");
- $display("\n");
-`ifdef WAVES
- $shm_open("waves");
- $shm_probe("AS",test,"AS");
- $display("INFO: Signal dump enabled ...\n\n");
-`endif
-
- kld = 0;
- clk = 0;
- rst = 0;
- error_cnt = 0;
- repeat(4) @(posedge clk);
- rst = 1;
- repeat(20) @(posedge clk);
-
- $display("");
- $display("");
- $display("Started random test ...");
-
-tv[0]= 384'h00000000000000000000000000000000f34481ec3cc627bacd5dc3fb08f273e60336763e966d92595a567cc9ce537f5e;
-tv[1]= 384'h000000000000000000000000000000009798c4640bad75c7c3227db910174e72a9a1631bf4996954ebc093957b234589;
-tv[2]= 384'h0000000000000000000000000000000096ab5c2ff612d9dfaae8c31f30c42168ff4f8391a6a40ca5b25d23bedd44a597;
-tv[3]= 384'h000000000000000000000000000000006a118a874519e64e9963798a503f1d35dc43be40be0e53712f7e2bf5ca707209;
-tv[4]= 384'h00000000000000000000000000000000cb9fceec81286ca3e989bd979b0cb28492beedab1895a94faa69b632e5cc47ce;
-tv[5]= 384'h00000000000000000000000000000000b26aeb1874e47ca8358ff22378f09144459264f4798f6a78bacb89c15ed3d601;
-tv[6]= 384'h0000000000000000000000000000000058c8e00b2631686d54eab84b91f0aca108a4e2efec8a8e3312ca7460b9040bbf;
-tv[7]= 384'h10a58869d74be5a374cf867cfb473859000000000000000000000000000000006d251e6944b051e04eaa6fb4dbf78465;
-tv[8]= 384'hcaea65cdbb75e9169ecd22ebe6e54675000000000000000000000000000000006e29201190152df4ee058139def610bb;
-tv[9]= 384'ha2e2fa9baf7d20822ca9f0542f764a4100000000000000000000000000000000c3b44b95d9d2f25670eee9a0de099fa3;
-tv[10]= 384'hb6364ac4e1de1e285eaf144a2415f7a0000000000000000000000000000000005d9b05578fc944b3cf1ccf0e746cd581;
-tv[11]= 384'h64cf9c7abc50b888af65f49d521944b200000000000000000000000000000000f7efc89d5dba578104016ce5ad659c05;
-tv[12]= 384'h47d6742eefcc0465dc96355e851b64d9000000000000000000000000000000000306194f666d183624aa230a8b264ae7;
-tv[13]= 384'h3eb39790678c56bee34bbcdeccf6cdb500000000000000000000000000000000858075d536d79ccee571f7d7204b1f67;
-tv[14]= 384'h64110a924f0743d500ccadae72c134270000000000000000000000000000000035870c6a57e9e92314bcb8087cde72ce;
-tv[15]= 384'h18d8126516f8a12ab1a36d9f04d68e51000000000000000000000000000000006c68e9be5ec41e22c825b7c7affb4363;
-tv[16]= 384'hf530357968578480b398a3c251cd109300000000000000000000000000000000f5df39990fc688f1b07224cc03e86cea;
-tv[17]= 384'hda84367f325d42d601b4326964802e8e00000000000000000000000000000000bba071bcb470f8f6586e5d3add18bc66;
-tv[18]= 384'he37b1c6aa2846f6fdb413f238b089f230000000000000000000000000000000043c9f7e62f5d288bb27aa40ef8fe1ea8;
-tv[19]= 384'h6c002b682483e0cabcc731c253be5674000000000000000000000000000000003580d19cff44f1014a7c966a69059de5;
-tv[20]= 384'h143ae8ed6555aba96110ab58893a8ae100000000000000000000000000000000806da864dd29d48deafbe764f8202aef;
-tv[21]= 384'hb69418a85332240dc82492353956ae0c00000000000000000000000000000000a303d940ded8f0baff6f75414cac5243;
-tv[22]= 384'h71b5c08a1993e1362e4d0ce9b22b78d500000000000000000000000000000000c2dabd117f8a3ecabfbb11d12194d9d0;
-tv[23]= 384'he234cdca2606b81f29408d5f6da2120600000000000000000000000000000000fff60a4740086b3b9c56195b98d91a7b;
-tv[24]= 384'h13237c49074a3da078dc1d828bb78c6f000000000000000000000000000000008146a08e2357f0caa30ca8c94d1a0544;
-tv[25]= 384'h3071a2a48fe6cbd04f1a129098e308f8000000000000000000000000000000004b98e06d356deb07ebb824e5713f7be3;
-tv[26]= 384'h90f42ec0f68385f2ffc5dfc03a654dce000000000000000000000000000000007a20a53d460fc9ce0423a7a0764c6cf2;
-tv[27]= 384'hfebd9a24d8b65c1c787d50a4ed3619a900000000000000000000000000000000f4a70d8af877f9b02b4c40df57d45b17;
-tv[28]= 384'h80000000000000000000000000000000000000000000000000000000000000000edd33d3c621e546455bd8ba1418bec8;
-tv[29]= 384'hc0000000000000000000000000000000000000000000000000000000000000004bc3f883450c113c64ca42e1112a9e87;
-tv[30]= 384'he00000000000000000000000000000000000000000000000000000000000000072a1da770f5d7ac4c9ef94d822affd97;
-tv[31]= 384'hf000000000000000000000000000000000000000000000000000000000000000970014d634e2b7650777e8e84d03ccd8;
-tv[32]= 384'hf800000000000000000000000000000000000000000000000000000000000000f17e79aed0db7e279e955b5f493875a7;
-tv[33]= 384'hfc000000000000000000000000000000000000000000000000000000000000009ed5a75136a940d0963da379db4af26a;
-tv[34]= 384'hfe00000000000000000000000000000000000000000000000000000000000000c4295f83465c7755e8fa364bac6a7ea5;
-tv[35]= 384'hff00000000000000000000000000000000000000000000000000000000000000b1d758256b28fd850ad4944208cf1155;
-tv[36]= 384'hff8000000000000000000000000000000000000000000000000000000000000042ffb34c743de4d88ca38011c990890b;
-tv[37]= 384'hffc00000000000000000000000000000000000000000000000000000000000009958f0ecea8b2172c0c1995f9182c0f3;
-tv[38]= 384'hffe0000000000000000000000000000000000000000000000000000000000000956d7798fac20f82a8823f984d06f7f5;
-tv[39]= 384'hfff0000000000000000000000000000000000000000000000000000000000000a01bf44f2d16be928ca44aaf7b9b106b;
-tv[40]= 384'hfff8000000000000000000000000000000000000000000000000000000000000b5f1a33e50d40d103764c76bd4c6b6f8;
-tv[41]= 384'hfffc0000000000000000000000000000000000000000000000000000000000002637050c9fc0d4817e2d69de878aee8d;
-tv[42]= 384'hfffe000000000000000000000000000000000000000000000000000000000000113ecbe4a453269a0dd26069467fb5b5;
-tv[43]= 384'hffff00000000000000000000000000000000000000000000000000000000000097d0754fe68f11b9e375d070a608c884;
-tv[44]= 384'hffff800000000000000000000000000000000000000000000000000000000000c6a0b3e998d05068a5399778405200b4;
-tv[45]= 384'hffffc00000000000000000000000000000000000000000000000000000000000df556a33438db87bc41b1752c55e5e49;
-tv[46]= 384'hffffe0000000000000000000000000000000000000000000000000000000000090fb128d3a1af6e548521bb962bf1f05;
-tv[47]= 384'hfffff0000000000000000000000000000000000000000000000000000000000026298e9c1db517c215fadfb7d2a8d691;
-tv[48]= 384'hfffff80000000000000000000000000000000000000000000000000000000000a6cb761d61f8292d0df393a279ad0380;
-tv[49]= 384'hfffffc000000000000000000000000000000000000000000000000000000000012acd89b13cd5f8726e34d44fd486108;
-tv[50]= 384'hfffffe000000000000000000000000000000000000000000000000000000000095b1703fc57ba09fe0c3580febdd7ed4;
-tv[51]= 384'hffffff0000000000000000000000000000000000000000000000000000000000de11722d893e9f9121c381becc1da59a;
-tv[52]= 384'hffffff80000000000000000000000000000000000000000000000000000000006d114ccb27bf391012e8974c546d9bf2;
-tv[53]= 384'hffffffc0000000000000000000000000000000000000000000000000000000005ce37e17eb4646ecfac29b9cc38d9340;
-tv[54]= 384'hffffffe00000000000000000000000000000000000000000000000000000000018c1b6e2157122056d0243d8a165cddb;
-tv[55]= 384'hfffffff00000000000000000000000000000000000000000000000000000000099693e6a59d1366c74d823562d7e1431;
-tv[56]= 384'hfffffff8000000000000000000000000000000000000000000000000000000006c7c64dc84a8bba758ed17eb025a57e3;
-tv[57]= 384'hfffffffc00000000000000000000000000000000000000000000000000000000e17bc79f30eaab2fac2cbbe3458d687a;
-tv[58]= 384'hfffffffe000000000000000000000000000000000000000000000000000000001114bc2028009b923f0b01915ce5e7c4;
-tv[59]= 384'hffffffff000000000000000000000000000000000000000000000000000000009c28524a16a1e1c1452971caa8d13476;
-tv[60]= 384'hffffffff80000000000000000000000000000000000000000000000000000000ed62e16363638360fdd6ad62112794f0;
-tv[61]= 384'hffffffffc00000000000000000000000000000000000000000000000000000005a8688f0b2a2c16224c161658ffd4044;
-tv[62]= 384'hffffffffe000000000000000000000000000000000000000000000000000000023f710842b9bb9c32f26648c786807ca;
-tv[63]= 384'hfffffffff000000000000000000000000000000000000000000000000000000044a98bf11e163f632c47ec6a49683a89;
-tv[64]= 384'hfffffffff80000000000000000000000000000000000000000000000000000000f18aff94274696d9b61848bd50ac5e5;
-tv[65]= 384'hfffffffffc00000000000000000000000000000000000000000000000000000082408571c3e2424540207f833b6dda69;
-tv[66]= 384'hfffffffffe000000000000000000000000000000000000000000000000000000303ff996947f0c7d1f43c8f3027b9b75;
-tv[67]= 384'hffffffffff0000000000000000000000000000000000000000000000000000007df4daf4ad29a3615a9b6ece5c99518a;
-tv[68]= 384'hffffffffff800000000000000000000000000000000000000000000000000000c72954a48d0774db0b4971c526260415;
-tv[69]= 384'hffffffffffc000000000000000000000000000000000000000000000000000001df9b76112dc6531e07d2cfda04411f0;
-tv[70]= 384'hffffffffffe000000000000000000000000000000000000000000000000000008e4d8e699119e1fc87545a647fb1d34f;
-tv[71]= 384'hfffffffffff00000000000000000000000000000000000000000000000000000e6c4807ae11f36f091c57d9fb68548d1;
-tv[72]= 384'hfffffffffff800000000000000000000000000000000000000000000000000008ebf73aad49c82007f77a5c1ccec6ab4;
-tv[73]= 384'hfffffffffffc00000000000000000000000000000000000000000000000000004fb288cc2040049001d2c7585ad123fc;
-tv[74]= 384'hfffffffffffe000000000000000000000000000000000000000000000000000004497110efb9dceb13e2b13fb4465564;
-tv[75]= 384'hffffffffffff000000000000000000000000000000000000000000000000000075550e6cb5a88e49634c9ab69eda0430;
-tv[76]= 384'hffffffffffff8000000000000000000000000000000000000000000000000000b6768473ce9843ea66a81405dd50b345;
-tv[77]= 384'hffffffffffffc000000000000000000000000000000000000000000000000000cb2f430383f9084e03a653571e065de6;
-tv[78]= 384'hffffffffffffe000000000000000000000000000000000000000000000000000ff4e66c07bae3e79fb7d210847a3b0ba;
-tv[79]= 384'hfffffffffffff0000000000000000000000000000000000000000000000000007b90785125505fad59b13c186dd66ce3;
-tv[80]= 384'hfffffffffffff8000000000000000000000000000000000000000000000000008b527a6aebdaec9eaef8eda2cb7783e5;
-tv[81]= 384'hfffffffffffffc0000000000000000000000000000000000000000000000000043fdaf53ebbc9880c228617d6a9b548b;
-tv[82]= 384'hfffffffffffffe0000000000000000000000000000000000000000000000000053786104b9744b98f052c46f1c850d0b;
-tv[83]= 384'hffffffffffffff00000000000000000000000000000000000000000000000000b5ab3013dd1e61df06cbaf34ca2aee78;
-tv[84]= 384'hffffffffffffff800000000000000000000000000000000000000000000000007470469be9723030fdcc73a8cd4fbb10;
-tv[85]= 384'hffffffffffffffc0000000000000000000000000000000000000000000000000a35a63f5343ebe9ef8167bcb48ad122e;
-tv[86]= 384'hffffffffffffffe0000000000000000000000000000000000000000000000000fd8687f0757a210e9fdf181204c30863;
-tv[87]= 384'hfffffffffffffff00000000000000000000000000000000000000000000000007a181e84bd5457d26a88fbae96018fb0;
-tv[88]= 384'hfffffffffffffff8000000000000000000000000000000000000000000000000653317b9362b6f9b9e1a580e68d494b5;
-tv[89]= 384'hfffffffffffffffc000000000000000000000000000000000000000000000000995c9dc0b689f03c45867b5faa5c18d1;
-tv[90]= 384'hfffffffffffffffe00000000000000000000000000000000000000000000000077a4d96d56dda398b9aabecfc75729fd;
-tv[91]= 384'hffffffffffffffff00000000000000000000000000000000000000000000000084be19e053635f09f2665e7bae85b42d;
-tv[92]= 384'hffffffffffffffff80000000000000000000000000000000000000000000000032cd652842926aea4aa6137bb2be2b5e;
-tv[93]= 384'hffffffffffffffffc00000000000000000000000000000000000000000000000493d4a4f38ebb337d10aa84e9171a554;
-tv[94]= 384'hffffffffffffffffe00000000000000000000000000000000000000000000000d9bff7ff454b0ec5a4a2a69566e2cb84;
-tv[95]= 384'hfffffffffffffffff000000000000000000000000000000000000000000000003535d565ace3f31eb249ba2cc6765d7a;
-tv[96]= 384'hfffffffffffffffff80000000000000000000000000000000000000000000000f60e91fc3269eecf3231c6e9945697c6;
-tv[97]= 384'hfffffffffffffffffc0000000000000000000000000000000000000000000000ab69cfadf51f8e604d9cc37182f6635a;
-tv[98]= 384'hfffffffffffffffffe00000000000000000000000000000000000000000000007866373f24a0b6ed56e0d96fcdafb877;
-tv[99]= 384'hffffffffffffffffff00000000000000000000000000000000000000000000001ea448c2aac954f5d812e9d78494446a;
-tv[100]= 384'hffffffffffffffffff8000000000000000000000000000000000000000000000acc5599dd8ac02239a0fef4a36dd1668;
-tv[101]= 384'hffffffffffffffffffc000000000000000000000000000000000000000000000d8764468bb103828cf7e1473ce895073;
-tv[102]= 384'hffffffffffffffffffe0000000000000000000000000000000000000000000001b0d02893683b9f180458e4aa6b73982;
-tv[103]= 384'hfffffffffffffffffff00000000000000000000000000000000000000000000096d9b017d302df410a937dcdb8bb6e43;
-tv[104]= 384'hfffffffffffffffffff800000000000000000000000000000000000000000000ef1623cc44313cff440b1594a7e21cc6;
-tv[105]= 384'hfffffffffffffffffffc00000000000000000000000000000000000000000000284ca2fa35807b8b0ae4d19e11d7dbd7;
-tv[106]= 384'hfffffffffffffffffffe00000000000000000000000000000000000000000000f2e976875755f9401d54f36e2a23a594;
-tv[107]= 384'hffffffffffffffffffff00000000000000000000000000000000000000000000ec198a18e10e532403b7e20887c8dd80;
-tv[108]= 384'hffffffffffffffffffff80000000000000000000000000000000000000000000545d50ebd919e4a6949d96ad47e46a80;
-tv[109]= 384'hffffffffffffffffffffc0000000000000000000000000000000000000000000dbdfb527060e0a71009c7bb0c68f1d44;
-tv[110]= 384'hffffffffffffffffffffe00000000000000000000000000000000000000000009cfa1322ea33da2173a024f2ff0d896d;
-tv[111]= 384'hfffffffffffffffffffff00000000000000000000000000000000000000000008785b1a75b0f3bd958dcd0e29318c521;
-tv[112]= 384'hfffffffffffffffffffff800000000000000000000000000000000000000000038f67b9e98e4a97b6df030a9fcdd0104;
-tv[113]= 384'hfffffffffffffffffffffc000000000000000000000000000000000000000000192afffb2c880e82b05926d0fc6c448b;
-tv[114]= 384'hfffffffffffffffffffffe0000000000000000000000000000000000000000006a7980ce7b105cf530952d74daaf798c;
-tv[115]= 384'hffffffffffffffffffffff000000000000000000000000000000000000000000ea3695e1351b9d6858bd958cf513ef6c;
-tv[116]= 384'hffffffffffffffffffffff8000000000000000000000000000000000000000006da0490ba0ba0343b935681d2cce5ba1;
-tv[117]= 384'hffffffffffffffffffffffc00000000000000000000000000000000000000000f0ea23af08534011c60009ab29ada2f1;
-tv[118]= 384'hffffffffffffffffffffffe00000000000000000000000000000000000000000ff13806cf19cc38721554d7c0fcdcd4b;
-tv[119]= 384'hfffffffffffffffffffffff000000000000000000000000000000000000000006838af1f4f69bae9d85dd188dcdf0688;
-tv[120]= 384'hfffffffffffffffffffffff8000000000000000000000000000000000000000036cf44c92d550bfb1ed28ef583ddf5d7;
-tv[121]= 384'hfffffffffffffffffffffffc0000000000000000000000000000000000000000d06e3195b5376f109d5c4ec6c5d62ced;
-tv[122]= 384'hfffffffffffffffffffffffe0000000000000000000000000000000000000000c440de014d3d610707279b13242a5c36;
-tv[123]= 384'hffffffffffffffffffffffff0000000000000000000000000000000000000000f0c5c6ffa5e0bd3a94c88f6b6f7c16b9;
-tv[124]= 384'hffffffffffffffffffffffff80000000000000000000000000000000000000003e40c3901cd7effc22bffc35dee0b4d9;
-tv[125]= 384'hffffffffffffffffffffffffc000000000000000000000000000000000000000b63305c72bedfab97382c406d0c49bc6;
-tv[126]= 384'hffffffffffffffffffffffffe00000000000000000000000000000000000000036bbaab22a6bd4925a99a2b408d2dbae;
-tv[127]= 384'hfffffffffffffffffffffffff000000000000000000000000000000000000000307c5b8fcd0533ab98bc51e27a6ce461;
-tv[128]= 384'hfffffffffffffffffffffffff800000000000000000000000000000000000000829c04ff4c07513c0b3ef05c03e337b5;
-tv[129]= 384'hfffffffffffffffffffffffffc00000000000000000000000000000000000000f17af0e895dda5eb98efc68066e84c54;
-tv[130]= 384'hfffffffffffffffffffffffffe00000000000000000000000000000000000000277167f3812afff1ffacb4a934379fc3;
-tv[131]= 384'hffffffffffffffffffffffffff000000000000000000000000000000000000002cb1dc3a9c72972e425ae2ef3eb597cd;
-tv[132]= 384'hffffffffffffffffffffffffff8000000000000000000000000000000000000036aeaa3a213e968d4b5b679d3a2c97fe;
-tv[133]= 384'hffffffffffffffffffffffffffc00000000000000000000000000000000000009241daca4fdd034a82372db50e1a0f3f;
-tv[134]= 384'hffffffffffffffffffffffffffe0000000000000000000000000000000000000c14574d9cd00cf2b5a7f77e53cd57885;
-tv[135]= 384'hfffffffffffffffffffffffffff0000000000000000000000000000000000000793de39236570aba83ab9b737cb521c9;
-tv[136]= 384'hfffffffffffffffffffffffffff800000000000000000000000000000000000016591c0f27d60e29b85a96c33861a7ef;
-tv[137]= 384'hfffffffffffffffffffffffffffc00000000000000000000000000000000000044fb5c4d4f5cb79be5c174a3b1c97348;
-tv[138]= 384'hfffffffffffffffffffffffffffe000000000000000000000000000000000000674d2b61633d162be59dde04222f4740;
-tv[139]= 384'hffffffffffffffffffffffffffff000000000000000000000000000000000000b4750ff263a65e1f9e924ccfd98f3e37;
-tv[140]= 384'hffffffffffffffffffffffffffff80000000000000000000000000000000000062d0662d6eaeddedebae7f7ea3a4f6b6;
-tv[141]= 384'hffffffffffffffffffffffffffffc0000000000000000000000000000000000070c46bb30692be657f7eaa93ebad9897;
-tv[142]= 384'hffffffffffffffffffffffffffffe00000000000000000000000000000000000323994cfb9da285a5d9642e1759b224a;
-tv[143]= 384'hfffffffffffffffffffffffffffff000000000000000000000000000000000001dbf57877b7b17385c85d0b54851e371;
-tv[144]= 384'hfffffffffffffffffffffffffffff80000000000000000000000000000000000dfa5c097cdc1532ac071d57b1d28d1bd;
-tv[145]= 384'hfffffffffffffffffffffffffffffc00000000000000000000000000000000003a0c53fa37311fc10bd2a9981f513174;
-tv[146]= 384'hfffffffffffffffffffffffffffffe0000000000000000000000000000000000ba4f970c0a25c41814bdae2e506be3b4;
-tv[147]= 384'hffffffffffffffffffffffffffffff00000000000000000000000000000000002dce3acb727cd13ccd76d425ea56e4f6;
-tv[148]= 384'hffffffffffffffffffffffffffffff80000000000000000000000000000000005160474d504b9b3eefb68d35f245f4b3;
-tv[149]= 384'hffffffffffffffffffffffffffffffc00000000000000000000000000000000041a8a947766635dec37553d9a6c0cbb7;
-tv[150]= 384'hffffffffffffffffffffffffffffffe00000000000000000000000000000000025d6cfe6881f2bf497dd14cd4ddf445b;
-tv[151]= 384'hfffffffffffffffffffffffffffffff00000000000000000000000000000000041c78c135ed9e98c096640647265da1e;
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-
-
-for(n=0;n<284;n=n+1)
- begin
- @(posedge clk);
- #1;
- kld = 1;
- @(posedge clk);
- #1;
- kld = 0;
- @(posedge clk);
-
- while(!done) @(posedge clk);
-
- //$display("INFO: (a) Vector %0d: xpected %x, Got %x %t", n, ciph, text_out, $time);
-
- if(text_out != ciph | (|text_out)==1'bx)
- begin
- $display("ERROR: (a) Vector %0d mismatch. Expected %x, Got %x",
- n, ciph, text_out);
- error_cnt = error_cnt + 1;
- end
-
-
- while(!done2) @(posedge clk);
-
- //$display("INFO: (b) Vector %0d: xpected %x, Got %x", n, plain, text_out2);
-
- if(text_out2 != plain | (|text_out2)==1'bx)
- begin
- $display("ERROR: (b) Vector %0d mismatch. Expected %x, Got %x",
- n, plain, text_out2);
- error_cnt = error_cnt + 1;
- end
-
- @(posedge clk);
- #1;
- end
-
-
- $display("");
- $display("");
- $display("Test Done. Found %0d Errors.", error_cnt);
- $display("");
- $display("");
- repeat(10) @(posedge clk);
- $finish;
-end
-
-assign tmp = tv[n];
-assign key = kld ? tmp[383:256] : 128'hx;
-assign text_in = kld ? tmp[255:128] : 128'hx;
-assign plain = tmp[255:128];
-assign ciph = tmp[127:0];
-
-always #5 clk = ~clk;
-
-aes_cipher_top u0(
- .clk( clk ),
- .rst( rst ),
- .ld( kld ),
- .done( done ),
- .key( key ),
- .text_in( text_in ),
- .text_out( text_out )
- );
-
-aes_inv_cipher_top u1(
- .clk( clk ),
- .rst( rst ),
- .kld( kld ),
- .ld( done ),
- .done( done2 ),
- .key( key ),
- .text_in( text_out ),
- .text_out( text_out2 )
- );
-
-endmodule
-
-
Index: trunk/rtl/verilog/aes_key_expand_128.v
===================================================================
--- trunk/rtl/verilog/aes_key_expand_128.v (revision 5)
+++ trunk/rtl/verilog/aes_key_expand_128.v (nonexistent)
@@ -1,84 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// AES Key Expand Block (for 128 bit keys) ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: aes_key_expand_128.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
-//
-// $Date: 2002-11-09 11:22:38 $
-// $Revision: 1.1.1.1 $
-// $Author: rudi $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
-input clk;
-input kld;
-input [127:0] key;
-output [31:0] wo_0, wo_1, wo_2, wo_3;
-reg [31:0] w[3:0];
-wire [31:0] tmp_w;
-wire [31:0] subword;
-wire [31:0] rcon;
-
-assign wo_0 = w[0];
-assign wo_1 = w[1];
-assign wo_2 = w[2];
-assign wo_3 = w[3];
-always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
-always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
-always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
-always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
-assign tmp_w = w[3];
-aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
-aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
-aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
-aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
-aes_rcon r0( .clk(clk), .kld(kld), .out(rcon));
-endmodule
-
Index: trunk/rtl/verilog/aes_rcon.v
===================================================================
--- trunk/rtl/verilog/aes_rcon.v (revision 5)
+++ trunk/rtl/verilog/aes_rcon.v (nonexistent)
@@ -1,93 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// AES RCON Block ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: aes_rcon.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
-//
-// $Date: 2002-11-09 11:22:38 $
-// $Revision: 1.1.1.1 $
-// $Author: rudi $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module aes_rcon(clk, kld, out);
-input clk;
-input kld;
-output [31:0] out;
-reg [31:0] out;
-reg [3:0] rcnt;
-wire [3:0] rcnt_next;
-
-always @(posedge clk)
- if(kld) out <= #1 32'h01_00_00_00;
- else out <= #1 frcon(rcnt_next);
-
-assign rcnt_next = rcnt + 4'h1;
-always @(posedge clk)
- if(kld) rcnt <= #1 4'h0;
- else rcnt <= #1 rcnt_next;
-
-function [31:0] frcon;
-input [3:0] i;
-case(i) // synopsys parallel_case
- 4'h0: frcon=32'h01_00_00_00;
- 4'h1: frcon=32'h02_00_00_00;
- 4'h2: frcon=32'h04_00_00_00;
- 4'h3: frcon=32'h08_00_00_00;
- 4'h4: frcon=32'h10_00_00_00;
- 4'h5: frcon=32'h20_00_00_00;
- 4'h6: frcon=32'h40_00_00_00;
- 4'h7: frcon=32'h80_00_00_00;
- 4'h8: frcon=32'h1b_00_00_00;
- 4'h9: frcon=32'h36_00_00_00;
- default: frcon=32'h00_00_00_00;
-endcase
-endfunction
-
-endmodule
Index: trunk/rtl/verilog/aes_inv_sbox.v
===================================================================
--- trunk/rtl/verilog/aes_inv_sbox.v (revision 5)
+++ trunk/rtl/verilog/aes_inv_sbox.v (nonexistent)
@@ -1,325 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// AES Inverse SBOX (ROM) ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: aes_inv_sbox.v,v 1.1.1.1 2002-11-09 11:22:55 rudi Exp $
-//
-// $Date: 2002-11-09 11:22:55 $
-// $Revision: 1.1.1.1 $
-// $Author: rudi $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module aes_inv_sbox(a,d);
-input [7:0] a;
-output [7:0] d;
-reg [7:0] d;
-
-always @(a)
- case(a) // synopsys full_case parallel_case
- 8'h00: d=8'h52;
- 8'h01: d=8'h09;
- 8'h02: d=8'h6a;
- 8'h03: d=8'hd5;
- 8'h04: d=8'h30;
- 8'h05: d=8'h36;
- 8'h06: d=8'ha5;
- 8'h07: d=8'h38;
- 8'h08: d=8'hbf;
- 8'h09: d=8'h40;
- 8'h0a: d=8'ha3;
- 8'h0b: d=8'h9e;
- 8'h0c: d=8'h81;
- 8'h0d: d=8'hf3;
- 8'h0e: d=8'hd7;
- 8'h0f: d=8'hfb;
- 8'h10: d=8'h7c;
- 8'h11: d=8'he3;
- 8'h12: d=8'h39;
- 8'h13: d=8'h82;
- 8'h14: d=8'h9b;
- 8'h15: d=8'h2f;
- 8'h16: d=8'hff;
- 8'h17: d=8'h87;
- 8'h18: d=8'h34;
- 8'h19: d=8'h8e;
- 8'h1a: d=8'h43;
- 8'h1b: d=8'h44;
- 8'h1c: d=8'hc4;
- 8'h1d: d=8'hde;
- 8'h1e: d=8'he9;
- 8'h1f: d=8'hcb;
- 8'h20: d=8'h54;
- 8'h21: d=8'h7b;
- 8'h22: d=8'h94;
- 8'h23: d=8'h32;
- 8'h24: d=8'ha6;
- 8'h25: d=8'hc2;
- 8'h26: d=8'h23;
- 8'h27: d=8'h3d;
- 8'h28: d=8'hee;
- 8'h29: d=8'h4c;
- 8'h2a: d=8'h95;
- 8'h2b: d=8'h0b;
- 8'h2c: d=8'h42;
- 8'h2d: d=8'hfa;
- 8'h2e: d=8'hc3;
- 8'h2f: d=8'h4e;
- 8'h30: d=8'h08;
- 8'h31: d=8'h2e;
- 8'h32: d=8'ha1;
- 8'h33: d=8'h66;
- 8'h34: d=8'h28;
- 8'h35: d=8'hd9;
- 8'h36: d=8'h24;
- 8'h37: d=8'hb2;
- 8'h38: d=8'h76;
- 8'h39: d=8'h5b;
- 8'h3a: d=8'ha2;
- 8'h3b: d=8'h49;
- 8'h3c: d=8'h6d;
- 8'h3d: d=8'h8b;
- 8'h3e: d=8'hd1;
- 8'h3f: d=8'h25;
- 8'h40: d=8'h72;
- 8'h41: d=8'hf8;
- 8'h42: d=8'hf6;
- 8'h43: d=8'h64;
- 8'h44: d=8'h86;
- 8'h45: d=8'h68;
- 8'h46: d=8'h98;
- 8'h47: d=8'h16;
- 8'h48: d=8'hd4;
- 8'h49: d=8'ha4;
- 8'h4a: d=8'h5c;
- 8'h4b: d=8'hcc;
- 8'h4c: d=8'h5d;
- 8'h4d: d=8'h65;
- 8'h4e: d=8'hb6;
- 8'h4f: d=8'h92;
- 8'h50: d=8'h6c;
- 8'h51: d=8'h70;
- 8'h52: d=8'h48;
- 8'h53: d=8'h50;
- 8'h54: d=8'hfd;
- 8'h55: d=8'hed;
- 8'h56: d=8'hb9;
- 8'h57: d=8'hda;
- 8'h58: d=8'h5e;
- 8'h59: d=8'h15;
- 8'h5a: d=8'h46;
- 8'h5b: d=8'h57;
- 8'h5c: d=8'ha7;
- 8'h5d: d=8'h8d;
- 8'h5e: d=8'h9d;
- 8'h5f: d=8'h84;
- 8'h60: d=8'h90;
- 8'h61: d=8'hd8;
- 8'h62: d=8'hab;
- 8'h63: d=8'h00;
- 8'h64: d=8'h8c;
- 8'h65: d=8'hbc;
- 8'h66: d=8'hd3;
- 8'h67: d=8'h0a;
- 8'h68: d=8'hf7;
- 8'h69: d=8'he4;
- 8'h6a: d=8'h58;
- 8'h6b: d=8'h05;
- 8'h6c: d=8'hb8;
- 8'h6d: d=8'hb3;
- 8'h6e: d=8'h45;
- 8'h6f: d=8'h06;
- 8'h70: d=8'hd0;
- 8'h71: d=8'h2c;
- 8'h72: d=8'h1e;
- 8'h73: d=8'h8f;
- 8'h74: d=8'hca;
- 8'h75: d=8'h3f;
- 8'h76: d=8'h0f;
- 8'h77: d=8'h02;
- 8'h78: d=8'hc1;
- 8'h79: d=8'haf;
- 8'h7a: d=8'hbd;
- 8'h7b: d=8'h03;
- 8'h7c: d=8'h01;
- 8'h7d: d=8'h13;
- 8'h7e: d=8'h8a;
- 8'h7f: d=8'h6b;
- 8'h80: d=8'h3a;
- 8'h81: d=8'h91;
- 8'h82: d=8'h11;
- 8'h83: d=8'h41;
- 8'h84: d=8'h4f;
- 8'h85: d=8'h67;
- 8'h86: d=8'hdc;
- 8'h87: d=8'hea;
- 8'h88: d=8'h97;
- 8'h89: d=8'hf2;
- 8'h8a: d=8'hcf;
- 8'h8b: d=8'hce;
- 8'h8c: d=8'hf0;
- 8'h8d: d=8'hb4;
- 8'h8e: d=8'he6;
- 8'h8f: d=8'h73;
- 8'h90: d=8'h96;
- 8'h91: d=8'hac;
- 8'h92: d=8'h74;
- 8'h93: d=8'h22;
- 8'h94: d=8'he7;
- 8'h95: d=8'had;
- 8'h96: d=8'h35;
- 8'h97: d=8'h85;
- 8'h98: d=8'he2;
- 8'h99: d=8'hf9;
- 8'h9a: d=8'h37;
- 8'h9b: d=8'he8;
- 8'h9c: d=8'h1c;
- 8'h9d: d=8'h75;
- 8'h9e: d=8'hdf;
- 8'h9f: d=8'h6e;
- 8'ha0: d=8'h47;
- 8'ha1: d=8'hf1;
- 8'ha2: d=8'h1a;
- 8'ha3: d=8'h71;
- 8'ha4: d=8'h1d;
- 8'ha5: d=8'h29;
- 8'ha6: d=8'hc5;
- 8'ha7: d=8'h89;
- 8'ha8: d=8'h6f;
- 8'ha9: d=8'hb7;
- 8'haa: d=8'h62;
- 8'hab: d=8'h0e;
- 8'hac: d=8'haa;
- 8'had: d=8'h18;
- 8'hae: d=8'hbe;
- 8'haf: d=8'h1b;
- 8'hb0: d=8'hfc;
- 8'hb1: d=8'h56;
- 8'hb2: d=8'h3e;
- 8'hb3: d=8'h4b;
- 8'hb4: d=8'hc6;
- 8'hb5: d=8'hd2;
- 8'hb6: d=8'h79;
- 8'hb7: d=8'h20;
- 8'hb8: d=8'h9a;
- 8'hb9: d=8'hdb;
- 8'hba: d=8'hc0;
- 8'hbb: d=8'hfe;
- 8'hbc: d=8'h78;
- 8'hbd: d=8'hcd;
- 8'hbe: d=8'h5a;
- 8'hbf: d=8'hf4;
- 8'hc0: d=8'h1f;
- 8'hc1: d=8'hdd;
- 8'hc2: d=8'ha8;
- 8'hc3: d=8'h33;
- 8'hc4: d=8'h88;
- 8'hc5: d=8'h07;
- 8'hc6: d=8'hc7;
- 8'hc7: d=8'h31;
- 8'hc8: d=8'hb1;
- 8'hc9: d=8'h12;
- 8'hca: d=8'h10;
- 8'hcb: d=8'h59;
- 8'hcc: d=8'h27;
- 8'hcd: d=8'h80;
- 8'hce: d=8'hec;
- 8'hcf: d=8'h5f;
- 8'hd0: d=8'h60;
- 8'hd1: d=8'h51;
- 8'hd2: d=8'h7f;
- 8'hd3: d=8'ha9;
- 8'hd4: d=8'h19;
- 8'hd5: d=8'hb5;
- 8'hd6: d=8'h4a;
- 8'hd7: d=8'h0d;
- 8'hd8: d=8'h2d;
- 8'hd9: d=8'he5;
- 8'hda: d=8'h7a;
- 8'hdb: d=8'h9f;
- 8'hdc: d=8'h93;
- 8'hdd: d=8'hc9;
- 8'hde: d=8'h9c;
- 8'hdf: d=8'hef;
- 8'he0: d=8'ha0;
- 8'he1: d=8'he0;
- 8'he2: d=8'h3b;
- 8'he3: d=8'h4d;
- 8'he4: d=8'hae;
- 8'he5: d=8'h2a;
- 8'he6: d=8'hf5;
- 8'he7: d=8'hb0;
- 8'he8: d=8'hc8;
- 8'he9: d=8'heb;
- 8'hea: d=8'hbb;
- 8'heb: d=8'h3c;
- 8'hec: d=8'h83;
- 8'hed: d=8'h53;
- 8'hee: d=8'h99;
- 8'hef: d=8'h61;
- 8'hf0: d=8'h17;
- 8'hf1: d=8'h2b;
- 8'hf2: d=8'h04;
- 8'hf3: d=8'h7e;
- 8'hf4: d=8'hba;
- 8'hf5: d=8'h77;
- 8'hf6: d=8'hd6;
- 8'hf7: d=8'h26;
- 8'hf8: d=8'he1;
- 8'hf9: d=8'h69;
- 8'hfa: d=8'h14;
- 8'hfb: d=8'h63;
- 8'hfc: d=8'h55;
- 8'hfd: d=8'h21;
- 8'hfe: d=8'h0c;
- 8'hff: d=8'h7d;
- endcase
-endmodule
-
-
Index: trunk/rtl/verilog/aes_inv_cipher_top.v
===================================================================
--- trunk/rtl/verilog/aes_inv_cipher_top.v (revision 5)
+++ trunk/rtl/verilog/aes_inv_cipher_top.v (nonexistent)
@@ -1,324 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// AES Inverse Cipher Top Level ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: aes_inv_cipher_top.v,v 1.1.1.1 2002-11-09 11:22:53 rudi Exp $
-//
-// $Date: 2002-11-09 11:22:53 $
-// $Revision: 1.1.1.1 $
-// $Author: rudi $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module aes_inv_cipher_top(clk, rst, kld, ld, done, key, text_in, text_out );
-input clk, rst;
-input kld, ld;
-output done;
-input [127:0] key;
-input [127:0] text_in;
-output [127:0] text_out;
-
-////////////////////////////////////////////////////////////////////
-//
-// Local Wires
-//
-
-wire [31:0] wk0, wk1, wk2, wk3;
-reg [31:0] w0, w1, w2, w3;
-reg [127:0] text_in_r;
-reg [127:0] text_out;
-reg [7:0] sa00, sa01, sa02, sa03;
-reg [7:0] sa10, sa11, sa12, sa13;
-reg [7:0] sa20, sa21, sa22, sa23;
-reg [7:0] sa30, sa31, sa32, sa33;
-wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
-wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
-wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
-wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
-wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
-wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
-wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
-wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
-wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
-wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
-wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
-wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
-wire [7:0] sa00_ark, sa01_ark, sa02_ark, sa03_ark;
-wire [7:0] sa10_ark, sa11_ark, sa12_ark, sa13_ark;
-wire [7:0] sa20_ark, sa21_ark, sa22_ark, sa23_ark;
-wire [7:0] sa30_ark, sa31_ark, sa32_ark, sa33_ark;
-reg ld_r, go, done;
-reg [3:0] dcnt;
-
-////////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-always @(posedge clk)
- if(!rst) dcnt <= #1 4'h0;
- else
- if(done) dcnt <= #1 4'h0;
- else
- if(ld) dcnt <= #1 4'h1;
- else
- if(go) dcnt <= #1 dcnt + 4'h1;
-
-always @(posedge clk) done <= #1 (dcnt==4'hb) & !ld;
-
-always @(posedge clk)
- if(!rst) go <= #1 1'b0;
- else
- if(ld) go <= #1 1'b1;
- else
- if(done) go <= #1 1'b0;
-
-always @(posedge clk) if(ld) text_in_r <= #1 text_in;
-
-always @(posedge clk) ld_r <= #1 ld;
-
-////////////////////////////////////////////////////////////////////
-//
-// Initial Permutation
-//
-
-always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
-always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
-always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
-always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
-always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
-always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
-always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
-always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
-always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
-always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
-always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
-always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
-always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
-always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
-always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
-always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
-
-////////////////////////////////////////////////////////////////////
-//
-// Round Permutations
-//
-
-assign sa00_sr = sa00;
-assign sa01_sr = sa01;
-assign sa02_sr = sa02;
-assign sa03_sr = sa03;
-assign sa10_sr = sa13;
-assign sa11_sr = sa10;
-assign sa12_sr = sa11;
-assign sa13_sr = sa12;
-assign sa20_sr = sa22;
-assign sa21_sr = sa23;
-assign sa22_sr = sa20;
-assign sa23_sr = sa21;
-assign sa30_sr = sa31;
-assign sa31_sr = sa32;
-assign sa32_sr = sa33;
-assign sa33_sr = sa30;
-assign sa00_ark = sa00_sub ^ w0[31:24];
-assign sa01_ark = sa01_sub ^ w1[31:24];
-assign sa02_ark = sa02_sub ^ w2[31:24];
-assign sa03_ark = sa03_sub ^ w3[31:24];
-assign sa10_ark = sa10_sub ^ w0[23:16];
-assign sa11_ark = sa11_sub ^ w1[23:16];
-assign sa12_ark = sa12_sub ^ w2[23:16];
-assign sa13_ark = sa13_sub ^ w3[23:16];
-assign sa20_ark = sa20_sub ^ w0[15:08];
-assign sa21_ark = sa21_sub ^ w1[15:08];
-assign sa22_ark = sa22_sub ^ w2[15:08];
-assign sa23_ark = sa23_sub ^ w3[15:08];
-assign sa30_ark = sa30_sub ^ w0[07:00];
-assign sa31_ark = sa31_sub ^ w1[07:00];
-assign sa32_ark = sa32_sub ^ w2[07:00];
-assign sa33_ark = sa33_sub ^ w3[07:00];
-assign {sa00_next, sa10_next, sa20_next, sa30_next} = inv_mix_col(sa00_ark,sa10_ark,sa20_ark,sa30_ark);
-assign {sa01_next, sa11_next, sa21_next, sa31_next} = inv_mix_col(sa01_ark,sa11_ark,sa21_ark,sa31_ark);
-assign {sa02_next, sa12_next, sa22_next, sa32_next} = inv_mix_col(sa02_ark,sa12_ark,sa22_ark,sa32_ark);
-assign {sa03_next, sa13_next, sa23_next, sa33_next} = inv_mix_col(sa03_ark,sa13_ark,sa23_ark,sa33_ark);
-
-////////////////////////////////////////////////////////////////////
-//
-// Final Text Output
-//
-
-always @(posedge clk) text_out[127:120] <= #1 sa00_ark;
-always @(posedge clk) text_out[095:088] <= #1 sa01_ark;
-always @(posedge clk) text_out[063:056] <= #1 sa02_ark;
-always @(posedge clk) text_out[031:024] <= #1 sa03_ark;
-always @(posedge clk) text_out[119:112] <= #1 sa10_ark;
-always @(posedge clk) text_out[087:080] <= #1 sa11_ark;
-always @(posedge clk) text_out[055:048] <= #1 sa12_ark;
-always @(posedge clk) text_out[023:016] <= #1 sa13_ark;
-always @(posedge clk) text_out[111:104] <= #1 sa20_ark;
-always @(posedge clk) text_out[079:072] <= #1 sa21_ark;
-always @(posedge clk) text_out[047:040] <= #1 sa22_ark;
-always @(posedge clk) text_out[015:008] <= #1 sa23_ark;
-always @(posedge clk) text_out[103:096] <= #1 sa30_ark;
-always @(posedge clk) text_out[071:064] <= #1 sa31_ark;
-always @(posedge clk) text_out[039:032] <= #1 sa32_ark;
-always @(posedge clk) text_out[007:000] <= #1 sa33_ark;
-
-////////////////////////////////////////////////////////////////////
-//
-// Generic Functions
-//
-
-function [31:0] inv_mix_col;
-input [7:0] s0,s1,s2,s3;
-begin
-inv_mix_col[31:24]=pmul_e(s0)^pmul_b(s1)^pmul_d(s2)^pmul_9(s3);
-inv_mix_col[23:16]=pmul_9(s0)^pmul_e(s1)^pmul_b(s2)^pmul_d(s3);
-inv_mix_col[15:08]=pmul_d(s0)^pmul_9(s1)^pmul_e(s2)^pmul_b(s3);
-inv_mix_col[07:00]=pmul_b(s0)^pmul_d(s1)^pmul_9(s2)^pmul_e(s3);
-end
-endfunction
-
-// Some synthesis tools don't like xtime being called recursevly ...
-function [7:0] pmul_e;
-input [7:0] b;
-reg [7:0] two,four,eight;
-begin
-two=xtime(b);four=xtime(two);eight=xtime(four);pmul_e=eight^four^two;
-end
-endfunction
-
-function [7:0] pmul_9;
-input [7:0] b;
-reg [7:0] two,four,eight;
-begin
-two=xtime(b);four=xtime(two);eight=xtime(four);pmul_9=eight^b;
-end
-endfunction
-
-function [7:0] pmul_d;
-input [7:0] b;
-reg [7:0] two,four,eight;
-begin
-two=xtime(b);four=xtime(two);eight=xtime(four);pmul_d=eight^four^b;
-end
-endfunction
-
-function [7:0] pmul_b;
-input [7:0] b;
-reg [7:0] two,four,eight;
-begin
-two=xtime(b);four=xtime(two);eight=xtime(four);pmul_b=eight^two^b;
-end
-endfunction
-
-function [7:0] xtime;
-input [7:0] b;xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
-endfunction
-
-////////////////////////////////////////////////////////////////////
-//
-// Key Buffer
-//
-
-reg [127:0] kb[10:0];
-reg [3:0] kcnt;
-reg kdone;
-reg kb_ld;
-
-always @(posedge clk)
- if(!rst) kcnt <= #1 4'ha;
- else
- if(kld) kcnt <= #1 4'ha;
- else
- if(kb_ld) kcnt <= #1 kcnt - 4'h1;
-
-always @(posedge clk)
- if(!rst) kb_ld <= #1 1'b0;
- else
- if(kld) kb_ld <= #1 1'b1;
- else
- if(kcnt==4'h0) kb_ld <= #1 1'b0;
-
-always @(posedge clk) kdone <= #1 (kcnt==4'h0) & !kld;
-always @(posedge clk) if(kb_ld) kb[kcnt] <= #1 {wk3, wk2, wk1, wk0};
-always @(posedge clk) {w3, w2, w1, w0} <= #1 kb[dcnt];
-
-////////////////////////////////////////////////////////////////////
-//
-// Modules
-//
-
-aes_key_expand_128 u0(
- .clk( clk ),
- .kld( kld ),
- .key( key ),
- .wo_0( wk0 ),
- .wo_1( wk1 ),
- .wo_2( wk2 ),
- .wo_3( wk3 ));
-
-aes_inv_sbox us00( .a( sa00_sr ), .d( sa00_sub ));
-aes_inv_sbox us01( .a( sa01_sr ), .d( sa01_sub ));
-aes_inv_sbox us02( .a( sa02_sr ), .d( sa02_sub ));
-aes_inv_sbox us03( .a( sa03_sr ), .d( sa03_sub ));
-aes_inv_sbox us10( .a( sa10_sr ), .d( sa10_sub ));
-aes_inv_sbox us11( .a( sa11_sr ), .d( sa11_sub ));
-aes_inv_sbox us12( .a( sa12_sr ), .d( sa12_sub ));
-aes_inv_sbox us13( .a( sa13_sr ), .d( sa13_sub ));
-aes_inv_sbox us20( .a( sa20_sr ), .d( sa20_sub ));
-aes_inv_sbox us21( .a( sa21_sr ), .d( sa21_sub ));
-aes_inv_sbox us22( .a( sa22_sr ), .d( sa22_sub ));
-aes_inv_sbox us23( .a( sa23_sr ), .d( sa23_sub ));
-aes_inv_sbox us30( .a( sa30_sr ), .d( sa30_sub ));
-aes_inv_sbox us31( .a( sa31_sr ), .d( sa31_sub ));
-aes_inv_sbox us32( .a( sa32_sr ), .d( sa32_sub ));
-aes_inv_sbox us33( .a( sa33_sr ), .d( sa33_sub ));
-
-endmodule
-
Index: trunk/rtl/verilog/aes_sbox.v
===================================================================
--- trunk/rtl/verilog/aes_sbox.v (revision 5)
+++ trunk/rtl/verilog/aes_sbox.v (nonexistent)
@@ -1,326 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// AES SBOX (ROM) ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: aes_sbox.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
-//
-// $Date: 2002-11-09 11:22:38 $
-// $Revision: 1.1.1.1 $
-// $Author: rudi $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module aes_sbox(a,d);
-input [7:0] a;
-output [7:0] d;
-reg [7:0] d;
-
-always @(a)
- case(a) // synopsys full_case parallel_case
- 8'h00: d=8'h63;
- 8'h01: d=8'h7c;
- 8'h02: d=8'h77;
- 8'h03: d=8'h7b;
- 8'h04: d=8'hf2;
- 8'h05: d=8'h6b;
- 8'h06: d=8'h6f;
- 8'h07: d=8'hc5;
- 8'h08: d=8'h30;
- 8'h09: d=8'h01;
- 8'h0a: d=8'h67;
- 8'h0b: d=8'h2b;
- 8'h0c: d=8'hfe;
- 8'h0d: d=8'hd7;
- 8'h0e: d=8'hab;
- 8'h0f: d=8'h76;
- 8'h10: d=8'hca;
- 8'h11: d=8'h82;
- 8'h12: d=8'hc9;
- 8'h13: d=8'h7d;
- 8'h14: d=8'hfa;
- 8'h15: d=8'h59;
- 8'h16: d=8'h47;
- 8'h17: d=8'hf0;
- 8'h18: d=8'had;
- 8'h19: d=8'hd4;
- 8'h1a: d=8'ha2;
- 8'h1b: d=8'haf;
- 8'h1c: d=8'h9c;
- 8'h1d: d=8'ha4;
- 8'h1e: d=8'h72;
- 8'h1f: d=8'hc0;
- 8'h20: d=8'hb7;
- 8'h21: d=8'hfd;
- 8'h22: d=8'h93;
- 8'h23: d=8'h26;
- 8'h24: d=8'h36;
- 8'h25: d=8'h3f;
- 8'h26: d=8'hf7;
- 8'h27: d=8'hcc;
- 8'h28: d=8'h34;
- 8'h29: d=8'ha5;
- 8'h2a: d=8'he5;
- 8'h2b: d=8'hf1;
- 8'h2c: d=8'h71;
- 8'h2d: d=8'hd8;
- 8'h2e: d=8'h31;
- 8'h2f: d=8'h15;
- 8'h30: d=8'h04;
- 8'h31: d=8'hc7;
- 8'h32: d=8'h23;
- 8'h33: d=8'hc3;
- 8'h34: d=8'h18;
- 8'h35: d=8'h96;
- 8'h36: d=8'h05;
- 8'h37: d=8'h9a;
- 8'h38: d=8'h07;
- 8'h39: d=8'h12;
- 8'h3a: d=8'h80;
- 8'h3b: d=8'he2;
- 8'h3c: d=8'heb;
- 8'h3d: d=8'h27;
- 8'h3e: d=8'hb2;
- 8'h3f: d=8'h75;
- 8'h40: d=8'h09;
- 8'h41: d=8'h83;
- 8'h42: d=8'h2c;
- 8'h43: d=8'h1a;
- 8'h44: d=8'h1b;
- 8'h45: d=8'h6e;
- 8'h46: d=8'h5a;
- 8'h47: d=8'ha0;
- 8'h48: d=8'h52;
- 8'h49: d=8'h3b;
- 8'h4a: d=8'hd6;
- 8'h4b: d=8'hb3;
- 8'h4c: d=8'h29;
- 8'h4d: d=8'he3;
- 8'h4e: d=8'h2f;
- 8'h4f: d=8'h84;
- 8'h50: d=8'h53;
- 8'h51: d=8'hd1;
- 8'h52: d=8'h00;
- 8'h53: d=8'hed;
- 8'h54: d=8'h20;
- 8'h55: d=8'hfc;
- 8'h56: d=8'hb1;
- 8'h57: d=8'h5b;
- 8'h58: d=8'h6a;
- 8'h59: d=8'hcb;
- 8'h5a: d=8'hbe;
- 8'h5b: d=8'h39;
- 8'h5c: d=8'h4a;
- 8'h5d: d=8'h4c;
- 8'h5e: d=8'h58;
- 8'h5f: d=8'hcf;
- 8'h60: d=8'hd0;
- 8'h61: d=8'hef;
- 8'h62: d=8'haa;
- 8'h63: d=8'hfb;
- 8'h64: d=8'h43;
- 8'h65: d=8'h4d;
- 8'h66: d=8'h33;
- 8'h67: d=8'h85;
- 8'h68: d=8'h45;
- 8'h69: d=8'hf9;
- 8'h6a: d=8'h02;
- 8'h6b: d=8'h7f;
- 8'h6c: d=8'h50;
- 8'h6d: d=8'h3c;
- 8'h6e: d=8'h9f;
- 8'h6f: d=8'ha8;
- 8'h70: d=8'h51;
- 8'h71: d=8'ha3;
- 8'h72: d=8'h40;
- 8'h73: d=8'h8f;
- 8'h74: d=8'h92;
- 8'h75: d=8'h9d;
- 8'h76: d=8'h38;
- 8'h77: d=8'hf5;
- 8'h78: d=8'hbc;
- 8'h79: d=8'hb6;
- 8'h7a: d=8'hda;
- 8'h7b: d=8'h21;
- 8'h7c: d=8'h10;
- 8'h7d: d=8'hff;
- 8'h7e: d=8'hf3;
- 8'h7f: d=8'hd2;
- 8'h80: d=8'hcd;
- 8'h81: d=8'h0c;
- 8'h82: d=8'h13;
- 8'h83: d=8'hec;
- 8'h84: d=8'h5f;
- 8'h85: d=8'h97;
- 8'h86: d=8'h44;
- 8'h87: d=8'h17;
- 8'h88: d=8'hc4;
- 8'h89: d=8'ha7;
- 8'h8a: d=8'h7e;
- 8'h8b: d=8'h3d;
- 8'h8c: d=8'h64;
- 8'h8d: d=8'h5d;
- 8'h8e: d=8'h19;
- 8'h8f: d=8'h73;
- 8'h90: d=8'h60;
- 8'h91: d=8'h81;
- 8'h92: d=8'h4f;
- 8'h93: d=8'hdc;
- 8'h94: d=8'h22;
- 8'h95: d=8'h2a;
- 8'h96: d=8'h90;
- 8'h97: d=8'h88;
- 8'h98: d=8'h46;
- 8'h99: d=8'hee;
- 8'h9a: d=8'hb8;
- 8'h9b: d=8'h14;
- 8'h9c: d=8'hde;
- 8'h9d: d=8'h5e;
- 8'h9e: d=8'h0b;
- 8'h9f: d=8'hdb;
- 8'ha0: d=8'he0;
- 8'ha1: d=8'h32;
- 8'ha2: d=8'h3a;
- 8'ha3: d=8'h0a;
- 8'ha4: d=8'h49;
- 8'ha5: d=8'h06;
- 8'ha6: d=8'h24;
- 8'ha7: d=8'h5c;
- 8'ha8: d=8'hc2;
- 8'ha9: d=8'hd3;
- 8'haa: d=8'hac;
- 8'hab: d=8'h62;
- 8'hac: d=8'h91;
- 8'had: d=8'h95;
- 8'hae: d=8'he4;
- 8'haf: d=8'h79;
- 8'hb0: d=8'he7;
- 8'hb1: d=8'hc8;
- 8'hb2: d=8'h37;
- 8'hb3: d=8'h6d;
- 8'hb4: d=8'h8d;
- 8'hb5: d=8'hd5;
- 8'hb6: d=8'h4e;
- 8'hb7: d=8'ha9;
- 8'hb8: d=8'h6c;
- 8'hb9: d=8'h56;
- 8'hba: d=8'hf4;
- 8'hbb: d=8'hea;
- 8'hbc: d=8'h65;
- 8'hbd: d=8'h7a;
- 8'hbe: d=8'hae;
- 8'hbf: d=8'h08;
- 8'hc0: d=8'hba;
- 8'hc1: d=8'h78;
- 8'hc2: d=8'h25;
- 8'hc3: d=8'h2e;
- 8'hc4: d=8'h1c;
- 8'hc5: d=8'ha6;
- 8'hc6: d=8'hb4;
- 8'hc7: d=8'hc6;
- 8'hc8: d=8'he8;
- 8'hc9: d=8'hdd;
- 8'hca: d=8'h74;
- 8'hcb: d=8'h1f;
- 8'hcc: d=8'h4b;
- 8'hcd: d=8'hbd;
- 8'hce: d=8'h8b;
- 8'hcf: d=8'h8a;
- 8'hd0: d=8'h70;
- 8'hd1: d=8'h3e;
- 8'hd2: d=8'hb5;
- 8'hd3: d=8'h66;
- 8'hd4: d=8'h48;
- 8'hd5: d=8'h03;
- 8'hd6: d=8'hf6;
- 8'hd7: d=8'h0e;
- 8'hd8: d=8'h61;
- 8'hd9: d=8'h35;
- 8'hda: d=8'h57;
- 8'hdb: d=8'hb9;
- 8'hdc: d=8'h86;
- 8'hdd: d=8'hc1;
- 8'hde: d=8'h1d;
- 8'hdf: d=8'h9e;
- 8'he0: d=8'he1;
- 8'he1: d=8'hf8;
- 8'he2: d=8'h98;
- 8'he3: d=8'h11;
- 8'he4: d=8'h69;
- 8'he5: d=8'hd9;
- 8'he6: d=8'h8e;
- 8'he7: d=8'h94;
- 8'he8: d=8'h9b;
- 8'he9: d=8'h1e;
- 8'hea: d=8'h87;
- 8'heb: d=8'he9;
- 8'hec: d=8'hce;
- 8'hed: d=8'h55;
- 8'hee: d=8'h28;
- 8'hef: d=8'hdf;
- 8'hf0: d=8'h8c;
- 8'hf1: d=8'ha1;
- 8'hf2: d=8'h89;
- 8'hf3: d=8'h0d;
- 8'hf4: d=8'hbf;
- 8'hf5: d=8'he6;
- 8'hf6: d=8'h42;
- 8'hf7: d=8'h68;
- 8'hf8: d=8'h41;
- 8'hf9: d=8'h99;
- 8'hfa: d=8'h2d;
- 8'hfb: d=8'h0f;
- 8'hfc: d=8'hb0;
- 8'hfd: d=8'h54;
- 8'hfe: d=8'hbb;
- 8'hff: d=8'h16;
- endcase
-
-endmodule
-
-
Index: trunk/rtl/verilog/aes_cipher_top.v
===================================================================
--- trunk/rtl/verilog/aes_cipher_top.v (revision 5)
+++ trunk/rtl/verilog/aes_cipher_top.v (nonexistent)
@@ -1,253 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// AES Cipher Top Level ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: aes_cipher_top.v,v 1.1.1.1 2002-11-09 11:22:48 rudi Exp $
-//
-// $Date: 2002-11-09 11:22:48 $
-// $Revision: 1.1.1.1 $
-// $Author: rudi $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: not supported by cvs2svn $
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out );
-input clk, rst;
-input ld;
-output done;
-input [127:0] key;
-input [127:0] text_in;
-output [127:0] text_out;
-
-////////////////////////////////////////////////////////////////////
-//
-// Local Wires
-//
-
-wire [31:0] w0, w1, w2, w3;
-reg [127:0] text_in_r;
-reg [127:0] text_out;
-reg [7:0] sa00, sa01, sa02, sa03;
-reg [7:0] sa10, sa11, sa12, sa13;
-reg [7:0] sa20, sa21, sa22, sa23;
-reg [7:0] sa30, sa31, sa32, sa33;
-wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
-wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
-wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
-wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
-wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
-wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
-wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
-wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
-wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
-wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
-wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
-wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
-wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc;
-wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc;
-wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc;
-wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc;
-reg done, ld_r;
-reg [3:0] dcnt;
-
-////////////////////////////////////////////////////////////////////
-//
-// Misc Logic
-//
-
-always @(posedge clk)
- if(!rst) dcnt <= #1 4'h0;
- else
- if(ld) dcnt <= #1 4'hb;
- else
- if(|dcnt) dcnt <= #1 dcnt - 4'h1;
-
-always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld;
-always @(posedge clk) if(ld) text_in_r <= #1 text_in;
-always @(posedge clk) ld_r <= #1 ld;
-
-////////////////////////////////////////////////////////////////////
-//
-// Initial Permutation (AddRoundKey)
-//
-
-always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
-always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
-always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
-always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
-always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
-always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
-always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
-always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
-always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
-always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
-always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
-always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
-always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
-always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
-always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
-always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
-
-////////////////////////////////////////////////////////////////////
-//
-// Round Permutations
-//
-
-assign sa00_sr = sa00_sub;
-assign sa01_sr = sa01_sub;
-assign sa02_sr = sa02_sub;
-assign sa03_sr = sa03_sub;
-assign sa10_sr = sa11_sub;
-assign sa11_sr = sa12_sub;
-assign sa12_sr = sa13_sub;
-assign sa13_sr = sa10_sub;
-assign sa20_sr = sa22_sub;
-assign sa21_sr = sa23_sub;
-assign sa22_sr = sa20_sub;
-assign sa23_sr = sa21_sub;
-assign sa30_sr = sa33_sub;
-assign sa31_sr = sa30_sub;
-assign sa32_sr = sa31_sub;
-assign sa33_sr = sa32_sub;
-assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc} = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
-assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc} = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
-assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc} = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
-assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc} = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
-assign sa00_next = sa00_mc ^ w0[31:24];
-assign sa01_next = sa01_mc ^ w1[31:24];
-assign sa02_next = sa02_mc ^ w2[31:24];
-assign sa03_next = sa03_mc ^ w3[31:24];
-assign sa10_next = sa10_mc ^ w0[23:16];
-assign sa11_next = sa11_mc ^ w1[23:16];
-assign sa12_next = sa12_mc ^ w2[23:16];
-assign sa13_next = sa13_mc ^ w3[23:16];
-assign sa20_next = sa20_mc ^ w0[15:08];
-assign sa21_next = sa21_mc ^ w1[15:08];
-assign sa22_next = sa22_mc ^ w2[15:08];
-assign sa23_next = sa23_mc ^ w3[15:08];
-assign sa30_next = sa30_mc ^ w0[07:00];
-assign sa31_next = sa31_mc ^ w1[07:00];
-assign sa32_next = sa32_mc ^ w2[07:00];
-assign sa33_next = sa33_mc ^ w3[07:00];
-
-////////////////////////////////////////////////////////////////////
-//
-// Final text output
-//
-
-always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24];
-always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24];
-always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24];
-always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24];
-always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16];
-always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16];
-always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16];
-always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16];
-always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08];
-always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08];
-always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08];
-always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08];
-always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00];
-always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00];
-always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00];
-always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00];
-
-////////////////////////////////////////////////////////////////////
-//
-// Generic Functions
-//
-
-function [31:0] mix_col;
-input [7:0] s0,s1,s2,s3;
-reg [7:0] s0_o,s1_o,s2_o,s3_o;
-begin
-mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
-mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
-mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
-mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
-end
-endfunction
-
-function [7:0] xtime;
-input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
-endfunction
-
-////////////////////////////////////////////////////////////////////
-//
-// Modules
-//
-
-aes_key_expand_128 u0(
- .clk( clk ),
- .kld( ld ),
- .key( key ),
- .wo_0( w0 ),
- .wo_1( w1 ),
- .wo_2( w2 ),
- .wo_3( w3 ));
-
-aes_sbox us00( .a( sa00 ), .d( sa00_sub ));
-aes_sbox us01( .a( sa01 ), .d( sa01_sub ));
-aes_sbox us02( .a( sa02 ), .d( sa02_sub ));
-aes_sbox us03( .a( sa03 ), .d( sa03_sub ));
-aes_sbox us10( .a( sa10 ), .d( sa10_sub ));
-aes_sbox us11( .a( sa11 ), .d( sa11_sub ));
-aes_sbox us12( .a( sa12 ), .d( sa12_sub ));
-aes_sbox us13( .a( sa13 ), .d( sa13_sub ));
-aes_sbox us20( .a( sa20 ), .d( sa20_sub ));
-aes_sbox us21( .a( sa21 ), .d( sa21_sub ));
-aes_sbox us22( .a( sa22 ), .d( sa22_sub ));
-aes_sbox us23( .a( sa23 ), .d( sa23_sub ));
-aes_sbox us30( .a( sa30 ), .d( sa30_sub ));
-aes_sbox us31( .a( sa31 ), .d( sa31_sub ));
-aes_sbox us32( .a( sa32 ), .d( sa32_sub ));
-aes_sbox us33( .a( sa33 ), .d( sa33_sub ));
-
-endmodule
-
-
Index: trunk/rtl/verilog/timescale.v
===================================================================
--- trunk/rtl/verilog/timescale.v (revision 5)
+++ trunk/rtl/verilog/timescale.v (nonexistent)
@@ -1 +0,0 @@
-`timescale 1ns / 10ps
Index: trunk/doc/aes.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/aes.pdf
===================================================================
--- trunk/doc/aes.pdf (revision 5)
+++ trunk/doc/aes.pdf (nonexistent)
trunk/doc/aes.pdf
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/vim_session.vim
===================================================================
--- trunk/vim_session.vim (revision 5)
+++ trunk/vim_session.vim (nonexistent)
@@ -1,243 +0,0 @@
-set nocompatible
-let s:cpo_save=&cpo
-set cpo&vim
-map!
-map!
-map!
-map!
-map!
-map!
-map!
-map!
-map!
-map!
-nnoremap 6_Paste "=@+.'xy'
-gPFx"_2x:echo
-map
-map
-map
-map
-map
-map
-map
-map
-map
-map
-let &cpo=s:cpo_save
-unlet s:cpo_save
-set background=dark
-set bufhidden=delete
-set buftype=nofile
-if &filetype != 'csh'
-set filetype=csh
-endif
-set guifont=-adobe-courier-medium-r-normal-*-*-120-*-*-m-*-iso8859-1
-set iminsert=0
-set imsearch=0
-set iskeyword=@,48-57,_,192-255,+,-,?
-set menuitems=50
-set mouse=a
-set noswapfile
-if &syntax != 'verilog'
-set syntax=verilog
-endif
-let s:so_save = &so | let s:siso_save = &siso | set so=0 siso=0
-let v:this_session=expand(":p")
-silent only
-cd ~/projects/aes_core
-set shortmess=aoO
-badd +1 rtl/verilog/aes_top.v
-badd +105 bench/verilog/test_bench_top.v
-badd +30 sim/rtl_sim/bin/Makefile
-badd +79 rtl/verilog/aes_key_expand_128.v
-badd +72 rtl/verilog/aes_key_expand_192.v
-badd +55 rtl/verilog/aes_key_expand_256.v
-badd +94 rtl/verilog/aes_rcon.v
-badd +80 rtl/verilog/aes_sbox.v
-badd +44 impl_results
-badd +1 rtl/verilog/aes_inv_cipher_top.v
-badd +471 rtl/verilog/aes_inv_sbox.v
-silent! argdel *
-set splitbelow splitright
-normal _|
-vsplit
-normal 1h
-normal w
-set nosplitbelow
-set nosplitright
-normal t
-set winheight=1 winwidth=1
-exe 'vert resize ' . ((&columns * 99 + 106) / 212)
-normal w
-exe 'vert resize ' . ((&columns * 112 + 106) / 212)
-normal w
-argglobal
-edit rtl/verilog/aes_sbox.v
-setlocal noautoindent
-setlocal autoread
-setlocal nobinary
-setlocal bufhidden=
-setlocal buflisted
-setlocal buftype=
-setlocal nocindent
-setlocal cinkeys=0{,0},0),:,0#,!^F,o,O,e
-setlocal cinoptions=
-setlocal cinwords=if,else,while,do,for,switch
-setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:-
-setlocal commentstring=/*%s*/
-setlocal complete=.,w,b,u,t,i
-setlocal define=
-setlocal dictionary=
-setlocal nodiff
-setlocal equalprg=
-setlocal errorformat=
-setlocal noexpandtab
-if &filetype != 'verilog'
-setlocal filetype=verilog
-endif
-setlocal foldcolumn=0
-setlocal foldenable
-setlocal foldexpr=0
-setlocal foldignore=#
-setlocal foldlevel=0
-setlocal foldmarker={{{,}}}
-setlocal foldmethod=manual
-setlocal foldminlines=1
-setlocal foldnestmax=20
-setlocal foldtext=foldtext()
-setlocal formatoptions=tcq
-setlocal grepprg=
-setlocal iminsert=0
-setlocal imsearch=0
-setlocal include=
-setlocal includeexpr=
-setlocal indentexpr=
-setlocal indentkeys=0{,0},:,0#,!^F,o,O,e
-setlocal noinfercase
-setlocal iskeyword=@,48-57,_,192-255,+,-,?
-setlocal keymap=
-setlocal nolinebreak
-setlocal nolisp
-setlocal nolist
-setlocal makeprg=
-setlocal matchpairs=(:),{:},[:]
-setlocal modeline
-setlocal modifiable
-setlocal nrformats=octal,hex
-setlocal nonumber
-setlocal path=
-setlocal nopreviewwindow
-setlocal noreadonly
-setlocal norightleft
-setlocal noscrollbind
-setlocal shiftwidth=8
-setlocal noshortname
-setlocal nosmartindent
-setlocal softtabstop=0
-setlocal suffixesadd=
-setlocal noswapfile
-if &syntax != 'verilog'
-setlocal syntax=verilog
-endif
-setlocal tabstop=8
-setlocal tags=
-setlocal textwidth=0
-setlocal thesaurus=
-setlocal wrap
-setlocal wrapmargin=0
-silent! normal zE
-let s:l = 65 - ((28 * winheight(0) + 34) / 69)
-if s:l < 1 | let s:l = 1 | endif
-exe s:l
-normal zt
-65
-normal 0
-normal w
-argglobal
-edit rtl/verilog/aes_inv_cipher_top.v
-setlocal noautoindent
-setlocal autoread
-setlocal nobinary
-setlocal bufhidden=
-setlocal buflisted
-setlocal buftype=
-setlocal nocindent
-setlocal cinkeys=0{,0},0),:,0#,!^F,o,O,e
-setlocal cinoptions=
-setlocal cinwords=if,else,while,do,for,switch
-setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:-
-setlocal commentstring=/*%s*/
-setlocal complete=.,w,b,u,t,i
-setlocal define=
-setlocal dictionary=
-setlocal nodiff
-setlocal equalprg=
-setlocal errorformat=
-setlocal noexpandtab
-if &filetype != 'verilog'
-setlocal filetype=verilog
-endif
-setlocal foldcolumn=0
-setlocal foldenable
-setlocal foldexpr=0
-setlocal foldignore=#
-setlocal foldlevel=0
-setlocal foldmarker={{{,}}}
-setlocal foldmethod=manual
-setlocal foldminlines=1
-setlocal foldnestmax=20
-setlocal foldtext=foldtext()
-setlocal formatoptions=tcq
-setlocal grepprg=
-setlocal iminsert=0
-setlocal imsearch=0
-setlocal include=
-setlocal includeexpr=
-setlocal indentexpr=
-setlocal indentkeys=0{,0},:,0#,!^F,o,O,e
-setlocal noinfercase
-setlocal iskeyword=@,48-57,_,192-255,+,-,?
-setlocal keymap=
-setlocal nolinebreak
-setlocal nolisp
-setlocal nolist
-setlocal makeprg=
-setlocal matchpairs=(:),{:},[:]
-setlocal modeline
-setlocal modifiable
-setlocal nrformats=octal,hex
-setlocal nonumber
-setlocal path=
-setlocal nopreviewwindow
-setlocal noreadonly
-setlocal norightleft
-setlocal noscrollbind
-setlocal shiftwidth=8
-setlocal noshortname
-setlocal nosmartindent
-setlocal softtabstop=0
-setlocal suffixesadd=
-setlocal noswapfile
-if &syntax != 'verilog'
-setlocal syntax=verilog
-endif
-setlocal tabstop=8
-setlocal tags=
-setlocal textwidth=0
-setlocal thesaurus=
-setlocal wrap
-setlocal wrapmargin=0
-silent! normal zE
-let s:l = 260 - ((19 * winheight(0) + 34) / 69)
-if s:l < 1 | let s:l = 1 | endif
-exe s:l
-normal zt
-260
-normal 09l
-normal w
-set winheight=1 winwidth=20 shortmess=filnxtToO
-let s:sx = expand(":p:r")."x.vim"
-if file_readable(s:sx)
- exe "source " . s:sx
-endif
-let &so = s:so_save | let &siso = s:siso_save
Index: trunk/sim/rtl_sim/run/waves/waves.do
===================================================================
--- trunk/sim/rtl_sim/run/waves/waves.do (revision 5)
+++ trunk/sim/rtl_sim/run/waves/waves.do (nonexistent)
@@ -1,209 +0,0 @@
-// Signalscan Version 6.8b1
-
-
-define noactivityindicator
-define analog waveform lines
-define add variable default overlay off
-define waveform window analogheight 1
-define terminal automatic
-define buttons control \
- 1 opensimmulationfile \
- 2 executedofile \
- 3 designbrowser \
- 4 waveform \
- 5 source \
- 6 breakpoints \
- 7 definesourcessearchpath \
- 8 exit \
- 9 createbreakpoint \
- 10 creategroup \
- 11 createmarker \
- 12 closesimmulationfile \
- 13 renamesimmulationfile \
- 14 replacesimulationfiledata \
- 15 listopensimmulationfiles \
- 16 savedofile
-define buttons waveform \
- 1 replacesimulationfiledata \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 zoomin \
- 7 zoomout \
- 8 zoomoutfull \
- 9 expand \
- 10 createmarker \
- 11 designbrowser:1 \
- 12 savedofile \
- 13 variableradixoctal \
- 14 variableradixdecimal \
- 15 variableradixhexadecimal \
- 16 variableradixascii
-define buttons designbrowser \
- 1 undo \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 cdupscope \
- 7 getallvariables \
- 8 getdeepallvariables \
- 9 addvariables \
- 10 addvarsandclosewindow \
- 11 closewindow \
- 12 scopefiltermodule \
- 13 scopefiltertask \
- 14 scopefilterfunction \
- 15 scopefilterblock \
- 16 scopefilterprimitive
-define buttons event \
- 1 undo \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 move \
- 7 closewindow \
- 8 duplicate \
- 9 defineasrisingedge \
- 10 defineasfallingedge \
- 11 defineasanyedge \
- 12 variableradixbinary \
- 13 variableradixoctal \
- 14 variableradixdecimal \
- 15 variableradixhexadecimal \
- 16 variableradixascii
-define buttons source \
- 1 undo \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 createbreakpoint \
- 7 creategroup \
- 8 createmarker \
- 9 createevent \
- 10 createregisterpage \
- 11 closewindow \
- 12 opensimmulationfile \
- 13 closesimmulationfile \
- 14 renamesimmulationfile \
- 15 replacesimulationfiledata \
- 16 listopensimmulationfiles
-define buttons register \
- 1 undo \
- 2 cut \
- 3 copy \
- 4 paste \
- 5 delete \
- 6 createregisterpage \
- 7 closewindow \
- 8 continuefor \
- 9 continueuntil \
- 10 continueforever \
- 11 stop \
- 12 previous \
- 13 next \
- 14 variableradixbinary \
- 15 variableradixhexadecimal \
- 16 variableradixascii
-define show related transactions
-define exit noprompt
-define event search direction forward
-define variable fullhierarchy
-define variable nofilenames
-define variable nofullpathfilenames
-include bookmark with filenames
-include scope history without filenames
-define waveform window listpane 7.95
-define waveform window namepane 33.97
-define multivalueindication
-define pattern curpos dot
-define pattern cursor1 dot
-define pattern cursor2 dot
-define pattern marker dot
-define print designer "Rudolf Usselmann"
-define print border
-define print color blackonwhite
-define print command "/usr/bin/lpr -P%P"
-define print printer lp
-define print size A4
-define print range visible
-define print variable visible
-define rise fall time low threshold percentage 10
-define rise fall time high threshold percentage 90
-define rise fall time low value 0
-define rise fall time high value 3.3
-define sendmail command "/usr/lib/sendmail"
-define sequence time width 30.00
-define snap
-
-define source noprompt
-define time units default
-define userdefinedbussymbol
-define user guide directory "/usr/local/designacc/signalscan-6.5s2/doc/html"
-define waveform window grid off
-define waveform window waveheight 14
-define waveform window wavespace 6
-define web browser command netscape
-define zoom outfull on initial add off
-add group \
- A \
- test.rst \
- test.clk \
- test.u0.ld \
- test.u0.ld_r \
- test.u0.key[127:0]'h \
- test.u0.text_in[127:0]'h \
- test.text_out[127:0]'h \
- test.u0.done \
- test.done2 \
- test.text_out2[127:0]'h \
- test.u0.w0[31:0]'h \
- test.u0.w1[31:0]'h \
- test.u0.w2[31:0]'h \
- test.u0.w3[31:0]'h \
- test.u0.sa00[7:0]'h \
- test.u0.sa01[7:0]'h \
- test.u0.sa02[7:0]'h \
- test.u0.sa03[7:0]'h \
- test.u0.sa10[7:0]'h \
- test.u0.sa11[7:0]'h \
- test.u0.sa12[7:0]'h \
- test.u0.sa13[7:0]'h \
- test.u0.sa20[7:0]'h \
- test.u0.sa21[7:0]'h \
- test.u0.sa22[7:0]'h \
- test.u0.sa23[7:0]'h \
- test.u0.sa30[7:0]'h \
- test.u0.sa31[7:0]'h \
- test.u0.sa32[7:0]'h \
- test.u0.sa33[7:0]'h \
- test.clk \
- test.u1.ld \
- test.u1.done \
- test.u1.w3[31:0]'h \
- test.u1.kdone \
- test.u1.kld \
- test.u1.text_in[127:0]'h \
- test.u1.text_in_r[127:0]'h \
- test.u1.text_out[127:0]'h \
- test.u1.kb_ld \
- test.u1.kcnt[3:0]'h \
- test.u1.dcnt[3:0]'h \
- test.u1.w0[31:0]'h \
- test.u1.w1[31:0]'h \
- test.u1.w2[31:0]'h \
- test.u1.w3[31:0]'h \
- test.u1.wk0[31:0]'h \
- test.u1.wk1[31:0]'h \
- test.u1.wk2[31:0]'h \
- test.u1.wk3[31:0]'h \
-
-
-deselect all
-create marker Marker1 0ns
-open window designbrowser 1 geometry 450 269 1020 752
-open window waveform 1 geometry 58 104 1540 838
-zoom at 0(0)ns 0.00803721 0.00000000
Index: trunk/sim/rtl_sim/bin/Makefile
===================================================================
--- trunk/sim/rtl_sim/bin/Makefile (revision 5)
+++ trunk/sim/rtl_sim/bin/Makefile (nonexistent)
@@ -1,82 +0,0 @@
-
-all: sim
-SHELL = /bin/sh
-MS="-s"
-
-##########################################################################
-#
-# DUT Sources
-#
-##########################################################################
-DUT_SRC_DIR=../../../rtl/verilog
-_TARGETS_= $(DUT_SRC_DIR)/aes_sbox.v \
- $(DUT_SRC_DIR)/aes_rcon.v \
- $(DUT_SRC_DIR)/aes_key_expand_128.v \
- $(DUT_SRC_DIR)/aes_cipher_top.v \
- $(DUT_SRC_DIR)/aes_inv_sbox.v \
- $(DUT_SRC_DIR)/aes_inv_cipher_top.v
-
-
-##########################################################################
-#
-# Test Bench Sources
-#
-##########################################################################
-TB_SRC_DIR=../../../bench/verilog
-_TB_= $(TB_SRC_DIR)/test_bench_top.v
-
-##########################################################################
-#
-# Misc Variables
-#
-##########################################################################
-
-INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
-LOGF=-l .nclog
-UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
-GATE_NETLIST = ../../../syn/out/aes_cipher_top.v
-
-##########################################################################
-#
-# Make Targets
-#
-##########################################################################
-ss:
- signalscan -do waves/waves.do -waves waves/waves.trn &
-
-simw:
- @$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
-
-sim:
- ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
- $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
- +ncuid+`hostname`
-
-ivl:
- /usr/local/bin/iverilog -D RUDIS_TB $(_TARGETS_) $(_TB_) \
- -I ./$(DUT_SRC_DIR)/ -I ./$(TB_SRC_DIR)/ \
- $(WAVES) $(ACCESS) -s test
-
-gatew:
- @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
-
-gate:
- ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \
- $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \
- $(LOGF) +ncstatus +ncuid+`hostname`
-
-hal:
- @echo ""
- @echo "----- Running HAL ... ----------"
- @hal +incdir+$(DUT_SRC_DIR) -NOP -NOS \
- -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
- $(_TARGETS_)
- @echo "----- DONE ... ----------"
-
-clean:
- rm -rf ./waves/*.dsn ./waves/*.trn \
- ncwork/.inc* ncwork/inc* \
- ./verilog.* .nclog hal.log INCA_libs
-
-##########################################################################
-
trunk/sim/rtl_sim/bin/Makefile
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/syn/bin/design_spec.dc
===================================================================
--- trunk/syn/bin/design_spec.dc (revision 5)
+++ trunk/syn/bin/design_spec.dc (nonexistent)
@@ -1,29 +0,0 @@
-###############################################################################
-#
-# Design Specification
-#
-# Author: Rudolf Usselmann
-# rudi@asics.ws
-#
-# Revision:
-# 3/7/01 RU Initial Sript
-#
-#
-###############################################################################
-
-# ==============================================
-# Setup Design Parameters
-
-set design_files {aes_rcon aes_sbox aes_key_expand_128 aes_cipher_top}
-set design_name aes_cipher_top
-set active_design aes_cipher_top
-
-#set design_files {aes_rcon aes_inv_sbox aes_key_expand_128 aes_inv_cipher_top}
-#set design_name aes_inv_cipher_top
-#set active_design aes_inv_cipher_top
-
-# Next Statement defines all clocks and resets in the design
-set special_net {clk}
-
-set hdl_src_dir ../../rtl/verilog/
-
Index: trunk/syn/bin/read.dc
===================================================================
--- trunk/syn/bin/read.dc (revision 5)
+++ trunk/syn/bin/read.dc (nonexistent)
@@ -1,67 +0,0 @@
-###############################################################################
-#
-# Pre Synthesis Script
-#
-# This script only reads in the design and saves it in a DB file
-#
-# Author: Rudolf Usselmann
-# rudi@asics.ws
-#
-# Revision:
-# 3/7/01 RU Initial Sript
-#
-#
-###############################################################################
-
-# ==============================================
-# Setup Design Parameters
-source ../bin/design_spec.dc
-
-# ==============================================
-# Setup Libraries
-source ../bin/lib_spec.dc
-
-# ==============================================
-# Setup IO Files
-
-append log_file ../log/$active_design "_pre.log"
-append pre_comp_db_file ../out/$design_name "_pre.db"
-
-sh rm -f $log_file
-
-# ==============================================
-# Setup Misc Variables
-
-set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
-
-# ==============================================
-# Read Design
-
-echo "+++++++++ Analyzing all design files ..." >> $log_file
-
-foreach module $design_files {
- echo "+++++++++ Reading: $module" >> $log_file
- echo +++++++++ Reading: $module
- set module_file_name ""
- append module_file_name $module ".v"
- analyze -f verilog $module_file_name >> $log_file
- elaborate $module >> $log_file
- }
-
-current_design $active_design
-
-echo "+++++++++ Linking Design ..." >> $log_file
-link >> $log_file
-
-echo "+++++++++ Uniquifying Design ..." >> $log_file
-uniquify >> $log_file
-
-echo "+++++++++ Checking Design ..." >> $log_file
-check_design >> $log_file
-
-# ==============================================
-# Save Design
-echo "+++++++++ Saving Design ..." >> $log_file
-write_file -hierarchy -format db -output $pre_comp_db_file
-
-quit
Index: trunk/syn/bin/comp.dc
===================================================================
--- trunk/syn/bin/comp.dc (revision 5)
+++ trunk/syn/bin/comp.dc (nonexistent)
@@ -1,142 +0,0 @@
-###############################################################################
-#
-# Actual Synthesis Script
-#
-# This script does the actual synthesis
-#
-# Author: Rudolf Usselmann
-# rudi@asics.ws
-#
-# Revision:
-# 3/7/01 RU Initial Sript
-#
-#
-###############################################################################
-
-# ==============================================
-# Setup Design Parameters
-source ../bin/design_spec.dc
-
-# ==============================================
-# Setup Libraries
-source ../bin/lib_spec.dc
-
-# ==============================================
-# Setup IO Files
-
-append log_file ../log/$active_design "_cmp.log"
-append pre_comp_db_file ../out/$design_name "_pre.db"
-append post_comp_db_file ../out/$design_name ".db"
-append post_syn_verilog_file ../out/$design_name "_ps.v"
-set junk_file /dev/null
-
-sh rm -f $log_file
-
-# ==============================================
-# Setup Misc Variables
-
-set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
-
-# ==============================================
-# Read Design
-
-echo "+++++++++ Reading Design ..." >> $log_file
-read_file $pre_comp_db_file >> $log_file
-
-# ==============================================
-# Operating conditions
-
-echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
-current_design $design_name
-set_operating_conditions WORST >> $log_file
-
-# ==============================================
-# Setup Clocks and Resets
-
-echo "+++++++++ Setting up Clocks ..." >> $log_file
-
-set_drive 0 [find port {clk}]
-
-# !!! Clock !!!
-set clock_period 2.5
-create_clock -period $clock_period clk
-set_clock_skew -uncertainty 0.1 clk
-set_clock_transition 0.2 clk
-set_dont_touch_network clk
-
-# ==============================================
-# Setup IOs
-
-echo "+++++++++ Setting up IOs ..." >> $log_file
-
-# Need to spell out external IOs
-
-set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
-set_load 0.2 [all_outputs]
-
-set_input_delay -max 1 -clock clk [all_inputs]
-set_output_delay -max 1 -clock clk [all_outputs]
-
-# ==============================================
-# Setup Area Constrains
-set_max_area 0.0
-
-# ==============================================
-# Force Ultra
-set_ultra_optimization -f
-set compile_new_optimization true
-
-# ==============================================
-# Compile Design
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Timing Loops Report +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-report_timing -loops -max_path 20 >> $log_file
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Starting Compile +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-
-set_wire_load_model -name suggested_160K [find design *]
-set_balance_registers true
-compile -boundary_optimization -ungroup_all
-optimize_registers -period 0
-compile -incremental_mapping -map_effort high -area_effort high -boundary_optimization -ungroup_all
-
-# ==============================================
-# Write Out the optimized design
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Saving Optimized Design +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-write_file -hierarchy -format verilog -output $post_syn_verilog_file
-write_file -hierarchy -format db -output $post_comp_db_file
-
-# ==============================================
-# Create Some Basic Reports
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Reporting Final Results +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-report_timing -path full_clock -nworst 10 -nets \
- -transition_time -capacitance -attributes \
- -sort_by slack >> $log_file
-
-echo "" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "+++++++++ Area Report +++++++++" >> $log_file
-echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
-echo "" >> $log_file
-
-report_area >> $log_file
-quit
-
Index: trunk/syn/bin/lib_spec.dc
===================================================================
--- trunk/syn/bin/lib_spec.dc (revision 5)
+++ trunk/syn/bin/lib_spec.dc (nonexistent)
@@ -1,43 +0,0 @@
-###############################################################################
-#
-# Library Specification
-#
-# Author: Rudolf Usselmann
-# rudi@asics.ws
-#
-# Revision:
-# 3/7/01 RU Initial Sript
-#
-#
-###############################################################################
-
-# ==============================================
-# Setup Libraries
-
-#tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
-#tools/dc_libraries/virtual_silicon/UMCL13L210D3_1.0/design_compiler/ \
-
-
-set search_path [list $search_path . \
- /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
- $hdl_src_dir]
-
-set snps [getenv "SYNOPSYS"]
-
-set synthetic_library ""
-append synthetic_library $snps "/libraries/syn/dw01.sldb "
-append synthetic_library $snps "/libraries/syn/dw02.sldb "
-append synthetic_library $snps "/libraries/syn/dw03.sldb "
-append synthetic_library $snps "/libraries/syn/dw04.sldb "
-append synthetic_library $snps "/libraries/syn/dw05.sldb "
-append synthetic_library $snps "/libraries/syn/dw06.sldb "
-append synthetic_library $snps "/libraries/syn/dw07.sldb "
-
-set target_library { umcl18u250t2_wc.db }
-#set target_library { umcl13l210t3_wc.db }
-
-set link_library ""
-append link_library $target_library " " $synthetic_library
-
-#set symbol_library { umcl13l210t3.sdb }
-
Index: aes_core/trunk/doc/aes.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: aes_core/trunk/doc/aes.pdf
===================================================================
--- aes_core/trunk/doc/aes.pdf (nonexistent)
+++ aes_core/trunk/doc/aes.pdf (revision 6)
aes_core/trunk/doc/aes.pdf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: aes_core/trunk/bench/verilog/test_bench_top.v
===================================================================
--- aes_core/trunk/bench/verilog/test_bench_top.v (nonexistent)
+++ aes_core/trunk/bench/verilog/test_bench_top.v (revision 6)
@@ -0,0 +1,467 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Test Bench ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: test_bench_top.v,v 1.2 2002-11-12 16:10:12 rudi Exp $
+//
+// $Date: 2002-11-12 16:10:12 $
+// $Revision: 1.2 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2002/11/09 11:22:56 rudi
+// Initial Checkin
+//
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module test;
+
+reg clk;
+reg rst;
+
+reg [383:0] tv[512:0]; // Test vectors
+wire [383:0] tmp;
+reg kld;
+wire [127:0] key, plain, ciph;
+wire [127:0] text_in;
+wire [127:0] text_out;
+wire [127:0] text_out2;
+reg [127:0] text_exp;
+wire done, done2;
+integer n, error_cnt;
+
+initial
+ begin
+ $display("\n\n");
+ $display("*****************************************************");
+ $display("* AES Test bench ...");
+ $display("*****************************************************");
+ $display("\n");
+`ifdef WAVES
+ $shm_open("waves");
+ $shm_probe("AS",test,"AS");
+ $display("INFO: Signal dump enabled ...\n\n");
+`endif
+
+ kld = 0;
+ clk = 0;
+ rst = 0;
+ error_cnt = 0;
+ repeat(4) @(posedge clk);
+ rst = 1;
+ repeat(20) @(posedge clk);
+
+ $display("");
+ $display("");
+ $display("Started random test ...");
+
+tv[0]= 384'h00000000000000000000000000000000f34481ec3cc627bacd5dc3fb08f273e60336763e966d92595a567cc9ce537f5e;
+tv[1]= 384'h000000000000000000000000000000009798c4640bad75c7c3227db910174e72a9a1631bf4996954ebc093957b234589;
+tv[2]= 384'h0000000000000000000000000000000096ab5c2ff612d9dfaae8c31f30c42168ff4f8391a6a40ca5b25d23bedd44a597;
+tv[3]= 384'h000000000000000000000000000000006a118a874519e64e9963798a503f1d35dc43be40be0e53712f7e2bf5ca707209;
+tv[4]= 384'h00000000000000000000000000000000cb9fceec81286ca3e989bd979b0cb28492beedab1895a94faa69b632e5cc47ce;
+tv[5]= 384'h00000000000000000000000000000000b26aeb1874e47ca8358ff22378f09144459264f4798f6a78bacb89c15ed3d601;
+tv[6]= 384'h0000000000000000000000000000000058c8e00b2631686d54eab84b91f0aca108a4e2efec8a8e3312ca7460b9040bbf;
+tv[7]= 384'h10a58869d74be5a374cf867cfb473859000000000000000000000000000000006d251e6944b051e04eaa6fb4dbf78465;
+tv[8]= 384'hcaea65cdbb75e9169ecd22ebe6e54675000000000000000000000000000000006e29201190152df4ee058139def610bb;
+tv[9]= 384'ha2e2fa9baf7d20822ca9f0542f764a4100000000000000000000000000000000c3b44b95d9d2f25670eee9a0de099fa3;
+tv[10]= 384'hb6364ac4e1de1e285eaf144a2415f7a0000000000000000000000000000000005d9b05578fc944b3cf1ccf0e746cd581;
+tv[11]= 384'h64cf9c7abc50b888af65f49d521944b200000000000000000000000000000000f7efc89d5dba578104016ce5ad659c05;
+tv[12]= 384'h47d6742eefcc0465dc96355e851b64d9000000000000000000000000000000000306194f666d183624aa230a8b264ae7;
+tv[13]= 384'h3eb39790678c56bee34bbcdeccf6cdb500000000000000000000000000000000858075d536d79ccee571f7d7204b1f67;
+tv[14]= 384'h64110a924f0743d500ccadae72c134270000000000000000000000000000000035870c6a57e9e92314bcb8087cde72ce;
+tv[15]= 384'h18d8126516f8a12ab1a36d9f04d68e51000000000000000000000000000000006c68e9be5ec41e22c825b7c7affb4363;
+tv[16]= 384'hf530357968578480b398a3c251cd109300000000000000000000000000000000f5df39990fc688f1b07224cc03e86cea;
+tv[17]= 384'hda84367f325d42d601b4326964802e8e00000000000000000000000000000000bba071bcb470f8f6586e5d3add18bc66;
+tv[18]= 384'he37b1c6aa2846f6fdb413f238b089f230000000000000000000000000000000043c9f7e62f5d288bb27aa40ef8fe1ea8;
+tv[19]= 384'h6c002b682483e0cabcc731c253be5674000000000000000000000000000000003580d19cff44f1014a7c966a69059de5;
+tv[20]= 384'h143ae8ed6555aba96110ab58893a8ae100000000000000000000000000000000806da864dd29d48deafbe764f8202aef;
+tv[21]= 384'hb69418a85332240dc82492353956ae0c00000000000000000000000000000000a303d940ded8f0baff6f75414cac5243;
+tv[22]= 384'h71b5c08a1993e1362e4d0ce9b22b78d500000000000000000000000000000000c2dabd117f8a3ecabfbb11d12194d9d0;
+tv[23]= 384'he234cdca2606b81f29408d5f6da2120600000000000000000000000000000000fff60a4740086b3b9c56195b98d91a7b;
+tv[24]= 384'h13237c49074a3da078dc1d828bb78c6f000000000000000000000000000000008146a08e2357f0caa30ca8c94d1a0544;
+tv[25]= 384'h3071a2a48fe6cbd04f1a129098e308f8000000000000000000000000000000004b98e06d356deb07ebb824e5713f7be3;
+tv[26]= 384'h90f42ec0f68385f2ffc5dfc03a654dce000000000000000000000000000000007a20a53d460fc9ce0423a7a0764c6cf2;
+tv[27]= 384'hfebd9a24d8b65c1c787d50a4ed3619a900000000000000000000000000000000f4a70d8af877f9b02b4c40df57d45b17;
+tv[28]= 384'h80000000000000000000000000000000000000000000000000000000000000000edd33d3c621e546455bd8ba1418bec8;
+tv[29]= 384'hc0000000000000000000000000000000000000000000000000000000000000004bc3f883450c113c64ca42e1112a9e87;
+tv[30]= 384'he00000000000000000000000000000000000000000000000000000000000000072a1da770f5d7ac4c9ef94d822affd97;
+tv[31]= 384'hf000000000000000000000000000000000000000000000000000000000000000970014d634e2b7650777e8e84d03ccd8;
+tv[32]= 384'hf800000000000000000000000000000000000000000000000000000000000000f17e79aed0db7e279e955b5f493875a7;
+tv[33]= 384'hfc000000000000000000000000000000000000000000000000000000000000009ed5a75136a940d0963da379db4af26a;
+tv[34]= 384'hfe00000000000000000000000000000000000000000000000000000000000000c4295f83465c7755e8fa364bac6a7ea5;
+tv[35]= 384'hff00000000000000000000000000000000000000000000000000000000000000b1d758256b28fd850ad4944208cf1155;
+tv[36]= 384'hff8000000000000000000000000000000000000000000000000000000000000042ffb34c743de4d88ca38011c990890b;
+tv[37]= 384'hffc00000000000000000000000000000000000000000000000000000000000009958f0ecea8b2172c0c1995f9182c0f3;
+tv[38]= 384'hffe0000000000000000000000000000000000000000000000000000000000000956d7798fac20f82a8823f984d06f7f5;
+tv[39]= 384'hfff0000000000000000000000000000000000000000000000000000000000000a01bf44f2d16be928ca44aaf7b9b106b;
+tv[40]= 384'hfff8000000000000000000000000000000000000000000000000000000000000b5f1a33e50d40d103764c76bd4c6b6f8;
+tv[41]= 384'hfffc0000000000000000000000000000000000000000000000000000000000002637050c9fc0d4817e2d69de878aee8d;
+tv[42]= 384'hfffe000000000000000000000000000000000000000000000000000000000000113ecbe4a453269a0dd26069467fb5b5;
+tv[43]= 384'hffff00000000000000000000000000000000000000000000000000000000000097d0754fe68f11b9e375d070a608c884;
+tv[44]= 384'hffff800000000000000000000000000000000000000000000000000000000000c6a0b3e998d05068a5399778405200b4;
+tv[45]= 384'hffffc00000000000000000000000000000000000000000000000000000000000df556a33438db87bc41b1752c55e5e49;
+tv[46]= 384'hffffe0000000000000000000000000000000000000000000000000000000000090fb128d3a1af6e548521bb962bf1f05;
+tv[47]= 384'hfffff0000000000000000000000000000000000000000000000000000000000026298e9c1db517c215fadfb7d2a8d691;
+tv[48]= 384'hfffff80000000000000000000000000000000000000000000000000000000000a6cb761d61f8292d0df393a279ad0380;
+tv[49]= 384'hfffffc000000000000000000000000000000000000000000000000000000000012acd89b13cd5f8726e34d44fd486108;
+tv[50]= 384'hfffffe000000000000000000000000000000000000000000000000000000000095b1703fc57ba09fe0c3580febdd7ed4;
+tv[51]= 384'hffffff0000000000000000000000000000000000000000000000000000000000de11722d893e9f9121c381becc1da59a;
+tv[52]= 384'hffffff80000000000000000000000000000000000000000000000000000000006d114ccb27bf391012e8974c546d9bf2;
+tv[53]= 384'hffffffc0000000000000000000000000000000000000000000000000000000005ce37e17eb4646ecfac29b9cc38d9340;
+tv[54]= 384'hffffffe00000000000000000000000000000000000000000000000000000000018c1b6e2157122056d0243d8a165cddb;
+tv[55]= 384'hfffffff00000000000000000000000000000000000000000000000000000000099693e6a59d1366c74d823562d7e1431;
+tv[56]= 384'hfffffff8000000000000000000000000000000000000000000000000000000006c7c64dc84a8bba758ed17eb025a57e3;
+tv[57]= 384'hfffffffc00000000000000000000000000000000000000000000000000000000e17bc79f30eaab2fac2cbbe3458d687a;
+tv[58]= 384'hfffffffe000000000000000000000000000000000000000000000000000000001114bc2028009b923f0b01915ce5e7c4;
+tv[59]= 384'hffffffff000000000000000000000000000000000000000000000000000000009c28524a16a1e1c1452971caa8d13476;
+tv[60]= 384'hffffffff80000000000000000000000000000000000000000000000000000000ed62e16363638360fdd6ad62112794f0;
+tv[61]= 384'hffffffffc00000000000000000000000000000000000000000000000000000005a8688f0b2a2c16224c161658ffd4044;
+tv[62]= 384'hffffffffe000000000000000000000000000000000000000000000000000000023f710842b9bb9c32f26648c786807ca;
+tv[63]= 384'hfffffffff000000000000000000000000000000000000000000000000000000044a98bf11e163f632c47ec6a49683a89;
+tv[64]= 384'hfffffffff80000000000000000000000000000000000000000000000000000000f18aff94274696d9b61848bd50ac5e5;
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+tv[68]= 384'hffffffffff800000000000000000000000000000000000000000000000000000c72954a48d0774db0b4971c526260415;
+tv[69]= 384'hffffffffffc000000000000000000000000000000000000000000000000000001df9b76112dc6531e07d2cfda04411f0;
+tv[70]= 384'hffffffffffe000000000000000000000000000000000000000000000000000008e4d8e699119e1fc87545a647fb1d34f;
+tv[71]= 384'hfffffffffff00000000000000000000000000000000000000000000000000000e6c4807ae11f36f091c57d9fb68548d1;
+tv[72]= 384'hfffffffffff800000000000000000000000000000000000000000000000000008ebf73aad49c82007f77a5c1ccec6ab4;
+tv[73]= 384'hfffffffffffc00000000000000000000000000000000000000000000000000004fb288cc2040049001d2c7585ad123fc;
+tv[74]= 384'hfffffffffffe000000000000000000000000000000000000000000000000000004497110efb9dceb13e2b13fb4465564;
+tv[75]= 384'hffffffffffff000000000000000000000000000000000000000000000000000075550e6cb5a88e49634c9ab69eda0430;
+tv[76]= 384'hffffffffffff8000000000000000000000000000000000000000000000000000b6768473ce9843ea66a81405dd50b345;
+tv[77]= 384'hffffffffffffc000000000000000000000000000000000000000000000000000cb2f430383f9084e03a653571e065de6;
+tv[78]= 384'hffffffffffffe000000000000000000000000000000000000000000000000000ff4e66c07bae3e79fb7d210847a3b0ba;
+tv[79]= 384'hfffffffffffff0000000000000000000000000000000000000000000000000007b90785125505fad59b13c186dd66ce3;
+tv[80]= 384'hfffffffffffff8000000000000000000000000000000000000000000000000008b527a6aebdaec9eaef8eda2cb7783e5;
+tv[81]= 384'hfffffffffffffc0000000000000000000000000000000000000000000000000043fdaf53ebbc9880c228617d6a9b548b;
+tv[82]= 384'hfffffffffffffe0000000000000000000000000000000000000000000000000053786104b9744b98f052c46f1c850d0b;
+tv[83]= 384'hffffffffffffff00000000000000000000000000000000000000000000000000b5ab3013dd1e61df06cbaf34ca2aee78;
+tv[84]= 384'hffffffffffffff800000000000000000000000000000000000000000000000007470469be9723030fdcc73a8cd4fbb10;
+tv[85]= 384'hffffffffffffffc0000000000000000000000000000000000000000000000000a35a63f5343ebe9ef8167bcb48ad122e;
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+tv[88]= 384'hfffffffffffffff8000000000000000000000000000000000000000000000000653317b9362b6f9b9e1a580e68d494b5;
+tv[89]= 384'hfffffffffffffffc000000000000000000000000000000000000000000000000995c9dc0b689f03c45867b5faa5c18d1;
+tv[90]= 384'hfffffffffffffffe00000000000000000000000000000000000000000000000077a4d96d56dda398b9aabecfc75729fd;
+tv[91]= 384'hffffffffffffffff00000000000000000000000000000000000000000000000084be19e053635f09f2665e7bae85b42d;
+tv[92]= 384'hffffffffffffffff80000000000000000000000000000000000000000000000032cd652842926aea4aa6137bb2be2b5e;
+tv[93]= 384'hffffffffffffffffc00000000000000000000000000000000000000000000000493d4a4f38ebb337d10aa84e9171a554;
+tv[94]= 384'hffffffffffffffffe00000000000000000000000000000000000000000000000d9bff7ff454b0ec5a4a2a69566e2cb84;
+tv[95]= 384'hfffffffffffffffff000000000000000000000000000000000000000000000003535d565ace3f31eb249ba2cc6765d7a;
+tv[96]= 384'hfffffffffffffffff80000000000000000000000000000000000000000000000f60e91fc3269eecf3231c6e9945697c6;
+tv[97]= 384'hfffffffffffffffffc0000000000000000000000000000000000000000000000ab69cfadf51f8e604d9cc37182f6635a;
+tv[98]= 384'hfffffffffffffffffe00000000000000000000000000000000000000000000007866373f24a0b6ed56e0d96fcdafb877;
+tv[99]= 384'hffffffffffffffffff00000000000000000000000000000000000000000000001ea448c2aac954f5d812e9d78494446a;
+tv[100]= 384'hffffffffffffffffff8000000000000000000000000000000000000000000000acc5599dd8ac02239a0fef4a36dd1668;
+tv[101]= 384'hffffffffffffffffffc000000000000000000000000000000000000000000000d8764468bb103828cf7e1473ce895073;
+tv[102]= 384'hffffffffffffffffffe0000000000000000000000000000000000000000000001b0d02893683b9f180458e4aa6b73982;
+tv[103]= 384'hfffffffffffffffffff00000000000000000000000000000000000000000000096d9b017d302df410a937dcdb8bb6e43;
+tv[104]= 384'hfffffffffffffffffff800000000000000000000000000000000000000000000ef1623cc44313cff440b1594a7e21cc6;
+tv[105]= 384'hfffffffffffffffffffc00000000000000000000000000000000000000000000284ca2fa35807b8b0ae4d19e11d7dbd7;
+tv[106]= 384'hfffffffffffffffffffe00000000000000000000000000000000000000000000f2e976875755f9401d54f36e2a23a594;
+tv[107]= 384'hffffffffffffffffffff00000000000000000000000000000000000000000000ec198a18e10e532403b7e20887c8dd80;
+tv[108]= 384'hffffffffffffffffffff80000000000000000000000000000000000000000000545d50ebd919e4a6949d96ad47e46a80;
+tv[109]= 384'hffffffffffffffffffffc0000000000000000000000000000000000000000000dbdfb527060e0a71009c7bb0c68f1d44;
+tv[110]= 384'hffffffffffffffffffffe00000000000000000000000000000000000000000009cfa1322ea33da2173a024f2ff0d896d;
+tv[111]= 384'hfffffffffffffffffffff00000000000000000000000000000000000000000008785b1a75b0f3bd958dcd0e29318c521;
+tv[112]= 384'hfffffffffffffffffffff800000000000000000000000000000000000000000038f67b9e98e4a97b6df030a9fcdd0104;
+tv[113]= 384'hfffffffffffffffffffffc000000000000000000000000000000000000000000192afffb2c880e82b05926d0fc6c448b;
+tv[114]= 384'hfffffffffffffffffffffe0000000000000000000000000000000000000000006a7980ce7b105cf530952d74daaf798c;
+tv[115]= 384'hffffffffffffffffffffff000000000000000000000000000000000000000000ea3695e1351b9d6858bd958cf513ef6c;
+tv[116]= 384'hffffffffffffffffffffff8000000000000000000000000000000000000000006da0490ba0ba0343b935681d2cce5ba1;
+tv[117]= 384'hffffffffffffffffffffffc00000000000000000000000000000000000000000f0ea23af08534011c60009ab29ada2f1;
+tv[118]= 384'hffffffffffffffffffffffe00000000000000000000000000000000000000000ff13806cf19cc38721554d7c0fcdcd4b;
+tv[119]= 384'hfffffffffffffffffffffff000000000000000000000000000000000000000006838af1f4f69bae9d85dd188dcdf0688;
+tv[120]= 384'hfffffffffffffffffffffff8000000000000000000000000000000000000000036cf44c92d550bfb1ed28ef583ddf5d7;
+tv[121]= 384'hfffffffffffffffffffffffc0000000000000000000000000000000000000000d06e3195b5376f109d5c4ec6c5d62ced;
+tv[122]= 384'hfffffffffffffffffffffffe0000000000000000000000000000000000000000c440de014d3d610707279b13242a5c36;
+tv[123]= 384'hffffffffffffffffffffffff0000000000000000000000000000000000000000f0c5c6ffa5e0bd3a94c88f6b6f7c16b9;
+tv[124]= 384'hffffffffffffffffffffffff80000000000000000000000000000000000000003e40c3901cd7effc22bffc35dee0b4d9;
+tv[125]= 384'hffffffffffffffffffffffffc000000000000000000000000000000000000000b63305c72bedfab97382c406d0c49bc6;
+tv[126]= 384'hffffffffffffffffffffffffe00000000000000000000000000000000000000036bbaab22a6bd4925a99a2b408d2dbae;
+tv[127]= 384'hfffffffffffffffffffffffff000000000000000000000000000000000000000307c5b8fcd0533ab98bc51e27a6ce461;
+tv[128]= 384'hfffffffffffffffffffffffff800000000000000000000000000000000000000829c04ff4c07513c0b3ef05c03e337b5;
+tv[129]= 384'hfffffffffffffffffffffffffc00000000000000000000000000000000000000f17af0e895dda5eb98efc68066e84c54;
+tv[130]= 384'hfffffffffffffffffffffffffe00000000000000000000000000000000000000277167f3812afff1ffacb4a934379fc3;
+tv[131]= 384'hffffffffffffffffffffffffff000000000000000000000000000000000000002cb1dc3a9c72972e425ae2ef3eb597cd;
+tv[132]= 384'hffffffffffffffffffffffffff8000000000000000000000000000000000000036aeaa3a213e968d4b5b679d3a2c97fe;
+tv[133]= 384'hffffffffffffffffffffffffffc00000000000000000000000000000000000009241daca4fdd034a82372db50e1a0f3f;
+tv[134]= 384'hffffffffffffffffffffffffffe0000000000000000000000000000000000000c14574d9cd00cf2b5a7f77e53cd57885;
+tv[135]= 384'hfffffffffffffffffffffffffff0000000000000000000000000000000000000793de39236570aba83ab9b737cb521c9;
+tv[136]= 384'hfffffffffffffffffffffffffff800000000000000000000000000000000000016591c0f27d60e29b85a96c33861a7ef;
+tv[137]= 384'hfffffffffffffffffffffffffffc00000000000000000000000000000000000044fb5c4d4f5cb79be5c174a3b1c97348;
+tv[138]= 384'hfffffffffffffffffffffffffffe000000000000000000000000000000000000674d2b61633d162be59dde04222f4740;
+tv[139]= 384'hffffffffffffffffffffffffffff000000000000000000000000000000000000b4750ff263a65e1f9e924ccfd98f3e37;
+tv[140]= 384'hffffffffffffffffffffffffffff80000000000000000000000000000000000062d0662d6eaeddedebae7f7ea3a4f6b6;
+tv[141]= 384'hffffffffffffffffffffffffffffc0000000000000000000000000000000000070c46bb30692be657f7eaa93ebad9897;
+tv[142]= 384'hffffffffffffffffffffffffffffe00000000000000000000000000000000000323994cfb9da285a5d9642e1759b224a;
+tv[143]= 384'hfffffffffffffffffffffffffffff000000000000000000000000000000000001dbf57877b7b17385c85d0b54851e371;
+tv[144]= 384'hfffffffffffffffffffffffffffff80000000000000000000000000000000000dfa5c097cdc1532ac071d57b1d28d1bd;
+tv[145]= 384'hfffffffffffffffffffffffffffffc00000000000000000000000000000000003a0c53fa37311fc10bd2a9981f513174;
+tv[146]= 384'hfffffffffffffffffffffffffffffe0000000000000000000000000000000000ba4f970c0a25c41814bdae2e506be3b4;
+tv[147]= 384'hffffffffffffffffffffffffffffff00000000000000000000000000000000002dce3acb727cd13ccd76d425ea56e4f6;
+tv[148]= 384'hffffffffffffffffffffffffffffff80000000000000000000000000000000005160474d504b9b3eefb68d35f245f4b3;
+tv[149]= 384'hffffffffffffffffffffffffffffffc00000000000000000000000000000000041a8a947766635dec37553d9a6c0cbb7;
+tv[150]= 384'hffffffffffffffffffffffffffffffe00000000000000000000000000000000025d6cfe6881f2bf497dd14cd4ddf445b;
+tv[151]= 384'hfffffffffffffffffffffffffffffff00000000000000000000000000000000041c78c135ed9e98c096640647265da1e;
+tv[152]= 384'hfffffffffffffffffffffffffffffff8000000000000000000000000000000005a4d404d8917e353e92a21072c3b2305;
+tv[153]= 384'hfffffffffffffffffffffffffffffffc0000000000000000000000000000000002bc96846b3fdc71643f384cd3cc3eaf;
+tv[154]= 384'hfffffffffffffffffffffffffffffffe000000000000000000000000000000009ba4a9143f4e5d4048521c4f8877d88e;
+tv[155]= 384'hffffffffffffffffffffffffffffffff00000000000000000000000000000000a1f6258c877d5fcd8964484538bfc92c;
+tv[156]= 384'h00000000000000000000000000000000800000000000000000000000000000003ad78e726c1ec02b7ebfe92b23d9ec34;
+tv[157]= 384'h00000000000000000000000000000000c0000000000000000000000000000000aae5939c8efdf2f04e60b9fe7117b2c2;
+tv[158]= 384'h00000000000000000000000000000000e0000000000000000000000000000000f031d4d74f5dcbf39daaf8ca3af6e527;
+tv[159]= 384'h00000000000000000000000000000000f000000000000000000000000000000096d9fd5cc4f07441727df0f33e401a36;
+tv[160]= 384'h00000000000000000000000000000000f800000000000000000000000000000030ccdb044646d7e1f3ccea3dca08b8c0;
+tv[161]= 384'h00000000000000000000000000000000fc00000000000000000000000000000016ae4ce5042a67ee8e177b7c587ecc82;
+tv[162]= 384'h00000000000000000000000000000000fe000000000000000000000000000000b6da0bb11a23855d9c5cb1b4c6412e0a;
+tv[163]= 384'h00000000000000000000000000000000ff000000000000000000000000000000db4f1aa530967d6732ce4715eb0ee24b;
+tv[164]= 384'h00000000000000000000000000000000ff800000000000000000000000000000a81738252621dd180a34f3455b4baa2f;
+tv[165]= 384'h00000000000000000000000000000000ffc0000000000000000000000000000077e2b508db7fd89234caf7939ee5621a;
+tv[166]= 384'h00000000000000000000000000000000ffe00000000000000000000000000000b8499c251f8442ee13f0933b688fcd19;
+tv[167]= 384'h00000000000000000000000000000000fff00000000000000000000000000000965135f8a81f25c9d630b17502f68e53;
+tv[168]= 384'h00000000000000000000000000000000fff800000000000000000000000000008b87145a01ad1c6cede995ea3670454f;
+tv[169]= 384'h00000000000000000000000000000000fffc00000000000000000000000000008eae3b10a0c8ca6d1d3b0fa61e56b0b2;
+tv[170]= 384'h00000000000000000000000000000000fffe000000000000000000000000000064b4d629810fda6bafdf08f3b0d8d2c5;
+tv[171]= 384'h00000000000000000000000000000000ffff0000000000000000000000000000d7e5dbd3324595f8fdc7d7c571da6c2a;
+tv[172]= 384'h00000000000000000000000000000000ffff8000000000000000000000000000f3f72375264e167fca9de2c1527d9606;
+tv[173]= 384'h00000000000000000000000000000000ffffc0000000000000000000000000008ee79dd4f401ff9b7ea945d86666c13b;
+tv[174]= 384'h00000000000000000000000000000000ffffe000000000000000000000000000dd35cea2799940b40db3f819cb94c08b;
+tv[175]= 384'h00000000000000000000000000000000fffff0000000000000000000000000006941cb6b3e08c2b7afa581ebdd607b87;
+tv[176]= 384'h00000000000000000000000000000000fffff8000000000000000000000000002c20f439f6bb097b29b8bd6d99aad799;
+tv[177]= 384'h00000000000000000000000000000000fffffc00000000000000000000000000625d01f058e565f77ae86378bd2c49b3;
+tv[178]= 384'h00000000000000000000000000000000fffffe00000000000000000000000000c0b5fd98190ef45fbb4301438d095950;
+tv[179]= 384'h00000000000000000000000000000000ffffff0000000000000000000000000013001ff5d99806efd25da34f56be854b;
+tv[180]= 384'h00000000000000000000000000000000ffffff800000000000000000000000003b594c60f5c8277a5113677f94208d82;
+tv[181]= 384'h00000000000000000000000000000000ffffffc0000000000000000000000000e9c0fc1818e4aa46bd2e39d638f89e05;
+tv[182]= 384'h00000000000000000000000000000000ffffffe0000000000000000000000000f8023ee9c3fdc45a019b4e985c7e1a54;
+tv[183]= 384'h00000000000000000000000000000000fffffff000000000000000000000000035f40182ab4662f3023baec1ee796b57;
+tv[184]= 384'h00000000000000000000000000000000fffffff80000000000000000000000003aebbad7303649b4194a6945c6cc3694;
+tv[185]= 384'h00000000000000000000000000000000fffffffc000000000000000000000000a2124bea53ec2834279bed7f7eb0f938;
+tv[186]= 384'h00000000000000000000000000000000fffffffe000000000000000000000000b9fb4399fa4facc7309e14ec98360b0a;
+tv[187]= 384'h00000000000000000000000000000000ffffffff000000000000000000000000c26277437420c5d634f715aea81a9132;
+tv[188]= 384'h00000000000000000000000000000000ffffffff800000000000000000000000171a0e1b2dd424f0e089af2c4c10f32f;
+tv[189]= 384'h00000000000000000000000000000000ffffffffc000000000000000000000007cadbe402d1b208fe735edce00aee7ce;
+tv[190]= 384'h00000000000000000000000000000000ffffffffe0000000000000000000000043b02ff929a1485af6f5c6d6558baa0f;
+tv[191]= 384'h00000000000000000000000000000000fffffffff00000000000000000000000092faacc9bf43508bf8fa8613ca75dea;
+tv[192]= 384'h00000000000000000000000000000000fffffffff80000000000000000000000cb2bf8280f3f9742c7ed513fe802629c;
+tv[193]= 384'h00000000000000000000000000000000fffffffffc0000000000000000000000215a41ee442fa992a6e323986ded3f68;
+tv[194]= 384'h00000000000000000000000000000000fffffffffe0000000000000000000000f21e99cf4f0f77cea836e11a2fe75fb1;
+tv[195]= 384'h00000000000000000000000000000000ffffffffff000000000000000000000095e3a0ca9079e646331df8b4e70d2cd6;
+tv[196]= 384'h00000000000000000000000000000000ffffffffff80000000000000000000004afe7f120ce7613f74fc12a01a828073;
+tv[197]= 384'h00000000000000000000000000000000ffffffffffc000000000000000000000827f000e75e2c8b9d479beed913fe678;
+tv[198]= 384'h00000000000000000000000000000000ffffffffffe00000000000000000000035830c8e7aaefe2d30310ef381cbf691;
+tv[199]= 384'h00000000000000000000000000000000fffffffffff000000000000000000000191aa0f2c8570144f38657ea4085ebe5;
+tv[200]= 384'h00000000000000000000000000000000fffffffffff80000000000000000000085062c2c909f15d9269b6c18ce99c4f0;
+tv[201]= 384'h00000000000000000000000000000000fffffffffffc00000000000000000000678034dc9e41b5a560ed239eeab1bc78;
+tv[202]= 384'h00000000000000000000000000000000fffffffffffe00000000000000000000c2f93a4ce5ab6d5d56f1b93cf19911c1;
+tv[203]= 384'h00000000000000000000000000000000ffffffffffff000000000000000000001c3112bcb0c1dcc749d799743691bf82;
+tv[204]= 384'h00000000000000000000000000000000ffffffffffff8000000000000000000000c55bd75c7f9c881989d3ec1911c0d4;
+tv[205]= 384'h00000000000000000000000000000000ffffffffffffc0000000000000000000ea2e6b5ef182b7dff3629abd6a12045f;
+tv[206]= 384'h00000000000000000000000000000000ffffffffffffe000000000000000000022322327e01780b17397f24087f8cc6f;
+tv[207]= 384'h00000000000000000000000000000000fffffffffffff0000000000000000000c9cacb5cd11692c373b2411768149ee7;
+tv[208]= 384'h00000000000000000000000000000000fffffffffffff8000000000000000000a18e3dbbca577860dab6b80da3139256;
+tv[209]= 384'h00000000000000000000000000000000fffffffffffffc00000000000000000079b61c37bf328ecca8d743265a3d425c;
+tv[210]= 384'h00000000000000000000000000000000fffffffffffffe000000000000000000d2d99c6bcc1f06fda8e27e8ae3f1ccc7;
+tv[211]= 384'h00000000000000000000000000000000ffffffffffffff0000000000000000001bfd4b91c701fd6b61b7f997829d663b;
+tv[212]= 384'h00000000000000000000000000000000ffffffffffffff80000000000000000011005d52f25f16bdc9545a876a63490a;
+tv[213]= 384'h00000000000000000000000000000000ffffffffffffffc000000000000000003a4d354f02bb5a5e47d39666867f246a;
+tv[214]= 384'h00000000000000000000000000000000ffffffffffffffe00000000000000000d451b8d6e1e1a0ebb155fbbf6e7b7dc3;
+tv[215]= 384'h00000000000000000000000000000000fffffffffffffff000000000000000006898d4f42fa7ba6a10ac05e87b9f2080;
+tv[216]= 384'h00000000000000000000000000000000fffffffffffffff80000000000000000b611295e739ca7d9b50f8e4c0e754a3f;
+tv[217]= 384'h00000000000000000000000000000000fffffffffffffffc00000000000000007d33fc7d8abe3ca1936759f8f5deaf20;
+tv[218]= 384'h00000000000000000000000000000000fffffffffffffffe00000000000000003b5e0f566dc96c298f0c12637539b25c;
+tv[219]= 384'h00000000000000000000000000000000ffffffffffffffff0000000000000000f807c3e7985fe0f5a50e2cdb25c5109e;
+tv[220]= 384'h00000000000000000000000000000000ffffffffffffffff800000000000000041f992a856fb278b389a62f5d274d7e9;
+tv[221]= 384'h00000000000000000000000000000000ffffffffffffffffc00000000000000010d3ed7a6fe15ab4d91acbc7d0767ab1;
+tv[222]= 384'h00000000000000000000000000000000ffffffffffffffffe00000000000000021feecd45b2e675973ac33bf0c5424fc;
+tv[223]= 384'h00000000000000000000000000000000fffffffffffffffff0000000000000001480cb3955ba62d09eea668f7c708817;
+tv[224]= 384'h00000000000000000000000000000000fffffffffffffffff80000000000000066404033d6b72b609354d5496e7eb511;
+tv[225]= 384'h00000000000000000000000000000000fffffffffffffffffc000000000000001c317a220a7d700da2b1e075b00266e1;
+tv[226]= 384'h00000000000000000000000000000000fffffffffffffffffe00000000000000ab3b89542233f1271bf8fd0c0f403545;
+tv[227]= 384'h00000000000000000000000000000000ffffffffffffffffff00000000000000d93eae966fac46dca927d6b114fa3f9e;
+tv[228]= 384'h00000000000000000000000000000000ffffffffffffffffff800000000000001bdec521316503d9d5ee65df3ea94ddf;
+tv[229]= 384'h00000000000000000000000000000000ffffffffffffffffffc0000000000000eef456431dea8b4acf83bdae3717f75f;
+tv[230]= 384'h00000000000000000000000000000000ffffffffffffffffffe000000000000006f2519a2fafaa596bfef5cfa15c21b9;
+tv[231]= 384'h00000000000000000000000000000000fffffffffffffffffff0000000000000251a7eac7e2fe809e4aa8d0d7012531a;
+tv[232]= 384'h00000000000000000000000000000000fffffffffffffffffff80000000000003bffc16e4c49b268a20f8d96a60b4058;
+tv[233]= 384'h00000000000000000000000000000000fffffffffffffffffffc000000000000e886f9281999c5bb3b3e8862e2f7c988;
+tv[234]= 384'h00000000000000000000000000000000fffffffffffffffffffe000000000000563bf90d61beef39f48dd625fcef1361;
+tv[235]= 384'h00000000000000000000000000000000ffffffffffffffffffff0000000000004d37c850644563c69fd0acd9a049325b;
+tv[236]= 384'h00000000000000000000000000000000ffffffffffffffffffff800000000000b87c921b91829ef3b13ca541ee1130a6;
+tv[237]= 384'h00000000000000000000000000000000ffffffffffffffffffffc000000000002e65eb6b6ea383e109accce8326b0393;
+tv[238]= 384'h00000000000000000000000000000000ffffffffffffffffffffe000000000009ca547f7439edc3e255c0f4d49aa8990;
+tv[239]= 384'h00000000000000000000000000000000fffffffffffffffffffff00000000000a5e652614c9300f37816b1f9fd0c87f9;
+tv[240]= 384'h00000000000000000000000000000000fffffffffffffffffffff8000000000014954f0b4697776f44494fe458d814ed;
+tv[241]= 384'h00000000000000000000000000000000fffffffffffffffffffffc00000000007c8d9ab6c2761723fe42f8bb506cbcf7;
+tv[242]= 384'h00000000000000000000000000000000fffffffffffffffffffffe0000000000db7e1932679fdd99742aab04aa0d5a80;
+tv[243]= 384'h00000000000000000000000000000000ffffffffffffffffffffff00000000004c6a1c83e568cd10f27c2d73ded19c28;
+tv[244]= 384'h00000000000000000000000000000000ffffffffffffffffffffff800000000090ecbe6177e674c98de412413f7ac915;
+tv[245]= 384'h00000000000000000000000000000000ffffffffffffffffffffffc00000000090684a2ac55fe1ec2b8ebd5622520b73;
+tv[246]= 384'h00000000000000000000000000000000ffffffffffffffffffffffe0000000007472f9a7988607ca79707795991035e6;
+tv[247]= 384'h00000000000000000000000000000000fffffffffffffffffffffff00000000056aff089878bf3352f8df172a3ae47d8;
+tv[248]= 384'h00000000000000000000000000000000fffffffffffffffffffffff80000000065c0526cbe40161b8019a2a3171abd23;
+tv[249]= 384'h00000000000000000000000000000000fffffffffffffffffffffffc00000000377be0be33b4e3e310b4aabda173f84f;
+tv[250]= 384'h00000000000000000000000000000000fffffffffffffffffffffffe000000009402e9aa6f69de6504da8d20c4fcaa2f;
+tv[251]= 384'h00000000000000000000000000000000ffffffffffffffffffffffff00000000123c1f4af313ad8c2ce648b2e71fb6e1;
+tv[252]= 384'h00000000000000000000000000000000ffffffffffffffffffffffff800000001ffc626d30203dcdb0019fb80f726cf4;
+tv[253]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffc000000076da1fbe3a50728c50fd2e621b5ad885;
+tv[254]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffe0000000082eb8be35f442fb52668e16a591d1d6;
+tv[255]= 384'h00000000000000000000000000000000fffffffffffffffffffffffff0000000e656f9ecf5fe27ec3e4a73d00c282fb3;
+tv[256]= 384'h00000000000000000000000000000000fffffffffffffffffffffffff80000002ca8209d63274cd9a29bb74bcd77683a;
+tv[257]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffc00000079bf5dce14bb7dd73a8e3611de7ce026;
+tv[258]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffe0000003c849939a5d29399f344c4a0eca8a576;
+tv[259]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffff000000ed3c0a94d59bece98835da7aa4f07ca2;
+tv[260]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffff80000063919ed4ce10196438b6ad09d99cd795;
+tv[261]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffc000007678f3a833f19fea95f3c6029e2bc610;
+tv[262]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffe000003aa426831067d36b92be7c5f81c13c56;
+tv[263]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffff000009272e2d2cdd11050998c845077a30ea0;
+tv[264]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffff80000088c4b53f5ec0ff814c19adae7f6246c;
+tv[265]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffc00004010a5e401fdf0a0354ddbcc0d012b17;
+tv[266]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffe0000a87a385736c0a6189bd6589bd8445a93;
+tv[267]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffff0000545f2b83d9616dccf60fa9830e9cd287;
+tv[268]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffff80004b706f7f92406352394037a6d4f4688d;
+tv[269]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffc000b7972b3941c44b90afa7b264bfba7387;
+tv[270]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffe0006f45732cf10881546f0fd23896d2bb60;
+tv[271]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffff0002e3579ca15af27f64b3c955a5bfc30ba;
+tv[272]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffff80034a2c5a91ae2aec99b7d1b5fa6780447;
+tv[273]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffc00a4d6616bd04f87335b0e53351227a9ee;
+tv[274]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffe007f692b03945867d16179a8cefc83ea3f;
+tv[275]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffff003bd141ee84a0e6414a26e7a4f281f8a2;
+tv[276]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffff80d1788f572d98b2b16ec5d5f3922b99bc;
+tv[277]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffffc00833ff6f61d98a57b288e8c3586b85a6;
+tv[278]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffffe08568261797de176bf0b43becc6285afb;
+tv[279]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffff0f9b0fda0c4a898f5b9e6f661c4ce4d07;
+tv[280]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffff88ade895913685c67c5269f8aae42983e;
+tv[281]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffffc39bde67d5c8ed8a8b1c37eb8fa9f5ac0;
+tv[282]= 384'h00000000000000000000000000000000fffffffffffffffffffffffffffffffe5c005e72c1418c44f569f2ea33ba54f3;
+tv[283]= 384'h00000000000000000000000000000000ffffffffffffffffffffffffffffffff3f5b8cc9ea855a0afa7347d23e8d664e;
+
+
+for(n=0;n<284;n=n+1)
+ begin
+ @(posedge clk);
+ #1;
+ kld = 1;
+ @(posedge clk);
+ #1;
+ kld = 0;
+ @(posedge clk);
+
+ while(!done) @(posedge clk);
+
+ //$display("INFO: (a) Vector %0d: xpected %x, Got %x %t", n, ciph, text_out, $time);
+
+ if(text_out != ciph | (|text_out)==1'bx)
+ begin
+ $display("ERROR: (a) Vector %0d mismatch. Expected %x, Got %x",
+ n, ciph, text_out);
+ error_cnt = error_cnt + 1;
+ end
+
+
+ while(!done2) @(posedge clk);
+
+ //$display("INFO: (b) Vector %0d: xpected %x, Got %x", n, plain, text_out2);
+
+ if(text_out2 != plain | (|text_out2)==1'bx)
+ begin
+ $display("ERROR: (b) Vector %0d mismatch. Expected %x, Got %x",
+ n, plain, text_out2);
+ error_cnt = error_cnt + 1;
+ end
+
+ @(posedge clk);
+ #1;
+ end
+
+
+ $display("");
+ $display("");
+ $display("Test Done. Found %0d Errors.", error_cnt);
+ $display("");
+ $display("");
+ repeat(10) @(posedge clk);
+ $finish;
+end
+
+assign tmp = tv[n];
+assign key = kld ? tmp[383:256] : 128'hx;
+assign text_in = kld ? tmp[255:128] : 128'hx;
+assign plain = tmp[255:128];
+assign ciph = tmp[127:0];
+
+always #5 clk = ~clk;
+
+aes_cipher_top u0(
+ .clk( clk ),
+ .rst( rst ),
+ .ld( kld ),
+ .done( done ),
+ .key( key ),
+ .text_in( text_in ),
+ .text_out( text_out )
+ );
+
+aes_inv_cipher_top u1(
+ .clk( clk ),
+ .rst( rst ),
+ .kld( kld ),
+ .ld( done ),
+ .done( done2 ),
+ .key( key ),
+ .text_in( text_out ),
+ .text_out( text_out2 )
+ );
+
+endmodule
+
+
Index: aes_core/trunk/rtl/verilog/timescale.v
===================================================================
--- aes_core/trunk/rtl/verilog/timescale.v (nonexistent)
+++ aes_core/trunk/rtl/verilog/timescale.v (revision 6)
@@ -0,0 +1 @@
+`timescale 1ns / 10ps
Index: aes_core/trunk/rtl/verilog/aes_inv_sbox.v
===================================================================
--- aes_core/trunk/rtl/verilog/aes_inv_sbox.v (nonexistent)
+++ aes_core/trunk/rtl/verilog/aes_inv_sbox.v (revision 6)
@@ -0,0 +1,325 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Inverse SBOX (ROM) ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_inv_sbox.v,v 1.1.1.1 2002-11-09 11:22:55 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:55 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_inv_sbox(a,d);
+input [7:0] a;
+output [7:0] d;
+reg [7:0] d;
+
+always @(a)
+ case(a) // synopsys full_case parallel_case
+ 8'h00: d=8'h52;
+ 8'h01: d=8'h09;
+ 8'h02: d=8'h6a;
+ 8'h03: d=8'hd5;
+ 8'h04: d=8'h30;
+ 8'h05: d=8'h36;
+ 8'h06: d=8'ha5;
+ 8'h07: d=8'h38;
+ 8'h08: d=8'hbf;
+ 8'h09: d=8'h40;
+ 8'h0a: d=8'ha3;
+ 8'h0b: d=8'h9e;
+ 8'h0c: d=8'h81;
+ 8'h0d: d=8'hf3;
+ 8'h0e: d=8'hd7;
+ 8'h0f: d=8'hfb;
+ 8'h10: d=8'h7c;
+ 8'h11: d=8'he3;
+ 8'h12: d=8'h39;
+ 8'h13: d=8'h82;
+ 8'h14: d=8'h9b;
+ 8'h15: d=8'h2f;
+ 8'h16: d=8'hff;
+ 8'h17: d=8'h87;
+ 8'h18: d=8'h34;
+ 8'h19: d=8'h8e;
+ 8'h1a: d=8'h43;
+ 8'h1b: d=8'h44;
+ 8'h1c: d=8'hc4;
+ 8'h1d: d=8'hde;
+ 8'h1e: d=8'he9;
+ 8'h1f: d=8'hcb;
+ 8'h20: d=8'h54;
+ 8'h21: d=8'h7b;
+ 8'h22: d=8'h94;
+ 8'h23: d=8'h32;
+ 8'h24: d=8'ha6;
+ 8'h25: d=8'hc2;
+ 8'h26: d=8'h23;
+ 8'h27: d=8'h3d;
+ 8'h28: d=8'hee;
+ 8'h29: d=8'h4c;
+ 8'h2a: d=8'h95;
+ 8'h2b: d=8'h0b;
+ 8'h2c: d=8'h42;
+ 8'h2d: d=8'hfa;
+ 8'h2e: d=8'hc3;
+ 8'h2f: d=8'h4e;
+ 8'h30: d=8'h08;
+ 8'h31: d=8'h2e;
+ 8'h32: d=8'ha1;
+ 8'h33: d=8'h66;
+ 8'h34: d=8'h28;
+ 8'h35: d=8'hd9;
+ 8'h36: d=8'h24;
+ 8'h37: d=8'hb2;
+ 8'h38: d=8'h76;
+ 8'h39: d=8'h5b;
+ 8'h3a: d=8'ha2;
+ 8'h3b: d=8'h49;
+ 8'h3c: d=8'h6d;
+ 8'h3d: d=8'h8b;
+ 8'h3e: d=8'hd1;
+ 8'h3f: d=8'h25;
+ 8'h40: d=8'h72;
+ 8'h41: d=8'hf8;
+ 8'h42: d=8'hf6;
+ 8'h43: d=8'h64;
+ 8'h44: d=8'h86;
+ 8'h45: d=8'h68;
+ 8'h46: d=8'h98;
+ 8'h47: d=8'h16;
+ 8'h48: d=8'hd4;
+ 8'h49: d=8'ha4;
+ 8'h4a: d=8'h5c;
+ 8'h4b: d=8'hcc;
+ 8'h4c: d=8'h5d;
+ 8'h4d: d=8'h65;
+ 8'h4e: d=8'hb6;
+ 8'h4f: d=8'h92;
+ 8'h50: d=8'h6c;
+ 8'h51: d=8'h70;
+ 8'h52: d=8'h48;
+ 8'h53: d=8'h50;
+ 8'h54: d=8'hfd;
+ 8'h55: d=8'hed;
+ 8'h56: d=8'hb9;
+ 8'h57: d=8'hda;
+ 8'h58: d=8'h5e;
+ 8'h59: d=8'h15;
+ 8'h5a: d=8'h46;
+ 8'h5b: d=8'h57;
+ 8'h5c: d=8'ha7;
+ 8'h5d: d=8'h8d;
+ 8'h5e: d=8'h9d;
+ 8'h5f: d=8'h84;
+ 8'h60: d=8'h90;
+ 8'h61: d=8'hd8;
+ 8'h62: d=8'hab;
+ 8'h63: d=8'h00;
+ 8'h64: d=8'h8c;
+ 8'h65: d=8'hbc;
+ 8'h66: d=8'hd3;
+ 8'h67: d=8'h0a;
+ 8'h68: d=8'hf7;
+ 8'h69: d=8'he4;
+ 8'h6a: d=8'h58;
+ 8'h6b: d=8'h05;
+ 8'h6c: d=8'hb8;
+ 8'h6d: d=8'hb3;
+ 8'h6e: d=8'h45;
+ 8'h6f: d=8'h06;
+ 8'h70: d=8'hd0;
+ 8'h71: d=8'h2c;
+ 8'h72: d=8'h1e;
+ 8'h73: d=8'h8f;
+ 8'h74: d=8'hca;
+ 8'h75: d=8'h3f;
+ 8'h76: d=8'h0f;
+ 8'h77: d=8'h02;
+ 8'h78: d=8'hc1;
+ 8'h79: d=8'haf;
+ 8'h7a: d=8'hbd;
+ 8'h7b: d=8'h03;
+ 8'h7c: d=8'h01;
+ 8'h7d: d=8'h13;
+ 8'h7e: d=8'h8a;
+ 8'h7f: d=8'h6b;
+ 8'h80: d=8'h3a;
+ 8'h81: d=8'h91;
+ 8'h82: d=8'h11;
+ 8'h83: d=8'h41;
+ 8'h84: d=8'h4f;
+ 8'h85: d=8'h67;
+ 8'h86: d=8'hdc;
+ 8'h87: d=8'hea;
+ 8'h88: d=8'h97;
+ 8'h89: d=8'hf2;
+ 8'h8a: d=8'hcf;
+ 8'h8b: d=8'hce;
+ 8'h8c: d=8'hf0;
+ 8'h8d: d=8'hb4;
+ 8'h8e: d=8'he6;
+ 8'h8f: d=8'h73;
+ 8'h90: d=8'h96;
+ 8'h91: d=8'hac;
+ 8'h92: d=8'h74;
+ 8'h93: d=8'h22;
+ 8'h94: d=8'he7;
+ 8'h95: d=8'had;
+ 8'h96: d=8'h35;
+ 8'h97: d=8'h85;
+ 8'h98: d=8'he2;
+ 8'h99: d=8'hf9;
+ 8'h9a: d=8'h37;
+ 8'h9b: d=8'he8;
+ 8'h9c: d=8'h1c;
+ 8'h9d: d=8'h75;
+ 8'h9e: d=8'hdf;
+ 8'h9f: d=8'h6e;
+ 8'ha0: d=8'h47;
+ 8'ha1: d=8'hf1;
+ 8'ha2: d=8'h1a;
+ 8'ha3: d=8'h71;
+ 8'ha4: d=8'h1d;
+ 8'ha5: d=8'h29;
+ 8'ha6: d=8'hc5;
+ 8'ha7: d=8'h89;
+ 8'ha8: d=8'h6f;
+ 8'ha9: d=8'hb7;
+ 8'haa: d=8'h62;
+ 8'hab: d=8'h0e;
+ 8'hac: d=8'haa;
+ 8'had: d=8'h18;
+ 8'hae: d=8'hbe;
+ 8'haf: d=8'h1b;
+ 8'hb0: d=8'hfc;
+ 8'hb1: d=8'h56;
+ 8'hb2: d=8'h3e;
+ 8'hb3: d=8'h4b;
+ 8'hb4: d=8'hc6;
+ 8'hb5: d=8'hd2;
+ 8'hb6: d=8'h79;
+ 8'hb7: d=8'h20;
+ 8'hb8: d=8'h9a;
+ 8'hb9: d=8'hdb;
+ 8'hba: d=8'hc0;
+ 8'hbb: d=8'hfe;
+ 8'hbc: d=8'h78;
+ 8'hbd: d=8'hcd;
+ 8'hbe: d=8'h5a;
+ 8'hbf: d=8'hf4;
+ 8'hc0: d=8'h1f;
+ 8'hc1: d=8'hdd;
+ 8'hc2: d=8'ha8;
+ 8'hc3: d=8'h33;
+ 8'hc4: d=8'h88;
+ 8'hc5: d=8'h07;
+ 8'hc6: d=8'hc7;
+ 8'hc7: d=8'h31;
+ 8'hc8: d=8'hb1;
+ 8'hc9: d=8'h12;
+ 8'hca: d=8'h10;
+ 8'hcb: d=8'h59;
+ 8'hcc: d=8'h27;
+ 8'hcd: d=8'h80;
+ 8'hce: d=8'hec;
+ 8'hcf: d=8'h5f;
+ 8'hd0: d=8'h60;
+ 8'hd1: d=8'h51;
+ 8'hd2: d=8'h7f;
+ 8'hd3: d=8'ha9;
+ 8'hd4: d=8'h19;
+ 8'hd5: d=8'hb5;
+ 8'hd6: d=8'h4a;
+ 8'hd7: d=8'h0d;
+ 8'hd8: d=8'h2d;
+ 8'hd9: d=8'he5;
+ 8'hda: d=8'h7a;
+ 8'hdb: d=8'h9f;
+ 8'hdc: d=8'h93;
+ 8'hdd: d=8'hc9;
+ 8'hde: d=8'h9c;
+ 8'hdf: d=8'hef;
+ 8'he0: d=8'ha0;
+ 8'he1: d=8'he0;
+ 8'he2: d=8'h3b;
+ 8'he3: d=8'h4d;
+ 8'he4: d=8'hae;
+ 8'he5: d=8'h2a;
+ 8'he6: d=8'hf5;
+ 8'he7: d=8'hb0;
+ 8'he8: d=8'hc8;
+ 8'he9: d=8'heb;
+ 8'hea: d=8'hbb;
+ 8'heb: d=8'h3c;
+ 8'hec: d=8'h83;
+ 8'hed: d=8'h53;
+ 8'hee: d=8'h99;
+ 8'hef: d=8'h61;
+ 8'hf0: d=8'h17;
+ 8'hf1: d=8'h2b;
+ 8'hf2: d=8'h04;
+ 8'hf3: d=8'h7e;
+ 8'hf4: d=8'hba;
+ 8'hf5: d=8'h77;
+ 8'hf6: d=8'hd6;
+ 8'hf7: d=8'h26;
+ 8'hf8: d=8'he1;
+ 8'hf9: d=8'h69;
+ 8'hfa: d=8'h14;
+ 8'hfb: d=8'h63;
+ 8'hfc: d=8'h55;
+ 8'hfd: d=8'h21;
+ 8'hfe: d=8'h0c;
+ 8'hff: d=8'h7d;
+ endcase
+endmodule
+
+
Index: aes_core/trunk/rtl/verilog/aes_inv_cipher_top.v
===================================================================
--- aes_core/trunk/rtl/verilog/aes_inv_cipher_top.v (nonexistent)
+++ aes_core/trunk/rtl/verilog/aes_inv_cipher_top.v (revision 6)
@@ -0,0 +1,324 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Inverse Cipher Top Level ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_inv_cipher_top.v,v 1.1.1.1 2002-11-09 11:22:53 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:53 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_inv_cipher_top(clk, rst, kld, ld, done, key, text_in, text_out );
+input clk, rst;
+input kld, ld;
+output done;
+input [127:0] key;
+input [127:0] text_in;
+output [127:0] text_out;
+
+////////////////////////////////////////////////////////////////////
+//
+// Local Wires
+//
+
+wire [31:0] wk0, wk1, wk2, wk3;
+reg [31:0] w0, w1, w2, w3;
+reg [127:0] text_in_r;
+reg [127:0] text_out;
+reg [7:0] sa00, sa01, sa02, sa03;
+reg [7:0] sa10, sa11, sa12, sa13;
+reg [7:0] sa20, sa21, sa22, sa23;
+reg [7:0] sa30, sa31, sa32, sa33;
+wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
+wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
+wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
+wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
+wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
+wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
+wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
+wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
+wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
+wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
+wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
+wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
+wire [7:0] sa00_ark, sa01_ark, sa02_ark, sa03_ark;
+wire [7:0] sa10_ark, sa11_ark, sa12_ark, sa13_ark;
+wire [7:0] sa20_ark, sa21_ark, sa22_ark, sa23_ark;
+wire [7:0] sa30_ark, sa31_ark, sa32_ark, sa33_ark;
+reg ld_r, go, done;
+reg [3:0] dcnt;
+
+////////////////////////////////////////////////////////////////////
+//
+// Misc Logic
+//
+
+always @(posedge clk)
+ if(!rst) dcnt <= #1 4'h0;
+ else
+ if(done) dcnt <= #1 4'h0;
+ else
+ if(ld) dcnt <= #1 4'h1;
+ else
+ if(go) dcnt <= #1 dcnt + 4'h1;
+
+always @(posedge clk) done <= #1 (dcnt==4'hb) & !ld;
+
+always @(posedge clk)
+ if(!rst) go <= #1 1'b0;
+ else
+ if(ld) go <= #1 1'b1;
+ else
+ if(done) go <= #1 1'b0;
+
+always @(posedge clk) if(ld) text_in_r <= #1 text_in;
+
+always @(posedge clk) ld_r <= #1 ld;
+
+////////////////////////////////////////////////////////////////////
+//
+// Initial Permutation
+//
+
+always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
+always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
+always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
+always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
+always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
+always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
+always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
+always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
+always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
+always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
+always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
+always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
+always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
+always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
+always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
+always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
+
+////////////////////////////////////////////////////////////////////
+//
+// Round Permutations
+//
+
+assign sa00_sr = sa00;
+assign sa01_sr = sa01;
+assign sa02_sr = sa02;
+assign sa03_sr = sa03;
+assign sa10_sr = sa13;
+assign sa11_sr = sa10;
+assign sa12_sr = sa11;
+assign sa13_sr = sa12;
+assign sa20_sr = sa22;
+assign sa21_sr = sa23;
+assign sa22_sr = sa20;
+assign sa23_sr = sa21;
+assign sa30_sr = sa31;
+assign sa31_sr = sa32;
+assign sa32_sr = sa33;
+assign sa33_sr = sa30;
+assign sa00_ark = sa00_sub ^ w0[31:24];
+assign sa01_ark = sa01_sub ^ w1[31:24];
+assign sa02_ark = sa02_sub ^ w2[31:24];
+assign sa03_ark = sa03_sub ^ w3[31:24];
+assign sa10_ark = sa10_sub ^ w0[23:16];
+assign sa11_ark = sa11_sub ^ w1[23:16];
+assign sa12_ark = sa12_sub ^ w2[23:16];
+assign sa13_ark = sa13_sub ^ w3[23:16];
+assign sa20_ark = sa20_sub ^ w0[15:08];
+assign sa21_ark = sa21_sub ^ w1[15:08];
+assign sa22_ark = sa22_sub ^ w2[15:08];
+assign sa23_ark = sa23_sub ^ w3[15:08];
+assign sa30_ark = sa30_sub ^ w0[07:00];
+assign sa31_ark = sa31_sub ^ w1[07:00];
+assign sa32_ark = sa32_sub ^ w2[07:00];
+assign sa33_ark = sa33_sub ^ w3[07:00];
+assign {sa00_next, sa10_next, sa20_next, sa30_next} = inv_mix_col(sa00_ark,sa10_ark,sa20_ark,sa30_ark);
+assign {sa01_next, sa11_next, sa21_next, sa31_next} = inv_mix_col(sa01_ark,sa11_ark,sa21_ark,sa31_ark);
+assign {sa02_next, sa12_next, sa22_next, sa32_next} = inv_mix_col(sa02_ark,sa12_ark,sa22_ark,sa32_ark);
+assign {sa03_next, sa13_next, sa23_next, sa33_next} = inv_mix_col(sa03_ark,sa13_ark,sa23_ark,sa33_ark);
+
+////////////////////////////////////////////////////////////////////
+//
+// Final Text Output
+//
+
+always @(posedge clk) text_out[127:120] <= #1 sa00_ark;
+always @(posedge clk) text_out[095:088] <= #1 sa01_ark;
+always @(posedge clk) text_out[063:056] <= #1 sa02_ark;
+always @(posedge clk) text_out[031:024] <= #1 sa03_ark;
+always @(posedge clk) text_out[119:112] <= #1 sa10_ark;
+always @(posedge clk) text_out[087:080] <= #1 sa11_ark;
+always @(posedge clk) text_out[055:048] <= #1 sa12_ark;
+always @(posedge clk) text_out[023:016] <= #1 sa13_ark;
+always @(posedge clk) text_out[111:104] <= #1 sa20_ark;
+always @(posedge clk) text_out[079:072] <= #1 sa21_ark;
+always @(posedge clk) text_out[047:040] <= #1 sa22_ark;
+always @(posedge clk) text_out[015:008] <= #1 sa23_ark;
+always @(posedge clk) text_out[103:096] <= #1 sa30_ark;
+always @(posedge clk) text_out[071:064] <= #1 sa31_ark;
+always @(posedge clk) text_out[039:032] <= #1 sa32_ark;
+always @(posedge clk) text_out[007:000] <= #1 sa33_ark;
+
+////////////////////////////////////////////////////////////////////
+//
+// Generic Functions
+//
+
+function [31:0] inv_mix_col;
+input [7:0] s0,s1,s2,s3;
+begin
+inv_mix_col[31:24]=pmul_e(s0)^pmul_b(s1)^pmul_d(s2)^pmul_9(s3);
+inv_mix_col[23:16]=pmul_9(s0)^pmul_e(s1)^pmul_b(s2)^pmul_d(s3);
+inv_mix_col[15:08]=pmul_d(s0)^pmul_9(s1)^pmul_e(s2)^pmul_b(s3);
+inv_mix_col[07:00]=pmul_b(s0)^pmul_d(s1)^pmul_9(s2)^pmul_e(s3);
+end
+endfunction
+
+// Some synthesis tools don't like xtime being called recursevly ...
+function [7:0] pmul_e;
+input [7:0] b;
+reg [7:0] two,four,eight;
+begin
+two=xtime(b);four=xtime(two);eight=xtime(four);pmul_e=eight^four^two;
+end
+endfunction
+
+function [7:0] pmul_9;
+input [7:0] b;
+reg [7:0] two,four,eight;
+begin
+two=xtime(b);four=xtime(two);eight=xtime(four);pmul_9=eight^b;
+end
+endfunction
+
+function [7:0] pmul_d;
+input [7:0] b;
+reg [7:0] two,four,eight;
+begin
+two=xtime(b);four=xtime(two);eight=xtime(four);pmul_d=eight^four^b;
+end
+endfunction
+
+function [7:0] pmul_b;
+input [7:0] b;
+reg [7:0] two,four,eight;
+begin
+two=xtime(b);four=xtime(two);eight=xtime(four);pmul_b=eight^two^b;
+end
+endfunction
+
+function [7:0] xtime;
+input [7:0] b;xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
+endfunction
+
+////////////////////////////////////////////////////////////////////
+//
+// Key Buffer
+//
+
+reg [127:0] kb[10:0];
+reg [3:0] kcnt;
+reg kdone;
+reg kb_ld;
+
+always @(posedge clk)
+ if(!rst) kcnt <= #1 4'ha;
+ else
+ if(kld) kcnt <= #1 4'ha;
+ else
+ if(kb_ld) kcnt <= #1 kcnt - 4'h1;
+
+always @(posedge clk)
+ if(!rst) kb_ld <= #1 1'b0;
+ else
+ if(kld) kb_ld <= #1 1'b1;
+ else
+ if(kcnt==4'h0) kb_ld <= #1 1'b0;
+
+always @(posedge clk) kdone <= #1 (kcnt==4'h0) & !kld;
+always @(posedge clk) if(kb_ld) kb[kcnt] <= #1 {wk3, wk2, wk1, wk0};
+always @(posedge clk) {w3, w2, w1, w0} <= #1 kb[dcnt];
+
+////////////////////////////////////////////////////////////////////
+//
+// Modules
+//
+
+aes_key_expand_128 u0(
+ .clk( clk ),
+ .kld( kld ),
+ .key( key ),
+ .wo_0( wk0 ),
+ .wo_1( wk1 ),
+ .wo_2( wk2 ),
+ .wo_3( wk3 ));
+
+aes_inv_sbox us00( .a( sa00_sr ), .d( sa00_sub ));
+aes_inv_sbox us01( .a( sa01_sr ), .d( sa01_sub ));
+aes_inv_sbox us02( .a( sa02_sr ), .d( sa02_sub ));
+aes_inv_sbox us03( .a( sa03_sr ), .d( sa03_sub ));
+aes_inv_sbox us10( .a( sa10_sr ), .d( sa10_sub ));
+aes_inv_sbox us11( .a( sa11_sr ), .d( sa11_sub ));
+aes_inv_sbox us12( .a( sa12_sr ), .d( sa12_sub ));
+aes_inv_sbox us13( .a( sa13_sr ), .d( sa13_sub ));
+aes_inv_sbox us20( .a( sa20_sr ), .d( sa20_sub ));
+aes_inv_sbox us21( .a( sa21_sr ), .d( sa21_sub ));
+aes_inv_sbox us22( .a( sa22_sr ), .d( sa22_sub ));
+aes_inv_sbox us23( .a( sa23_sr ), .d( sa23_sub ));
+aes_inv_sbox us30( .a( sa30_sr ), .d( sa30_sub ));
+aes_inv_sbox us31( .a( sa31_sr ), .d( sa31_sub ));
+aes_inv_sbox us32( .a( sa32_sr ), .d( sa32_sub ));
+aes_inv_sbox us33( .a( sa33_sr ), .d( sa33_sub ));
+
+endmodule
+
Index: aes_core/trunk/rtl/verilog/aes_sbox.v
===================================================================
--- aes_core/trunk/rtl/verilog/aes_sbox.v (nonexistent)
+++ aes_core/trunk/rtl/verilog/aes_sbox.v (revision 6)
@@ -0,0 +1,326 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES SBOX (ROM) ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_sbox.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:38 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_sbox(a,d);
+input [7:0] a;
+output [7:0] d;
+reg [7:0] d;
+
+always @(a)
+ case(a) // synopsys full_case parallel_case
+ 8'h00: d=8'h63;
+ 8'h01: d=8'h7c;
+ 8'h02: d=8'h77;
+ 8'h03: d=8'h7b;
+ 8'h04: d=8'hf2;
+ 8'h05: d=8'h6b;
+ 8'h06: d=8'h6f;
+ 8'h07: d=8'hc5;
+ 8'h08: d=8'h30;
+ 8'h09: d=8'h01;
+ 8'h0a: d=8'h67;
+ 8'h0b: d=8'h2b;
+ 8'h0c: d=8'hfe;
+ 8'h0d: d=8'hd7;
+ 8'h0e: d=8'hab;
+ 8'h0f: d=8'h76;
+ 8'h10: d=8'hca;
+ 8'h11: d=8'h82;
+ 8'h12: d=8'hc9;
+ 8'h13: d=8'h7d;
+ 8'h14: d=8'hfa;
+ 8'h15: d=8'h59;
+ 8'h16: d=8'h47;
+ 8'h17: d=8'hf0;
+ 8'h18: d=8'had;
+ 8'h19: d=8'hd4;
+ 8'h1a: d=8'ha2;
+ 8'h1b: d=8'haf;
+ 8'h1c: d=8'h9c;
+ 8'h1d: d=8'ha4;
+ 8'h1e: d=8'h72;
+ 8'h1f: d=8'hc0;
+ 8'h20: d=8'hb7;
+ 8'h21: d=8'hfd;
+ 8'h22: d=8'h93;
+ 8'h23: d=8'h26;
+ 8'h24: d=8'h36;
+ 8'h25: d=8'h3f;
+ 8'h26: d=8'hf7;
+ 8'h27: d=8'hcc;
+ 8'h28: d=8'h34;
+ 8'h29: d=8'ha5;
+ 8'h2a: d=8'he5;
+ 8'h2b: d=8'hf1;
+ 8'h2c: d=8'h71;
+ 8'h2d: d=8'hd8;
+ 8'h2e: d=8'h31;
+ 8'h2f: d=8'h15;
+ 8'h30: d=8'h04;
+ 8'h31: d=8'hc7;
+ 8'h32: d=8'h23;
+ 8'h33: d=8'hc3;
+ 8'h34: d=8'h18;
+ 8'h35: d=8'h96;
+ 8'h36: d=8'h05;
+ 8'h37: d=8'h9a;
+ 8'h38: d=8'h07;
+ 8'h39: d=8'h12;
+ 8'h3a: d=8'h80;
+ 8'h3b: d=8'he2;
+ 8'h3c: d=8'heb;
+ 8'h3d: d=8'h27;
+ 8'h3e: d=8'hb2;
+ 8'h3f: d=8'h75;
+ 8'h40: d=8'h09;
+ 8'h41: d=8'h83;
+ 8'h42: d=8'h2c;
+ 8'h43: d=8'h1a;
+ 8'h44: d=8'h1b;
+ 8'h45: d=8'h6e;
+ 8'h46: d=8'h5a;
+ 8'h47: d=8'ha0;
+ 8'h48: d=8'h52;
+ 8'h49: d=8'h3b;
+ 8'h4a: d=8'hd6;
+ 8'h4b: d=8'hb3;
+ 8'h4c: d=8'h29;
+ 8'h4d: d=8'he3;
+ 8'h4e: d=8'h2f;
+ 8'h4f: d=8'h84;
+ 8'h50: d=8'h53;
+ 8'h51: d=8'hd1;
+ 8'h52: d=8'h00;
+ 8'h53: d=8'hed;
+ 8'h54: d=8'h20;
+ 8'h55: d=8'hfc;
+ 8'h56: d=8'hb1;
+ 8'h57: d=8'h5b;
+ 8'h58: d=8'h6a;
+ 8'h59: d=8'hcb;
+ 8'h5a: d=8'hbe;
+ 8'h5b: d=8'h39;
+ 8'h5c: d=8'h4a;
+ 8'h5d: d=8'h4c;
+ 8'h5e: d=8'h58;
+ 8'h5f: d=8'hcf;
+ 8'h60: d=8'hd0;
+ 8'h61: d=8'hef;
+ 8'h62: d=8'haa;
+ 8'h63: d=8'hfb;
+ 8'h64: d=8'h43;
+ 8'h65: d=8'h4d;
+ 8'h66: d=8'h33;
+ 8'h67: d=8'h85;
+ 8'h68: d=8'h45;
+ 8'h69: d=8'hf9;
+ 8'h6a: d=8'h02;
+ 8'h6b: d=8'h7f;
+ 8'h6c: d=8'h50;
+ 8'h6d: d=8'h3c;
+ 8'h6e: d=8'h9f;
+ 8'h6f: d=8'ha8;
+ 8'h70: d=8'h51;
+ 8'h71: d=8'ha3;
+ 8'h72: d=8'h40;
+ 8'h73: d=8'h8f;
+ 8'h74: d=8'h92;
+ 8'h75: d=8'h9d;
+ 8'h76: d=8'h38;
+ 8'h77: d=8'hf5;
+ 8'h78: d=8'hbc;
+ 8'h79: d=8'hb6;
+ 8'h7a: d=8'hda;
+ 8'h7b: d=8'h21;
+ 8'h7c: d=8'h10;
+ 8'h7d: d=8'hff;
+ 8'h7e: d=8'hf3;
+ 8'h7f: d=8'hd2;
+ 8'h80: d=8'hcd;
+ 8'h81: d=8'h0c;
+ 8'h82: d=8'h13;
+ 8'h83: d=8'hec;
+ 8'h84: d=8'h5f;
+ 8'h85: d=8'h97;
+ 8'h86: d=8'h44;
+ 8'h87: d=8'h17;
+ 8'h88: d=8'hc4;
+ 8'h89: d=8'ha7;
+ 8'h8a: d=8'h7e;
+ 8'h8b: d=8'h3d;
+ 8'h8c: d=8'h64;
+ 8'h8d: d=8'h5d;
+ 8'h8e: d=8'h19;
+ 8'h8f: d=8'h73;
+ 8'h90: d=8'h60;
+ 8'h91: d=8'h81;
+ 8'h92: d=8'h4f;
+ 8'h93: d=8'hdc;
+ 8'h94: d=8'h22;
+ 8'h95: d=8'h2a;
+ 8'h96: d=8'h90;
+ 8'h97: d=8'h88;
+ 8'h98: d=8'h46;
+ 8'h99: d=8'hee;
+ 8'h9a: d=8'hb8;
+ 8'h9b: d=8'h14;
+ 8'h9c: d=8'hde;
+ 8'h9d: d=8'h5e;
+ 8'h9e: d=8'h0b;
+ 8'h9f: d=8'hdb;
+ 8'ha0: d=8'he0;
+ 8'ha1: d=8'h32;
+ 8'ha2: d=8'h3a;
+ 8'ha3: d=8'h0a;
+ 8'ha4: d=8'h49;
+ 8'ha5: d=8'h06;
+ 8'ha6: d=8'h24;
+ 8'ha7: d=8'h5c;
+ 8'ha8: d=8'hc2;
+ 8'ha9: d=8'hd3;
+ 8'haa: d=8'hac;
+ 8'hab: d=8'h62;
+ 8'hac: d=8'h91;
+ 8'had: d=8'h95;
+ 8'hae: d=8'he4;
+ 8'haf: d=8'h79;
+ 8'hb0: d=8'he7;
+ 8'hb1: d=8'hc8;
+ 8'hb2: d=8'h37;
+ 8'hb3: d=8'h6d;
+ 8'hb4: d=8'h8d;
+ 8'hb5: d=8'hd5;
+ 8'hb6: d=8'h4e;
+ 8'hb7: d=8'ha9;
+ 8'hb8: d=8'h6c;
+ 8'hb9: d=8'h56;
+ 8'hba: d=8'hf4;
+ 8'hbb: d=8'hea;
+ 8'hbc: d=8'h65;
+ 8'hbd: d=8'h7a;
+ 8'hbe: d=8'hae;
+ 8'hbf: d=8'h08;
+ 8'hc0: d=8'hba;
+ 8'hc1: d=8'h78;
+ 8'hc2: d=8'h25;
+ 8'hc3: d=8'h2e;
+ 8'hc4: d=8'h1c;
+ 8'hc5: d=8'ha6;
+ 8'hc6: d=8'hb4;
+ 8'hc7: d=8'hc6;
+ 8'hc8: d=8'he8;
+ 8'hc9: d=8'hdd;
+ 8'hca: d=8'h74;
+ 8'hcb: d=8'h1f;
+ 8'hcc: d=8'h4b;
+ 8'hcd: d=8'hbd;
+ 8'hce: d=8'h8b;
+ 8'hcf: d=8'h8a;
+ 8'hd0: d=8'h70;
+ 8'hd1: d=8'h3e;
+ 8'hd2: d=8'hb5;
+ 8'hd3: d=8'h66;
+ 8'hd4: d=8'h48;
+ 8'hd5: d=8'h03;
+ 8'hd6: d=8'hf6;
+ 8'hd7: d=8'h0e;
+ 8'hd8: d=8'h61;
+ 8'hd9: d=8'h35;
+ 8'hda: d=8'h57;
+ 8'hdb: d=8'hb9;
+ 8'hdc: d=8'h86;
+ 8'hdd: d=8'hc1;
+ 8'hde: d=8'h1d;
+ 8'hdf: d=8'h9e;
+ 8'he0: d=8'he1;
+ 8'he1: d=8'hf8;
+ 8'he2: d=8'h98;
+ 8'he3: d=8'h11;
+ 8'he4: d=8'h69;
+ 8'he5: d=8'hd9;
+ 8'he6: d=8'h8e;
+ 8'he7: d=8'h94;
+ 8'he8: d=8'h9b;
+ 8'he9: d=8'h1e;
+ 8'hea: d=8'h87;
+ 8'heb: d=8'he9;
+ 8'hec: d=8'hce;
+ 8'hed: d=8'h55;
+ 8'hee: d=8'h28;
+ 8'hef: d=8'hdf;
+ 8'hf0: d=8'h8c;
+ 8'hf1: d=8'ha1;
+ 8'hf2: d=8'h89;
+ 8'hf3: d=8'h0d;
+ 8'hf4: d=8'hbf;
+ 8'hf5: d=8'he6;
+ 8'hf6: d=8'h42;
+ 8'hf7: d=8'h68;
+ 8'hf8: d=8'h41;
+ 8'hf9: d=8'h99;
+ 8'hfa: d=8'h2d;
+ 8'hfb: d=8'h0f;
+ 8'hfc: d=8'hb0;
+ 8'hfd: d=8'h54;
+ 8'hfe: d=8'hbb;
+ 8'hff: d=8'h16;
+ endcase
+
+endmodule
+
+
Index: aes_core/trunk/rtl/verilog/aes_cipher_top.v
===================================================================
--- aes_core/trunk/rtl/verilog/aes_cipher_top.v (nonexistent)
+++ aes_core/trunk/rtl/verilog/aes_cipher_top.v (revision 6)
@@ -0,0 +1,253 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Cipher Top Level ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_cipher_top.v,v 1.1.1.1 2002-11-09 11:22:48 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:48 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out );
+input clk, rst;
+input ld;
+output done;
+input [127:0] key;
+input [127:0] text_in;
+output [127:0] text_out;
+
+////////////////////////////////////////////////////////////////////
+//
+// Local Wires
+//
+
+wire [31:0] w0, w1, w2, w3;
+reg [127:0] text_in_r;
+reg [127:0] text_out;
+reg [7:0] sa00, sa01, sa02, sa03;
+reg [7:0] sa10, sa11, sa12, sa13;
+reg [7:0] sa20, sa21, sa22, sa23;
+reg [7:0] sa30, sa31, sa32, sa33;
+wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
+wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
+wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
+wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
+wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
+wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
+wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
+wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
+wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
+wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
+wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
+wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
+wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc;
+wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc;
+wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc;
+wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc;
+reg done, ld_r;
+reg [3:0] dcnt;
+
+////////////////////////////////////////////////////////////////////
+//
+// Misc Logic
+//
+
+always @(posedge clk)
+ if(!rst) dcnt <= #1 4'h0;
+ else
+ if(ld) dcnt <= #1 4'hb;
+ else
+ if(|dcnt) dcnt <= #1 dcnt - 4'h1;
+
+always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld;
+always @(posedge clk) if(ld) text_in_r <= #1 text_in;
+always @(posedge clk) ld_r <= #1 ld;
+
+////////////////////////////////////////////////////////////////////
+//
+// Initial Permutation (AddRoundKey)
+//
+
+always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
+always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
+always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
+always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
+always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
+always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
+always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
+always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
+always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
+always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
+always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
+always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
+always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
+always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
+always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
+always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
+
+////////////////////////////////////////////////////////////////////
+//
+// Round Permutations
+//
+
+assign sa00_sr = sa00_sub;
+assign sa01_sr = sa01_sub;
+assign sa02_sr = sa02_sub;
+assign sa03_sr = sa03_sub;
+assign sa10_sr = sa11_sub;
+assign sa11_sr = sa12_sub;
+assign sa12_sr = sa13_sub;
+assign sa13_sr = sa10_sub;
+assign sa20_sr = sa22_sub;
+assign sa21_sr = sa23_sub;
+assign sa22_sr = sa20_sub;
+assign sa23_sr = sa21_sub;
+assign sa30_sr = sa33_sub;
+assign sa31_sr = sa30_sub;
+assign sa32_sr = sa31_sub;
+assign sa33_sr = sa32_sub;
+assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc} = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
+assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc} = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
+assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc} = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
+assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc} = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
+assign sa00_next = sa00_mc ^ w0[31:24];
+assign sa01_next = sa01_mc ^ w1[31:24];
+assign sa02_next = sa02_mc ^ w2[31:24];
+assign sa03_next = sa03_mc ^ w3[31:24];
+assign sa10_next = sa10_mc ^ w0[23:16];
+assign sa11_next = sa11_mc ^ w1[23:16];
+assign sa12_next = sa12_mc ^ w2[23:16];
+assign sa13_next = sa13_mc ^ w3[23:16];
+assign sa20_next = sa20_mc ^ w0[15:08];
+assign sa21_next = sa21_mc ^ w1[15:08];
+assign sa22_next = sa22_mc ^ w2[15:08];
+assign sa23_next = sa23_mc ^ w3[15:08];
+assign sa30_next = sa30_mc ^ w0[07:00];
+assign sa31_next = sa31_mc ^ w1[07:00];
+assign sa32_next = sa32_mc ^ w2[07:00];
+assign sa33_next = sa33_mc ^ w3[07:00];
+
+////////////////////////////////////////////////////////////////////
+//
+// Final text output
+//
+
+always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24];
+always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24];
+always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24];
+always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24];
+always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16];
+always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16];
+always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16];
+always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16];
+always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08];
+always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08];
+always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08];
+always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08];
+always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00];
+always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00];
+always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00];
+always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00];
+
+////////////////////////////////////////////////////////////////////
+//
+// Generic Functions
+//
+
+function [31:0] mix_col;
+input [7:0] s0,s1,s2,s3;
+reg [7:0] s0_o,s1_o,s2_o,s3_o;
+begin
+mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
+mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
+mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
+mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
+end
+endfunction
+
+function [7:0] xtime;
+input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
+endfunction
+
+////////////////////////////////////////////////////////////////////
+//
+// Modules
+//
+
+aes_key_expand_128 u0(
+ .clk( clk ),
+ .kld( ld ),
+ .key( key ),
+ .wo_0( w0 ),
+ .wo_1( w1 ),
+ .wo_2( w2 ),
+ .wo_3( w3 ));
+
+aes_sbox us00( .a( sa00 ), .d( sa00_sub ));
+aes_sbox us01( .a( sa01 ), .d( sa01_sub ));
+aes_sbox us02( .a( sa02 ), .d( sa02_sub ));
+aes_sbox us03( .a( sa03 ), .d( sa03_sub ));
+aes_sbox us10( .a( sa10 ), .d( sa10_sub ));
+aes_sbox us11( .a( sa11 ), .d( sa11_sub ));
+aes_sbox us12( .a( sa12 ), .d( sa12_sub ));
+aes_sbox us13( .a( sa13 ), .d( sa13_sub ));
+aes_sbox us20( .a( sa20 ), .d( sa20_sub ));
+aes_sbox us21( .a( sa21 ), .d( sa21_sub ));
+aes_sbox us22( .a( sa22 ), .d( sa22_sub ));
+aes_sbox us23( .a( sa23 ), .d( sa23_sub ));
+aes_sbox us30( .a( sa30 ), .d( sa30_sub ));
+aes_sbox us31( .a( sa31 ), .d( sa31_sub ));
+aes_sbox us32( .a( sa32 ), .d( sa32_sub ));
+aes_sbox us33( .a( sa33 ), .d( sa33_sub ));
+
+endmodule
+
+
Index: aes_core/trunk/rtl/verilog/aes_key_expand_128.v
===================================================================
--- aes_core/trunk/rtl/verilog/aes_key_expand_128.v (nonexistent)
+++ aes_core/trunk/rtl/verilog/aes_key_expand_128.v (revision 6)
@@ -0,0 +1,84 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Key Expand Block (for 128 bit keys) ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_key_expand_128.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:38 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
+input clk;
+input kld;
+input [127:0] key;
+output [31:0] wo_0, wo_1, wo_2, wo_3;
+reg [31:0] w[3:0];
+wire [31:0] tmp_w;
+wire [31:0] subword;
+wire [31:0] rcon;
+
+assign wo_0 = w[0];
+assign wo_1 = w[1];
+assign wo_2 = w[2];
+assign wo_3 = w[3];
+always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
+always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
+always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
+always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
+assign tmp_w = w[3];
+aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
+aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
+aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
+aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
+aes_rcon r0( .clk(clk), .kld(kld), .out(rcon));
+endmodule
+
Index: aes_core/trunk/rtl/verilog/aes_rcon.v
===================================================================
--- aes_core/trunk/rtl/verilog/aes_rcon.v (nonexistent)
+++ aes_core/trunk/rtl/verilog/aes_rcon.v (revision 6)
@@ -0,0 +1,93 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES RCON Block ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_rcon.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:38 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_rcon(clk, kld, out);
+input clk;
+input kld;
+output [31:0] out;
+reg [31:0] out;
+reg [3:0] rcnt;
+wire [3:0] rcnt_next;
+
+always @(posedge clk)
+ if(kld) out <= #1 32'h01_00_00_00;
+ else out <= #1 frcon(rcnt_next);
+
+assign rcnt_next = rcnt + 4'h1;
+always @(posedge clk)
+ if(kld) rcnt <= #1 4'h0;
+ else rcnt <= #1 rcnt_next;
+
+function [31:0] frcon;
+input [3:0] i;
+case(i) // synopsys parallel_case
+ 4'h0: frcon=32'h01_00_00_00;
+ 4'h1: frcon=32'h02_00_00_00;
+ 4'h2: frcon=32'h04_00_00_00;
+ 4'h3: frcon=32'h08_00_00_00;
+ 4'h4: frcon=32'h10_00_00_00;
+ 4'h5: frcon=32'h20_00_00_00;
+ 4'h6: frcon=32'h40_00_00_00;
+ 4'h7: frcon=32'h80_00_00_00;
+ 4'h8: frcon=32'h1b_00_00_00;
+ 4'h9: frcon=32'h36_00_00_00;
+ default: frcon=32'h00_00_00_00;
+endcase
+endfunction
+
+endmodule
Index: aes_core/trunk/sim/rtl_sim/run/waves/waves.do
===================================================================
--- aes_core/trunk/sim/rtl_sim/run/waves/waves.do (nonexistent)
+++ aes_core/trunk/sim/rtl_sim/run/waves/waves.do (revision 6)
@@ -0,0 +1,209 @@
+// Signalscan Version 6.8b1
+
+
+define noactivityindicator
+define analog waveform lines
+define add variable default overlay off
+define waveform window analogheight 1
+define terminal automatic
+define buttons control \
+ 1 opensimmulationfile \
+ 2 executedofile \
+ 3 designbrowser \
+ 4 waveform \
+ 5 source \
+ 6 breakpoints \
+ 7 definesourcessearchpath \
+ 8 exit \
+ 9 createbreakpoint \
+ 10 creategroup \
+ 11 createmarker \
+ 12 closesimmulationfile \
+ 13 renamesimmulationfile \
+ 14 replacesimulationfiledata \
+ 15 listopensimmulationfiles \
+ 16 savedofile
+define buttons waveform \
+ 1 replacesimulationfiledata \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 zoomin \
+ 7 zoomout \
+ 8 zoomoutfull \
+ 9 expand \
+ 10 createmarker \
+ 11 designbrowser:1 \
+ 12 savedofile \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons designbrowser \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 cdupscope \
+ 7 getallvariables \
+ 8 getdeepallvariables \
+ 9 addvariables \
+ 10 addvarsandclosewindow \
+ 11 closewindow \
+ 12 scopefiltermodule \
+ 13 scopefiltertask \
+ 14 scopefilterfunction \
+ 15 scopefilterblock \
+ 16 scopefilterprimitive
+define buttons event \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 move \
+ 7 closewindow \
+ 8 duplicate \
+ 9 defineasrisingedge \
+ 10 defineasfallingedge \
+ 11 defineasanyedge \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons source \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createbreakpoint \
+ 7 creategroup \
+ 8 createmarker \
+ 9 createevent \
+ 10 createregisterpage \
+ 11 closewindow \
+ 12 opensimmulationfile \
+ 13 closesimmulationfile \
+ 14 renamesimmulationfile \
+ 15 replacesimulationfiledata \
+ 16 listopensimmulationfiles
+define buttons register \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createregisterpage \
+ 7 closewindow \
+ 8 continuefor \
+ 9 continueuntil \
+ 10 continueforever \
+ 11 stop \
+ 12 previous \
+ 13 next \
+ 14 variableradixbinary \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define show related transactions
+define exit noprompt
+define event search direction forward
+define variable fullhierarchy
+define variable nofilenames
+define variable nofullpathfilenames
+include bookmark with filenames
+include scope history without filenames
+define waveform window listpane 7.95
+define waveform window namepane 33.97
+define multivalueindication
+define pattern curpos dot
+define pattern cursor1 dot
+define pattern cursor2 dot
+define pattern marker dot
+define print designer "Rudolf Usselmann"
+define print border
+define print color blackonwhite
+define print command "/usr/bin/lpr -P%P"
+define print printer lp
+define print size A4
+define print range visible
+define print variable visible
+define rise fall time low threshold percentage 10
+define rise fall time high threshold percentage 90
+define rise fall time low value 0
+define rise fall time high value 3.3
+define sendmail command "/usr/lib/sendmail"
+define sequence time width 30.00
+define snap
+
+define source noprompt
+define time units default
+define userdefinedbussymbol
+define user guide directory "/usr/local/designacc/signalscan-6.5s2/doc/html"
+define waveform window grid off
+define waveform window waveheight 14
+define waveform window wavespace 6
+define web browser command netscape
+define zoom outfull on initial add off
+add group \
+ A \
+ test.rst \
+ test.clk \
+ test.u0.ld \
+ test.u0.ld_r \
+ test.u0.key[127:0]'h \
+ test.u0.text_in[127:0]'h \
+ test.text_out[127:0]'h \
+ test.u0.done \
+ test.done2 \
+ test.text_out2[127:0]'h \
+ test.u0.w0[31:0]'h \
+ test.u0.w1[31:0]'h \
+ test.u0.w2[31:0]'h \
+ test.u0.w3[31:0]'h \
+ test.u0.sa00[7:0]'h \
+ test.u0.sa01[7:0]'h \
+ test.u0.sa02[7:0]'h \
+ test.u0.sa03[7:0]'h \
+ test.u0.sa10[7:0]'h \
+ test.u0.sa11[7:0]'h \
+ test.u0.sa12[7:0]'h \
+ test.u0.sa13[7:0]'h \
+ test.u0.sa20[7:0]'h \
+ test.u0.sa21[7:0]'h \
+ test.u0.sa22[7:0]'h \
+ test.u0.sa23[7:0]'h \
+ test.u0.sa30[7:0]'h \
+ test.u0.sa31[7:0]'h \
+ test.u0.sa32[7:0]'h \
+ test.u0.sa33[7:0]'h \
+ test.clk \
+ test.u1.ld \
+ test.u1.done \
+ test.u1.w3[31:0]'h \
+ test.u1.kdone \
+ test.u1.kld \
+ test.u1.text_in[127:0]'h \
+ test.u1.text_in_r[127:0]'h \
+ test.u1.text_out[127:0]'h \
+ test.u1.kb_ld \
+ test.u1.kcnt[3:0]'h \
+ test.u1.dcnt[3:0]'h \
+ test.u1.w0[31:0]'h \
+ test.u1.w1[31:0]'h \
+ test.u1.w2[31:0]'h \
+ test.u1.w3[31:0]'h \
+ test.u1.wk0[31:0]'h \
+ test.u1.wk1[31:0]'h \
+ test.u1.wk2[31:0]'h \
+ test.u1.wk3[31:0]'h \
+
+
+deselect all
+create marker Marker1 0ns
+open window designbrowser 1 geometry 450 269 1020 752
+open window waveform 1 geometry 58 104 1540 838
+zoom at 0(0)ns 0.00803721 0.00000000
Index: aes_core/trunk/sim/rtl_sim/bin/Makefile
===================================================================
--- aes_core/trunk/sim/rtl_sim/bin/Makefile (nonexistent)
+++ aes_core/trunk/sim/rtl_sim/bin/Makefile (revision 6)
@@ -0,0 +1,82 @@
+
+all: sim
+SHELL = /bin/sh
+MS="-s"
+
+##########################################################################
+#
+# DUT Sources
+#
+##########################################################################
+DUT_SRC_DIR=../../../rtl/verilog
+_TARGETS_= $(DUT_SRC_DIR)/aes_sbox.v \
+ $(DUT_SRC_DIR)/aes_rcon.v \
+ $(DUT_SRC_DIR)/aes_key_expand_128.v \
+ $(DUT_SRC_DIR)/aes_cipher_top.v \
+ $(DUT_SRC_DIR)/aes_inv_sbox.v \
+ $(DUT_SRC_DIR)/aes_inv_cipher_top.v
+
+
+##########################################################################
+#
+# Test Bench Sources
+#
+##########################################################################
+TB_SRC_DIR=../../../bench/verilog
+_TB_= $(TB_SRC_DIR)/test_bench_top.v
+
+##########################################################################
+#
+# Misc Variables
+#
+##########################################################################
+
+INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
+LOGF=-l .nclog
+UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
+GATE_NETLIST = ../../../syn/out/aes_cipher_top.v
+
+##########################################################################
+#
+# Make Targets
+#
+##########################################################################
+ss:
+ signalscan -do waves/waves.do -waves waves/waves.trn &
+
+simw:
+ @$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
+
+sim:
+ ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
+ $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
+ +ncuid+`hostname`
+
+ivl:
+ /usr/local/bin/iverilog -D RUDIS_TB $(_TARGETS_) $(_TB_) \
+ -I ./$(DUT_SRC_DIR)/ -I ./$(TB_SRC_DIR)/ \
+ $(WAVES) $(ACCESS) -s test
+
+gatew:
+ @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
+
+gate:
+ ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \
+ $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \
+ $(LOGF) +ncstatus +ncuid+`hostname`
+
+hal:
+ @echo ""
+ @echo "----- Running HAL ... ----------"
+ @hal +incdir+$(DUT_SRC_DIR) -NOP -NOS \
+ -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
+ $(_TARGETS_)
+ @echo "----- DONE ... ----------"
+
+clean:
+ rm -rf ./waves/*.dsn ./waves/*.trn \
+ ncwork/.inc* ncwork/inc* \
+ ./verilog.* .nclog hal.log INCA_libs
+
+##########################################################################
+
aes_core/trunk/sim/rtl_sim/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aes_core/trunk/vim_session.vim
===================================================================
--- aes_core/trunk/vim_session.vim (nonexistent)
+++ aes_core/trunk/vim_session.vim (revision 6)
@@ -0,0 +1,243 @@
+set nocompatible
+let s:cpo_save=&cpo
+set cpo&vim
+map!
+map!
+map!
+map!
+map!
+map!
+map!
+map!
+map!
+map!
+nnoremap 6_Paste "=@+.'xy'
+gPFx"_2x:echo
+map
+map
+map
+map
+map
+map
+map
+map
+map
+map
+let &cpo=s:cpo_save
+unlet s:cpo_save
+set background=dark
+set bufhidden=delete
+set buftype=nofile
+if &filetype != 'csh'
+set filetype=csh
+endif
+set guifont=-adobe-courier-medium-r-normal-*-*-120-*-*-m-*-iso8859-1
+set iminsert=0
+set imsearch=0
+set iskeyword=@,48-57,_,192-255,+,-,?
+set menuitems=50
+set mouse=a
+set noswapfile
+if &syntax != 'verilog'
+set syntax=verilog
+endif
+let s:so_save = &so | let s:siso_save = &siso | set so=0 siso=0
+let v:this_session=expand(":p")
+silent only
+cd ~/projects/aes_core
+set shortmess=aoO
+badd +1 rtl/verilog/aes_top.v
+badd +105 bench/verilog/test_bench_top.v
+badd +30 sim/rtl_sim/bin/Makefile
+badd +79 rtl/verilog/aes_key_expand_128.v
+badd +72 rtl/verilog/aes_key_expand_192.v
+badd +55 rtl/verilog/aes_key_expand_256.v
+badd +94 rtl/verilog/aes_rcon.v
+badd +80 rtl/verilog/aes_sbox.v
+badd +44 impl_results
+badd +1 rtl/verilog/aes_inv_cipher_top.v
+badd +471 rtl/verilog/aes_inv_sbox.v
+silent! argdel *
+set splitbelow splitright
+normal _|
+vsplit
+normal 1h
+normal w
+set nosplitbelow
+set nosplitright
+normal t
+set winheight=1 winwidth=1
+exe 'vert resize ' . ((&columns * 99 + 106) / 212)
+normal w
+exe 'vert resize ' . ((&columns * 112 + 106) / 212)
+normal w
+argglobal
+edit rtl/verilog/aes_sbox.v
+setlocal noautoindent
+setlocal autoread
+setlocal nobinary
+setlocal bufhidden=
+setlocal buflisted
+setlocal buftype=
+setlocal nocindent
+setlocal cinkeys=0{,0},0),:,0#,!^F,o,O,e
+setlocal cinoptions=
+setlocal cinwords=if,else,while,do,for,switch
+setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:-
+setlocal commentstring=/*%s*/
+setlocal complete=.,w,b,u,t,i
+setlocal define=
+setlocal dictionary=
+setlocal nodiff
+setlocal equalprg=
+setlocal errorformat=
+setlocal noexpandtab
+if &filetype != 'verilog'
+setlocal filetype=verilog
+endif
+setlocal foldcolumn=0
+setlocal foldenable
+setlocal foldexpr=0
+setlocal foldignore=#
+setlocal foldlevel=0
+setlocal foldmarker={{{,}}}
+setlocal foldmethod=manual
+setlocal foldminlines=1
+setlocal foldnestmax=20
+setlocal foldtext=foldtext()
+setlocal formatoptions=tcq
+setlocal grepprg=
+setlocal iminsert=0
+setlocal imsearch=0
+setlocal include=
+setlocal includeexpr=
+setlocal indentexpr=
+setlocal indentkeys=0{,0},:,0#,!^F,o,O,e
+setlocal noinfercase
+setlocal iskeyword=@,48-57,_,192-255,+,-,?
+setlocal keymap=
+setlocal nolinebreak
+setlocal nolisp
+setlocal nolist
+setlocal makeprg=
+setlocal matchpairs=(:),{:},[:]
+setlocal modeline
+setlocal modifiable
+setlocal nrformats=octal,hex
+setlocal nonumber
+setlocal path=
+setlocal nopreviewwindow
+setlocal noreadonly
+setlocal norightleft
+setlocal noscrollbind
+setlocal shiftwidth=8
+setlocal noshortname
+setlocal nosmartindent
+setlocal softtabstop=0
+setlocal suffixesadd=
+setlocal noswapfile
+if &syntax != 'verilog'
+setlocal syntax=verilog
+endif
+setlocal tabstop=8
+setlocal tags=
+setlocal textwidth=0
+setlocal thesaurus=
+setlocal wrap
+setlocal wrapmargin=0
+silent! normal zE
+let s:l = 65 - ((28 * winheight(0) + 34) / 69)
+if s:l < 1 | let s:l = 1 | endif
+exe s:l
+normal zt
+65
+normal 0
+normal w
+argglobal
+edit rtl/verilog/aes_inv_cipher_top.v
+setlocal noautoindent
+setlocal autoread
+setlocal nobinary
+setlocal bufhidden=
+setlocal buflisted
+setlocal buftype=
+setlocal nocindent
+setlocal cinkeys=0{,0},0),:,0#,!^F,o,O,e
+setlocal cinoptions=
+setlocal cinwords=if,else,while,do,for,switch
+setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:-
+setlocal commentstring=/*%s*/
+setlocal complete=.,w,b,u,t,i
+setlocal define=
+setlocal dictionary=
+setlocal nodiff
+setlocal equalprg=
+setlocal errorformat=
+setlocal noexpandtab
+if &filetype != 'verilog'
+setlocal filetype=verilog
+endif
+setlocal foldcolumn=0
+setlocal foldenable
+setlocal foldexpr=0
+setlocal foldignore=#
+setlocal foldlevel=0
+setlocal foldmarker={{{,}}}
+setlocal foldmethod=manual
+setlocal foldminlines=1
+setlocal foldnestmax=20
+setlocal foldtext=foldtext()
+setlocal formatoptions=tcq
+setlocal grepprg=
+setlocal iminsert=0
+setlocal imsearch=0
+setlocal include=
+setlocal includeexpr=
+setlocal indentexpr=
+setlocal indentkeys=0{,0},:,0#,!^F,o,O,e
+setlocal noinfercase
+setlocal iskeyword=@,48-57,_,192-255,+,-,?
+setlocal keymap=
+setlocal nolinebreak
+setlocal nolisp
+setlocal nolist
+setlocal makeprg=
+setlocal matchpairs=(:),{:},[:]
+setlocal modeline
+setlocal modifiable
+setlocal nrformats=octal,hex
+setlocal nonumber
+setlocal path=
+setlocal nopreviewwindow
+setlocal noreadonly
+setlocal norightleft
+setlocal noscrollbind
+setlocal shiftwidth=8
+setlocal noshortname
+setlocal nosmartindent
+setlocal softtabstop=0
+setlocal suffixesadd=
+setlocal noswapfile
+if &syntax != 'verilog'
+setlocal syntax=verilog
+endif
+setlocal tabstop=8
+setlocal tags=
+setlocal textwidth=0
+setlocal thesaurus=
+setlocal wrap
+setlocal wrapmargin=0
+silent! normal zE
+let s:l = 260 - ((19 * winheight(0) + 34) / 69)
+if s:l < 1 | let s:l = 1 | endif
+exe s:l
+normal zt
+260
+normal 09l
+normal w
+set winheight=1 winwidth=20 shortmess=filnxtToO
+let s:sx = expand(":p:r")."x.vim"
+if file_readable(s:sx)
+ exe "source " . s:sx
+endif
+let &so = s:so_save | let &siso = s:siso_save
Index: aes_core/trunk/syn/bin/read.dc
===================================================================
--- aes_core/trunk/syn/bin/read.dc (nonexistent)
+++ aes_core/trunk/syn/bin/read.dc (revision 6)
@@ -0,0 +1,67 @@
+###############################################################################
+#
+# Pre Synthesis Script
+#
+# This script only reads in the design and saves it in a DB file
+#
+# Author: Rudolf Usselmann
+# rudi@asics.ws
+#
+# Revision:
+# 3/7/01 RU Initial Sript
+#
+#
+###############################################################################
+
+# ==============================================
+# Setup Design Parameters
+source ../bin/design_spec.dc
+
+# ==============================================
+# Setup Libraries
+source ../bin/lib_spec.dc
+
+# ==============================================
+# Setup IO Files
+
+append log_file ../log/$active_design "_pre.log"
+append pre_comp_db_file ../out/$design_name "_pre.db"
+
+sh rm -f $log_file
+
+# ==============================================
+# Setup Misc Variables
+
+set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
+
+# ==============================================
+# Read Design
+
+echo "+++++++++ Analyzing all design files ..." >> $log_file
+
+foreach module $design_files {
+ echo "+++++++++ Reading: $module" >> $log_file
+ echo +++++++++ Reading: $module
+ set module_file_name ""
+ append module_file_name $module ".v"
+ analyze -f verilog $module_file_name >> $log_file
+ elaborate $module >> $log_file
+ }
+
+current_design $active_design
+
+echo "+++++++++ Linking Design ..." >> $log_file
+link >> $log_file
+
+echo "+++++++++ Uniquifying Design ..." >> $log_file
+uniquify >> $log_file
+
+echo "+++++++++ Checking Design ..." >> $log_file
+check_design >> $log_file
+
+# ==============================================
+# Save Design
+echo "+++++++++ Saving Design ..." >> $log_file
+write_file -hierarchy -format db -output $pre_comp_db_file
+
+quit
Index: aes_core/trunk/syn/bin/comp.dc
===================================================================
--- aes_core/trunk/syn/bin/comp.dc (nonexistent)
+++ aes_core/trunk/syn/bin/comp.dc (revision 6)
@@ -0,0 +1,142 @@
+###############################################################################
+#
+# Actual Synthesis Script
+#
+# This script does the actual synthesis
+#
+# Author: Rudolf Usselmann
+# rudi@asics.ws
+#
+# Revision:
+# 3/7/01 RU Initial Sript
+#
+#
+###############################################################################
+
+# ==============================================
+# Setup Design Parameters
+source ../bin/design_spec.dc
+
+# ==============================================
+# Setup Libraries
+source ../bin/lib_spec.dc
+
+# ==============================================
+# Setup IO Files
+
+append log_file ../log/$active_design "_cmp.log"
+append pre_comp_db_file ../out/$design_name "_pre.db"
+append post_comp_db_file ../out/$design_name ".db"
+append post_syn_verilog_file ../out/$design_name "_ps.v"
+set junk_file /dev/null
+
+sh rm -f $log_file
+
+# ==============================================
+# Setup Misc Variables
+
+set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
+
+# ==============================================
+# Read Design
+
+echo "+++++++++ Reading Design ..." >> $log_file
+read_file $pre_comp_db_file >> $log_file
+
+# ==============================================
+# Operating conditions
+
+echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
+current_design $design_name
+set_operating_conditions WORST >> $log_file
+
+# ==============================================
+# Setup Clocks and Resets
+
+echo "+++++++++ Setting up Clocks ..." >> $log_file
+
+set_drive 0 [find port {clk}]
+
+# !!! Clock !!!
+set clock_period 2.5
+create_clock -period $clock_period clk
+set_clock_skew -uncertainty 0.1 clk
+set_clock_transition 0.2 clk
+set_dont_touch_network clk
+
+# ==============================================
+# Setup IOs
+
+echo "+++++++++ Setting up IOs ..." >> $log_file
+
+# Need to spell out external IOs
+
+set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
+set_load 0.2 [all_outputs]
+
+set_input_delay -max 1 -clock clk [all_inputs]
+set_output_delay -max 1 -clock clk [all_outputs]
+
+# ==============================================
+# Setup Area Constrains
+set_max_area 0.0
+
+# ==============================================
+# Force Ultra
+set_ultra_optimization -f
+set compile_new_optimization true
+
+# ==============================================
+# Compile Design
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Timing Loops Report +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+report_timing -loops -max_path 20 >> $log_file
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Starting Compile +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+
+set_wire_load_model -name suggested_160K [find design *]
+set_balance_registers true
+compile -boundary_optimization -ungroup_all
+optimize_registers -period 0
+compile -incremental_mapping -map_effort high -area_effort high -boundary_optimization -ungroup_all
+
+# ==============================================
+# Write Out the optimized design
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Saving Optimized Design +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+write_file -hierarchy -format verilog -output $post_syn_verilog_file
+write_file -hierarchy -format db -output $post_comp_db_file
+
+# ==============================================
+# Create Some Basic Reports
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Reporting Final Results +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+report_timing -path full_clock -nworst 10 -nets \
+ -transition_time -capacitance -attributes \
+ -sort_by slack >> $log_file
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Area Report +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+
+report_area >> $log_file
+quit
+
Index: aes_core/trunk/syn/bin/lib_spec.dc
===================================================================
--- aes_core/trunk/syn/bin/lib_spec.dc (nonexistent)
+++ aes_core/trunk/syn/bin/lib_spec.dc (revision 6)
@@ -0,0 +1,43 @@
+###############################################################################
+#
+# Library Specification
+#
+# Author: Rudolf Usselmann
+# rudi@asics.ws
+#
+# Revision:
+# 3/7/01 RU Initial Sript
+#
+#
+###############################################################################
+
+# ==============================================
+# Setup Libraries
+
+#tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
+#tools/dc_libraries/virtual_silicon/UMCL13L210D3_1.0/design_compiler/ \
+
+
+set search_path [list $search_path . \
+ /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
+ $hdl_src_dir]
+
+set snps [getenv "SYNOPSYS"]
+
+set synthetic_library ""
+append synthetic_library $snps "/libraries/syn/dw01.sldb "
+append synthetic_library $snps "/libraries/syn/dw02.sldb "
+append synthetic_library $snps "/libraries/syn/dw03.sldb "
+append synthetic_library $snps "/libraries/syn/dw04.sldb "
+append synthetic_library $snps "/libraries/syn/dw05.sldb "
+append synthetic_library $snps "/libraries/syn/dw06.sldb "
+append synthetic_library $snps "/libraries/syn/dw07.sldb "
+
+set target_library { umcl18u250t2_wc.db }
+#set target_library { umcl13l210t3_wc.db }
+
+set link_library ""
+append link_library $target_library " " $synthetic_library
+
+#set symbol_library { umcl13l210t3.sdb }
+
Index: aes_core/trunk/syn/bin/design_spec.dc
===================================================================
--- aes_core/trunk/syn/bin/design_spec.dc (nonexistent)
+++ aes_core/trunk/syn/bin/design_spec.dc (revision 6)
@@ -0,0 +1,29 @@
+###############################################################################
+#
+# Design Specification
+#
+# Author: Rudolf Usselmann
+# rudi@asics.ws
+#
+# Revision:
+# 3/7/01 RU Initial Sript
+#
+#
+###############################################################################
+
+# ==============================================
+# Setup Design Parameters
+
+set design_files {aes_rcon aes_sbox aes_key_expand_128 aes_cipher_top}
+set design_name aes_cipher_top
+set active_design aes_cipher_top
+
+#set design_files {aes_rcon aes_inv_sbox aes_key_expand_128 aes_inv_cipher_top}
+#set design_name aes_inv_cipher_top
+#set active_design aes_inv_cipher_top
+
+# Next Statement defines all clocks and resets in the design
+set special_net {clk}
+
+set hdl_src_dir ../../rtl/verilog/
+
Index: aes_core/trunk
===================================================================
--- aes_core/trunk (nonexistent)
+++ aes_core/trunk (revision 6)
aes_core/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: aes_core/web_uploads
===================================================================
--- aes_core/web_uploads (nonexistent)
+++ aes_core/web_uploads (revision 6)
aes_core/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: aes_core/branches
===================================================================
--- aes_core/branches (nonexistent)
+++ aes_core/branches (revision 6)
aes_core/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: aes_core/tags/start/bench/verilog/test_bench_top.v
===================================================================
--- aes_core/tags/start/bench/verilog/test_bench_top.v (nonexistent)
+++ aes_core/tags/start/bench/verilog/test_bench_top.v (revision 6)
@@ -0,0 +1,173 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Test Bench ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: test_bench_top.v,v 1.1.1.1 2002-11-09 11:22:56 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:56 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module test;
+
+reg clk;
+reg rst;
+
+reg kld;
+reg [127:0] key;
+reg [127:0] text_in;
+wire [127:0] text_out;
+wire [127:0] text_out2;
+reg [127:0] text_exp;
+wire done, done2;
+integer n, error_cnt;
+
+initial
+ begin
+ $display("\n\n");
+ $display("*****************************************************");
+ $display("* AES Test bench ...");
+ $display("*****************************************************");
+ $display("\n");
+`ifdef WAVES
+ $shm_open("waves");
+ $shm_probe("AS",test,"AS");
+ $display("INFO: Signal dump enabled ...\n\n");
+`endif
+
+ kld = 0;
+ clk = 0;
+ rst = 0;
+ key = 128'hx;
+ text_in = 128'hx;
+ error_cnt = 0;
+ repeat(4) @(posedge clk);
+ rst = 1;
+ repeat(20) @(posedge clk);
+
+ $display("");
+ $display("");
+ $display("Started random test ...");
+
+for(n=0;n<100;n=n+1)
+ begin
+ @(posedge clk);
+ #1;
+ kld = 1;
+ case(n)
+ 0: begin
+ key = 128'h000102030405060708090a0b0c0d0e0f;
+ text_in=128'h00112233445566778899aabbccddeeff;
+ end
+ default:
+ begin
+ key = {$random, $random, $random, $random};
+ text_in= {$random, $random, $random, $random};
+ end
+ endcase
+
+ @(posedge clk);
+ #1;
+ kld = 0;
+ key = 128'hx;
+ text_exp = text_in;
+ text_in = 128'hx;
+ @(posedge clk);
+
+ while(!done2) @(posedge clk);
+
+ //$display("INFO: Vector %0d: xpected %x, Got %x", n, text_exp, text_out2);
+
+ if(text_out2 != text_exp)
+ begin
+ $display("ERROR: Vector %0d mismatch. Expected %x, Got %x",
+ n, text_exp, text_out2);
+ error_cnt = error_cnt + 1;
+ end
+
+ @(posedge clk);
+ end
+
+ $display("");
+ $display("");
+ $display("Test Done. Found %0d Errors.", error_cnt);
+ $display("");
+ $display("");
+ repeat(100) @(posedge clk);
+ $finish;
+end
+
+always #5 clk = ~clk;
+
+aes_cipher_top u0(
+ .clk( clk ),
+ .rst( rst ),
+ .ld( kld ),
+ .done( done ),
+ .key( key ),
+ .text_in( text_in ),
+ .text_out( text_out )
+ );
+
+aes_inv_cipher_top u1(
+ .clk( clk ),
+ .rst( rst ),
+ .kld( kld ),
+ .ld( done ),
+ .done( done2 ),
+ .key( key ),
+ .text_in( text_out ),
+ .text_out( text_out2 )
+ );
+
+endmodule
+
+
Index: aes_core/tags/start/rtl/verilog/aes_inv_sbox.v
===================================================================
--- aes_core/tags/start/rtl/verilog/aes_inv_sbox.v (nonexistent)
+++ aes_core/tags/start/rtl/verilog/aes_inv_sbox.v (revision 6)
@@ -0,0 +1,325 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Inverse SBOX (ROM) ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_inv_sbox.v,v 1.1.1.1 2002-11-09 11:22:55 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:55 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_inv_sbox(a,d);
+input [7:0] a;
+output [7:0] d;
+reg [7:0] d;
+
+always @(a)
+ case(a) // synopsys full_case parallel_case
+ 8'h00: d=8'h52;
+ 8'h01: d=8'h09;
+ 8'h02: d=8'h6a;
+ 8'h03: d=8'hd5;
+ 8'h04: d=8'h30;
+ 8'h05: d=8'h36;
+ 8'h06: d=8'ha5;
+ 8'h07: d=8'h38;
+ 8'h08: d=8'hbf;
+ 8'h09: d=8'h40;
+ 8'h0a: d=8'ha3;
+ 8'h0b: d=8'h9e;
+ 8'h0c: d=8'h81;
+ 8'h0d: d=8'hf3;
+ 8'h0e: d=8'hd7;
+ 8'h0f: d=8'hfb;
+ 8'h10: d=8'h7c;
+ 8'h11: d=8'he3;
+ 8'h12: d=8'h39;
+ 8'h13: d=8'h82;
+ 8'h14: d=8'h9b;
+ 8'h15: d=8'h2f;
+ 8'h16: d=8'hff;
+ 8'h17: d=8'h87;
+ 8'h18: d=8'h34;
+ 8'h19: d=8'h8e;
+ 8'h1a: d=8'h43;
+ 8'h1b: d=8'h44;
+ 8'h1c: d=8'hc4;
+ 8'h1d: d=8'hde;
+ 8'h1e: d=8'he9;
+ 8'h1f: d=8'hcb;
+ 8'h20: d=8'h54;
+ 8'h21: d=8'h7b;
+ 8'h22: d=8'h94;
+ 8'h23: d=8'h32;
+ 8'h24: d=8'ha6;
+ 8'h25: d=8'hc2;
+ 8'h26: d=8'h23;
+ 8'h27: d=8'h3d;
+ 8'h28: d=8'hee;
+ 8'h29: d=8'h4c;
+ 8'h2a: d=8'h95;
+ 8'h2b: d=8'h0b;
+ 8'h2c: d=8'h42;
+ 8'h2d: d=8'hfa;
+ 8'h2e: d=8'hc3;
+ 8'h2f: d=8'h4e;
+ 8'h30: d=8'h08;
+ 8'h31: d=8'h2e;
+ 8'h32: d=8'ha1;
+ 8'h33: d=8'h66;
+ 8'h34: d=8'h28;
+ 8'h35: d=8'hd9;
+ 8'h36: d=8'h24;
+ 8'h37: d=8'hb2;
+ 8'h38: d=8'h76;
+ 8'h39: d=8'h5b;
+ 8'h3a: d=8'ha2;
+ 8'h3b: d=8'h49;
+ 8'h3c: d=8'h6d;
+ 8'h3d: d=8'h8b;
+ 8'h3e: d=8'hd1;
+ 8'h3f: d=8'h25;
+ 8'h40: d=8'h72;
+ 8'h41: d=8'hf8;
+ 8'h42: d=8'hf6;
+ 8'h43: d=8'h64;
+ 8'h44: d=8'h86;
+ 8'h45: d=8'h68;
+ 8'h46: d=8'h98;
+ 8'h47: d=8'h16;
+ 8'h48: d=8'hd4;
+ 8'h49: d=8'ha4;
+ 8'h4a: d=8'h5c;
+ 8'h4b: d=8'hcc;
+ 8'h4c: d=8'h5d;
+ 8'h4d: d=8'h65;
+ 8'h4e: d=8'hb6;
+ 8'h4f: d=8'h92;
+ 8'h50: d=8'h6c;
+ 8'h51: d=8'h70;
+ 8'h52: d=8'h48;
+ 8'h53: d=8'h50;
+ 8'h54: d=8'hfd;
+ 8'h55: d=8'hed;
+ 8'h56: d=8'hb9;
+ 8'h57: d=8'hda;
+ 8'h58: d=8'h5e;
+ 8'h59: d=8'h15;
+ 8'h5a: d=8'h46;
+ 8'h5b: d=8'h57;
+ 8'h5c: d=8'ha7;
+ 8'h5d: d=8'h8d;
+ 8'h5e: d=8'h9d;
+ 8'h5f: d=8'h84;
+ 8'h60: d=8'h90;
+ 8'h61: d=8'hd8;
+ 8'h62: d=8'hab;
+ 8'h63: d=8'h00;
+ 8'h64: d=8'h8c;
+ 8'h65: d=8'hbc;
+ 8'h66: d=8'hd3;
+ 8'h67: d=8'h0a;
+ 8'h68: d=8'hf7;
+ 8'h69: d=8'he4;
+ 8'h6a: d=8'h58;
+ 8'h6b: d=8'h05;
+ 8'h6c: d=8'hb8;
+ 8'h6d: d=8'hb3;
+ 8'h6e: d=8'h45;
+ 8'h6f: d=8'h06;
+ 8'h70: d=8'hd0;
+ 8'h71: d=8'h2c;
+ 8'h72: d=8'h1e;
+ 8'h73: d=8'h8f;
+ 8'h74: d=8'hca;
+ 8'h75: d=8'h3f;
+ 8'h76: d=8'h0f;
+ 8'h77: d=8'h02;
+ 8'h78: d=8'hc1;
+ 8'h79: d=8'haf;
+ 8'h7a: d=8'hbd;
+ 8'h7b: d=8'h03;
+ 8'h7c: d=8'h01;
+ 8'h7d: d=8'h13;
+ 8'h7e: d=8'h8a;
+ 8'h7f: d=8'h6b;
+ 8'h80: d=8'h3a;
+ 8'h81: d=8'h91;
+ 8'h82: d=8'h11;
+ 8'h83: d=8'h41;
+ 8'h84: d=8'h4f;
+ 8'h85: d=8'h67;
+ 8'h86: d=8'hdc;
+ 8'h87: d=8'hea;
+ 8'h88: d=8'h97;
+ 8'h89: d=8'hf2;
+ 8'h8a: d=8'hcf;
+ 8'h8b: d=8'hce;
+ 8'h8c: d=8'hf0;
+ 8'h8d: d=8'hb4;
+ 8'h8e: d=8'he6;
+ 8'h8f: d=8'h73;
+ 8'h90: d=8'h96;
+ 8'h91: d=8'hac;
+ 8'h92: d=8'h74;
+ 8'h93: d=8'h22;
+ 8'h94: d=8'he7;
+ 8'h95: d=8'had;
+ 8'h96: d=8'h35;
+ 8'h97: d=8'h85;
+ 8'h98: d=8'he2;
+ 8'h99: d=8'hf9;
+ 8'h9a: d=8'h37;
+ 8'h9b: d=8'he8;
+ 8'h9c: d=8'h1c;
+ 8'h9d: d=8'h75;
+ 8'h9e: d=8'hdf;
+ 8'h9f: d=8'h6e;
+ 8'ha0: d=8'h47;
+ 8'ha1: d=8'hf1;
+ 8'ha2: d=8'h1a;
+ 8'ha3: d=8'h71;
+ 8'ha4: d=8'h1d;
+ 8'ha5: d=8'h29;
+ 8'ha6: d=8'hc5;
+ 8'ha7: d=8'h89;
+ 8'ha8: d=8'h6f;
+ 8'ha9: d=8'hb7;
+ 8'haa: d=8'h62;
+ 8'hab: d=8'h0e;
+ 8'hac: d=8'haa;
+ 8'had: d=8'h18;
+ 8'hae: d=8'hbe;
+ 8'haf: d=8'h1b;
+ 8'hb0: d=8'hfc;
+ 8'hb1: d=8'h56;
+ 8'hb2: d=8'h3e;
+ 8'hb3: d=8'h4b;
+ 8'hb4: d=8'hc6;
+ 8'hb5: d=8'hd2;
+ 8'hb6: d=8'h79;
+ 8'hb7: d=8'h20;
+ 8'hb8: d=8'h9a;
+ 8'hb9: d=8'hdb;
+ 8'hba: d=8'hc0;
+ 8'hbb: d=8'hfe;
+ 8'hbc: d=8'h78;
+ 8'hbd: d=8'hcd;
+ 8'hbe: d=8'h5a;
+ 8'hbf: d=8'hf4;
+ 8'hc0: d=8'h1f;
+ 8'hc1: d=8'hdd;
+ 8'hc2: d=8'ha8;
+ 8'hc3: d=8'h33;
+ 8'hc4: d=8'h88;
+ 8'hc5: d=8'h07;
+ 8'hc6: d=8'hc7;
+ 8'hc7: d=8'h31;
+ 8'hc8: d=8'hb1;
+ 8'hc9: d=8'h12;
+ 8'hca: d=8'h10;
+ 8'hcb: d=8'h59;
+ 8'hcc: d=8'h27;
+ 8'hcd: d=8'h80;
+ 8'hce: d=8'hec;
+ 8'hcf: d=8'h5f;
+ 8'hd0: d=8'h60;
+ 8'hd1: d=8'h51;
+ 8'hd2: d=8'h7f;
+ 8'hd3: d=8'ha9;
+ 8'hd4: d=8'h19;
+ 8'hd5: d=8'hb5;
+ 8'hd6: d=8'h4a;
+ 8'hd7: d=8'h0d;
+ 8'hd8: d=8'h2d;
+ 8'hd9: d=8'he5;
+ 8'hda: d=8'h7a;
+ 8'hdb: d=8'h9f;
+ 8'hdc: d=8'h93;
+ 8'hdd: d=8'hc9;
+ 8'hde: d=8'h9c;
+ 8'hdf: d=8'hef;
+ 8'he0: d=8'ha0;
+ 8'he1: d=8'he0;
+ 8'he2: d=8'h3b;
+ 8'he3: d=8'h4d;
+ 8'he4: d=8'hae;
+ 8'he5: d=8'h2a;
+ 8'he6: d=8'hf5;
+ 8'he7: d=8'hb0;
+ 8'he8: d=8'hc8;
+ 8'he9: d=8'heb;
+ 8'hea: d=8'hbb;
+ 8'heb: d=8'h3c;
+ 8'hec: d=8'h83;
+ 8'hed: d=8'h53;
+ 8'hee: d=8'h99;
+ 8'hef: d=8'h61;
+ 8'hf0: d=8'h17;
+ 8'hf1: d=8'h2b;
+ 8'hf2: d=8'h04;
+ 8'hf3: d=8'h7e;
+ 8'hf4: d=8'hba;
+ 8'hf5: d=8'h77;
+ 8'hf6: d=8'hd6;
+ 8'hf7: d=8'h26;
+ 8'hf8: d=8'he1;
+ 8'hf9: d=8'h69;
+ 8'hfa: d=8'h14;
+ 8'hfb: d=8'h63;
+ 8'hfc: d=8'h55;
+ 8'hfd: d=8'h21;
+ 8'hfe: d=8'h0c;
+ 8'hff: d=8'h7d;
+ endcase
+endmodule
+
+
Index: aes_core/tags/start/rtl/verilog/aes_inv_cipher_top.v
===================================================================
--- aes_core/tags/start/rtl/verilog/aes_inv_cipher_top.v (nonexistent)
+++ aes_core/tags/start/rtl/verilog/aes_inv_cipher_top.v (revision 6)
@@ -0,0 +1,324 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Inverse Cipher Top Level ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_inv_cipher_top.v,v 1.1.1.1 2002-11-09 11:22:53 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:53 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_inv_cipher_top(clk, rst, kld, ld, done, key, text_in, text_out );
+input clk, rst;
+input kld, ld;
+output done;
+input [127:0] key;
+input [127:0] text_in;
+output [127:0] text_out;
+
+////////////////////////////////////////////////////////////////////
+//
+// Local Wires
+//
+
+wire [31:0] wk0, wk1, wk2, wk3;
+reg [31:0] w0, w1, w2, w3;
+reg [127:0] text_in_r;
+reg [127:0] text_out;
+reg [7:0] sa00, sa01, sa02, sa03;
+reg [7:0] sa10, sa11, sa12, sa13;
+reg [7:0] sa20, sa21, sa22, sa23;
+reg [7:0] sa30, sa31, sa32, sa33;
+wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
+wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
+wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
+wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
+wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
+wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
+wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
+wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
+wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
+wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
+wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
+wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
+wire [7:0] sa00_ark, sa01_ark, sa02_ark, sa03_ark;
+wire [7:0] sa10_ark, sa11_ark, sa12_ark, sa13_ark;
+wire [7:0] sa20_ark, sa21_ark, sa22_ark, sa23_ark;
+wire [7:0] sa30_ark, sa31_ark, sa32_ark, sa33_ark;
+reg ld_r, go, done;
+reg [3:0] dcnt;
+
+////////////////////////////////////////////////////////////////////
+//
+// Misc Logic
+//
+
+always @(posedge clk)
+ if(!rst) dcnt <= #1 4'h0;
+ else
+ if(done) dcnt <= #1 4'h0;
+ else
+ if(ld) dcnt <= #1 4'h1;
+ else
+ if(go) dcnt <= #1 dcnt + 4'h1;
+
+always @(posedge clk) done <= #1 (dcnt==4'hb) & !ld;
+
+always @(posedge clk)
+ if(!rst) go <= #1 1'b0;
+ else
+ if(ld) go <= #1 1'b1;
+ else
+ if(done) go <= #1 1'b0;
+
+always @(posedge clk) if(ld) text_in_r <= #1 text_in;
+
+always @(posedge clk) ld_r <= #1 ld;
+
+////////////////////////////////////////////////////////////////////
+//
+// Initial Permutation
+//
+
+always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
+always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
+always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
+always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
+always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
+always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
+always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
+always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
+always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
+always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
+always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
+always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
+always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
+always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
+always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
+always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
+
+////////////////////////////////////////////////////////////////////
+//
+// Round Permutations
+//
+
+assign sa00_sr = sa00;
+assign sa01_sr = sa01;
+assign sa02_sr = sa02;
+assign sa03_sr = sa03;
+assign sa10_sr = sa13;
+assign sa11_sr = sa10;
+assign sa12_sr = sa11;
+assign sa13_sr = sa12;
+assign sa20_sr = sa22;
+assign sa21_sr = sa23;
+assign sa22_sr = sa20;
+assign sa23_sr = sa21;
+assign sa30_sr = sa31;
+assign sa31_sr = sa32;
+assign sa32_sr = sa33;
+assign sa33_sr = sa30;
+assign sa00_ark = sa00_sub ^ w0[31:24];
+assign sa01_ark = sa01_sub ^ w1[31:24];
+assign sa02_ark = sa02_sub ^ w2[31:24];
+assign sa03_ark = sa03_sub ^ w3[31:24];
+assign sa10_ark = sa10_sub ^ w0[23:16];
+assign sa11_ark = sa11_sub ^ w1[23:16];
+assign sa12_ark = sa12_sub ^ w2[23:16];
+assign sa13_ark = sa13_sub ^ w3[23:16];
+assign sa20_ark = sa20_sub ^ w0[15:08];
+assign sa21_ark = sa21_sub ^ w1[15:08];
+assign sa22_ark = sa22_sub ^ w2[15:08];
+assign sa23_ark = sa23_sub ^ w3[15:08];
+assign sa30_ark = sa30_sub ^ w0[07:00];
+assign sa31_ark = sa31_sub ^ w1[07:00];
+assign sa32_ark = sa32_sub ^ w2[07:00];
+assign sa33_ark = sa33_sub ^ w3[07:00];
+assign {sa00_next, sa10_next, sa20_next, sa30_next} = inv_mix_col(sa00_ark,sa10_ark,sa20_ark,sa30_ark);
+assign {sa01_next, sa11_next, sa21_next, sa31_next} = inv_mix_col(sa01_ark,sa11_ark,sa21_ark,sa31_ark);
+assign {sa02_next, sa12_next, sa22_next, sa32_next} = inv_mix_col(sa02_ark,sa12_ark,sa22_ark,sa32_ark);
+assign {sa03_next, sa13_next, sa23_next, sa33_next} = inv_mix_col(sa03_ark,sa13_ark,sa23_ark,sa33_ark);
+
+////////////////////////////////////////////////////////////////////
+//
+// Final Text Output
+//
+
+always @(posedge clk) text_out[127:120] <= #1 sa00_ark;
+always @(posedge clk) text_out[095:088] <= #1 sa01_ark;
+always @(posedge clk) text_out[063:056] <= #1 sa02_ark;
+always @(posedge clk) text_out[031:024] <= #1 sa03_ark;
+always @(posedge clk) text_out[119:112] <= #1 sa10_ark;
+always @(posedge clk) text_out[087:080] <= #1 sa11_ark;
+always @(posedge clk) text_out[055:048] <= #1 sa12_ark;
+always @(posedge clk) text_out[023:016] <= #1 sa13_ark;
+always @(posedge clk) text_out[111:104] <= #1 sa20_ark;
+always @(posedge clk) text_out[079:072] <= #1 sa21_ark;
+always @(posedge clk) text_out[047:040] <= #1 sa22_ark;
+always @(posedge clk) text_out[015:008] <= #1 sa23_ark;
+always @(posedge clk) text_out[103:096] <= #1 sa30_ark;
+always @(posedge clk) text_out[071:064] <= #1 sa31_ark;
+always @(posedge clk) text_out[039:032] <= #1 sa32_ark;
+always @(posedge clk) text_out[007:000] <= #1 sa33_ark;
+
+////////////////////////////////////////////////////////////////////
+//
+// Generic Functions
+//
+
+function [31:0] inv_mix_col;
+input [7:0] s0,s1,s2,s3;
+begin
+inv_mix_col[31:24]=pmul_e(s0)^pmul_b(s1)^pmul_d(s2)^pmul_9(s3);
+inv_mix_col[23:16]=pmul_9(s0)^pmul_e(s1)^pmul_b(s2)^pmul_d(s3);
+inv_mix_col[15:08]=pmul_d(s0)^pmul_9(s1)^pmul_e(s2)^pmul_b(s3);
+inv_mix_col[07:00]=pmul_b(s0)^pmul_d(s1)^pmul_9(s2)^pmul_e(s3);
+end
+endfunction
+
+// Some synthesis tools don't like xtime being called recursevly ...
+function [7:0] pmul_e;
+input [7:0] b;
+reg [7:0] two,four,eight;
+begin
+two=xtime(b);four=xtime(two);eight=xtime(four);pmul_e=eight^four^two;
+end
+endfunction
+
+function [7:0] pmul_9;
+input [7:0] b;
+reg [7:0] two,four,eight;
+begin
+two=xtime(b);four=xtime(two);eight=xtime(four);pmul_9=eight^b;
+end
+endfunction
+
+function [7:0] pmul_d;
+input [7:0] b;
+reg [7:0] two,four,eight;
+begin
+two=xtime(b);four=xtime(two);eight=xtime(four);pmul_d=eight^four^b;
+end
+endfunction
+
+function [7:0] pmul_b;
+input [7:0] b;
+reg [7:0] two,four,eight;
+begin
+two=xtime(b);four=xtime(two);eight=xtime(four);pmul_b=eight^two^b;
+end
+endfunction
+
+function [7:0] xtime;
+input [7:0] b;xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
+endfunction
+
+////////////////////////////////////////////////////////////////////
+//
+// Key Buffer
+//
+
+reg [127:0] kb[10:0];
+reg [3:0] kcnt;
+reg kdone;
+reg kb_ld;
+
+always @(posedge clk)
+ if(!rst) kcnt <= #1 4'ha;
+ else
+ if(kld) kcnt <= #1 4'ha;
+ else
+ if(kb_ld) kcnt <= #1 kcnt - 4'h1;
+
+always @(posedge clk)
+ if(!rst) kb_ld <= #1 1'b0;
+ else
+ if(kld) kb_ld <= #1 1'b1;
+ else
+ if(kcnt==4'h0) kb_ld <= #1 1'b0;
+
+always @(posedge clk) kdone <= #1 (kcnt==4'h0) & !kld;
+always @(posedge clk) if(kb_ld) kb[kcnt] <= #1 {wk3, wk2, wk1, wk0};
+always @(posedge clk) {w3, w2, w1, w0} <= #1 kb[dcnt];
+
+////////////////////////////////////////////////////////////////////
+//
+// Modules
+//
+
+aes_key_expand_128 u0(
+ .clk( clk ),
+ .kld( kld ),
+ .key( key ),
+ .wo_0( wk0 ),
+ .wo_1( wk1 ),
+ .wo_2( wk2 ),
+ .wo_3( wk3 ));
+
+aes_inv_sbox us00( .a( sa00_sr ), .d( sa00_sub ));
+aes_inv_sbox us01( .a( sa01_sr ), .d( sa01_sub ));
+aes_inv_sbox us02( .a( sa02_sr ), .d( sa02_sub ));
+aes_inv_sbox us03( .a( sa03_sr ), .d( sa03_sub ));
+aes_inv_sbox us10( .a( sa10_sr ), .d( sa10_sub ));
+aes_inv_sbox us11( .a( sa11_sr ), .d( sa11_sub ));
+aes_inv_sbox us12( .a( sa12_sr ), .d( sa12_sub ));
+aes_inv_sbox us13( .a( sa13_sr ), .d( sa13_sub ));
+aes_inv_sbox us20( .a( sa20_sr ), .d( sa20_sub ));
+aes_inv_sbox us21( .a( sa21_sr ), .d( sa21_sub ));
+aes_inv_sbox us22( .a( sa22_sr ), .d( sa22_sub ));
+aes_inv_sbox us23( .a( sa23_sr ), .d( sa23_sub ));
+aes_inv_sbox us30( .a( sa30_sr ), .d( sa30_sub ));
+aes_inv_sbox us31( .a( sa31_sr ), .d( sa31_sub ));
+aes_inv_sbox us32( .a( sa32_sr ), .d( sa32_sub ));
+aes_inv_sbox us33( .a( sa33_sr ), .d( sa33_sub ));
+
+endmodule
+
Index: aes_core/tags/start/rtl/verilog/aes_sbox.v
===================================================================
--- aes_core/tags/start/rtl/verilog/aes_sbox.v (nonexistent)
+++ aes_core/tags/start/rtl/verilog/aes_sbox.v (revision 6)
@@ -0,0 +1,326 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES SBOX (ROM) ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_sbox.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:38 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_sbox(a,d);
+input [7:0] a;
+output [7:0] d;
+reg [7:0] d;
+
+always @(a)
+ case(a) // synopsys full_case parallel_case
+ 8'h00: d=8'h63;
+ 8'h01: d=8'h7c;
+ 8'h02: d=8'h77;
+ 8'h03: d=8'h7b;
+ 8'h04: d=8'hf2;
+ 8'h05: d=8'h6b;
+ 8'h06: d=8'h6f;
+ 8'h07: d=8'hc5;
+ 8'h08: d=8'h30;
+ 8'h09: d=8'h01;
+ 8'h0a: d=8'h67;
+ 8'h0b: d=8'h2b;
+ 8'h0c: d=8'hfe;
+ 8'h0d: d=8'hd7;
+ 8'h0e: d=8'hab;
+ 8'h0f: d=8'h76;
+ 8'h10: d=8'hca;
+ 8'h11: d=8'h82;
+ 8'h12: d=8'hc9;
+ 8'h13: d=8'h7d;
+ 8'h14: d=8'hfa;
+ 8'h15: d=8'h59;
+ 8'h16: d=8'h47;
+ 8'h17: d=8'hf0;
+ 8'h18: d=8'had;
+ 8'h19: d=8'hd4;
+ 8'h1a: d=8'ha2;
+ 8'h1b: d=8'haf;
+ 8'h1c: d=8'h9c;
+ 8'h1d: d=8'ha4;
+ 8'h1e: d=8'h72;
+ 8'h1f: d=8'hc0;
+ 8'h20: d=8'hb7;
+ 8'h21: d=8'hfd;
+ 8'h22: d=8'h93;
+ 8'h23: d=8'h26;
+ 8'h24: d=8'h36;
+ 8'h25: d=8'h3f;
+ 8'h26: d=8'hf7;
+ 8'h27: d=8'hcc;
+ 8'h28: d=8'h34;
+ 8'h29: d=8'ha5;
+ 8'h2a: d=8'he5;
+ 8'h2b: d=8'hf1;
+ 8'h2c: d=8'h71;
+ 8'h2d: d=8'hd8;
+ 8'h2e: d=8'h31;
+ 8'h2f: d=8'h15;
+ 8'h30: d=8'h04;
+ 8'h31: d=8'hc7;
+ 8'h32: d=8'h23;
+ 8'h33: d=8'hc3;
+ 8'h34: d=8'h18;
+ 8'h35: d=8'h96;
+ 8'h36: d=8'h05;
+ 8'h37: d=8'h9a;
+ 8'h38: d=8'h07;
+ 8'h39: d=8'h12;
+ 8'h3a: d=8'h80;
+ 8'h3b: d=8'he2;
+ 8'h3c: d=8'heb;
+ 8'h3d: d=8'h27;
+ 8'h3e: d=8'hb2;
+ 8'h3f: d=8'h75;
+ 8'h40: d=8'h09;
+ 8'h41: d=8'h83;
+ 8'h42: d=8'h2c;
+ 8'h43: d=8'h1a;
+ 8'h44: d=8'h1b;
+ 8'h45: d=8'h6e;
+ 8'h46: d=8'h5a;
+ 8'h47: d=8'ha0;
+ 8'h48: d=8'h52;
+ 8'h49: d=8'h3b;
+ 8'h4a: d=8'hd6;
+ 8'h4b: d=8'hb3;
+ 8'h4c: d=8'h29;
+ 8'h4d: d=8'he3;
+ 8'h4e: d=8'h2f;
+ 8'h4f: d=8'h84;
+ 8'h50: d=8'h53;
+ 8'h51: d=8'hd1;
+ 8'h52: d=8'h00;
+ 8'h53: d=8'hed;
+ 8'h54: d=8'h20;
+ 8'h55: d=8'hfc;
+ 8'h56: d=8'hb1;
+ 8'h57: d=8'h5b;
+ 8'h58: d=8'h6a;
+ 8'h59: d=8'hcb;
+ 8'h5a: d=8'hbe;
+ 8'h5b: d=8'h39;
+ 8'h5c: d=8'h4a;
+ 8'h5d: d=8'h4c;
+ 8'h5e: d=8'h58;
+ 8'h5f: d=8'hcf;
+ 8'h60: d=8'hd0;
+ 8'h61: d=8'hef;
+ 8'h62: d=8'haa;
+ 8'h63: d=8'hfb;
+ 8'h64: d=8'h43;
+ 8'h65: d=8'h4d;
+ 8'h66: d=8'h33;
+ 8'h67: d=8'h85;
+ 8'h68: d=8'h45;
+ 8'h69: d=8'hf9;
+ 8'h6a: d=8'h02;
+ 8'h6b: d=8'h7f;
+ 8'h6c: d=8'h50;
+ 8'h6d: d=8'h3c;
+ 8'h6e: d=8'h9f;
+ 8'h6f: d=8'ha8;
+ 8'h70: d=8'h51;
+ 8'h71: d=8'ha3;
+ 8'h72: d=8'h40;
+ 8'h73: d=8'h8f;
+ 8'h74: d=8'h92;
+ 8'h75: d=8'h9d;
+ 8'h76: d=8'h38;
+ 8'h77: d=8'hf5;
+ 8'h78: d=8'hbc;
+ 8'h79: d=8'hb6;
+ 8'h7a: d=8'hda;
+ 8'h7b: d=8'h21;
+ 8'h7c: d=8'h10;
+ 8'h7d: d=8'hff;
+ 8'h7e: d=8'hf3;
+ 8'h7f: d=8'hd2;
+ 8'h80: d=8'hcd;
+ 8'h81: d=8'h0c;
+ 8'h82: d=8'h13;
+ 8'h83: d=8'hec;
+ 8'h84: d=8'h5f;
+ 8'h85: d=8'h97;
+ 8'h86: d=8'h44;
+ 8'h87: d=8'h17;
+ 8'h88: d=8'hc4;
+ 8'h89: d=8'ha7;
+ 8'h8a: d=8'h7e;
+ 8'h8b: d=8'h3d;
+ 8'h8c: d=8'h64;
+ 8'h8d: d=8'h5d;
+ 8'h8e: d=8'h19;
+ 8'h8f: d=8'h73;
+ 8'h90: d=8'h60;
+ 8'h91: d=8'h81;
+ 8'h92: d=8'h4f;
+ 8'h93: d=8'hdc;
+ 8'h94: d=8'h22;
+ 8'h95: d=8'h2a;
+ 8'h96: d=8'h90;
+ 8'h97: d=8'h88;
+ 8'h98: d=8'h46;
+ 8'h99: d=8'hee;
+ 8'h9a: d=8'hb8;
+ 8'h9b: d=8'h14;
+ 8'h9c: d=8'hde;
+ 8'h9d: d=8'h5e;
+ 8'h9e: d=8'h0b;
+ 8'h9f: d=8'hdb;
+ 8'ha0: d=8'he0;
+ 8'ha1: d=8'h32;
+ 8'ha2: d=8'h3a;
+ 8'ha3: d=8'h0a;
+ 8'ha4: d=8'h49;
+ 8'ha5: d=8'h06;
+ 8'ha6: d=8'h24;
+ 8'ha7: d=8'h5c;
+ 8'ha8: d=8'hc2;
+ 8'ha9: d=8'hd3;
+ 8'haa: d=8'hac;
+ 8'hab: d=8'h62;
+ 8'hac: d=8'h91;
+ 8'had: d=8'h95;
+ 8'hae: d=8'he4;
+ 8'haf: d=8'h79;
+ 8'hb0: d=8'he7;
+ 8'hb1: d=8'hc8;
+ 8'hb2: d=8'h37;
+ 8'hb3: d=8'h6d;
+ 8'hb4: d=8'h8d;
+ 8'hb5: d=8'hd5;
+ 8'hb6: d=8'h4e;
+ 8'hb7: d=8'ha9;
+ 8'hb8: d=8'h6c;
+ 8'hb9: d=8'h56;
+ 8'hba: d=8'hf4;
+ 8'hbb: d=8'hea;
+ 8'hbc: d=8'h65;
+ 8'hbd: d=8'h7a;
+ 8'hbe: d=8'hae;
+ 8'hbf: d=8'h08;
+ 8'hc0: d=8'hba;
+ 8'hc1: d=8'h78;
+ 8'hc2: d=8'h25;
+ 8'hc3: d=8'h2e;
+ 8'hc4: d=8'h1c;
+ 8'hc5: d=8'ha6;
+ 8'hc6: d=8'hb4;
+ 8'hc7: d=8'hc6;
+ 8'hc8: d=8'he8;
+ 8'hc9: d=8'hdd;
+ 8'hca: d=8'h74;
+ 8'hcb: d=8'h1f;
+ 8'hcc: d=8'h4b;
+ 8'hcd: d=8'hbd;
+ 8'hce: d=8'h8b;
+ 8'hcf: d=8'h8a;
+ 8'hd0: d=8'h70;
+ 8'hd1: d=8'h3e;
+ 8'hd2: d=8'hb5;
+ 8'hd3: d=8'h66;
+ 8'hd4: d=8'h48;
+ 8'hd5: d=8'h03;
+ 8'hd6: d=8'hf6;
+ 8'hd7: d=8'h0e;
+ 8'hd8: d=8'h61;
+ 8'hd9: d=8'h35;
+ 8'hda: d=8'h57;
+ 8'hdb: d=8'hb9;
+ 8'hdc: d=8'h86;
+ 8'hdd: d=8'hc1;
+ 8'hde: d=8'h1d;
+ 8'hdf: d=8'h9e;
+ 8'he0: d=8'he1;
+ 8'he1: d=8'hf8;
+ 8'he2: d=8'h98;
+ 8'he3: d=8'h11;
+ 8'he4: d=8'h69;
+ 8'he5: d=8'hd9;
+ 8'he6: d=8'h8e;
+ 8'he7: d=8'h94;
+ 8'he8: d=8'h9b;
+ 8'he9: d=8'h1e;
+ 8'hea: d=8'h87;
+ 8'heb: d=8'he9;
+ 8'hec: d=8'hce;
+ 8'hed: d=8'h55;
+ 8'hee: d=8'h28;
+ 8'hef: d=8'hdf;
+ 8'hf0: d=8'h8c;
+ 8'hf1: d=8'ha1;
+ 8'hf2: d=8'h89;
+ 8'hf3: d=8'h0d;
+ 8'hf4: d=8'hbf;
+ 8'hf5: d=8'he6;
+ 8'hf6: d=8'h42;
+ 8'hf7: d=8'h68;
+ 8'hf8: d=8'h41;
+ 8'hf9: d=8'h99;
+ 8'hfa: d=8'h2d;
+ 8'hfb: d=8'h0f;
+ 8'hfc: d=8'hb0;
+ 8'hfd: d=8'h54;
+ 8'hfe: d=8'hbb;
+ 8'hff: d=8'h16;
+ endcase
+
+endmodule
+
+
Index: aes_core/tags/start/rtl/verilog/aes_cipher_top.v
===================================================================
--- aes_core/tags/start/rtl/verilog/aes_cipher_top.v (nonexistent)
+++ aes_core/tags/start/rtl/verilog/aes_cipher_top.v (revision 6)
@@ -0,0 +1,253 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Cipher Top Level ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_cipher_top.v,v 1.1.1.1 2002-11-09 11:22:48 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:48 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out );
+input clk, rst;
+input ld;
+output done;
+input [127:0] key;
+input [127:0] text_in;
+output [127:0] text_out;
+
+////////////////////////////////////////////////////////////////////
+//
+// Local Wires
+//
+
+wire [31:0] w0, w1, w2, w3;
+reg [127:0] text_in_r;
+reg [127:0] text_out;
+reg [7:0] sa00, sa01, sa02, sa03;
+reg [7:0] sa10, sa11, sa12, sa13;
+reg [7:0] sa20, sa21, sa22, sa23;
+reg [7:0] sa30, sa31, sa32, sa33;
+wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
+wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
+wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
+wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
+wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
+wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
+wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
+wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
+wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
+wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
+wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
+wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
+wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc;
+wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc;
+wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc;
+wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc;
+reg done, ld_r;
+reg [3:0] dcnt;
+
+////////////////////////////////////////////////////////////////////
+//
+// Misc Logic
+//
+
+always @(posedge clk)
+ if(!rst) dcnt <= #1 4'h0;
+ else
+ if(ld) dcnt <= #1 4'hb;
+ else
+ if(|dcnt) dcnt <= #1 dcnt - 4'h1;
+
+always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld;
+always @(posedge clk) if(ld) text_in_r <= #1 text_in;
+always @(posedge clk) ld_r <= #1 ld;
+
+////////////////////////////////////////////////////////////////////
+//
+// Initial Permutation (AddRoundKey)
+//
+
+always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
+always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
+always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
+always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
+always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
+always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
+always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
+always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
+always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
+always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
+always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
+always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
+always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
+always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
+always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
+always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
+
+////////////////////////////////////////////////////////////////////
+//
+// Round Permutations
+//
+
+assign sa00_sr = sa00_sub;
+assign sa01_sr = sa01_sub;
+assign sa02_sr = sa02_sub;
+assign sa03_sr = sa03_sub;
+assign sa10_sr = sa11_sub;
+assign sa11_sr = sa12_sub;
+assign sa12_sr = sa13_sub;
+assign sa13_sr = sa10_sub;
+assign sa20_sr = sa22_sub;
+assign sa21_sr = sa23_sub;
+assign sa22_sr = sa20_sub;
+assign sa23_sr = sa21_sub;
+assign sa30_sr = sa33_sub;
+assign sa31_sr = sa30_sub;
+assign sa32_sr = sa31_sub;
+assign sa33_sr = sa32_sub;
+assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc} = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
+assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc} = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
+assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc} = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
+assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc} = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
+assign sa00_next = sa00_mc ^ w0[31:24];
+assign sa01_next = sa01_mc ^ w1[31:24];
+assign sa02_next = sa02_mc ^ w2[31:24];
+assign sa03_next = sa03_mc ^ w3[31:24];
+assign sa10_next = sa10_mc ^ w0[23:16];
+assign sa11_next = sa11_mc ^ w1[23:16];
+assign sa12_next = sa12_mc ^ w2[23:16];
+assign sa13_next = sa13_mc ^ w3[23:16];
+assign sa20_next = sa20_mc ^ w0[15:08];
+assign sa21_next = sa21_mc ^ w1[15:08];
+assign sa22_next = sa22_mc ^ w2[15:08];
+assign sa23_next = sa23_mc ^ w3[15:08];
+assign sa30_next = sa30_mc ^ w0[07:00];
+assign sa31_next = sa31_mc ^ w1[07:00];
+assign sa32_next = sa32_mc ^ w2[07:00];
+assign sa33_next = sa33_mc ^ w3[07:00];
+
+////////////////////////////////////////////////////////////////////
+//
+// Final text output
+//
+
+always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24];
+always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24];
+always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24];
+always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24];
+always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16];
+always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16];
+always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16];
+always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16];
+always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08];
+always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08];
+always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08];
+always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08];
+always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00];
+always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00];
+always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00];
+always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00];
+
+////////////////////////////////////////////////////////////////////
+//
+// Generic Functions
+//
+
+function [31:0] mix_col;
+input [7:0] s0,s1,s2,s3;
+reg [7:0] s0_o,s1_o,s2_o,s3_o;
+begin
+mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
+mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
+mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
+mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
+end
+endfunction
+
+function [7:0] xtime;
+input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
+endfunction
+
+////////////////////////////////////////////////////////////////////
+//
+// Modules
+//
+
+aes_key_expand_128 u0(
+ .clk( clk ),
+ .kld( ld ),
+ .key( key ),
+ .wo_0( w0 ),
+ .wo_1( w1 ),
+ .wo_2( w2 ),
+ .wo_3( w3 ));
+
+aes_sbox us00( .a( sa00 ), .d( sa00_sub ));
+aes_sbox us01( .a( sa01 ), .d( sa01_sub ));
+aes_sbox us02( .a( sa02 ), .d( sa02_sub ));
+aes_sbox us03( .a( sa03 ), .d( sa03_sub ));
+aes_sbox us10( .a( sa10 ), .d( sa10_sub ));
+aes_sbox us11( .a( sa11 ), .d( sa11_sub ));
+aes_sbox us12( .a( sa12 ), .d( sa12_sub ));
+aes_sbox us13( .a( sa13 ), .d( sa13_sub ));
+aes_sbox us20( .a( sa20 ), .d( sa20_sub ));
+aes_sbox us21( .a( sa21 ), .d( sa21_sub ));
+aes_sbox us22( .a( sa22 ), .d( sa22_sub ));
+aes_sbox us23( .a( sa23 ), .d( sa23_sub ));
+aes_sbox us30( .a( sa30 ), .d( sa30_sub ));
+aes_sbox us31( .a( sa31 ), .d( sa31_sub ));
+aes_sbox us32( .a( sa32 ), .d( sa32_sub ));
+aes_sbox us33( .a( sa33 ), .d( sa33_sub ));
+
+endmodule
+
+
Index: aes_core/tags/start/rtl/verilog/aes_key_expand_128.v
===================================================================
--- aes_core/tags/start/rtl/verilog/aes_key_expand_128.v (nonexistent)
+++ aes_core/tags/start/rtl/verilog/aes_key_expand_128.v (revision 6)
@@ -0,0 +1,84 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES Key Expand Block (for 128 bit keys) ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_key_expand_128.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:38 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
+input clk;
+input kld;
+input [127:0] key;
+output [31:0] wo_0, wo_1, wo_2, wo_3;
+reg [31:0] w[3:0];
+wire [31:0] tmp_w;
+wire [31:0] subword;
+wire [31:0] rcon;
+
+assign wo_0 = w[0];
+assign wo_1 = w[1];
+assign wo_2 = w[2];
+assign wo_3 = w[3];
+always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
+always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
+always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
+always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
+assign tmp_w = w[3];
+aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
+aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
+aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
+aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
+aes_rcon r0( .clk(clk), .kld(kld), .out(rcon));
+endmodule
+
Index: aes_core/tags/start/rtl/verilog/aes_rcon.v
===================================================================
--- aes_core/tags/start/rtl/verilog/aes_rcon.v (nonexistent)
+++ aes_core/tags/start/rtl/verilog/aes_rcon.v (revision 6)
@@ -0,0 +1,93 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// AES RCON Block ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// CVS Log
+//
+// $Id: aes_rcon.v,v 1.1.1.1 2002-11-09 11:22:38 rudi Exp $
+//
+// $Date: 2002-11-09 11:22:38 $
+// $Revision: 1.1.1.1 $
+// $Author: rudi $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module aes_rcon(clk, kld, out);
+input clk;
+input kld;
+output [31:0] out;
+reg [31:0] out;
+reg [3:0] rcnt;
+wire [3:0] rcnt_next;
+
+always @(posedge clk)
+ if(kld) out <= #1 32'h01_00_00_00;
+ else out <= #1 frcon(rcnt_next);
+
+assign rcnt_next = rcnt + 4'h1;
+always @(posedge clk)
+ if(kld) rcnt <= #1 4'h0;
+ else rcnt <= #1 rcnt_next;
+
+function [31:0] frcon;
+input [3:0] i;
+case(i) // synopsys parallel_case
+ 4'h0: frcon=32'h01_00_00_00;
+ 4'h1: frcon=32'h02_00_00_00;
+ 4'h2: frcon=32'h04_00_00_00;
+ 4'h3: frcon=32'h08_00_00_00;
+ 4'h4: frcon=32'h10_00_00_00;
+ 4'h5: frcon=32'h20_00_00_00;
+ 4'h6: frcon=32'h40_00_00_00;
+ 4'h7: frcon=32'h80_00_00_00;
+ 4'h8: frcon=32'h1b_00_00_00;
+ 4'h9: frcon=32'h36_00_00_00;
+ default: frcon=32'h00_00_00_00;
+endcase
+endfunction
+
+endmodule
Index: aes_core/tags/start/doc/aes.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: aes_core/tags/start/doc/aes.pdf
===================================================================
--- aes_core/tags/start/doc/aes.pdf (nonexistent)
+++ aes_core/tags/start/doc/aes.pdf (revision 6)
aes_core/tags/start/doc/aes.pdf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: aes_core/tags/start/sim/rtl_sim/run/waves/waves.do
===================================================================
--- aes_core/tags/start/sim/rtl_sim/run/waves/waves.do (nonexistent)
+++ aes_core/tags/start/sim/rtl_sim/run/waves/waves.do (revision 6)
@@ -0,0 +1,209 @@
+// Signalscan Version 6.8b1
+
+
+define noactivityindicator
+define analog waveform lines
+define add variable default overlay off
+define waveform window analogheight 1
+define terminal automatic
+define buttons control \
+ 1 opensimmulationfile \
+ 2 executedofile \
+ 3 designbrowser \
+ 4 waveform \
+ 5 source \
+ 6 breakpoints \
+ 7 definesourcessearchpath \
+ 8 exit \
+ 9 createbreakpoint \
+ 10 creategroup \
+ 11 createmarker \
+ 12 closesimmulationfile \
+ 13 renamesimmulationfile \
+ 14 replacesimulationfiledata \
+ 15 listopensimmulationfiles \
+ 16 savedofile
+define buttons waveform \
+ 1 replacesimulationfiledata \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 zoomin \
+ 7 zoomout \
+ 8 zoomoutfull \
+ 9 expand \
+ 10 createmarker \
+ 11 designbrowser:1 \
+ 12 savedofile \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons designbrowser \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 cdupscope \
+ 7 getallvariables \
+ 8 getdeepallvariables \
+ 9 addvariables \
+ 10 addvarsandclosewindow \
+ 11 closewindow \
+ 12 scopefiltermodule \
+ 13 scopefiltertask \
+ 14 scopefilterfunction \
+ 15 scopefilterblock \
+ 16 scopefilterprimitive
+define buttons event \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 move \
+ 7 closewindow \
+ 8 duplicate \
+ 9 defineasrisingedge \
+ 10 defineasfallingedge \
+ 11 defineasanyedge \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons source \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createbreakpoint \
+ 7 creategroup \
+ 8 createmarker \
+ 9 createevent \
+ 10 createregisterpage \
+ 11 closewindow \
+ 12 opensimmulationfile \
+ 13 closesimmulationfile \
+ 14 renamesimmulationfile \
+ 15 replacesimulationfiledata \
+ 16 listopensimmulationfiles
+define buttons register \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createregisterpage \
+ 7 closewindow \
+ 8 continuefor \
+ 9 continueuntil \
+ 10 continueforever \
+ 11 stop \
+ 12 previous \
+ 13 next \
+ 14 variableradixbinary \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define show related transactions
+define exit noprompt
+define event search direction forward
+define variable fullhierarchy
+define variable nofilenames
+define variable nofullpathfilenames
+include bookmark with filenames
+include scope history without filenames
+define waveform window listpane 7.95
+define waveform window namepane 33.97
+define multivalueindication
+define pattern curpos dot
+define pattern cursor1 dot
+define pattern cursor2 dot
+define pattern marker dot
+define print designer "Rudolf Usselmann"
+define print border
+define print color blackonwhite
+define print command "/usr/bin/lpr -P%P"
+define print printer lp
+define print size A4
+define print range visible
+define print variable visible
+define rise fall time low threshold percentage 10
+define rise fall time high threshold percentage 90
+define rise fall time low value 0
+define rise fall time high value 3.3
+define sendmail command "/usr/lib/sendmail"
+define sequence time width 30.00
+define snap
+
+define source noprompt
+define time units default
+define userdefinedbussymbol
+define user guide directory "/usr/local/designacc/signalscan-6.5s2/doc/html"
+define waveform window grid off
+define waveform window waveheight 14
+define waveform window wavespace 6
+define web browser command netscape
+define zoom outfull on initial add off
+add group \
+ A \
+ test.rst \
+ test.clk \
+ test.u0.ld \
+ test.u0.ld_r \
+ test.u0.key[127:0]'h \
+ test.u0.text_in[127:0]'h \
+ test.text_out[127:0]'h \
+ test.u0.done \
+ test.done2 \
+ test.text_out2[127:0]'h \
+ test.u0.w0[31:0]'h \
+ test.u0.w1[31:0]'h \
+ test.u0.w2[31:0]'h \
+ test.u0.w3[31:0]'h \
+ test.u0.sa00[7:0]'h \
+ test.u0.sa01[7:0]'h \
+ test.u0.sa02[7:0]'h \
+ test.u0.sa03[7:0]'h \
+ test.u0.sa10[7:0]'h \
+ test.u0.sa11[7:0]'h \
+ test.u0.sa12[7:0]'h \
+ test.u0.sa13[7:0]'h \
+ test.u0.sa20[7:0]'h \
+ test.u0.sa21[7:0]'h \
+ test.u0.sa22[7:0]'h \
+ test.u0.sa23[7:0]'h \
+ test.u0.sa30[7:0]'h \
+ test.u0.sa31[7:0]'h \
+ test.u0.sa32[7:0]'h \
+ test.u0.sa33[7:0]'h \
+ test.clk \
+ test.u1.ld \
+ test.u1.done \
+ test.u1.w3[31:0]'h \
+ test.u1.kdone \
+ test.u1.kld \
+ test.u1.text_in[127:0]'h \
+ test.u1.text_in_r[127:0]'h \
+ test.u1.text_out[127:0]'h \
+ test.u1.kb_ld \
+ test.u1.kcnt[3:0]'h \
+ test.u1.dcnt[3:0]'h \
+ test.u1.w0[31:0]'h \
+ test.u1.w1[31:0]'h \
+ test.u1.w2[31:0]'h \
+ test.u1.w3[31:0]'h \
+ test.u1.wk0[31:0]'h \
+ test.u1.wk1[31:0]'h \
+ test.u1.wk2[31:0]'h \
+ test.u1.wk3[31:0]'h \
+
+
+deselect all
+create marker Marker1 0ns
+open window designbrowser 1 geometry 450 269 1020 752
+open window waveform 1 geometry 58 104 1540 838
+zoom at 0(0)ns 0.00803721 0.00000000
Index: aes_core/tags/start/sim/rtl_sim/bin/Makefile
===================================================================
--- aes_core/tags/start/sim/rtl_sim/bin/Makefile (nonexistent)
+++ aes_core/tags/start/sim/rtl_sim/bin/Makefile (revision 6)
@@ -0,0 +1,82 @@
+
+all: sim
+SHELL = /bin/sh
+MS="-s"
+
+##########################################################################
+#
+# DUT Sources
+#
+##########################################################################
+DUT_SRC_DIR=../../../rtl/verilog
+_TARGETS_= $(DUT_SRC_DIR)/aes_sbox.v \
+ $(DUT_SRC_DIR)/aes_rcon.v \
+ $(DUT_SRC_DIR)/aes_key_expand_128.v \
+ $(DUT_SRC_DIR)/aes_cipher_top.v \
+ $(DUT_SRC_DIR)/aes_inv_sbox.v \
+ $(DUT_SRC_DIR)/aes_inv_cipher_top.v
+
+
+##########################################################################
+#
+# Test Bench Sources
+#
+##########################################################################
+TB_SRC_DIR=../../../bench/verilog
+_TB_= $(TB_SRC_DIR)/test_bench_top.v
+
+##########################################################################
+#
+# Misc Variables
+#
+##########################################################################
+
+INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
+LOGF=-l .nclog
+UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
+GATE_NETLIST = ../../../syn/out/aes_cipher_top.v
+
+##########################################################################
+#
+# Make Targets
+#
+##########################################################################
+ss:
+ signalscan -do waves/waves.do -waves waves/waves.trn &
+
+simw:
+ @$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
+
+sim:
+ ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
+ $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
+ +ncuid+`hostname`
+
+ivl:
+ /usr/local/bin/iverilog -D RUDIS_TB $(_TARGETS_) $(_TB_) \
+ -I ./$(DUT_SRC_DIR)/ -I ./$(TB_SRC_DIR)/ \
+ $(WAVES) $(ACCESS) -s test
+
+gatew:
+ @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"
+
+gate:
+ ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \
+ $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \
+ $(LOGF) +ncstatus +ncuid+`hostname`
+
+hal:
+ @echo ""
+ @echo "----- Running HAL ... ----------"
+ @hal +incdir+$(DUT_SRC_DIR) -NOP -NOS \
+ -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
+ $(_TARGETS_)
+ @echo "----- DONE ... ----------"
+
+clean:
+ rm -rf ./waves/*.dsn ./waves/*.trn \
+ ncwork/.inc* ncwork/inc* \
+ ./verilog.* .nclog hal.log INCA_libs
+
+##########################################################################
+
aes_core/tags/start/sim/rtl_sim/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aes_core/tags/start/vim_session.vim
===================================================================
--- aes_core/tags/start/vim_session.vim (nonexistent)
+++ aes_core/tags/start/vim_session.vim (revision 6)
@@ -0,0 +1,243 @@
+set nocompatible
+let s:cpo_save=&cpo
+set cpo&vim
+map!
+map!
+map!
+map!
+map!
+map!
+map!
+map!
+map!
+map!
+nnoremap 6_Paste "=@+.'xy'
+gPFx"_2x:echo
+map
+map
+map
+map
+map
+map
+map
+map
+map
+map
+let &cpo=s:cpo_save
+unlet s:cpo_save
+set background=dark
+set bufhidden=delete
+set buftype=nofile
+if &filetype != 'csh'
+set filetype=csh
+endif
+set guifont=-adobe-courier-medium-r-normal-*-*-120-*-*-m-*-iso8859-1
+set iminsert=0
+set imsearch=0
+set iskeyword=@,48-57,_,192-255,+,-,?
+set menuitems=50
+set mouse=a
+set noswapfile
+if &syntax != 'verilog'
+set syntax=verilog
+endif
+let s:so_save = &so | let s:siso_save = &siso | set so=0 siso=0
+let v:this_session=expand(":p")
+silent only
+cd ~/projects/aes_core
+set shortmess=aoO
+badd +1 rtl/verilog/aes_top.v
+badd +105 bench/verilog/test_bench_top.v
+badd +30 sim/rtl_sim/bin/Makefile
+badd +79 rtl/verilog/aes_key_expand_128.v
+badd +72 rtl/verilog/aes_key_expand_192.v
+badd +55 rtl/verilog/aes_key_expand_256.v
+badd +94 rtl/verilog/aes_rcon.v
+badd +80 rtl/verilog/aes_sbox.v
+badd +44 impl_results
+badd +1 rtl/verilog/aes_inv_cipher_top.v
+badd +471 rtl/verilog/aes_inv_sbox.v
+silent! argdel *
+set splitbelow splitright
+normal _|
+vsplit
+normal 1h
+normal w
+set nosplitbelow
+set nosplitright
+normal t
+set winheight=1 winwidth=1
+exe 'vert resize ' . ((&columns * 99 + 106) / 212)
+normal w
+exe 'vert resize ' . ((&columns * 112 + 106) / 212)
+normal w
+argglobal
+edit rtl/verilog/aes_sbox.v
+setlocal noautoindent
+setlocal autoread
+setlocal nobinary
+setlocal bufhidden=
+setlocal buflisted
+setlocal buftype=
+setlocal nocindent
+setlocal cinkeys=0{,0},0),:,0#,!^F,o,O,e
+setlocal cinoptions=
+setlocal cinwords=if,else,while,do,for,switch
+setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:-
+setlocal commentstring=/*%s*/
+setlocal complete=.,w,b,u,t,i
+setlocal define=
+setlocal dictionary=
+setlocal nodiff
+setlocal equalprg=
+setlocal errorformat=
+setlocal noexpandtab
+if &filetype != 'verilog'
+setlocal filetype=verilog
+endif
+setlocal foldcolumn=0
+setlocal foldenable
+setlocal foldexpr=0
+setlocal foldignore=#
+setlocal foldlevel=0
+setlocal foldmarker={{{,}}}
+setlocal foldmethod=manual
+setlocal foldminlines=1
+setlocal foldnestmax=20
+setlocal foldtext=foldtext()
+setlocal formatoptions=tcq
+setlocal grepprg=
+setlocal iminsert=0
+setlocal imsearch=0
+setlocal include=
+setlocal includeexpr=
+setlocal indentexpr=
+setlocal indentkeys=0{,0},:,0#,!^F,o,O,e
+setlocal noinfercase
+setlocal iskeyword=@,48-57,_,192-255,+,-,?
+setlocal keymap=
+setlocal nolinebreak
+setlocal nolisp
+setlocal nolist
+setlocal makeprg=
+setlocal matchpairs=(:),{:},[:]
+setlocal modeline
+setlocal modifiable
+setlocal nrformats=octal,hex
+setlocal nonumber
+setlocal path=
+setlocal nopreviewwindow
+setlocal noreadonly
+setlocal norightleft
+setlocal noscrollbind
+setlocal shiftwidth=8
+setlocal noshortname
+setlocal nosmartindent
+setlocal softtabstop=0
+setlocal suffixesadd=
+setlocal noswapfile
+if &syntax != 'verilog'
+setlocal syntax=verilog
+endif
+setlocal tabstop=8
+setlocal tags=
+setlocal textwidth=0
+setlocal thesaurus=
+setlocal wrap
+setlocal wrapmargin=0
+silent! normal zE
+let s:l = 65 - ((28 * winheight(0) + 34) / 69)
+if s:l < 1 | let s:l = 1 | endif
+exe s:l
+normal zt
+65
+normal 0
+normal w
+argglobal
+edit rtl/verilog/aes_inv_cipher_top.v
+setlocal noautoindent
+setlocal autoread
+setlocal nobinary
+setlocal bufhidden=
+setlocal buflisted
+setlocal buftype=
+setlocal nocindent
+setlocal cinkeys=0{,0},0),:,0#,!^F,o,O,e
+setlocal cinoptions=
+setlocal cinwords=if,else,while,do,for,switch
+setlocal comments=s1:/*,mb:*,ex:*/,://,b:#,:%,:XCOMM,n:>,fb:-
+setlocal commentstring=/*%s*/
+setlocal complete=.,w,b,u,t,i
+setlocal define=
+setlocal dictionary=
+setlocal nodiff
+setlocal equalprg=
+setlocal errorformat=
+setlocal noexpandtab
+if &filetype != 'verilog'
+setlocal filetype=verilog
+endif
+setlocal foldcolumn=0
+setlocal foldenable
+setlocal foldexpr=0
+setlocal foldignore=#
+setlocal foldlevel=0
+setlocal foldmarker={{{,}}}
+setlocal foldmethod=manual
+setlocal foldminlines=1
+setlocal foldnestmax=20
+setlocal foldtext=foldtext()
+setlocal formatoptions=tcq
+setlocal grepprg=
+setlocal iminsert=0
+setlocal imsearch=0
+setlocal include=
+setlocal includeexpr=
+setlocal indentexpr=
+setlocal indentkeys=0{,0},:,0#,!^F,o,O,e
+setlocal noinfercase
+setlocal iskeyword=@,48-57,_,192-255,+,-,?
+setlocal keymap=
+setlocal nolinebreak
+setlocal nolisp
+setlocal nolist
+setlocal makeprg=
+setlocal matchpairs=(:),{:},[:]
+setlocal modeline
+setlocal modifiable
+setlocal nrformats=octal,hex
+setlocal nonumber
+setlocal path=
+setlocal nopreviewwindow
+setlocal noreadonly
+setlocal norightleft
+setlocal noscrollbind
+setlocal shiftwidth=8
+setlocal noshortname
+setlocal nosmartindent
+setlocal softtabstop=0
+setlocal suffixesadd=
+setlocal noswapfile
+if &syntax != 'verilog'
+setlocal syntax=verilog
+endif
+setlocal tabstop=8
+setlocal tags=
+setlocal textwidth=0
+setlocal thesaurus=
+setlocal wrap
+setlocal wrapmargin=0
+silent! normal zE
+let s:l = 260 - ((19 * winheight(0) + 34) / 69)
+if s:l < 1 | let s:l = 1 | endif
+exe s:l
+normal zt
+260
+normal 09l
+normal w
+set winheight=1 winwidth=20 shortmess=filnxtToO
+let s:sx = expand(":p:r")."x.vim"
+if file_readable(s:sx)
+ exe "source " . s:sx
+endif
+let &so = s:so_save | let &siso = s:siso_save
Index: aes_core/tags/start/syn/bin/read.dc
===================================================================
--- aes_core/tags/start/syn/bin/read.dc (nonexistent)
+++ aes_core/tags/start/syn/bin/read.dc (revision 6)
@@ -0,0 +1,67 @@
+###############################################################################
+#
+# Pre Synthesis Script
+#
+# This script only reads in the design and saves it in a DB file
+#
+# Author: Rudolf Usselmann
+# rudi@asics.ws
+#
+# Revision:
+# 3/7/01 RU Initial Sript
+#
+#
+###############################################################################
+
+# ==============================================
+# Setup Design Parameters
+source ../bin/design_spec.dc
+
+# ==============================================
+# Setup Libraries
+source ../bin/lib_spec.dc
+
+# ==============================================
+# Setup IO Files
+
+append log_file ../log/$active_design "_pre.log"
+append pre_comp_db_file ../out/$design_name "_pre.db"
+
+sh rm -f $log_file
+
+# ==============================================
+# Setup Misc Variables
+
+set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
+
+# ==============================================
+# Read Design
+
+echo "+++++++++ Analyzing all design files ..." >> $log_file
+
+foreach module $design_files {
+ echo "+++++++++ Reading: $module" >> $log_file
+ echo +++++++++ Reading: $module
+ set module_file_name ""
+ append module_file_name $module ".v"
+ analyze -f verilog $module_file_name >> $log_file
+ elaborate $module >> $log_file
+ }
+
+current_design $active_design
+
+echo "+++++++++ Linking Design ..." >> $log_file
+link >> $log_file
+
+echo "+++++++++ Uniquifying Design ..." >> $log_file
+uniquify >> $log_file
+
+echo "+++++++++ Checking Design ..." >> $log_file
+check_design >> $log_file
+
+# ==============================================
+# Save Design
+echo "+++++++++ Saving Design ..." >> $log_file
+write_file -hierarchy -format db -output $pre_comp_db_file
+
+quit
Index: aes_core/tags/start/syn/bin/comp.dc
===================================================================
--- aes_core/tags/start/syn/bin/comp.dc (nonexistent)
+++ aes_core/tags/start/syn/bin/comp.dc (revision 6)
@@ -0,0 +1,142 @@
+###############################################################################
+#
+# Actual Synthesis Script
+#
+# This script does the actual synthesis
+#
+# Author: Rudolf Usselmann
+# rudi@asics.ws
+#
+# Revision:
+# 3/7/01 RU Initial Sript
+#
+#
+###############################################################################
+
+# ==============================================
+# Setup Design Parameters
+source ../bin/design_spec.dc
+
+# ==============================================
+# Setup Libraries
+source ../bin/lib_spec.dc
+
+# ==============================================
+# Setup IO Files
+
+append log_file ../log/$active_design "_cmp.log"
+append pre_comp_db_file ../out/$design_name "_pre.db"
+append post_comp_db_file ../out/$design_name ".db"
+append post_syn_verilog_file ../out/$design_name "_ps.v"
+set junk_file /dev/null
+
+sh rm -f $log_file
+
+# ==============================================
+# Setup Misc Variables
+
+set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
+
+# ==============================================
+# Read Design
+
+echo "+++++++++ Reading Design ..." >> $log_file
+read_file $pre_comp_db_file >> $log_file
+
+# ==============================================
+# Operating conditions
+
+echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
+current_design $design_name
+set_operating_conditions WORST >> $log_file
+
+# ==============================================
+# Setup Clocks and Resets
+
+echo "+++++++++ Setting up Clocks ..." >> $log_file
+
+set_drive 0 [find port {clk}]
+
+# !!! Clock !!!
+set clock_period 2.5
+create_clock -period $clock_period clk
+set_clock_skew -uncertainty 0.1 clk
+set_clock_transition 0.2 clk
+set_dont_touch_network clk
+
+# ==============================================
+# Setup IOs
+
+echo "+++++++++ Setting up IOs ..." >> $log_file
+
+# Need to spell out external IOs
+
+set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
+set_load 0.2 [all_outputs]
+
+set_input_delay -max 1 -clock clk [all_inputs]
+set_output_delay -max 1 -clock clk [all_outputs]
+
+# ==============================================
+# Setup Area Constrains
+set_max_area 0.0
+
+# ==============================================
+# Force Ultra
+set_ultra_optimization -f
+set compile_new_optimization true
+
+# ==============================================
+# Compile Design
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Timing Loops Report +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+report_timing -loops -max_path 20 >> $log_file
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Starting Compile +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+
+set_wire_load_model -name suggested_160K [find design *]
+set_balance_registers true
+compile -boundary_optimization -ungroup_all
+optimize_registers -period 0
+compile -incremental_mapping -map_effort high -area_effort high -boundary_optimization -ungroup_all
+
+# ==============================================
+# Write Out the optimized design
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Saving Optimized Design +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+write_file -hierarchy -format verilog -output $post_syn_verilog_file
+write_file -hierarchy -format db -output $post_comp_db_file
+
+# ==============================================
+# Create Some Basic Reports
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Reporting Final Results +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+report_timing -path full_clock -nworst 10 -nets \
+ -transition_time -capacitance -attributes \
+ -sort_by slack >> $log_file
+
+echo "" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "+++++++++ Area Report +++++++++" >> $log_file
+echo "++++++++++++++++++++++++++++++++++++++++++++++" >> $log_file
+echo "" >> $log_file
+
+report_area >> $log_file
+quit
+
Index: aes_core/tags/start/syn/bin/lib_spec.dc
===================================================================
--- aes_core/tags/start/syn/bin/lib_spec.dc (nonexistent)
+++ aes_core/tags/start/syn/bin/lib_spec.dc (revision 6)
@@ -0,0 +1,43 @@
+###############################################################################
+#
+# Library Specification
+#
+# Author: Rudolf Usselmann
+# rudi@asics.ws
+#
+# Revision:
+# 3/7/01 RU Initial Sript
+#
+#
+###############################################################################
+
+# ==============================================
+# Setup Libraries
+
+#tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
+#tools/dc_libraries/virtual_silicon/UMCL13L210D3_1.0/design_compiler/ \
+
+
+set search_path [list $search_path . \
+ /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
+ $hdl_src_dir]
+
+set snps [getenv "SYNOPSYS"]
+
+set synthetic_library ""
+append synthetic_library $snps "/libraries/syn/dw01.sldb "
+append synthetic_library $snps "/libraries/syn/dw02.sldb "
+append synthetic_library $snps "/libraries/syn/dw03.sldb "
+append synthetic_library $snps "/libraries/syn/dw04.sldb "
+append synthetic_library $snps "/libraries/syn/dw05.sldb "
+append synthetic_library $snps "/libraries/syn/dw06.sldb "
+append synthetic_library $snps "/libraries/syn/dw07.sldb "
+
+set target_library { umcl18u250t2_wc.db }
+#set target_library { umcl13l210t3_wc.db }
+
+set link_library ""
+append link_library $target_library " " $synthetic_library
+
+#set symbol_library { umcl13l210t3.sdb }
+
Index: aes_core/tags/start/syn/bin/design_spec.dc
===================================================================
--- aes_core/tags/start/syn/bin/design_spec.dc (nonexistent)
+++ aes_core/tags/start/syn/bin/design_spec.dc (revision 6)
@@ -0,0 +1,29 @@
+###############################################################################
+#
+# Design Specification
+#
+# Author: Rudolf Usselmann
+# rudi@asics.ws
+#
+# Revision:
+# 3/7/01 RU Initial Sript
+#
+#
+###############################################################################
+
+# ==============================================
+# Setup Design Parameters
+
+set design_files {aes_rcon aes_sbox aes_key_expand_128 aes_cipher_top}
+set design_name aes_cipher_top
+set active_design aes_cipher_top
+
+#set design_files {aes_rcon aes_inv_sbox aes_key_expand_128 aes_inv_cipher_top}
+#set design_name aes_inv_cipher_top
+#set active_design aes_inv_cipher_top
+
+# Next Statement defines all clocks and resets in the design
+set special_net {clk}
+
+set hdl_src_dir ../../rtl/verilog/
+
Index: aes_core/tags
===================================================================
--- aes_core/tags (nonexistent)
+++ aes_core/tags (revision 6)
aes_core/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##