URL
https://opencores.org/ocsvn/ata/ata/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/verilog/ocidec-1/counter.v
5,6 → 5,7
// Rev. 1.0 June 27th, 2001. Initial Verilog release |
// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list. |
// |
`timescale 1ns / 10ps |
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///////////////////////////// |
101,3 → 102,4
assign done = rco; |
endmodule |
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/trunk/verilog/ocidec-1/pio_tctrl.v
41,6 → 41,7
// when write, hold data for T4, disable output-enable signal |
// 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest |
// 7) start new cycle |
`timescale 1ns / 10ps |
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module PIO_tctrl(clk, nReset, rst, IORDY_en, T1, T2, T4, Teoc, go, we, oe, done, dstrb, DIOR, DIOW, IORDY); |
// parameter declarations |
180,3 → 181,5
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/trunk/verilog/ocidec-1/controller.v
4,11 → 4,13
// author : Richard Herveille |
// rev.: 1.0 june 28th, 2001. Initial Verilog release |
// rev.: 1.1 July 3rd, 2001. Rewrote "IORDY" and "INTRQ" capture section. |
// rev.: 1.2 July 9th, 2001. Added "timescale". Undo "IORDY & INTRQ" rewrite. |
// |
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// OCIDEC1 supports: |
// -Common Compatible timing access to all connected devices |
// |
`timescale 1ns / 10ps |
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module controller (clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, |
PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc, PIO_cmdport_IORDYen, |
102,11 → 104,12
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// synchronize incoming signals |
always@(posedge clk) |
begin |
always |
begin : synch_incoming |
reg cIORDY; // capture IORDY |
reg cINTRQ; // capture INTRQ |
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@(posedge clk) |
begin |
cIORDY <= IORDY; |
cINTRQ <= INTRQ; |
185,3 → 188,5
assign PIOack = PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request) |
endmodule |
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/trunk/verilog/ocidec-1/ata.v
4,7 → 4,7
// Author: Richard Herveille |
// rev.: 1.0 June 29th, 2001. Initial Verilog release |
// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list. |
// |
// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected. |
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// DeviceType: OCIDEC-1: OpenCores IDE Controller type1 |
// Features: PIO Compatible Timing |
20,8 → 20,9
// CS0- select command block registers |
// CS1- select control block registers |
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`timescale 1ns / 10ps |
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module atahost (CLK_I, nReset, RST_I, CYC_I, STB_I, ACK_O, ERR_O, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, INTA_O, |
module ata (CLK_I, nReset, RST_I, CYC_I, STB_I, ACK_O, ERR_O, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, INTA_O, |
RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ); |
// |
// Parameter declarations |
131,7 → 132,7
CtrlReg[31:1] <= 0; |
CtrlReg[0] <= 1'b1; // set reset bit (ATA-RESETn line) |
end |
else |
else if (sel_ctrl) |
CtrlReg <= DAT_I; |
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// assign bits |
185,7 → 186,7
PIO_cmdport_T4 = PIO_mode0_T4; |
PIO_cmdport_Teoc = PIO_mode0_Teoc; |
end |
else |
else if(sel_PIO_cmdport) |
begin |
PIO_cmdport_T1 = DAT_I[ 7: 0]; |
PIO_cmdport_T2 = DAT_I[15: 8]; |
227,4 → 228,3
// assign DAT_O output |
assign DAT_O = ADR_I[6] ? {16'h0000, PIOq} : Q; |
endmodule |
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