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Rev 5 → Rev 6
/trunk/bench/verilog/bench_div_top.v
34,10 → 34,10
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// CVS Log |
// |
// $Id: bench_div_top.v,v 1.2 2002-10-31 13:53:55 rherveille Exp $ |
// $Id: bench_div_top.v,v 1.3 2003-09-17 13:09:23 rherveille Exp $ |
// |
// $Date: 2002-10-31 13:53:55 $ |
// $Revision: 1.2 $ |
// $Date: 2003-09-17 13:09:23 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,6 → 44,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/31 13:53:55 rherveille |
// Modified testbench. Fixed a bug in the remainder output size of div_su.v |
// |
// Revision 1.1.1.1 2002/10/29 20:29:08 rherveille |
// |
// |
56,10 → 59,10
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module bench_div_top(); |
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parameter z_width = 8; |
parameter z_width = 16; |
parameter d_width = z_width /2; |
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parameter pipeline = 8; |
parameter pipeline = d_width +4; |
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parameter show_div0 = 0; |
parameter show_ovf = 0; |
70,10 → 73,10
reg clk; |
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integer z, d, n; |
integer dz [pipeline-1:0]; |
integer dd [pipeline-1:0]; |
reg [d_width -1:0] di; |
reg [z_width -1:0] zi; |
integer dz [pipeline:1]; |
integer dd [pipeline:1]; |
reg [d_width:1] di; |
reg [z_width:1] zi; |
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integer sr, qr; |
|
82,8 → 85,18
wire div0, ovf; |
reg [d_width :0] sc, qc; |
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reg err_cnt; |
integer err_cnt; |
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function integer twos; |
input [d_width:1] d; |
begin |
if(d[d_width]) |
twos = -(~d[d_width:1] +1); |
else |
twos = d[d_width:1]; |
end |
endfunction |
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// |
// hookup division unit |
// |
101,7 → 114,7
always #2.5 clk <= ~clk; |
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always @(posedge clk) |
for(n=1; n<=pipeline-1; n=n+1) |
for(n=2; n<=pipeline; n=n+1) |
begin |
dz[n] <= #1 dz[n-1]; |
dd[n] <= #1 dd[n-1]; |
112,6 → 125,13
$display("*"); |
$display("* Starting testbench"); |
$display("*"); |
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`ifdef WAVES |
$shm_open("waves"); |
$shm_probe("AS",bench_div_top,"AS"); |
$display("INFO: Signal dump enabled ...\n\n"); |
`endif |
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err_cnt = 0; |
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clk = 0; // start with low-level clock |
123,22 → 143,20
for(z=-(1<<(z_width -1)); z < 1<<(z_width -1); z=z+1) |
for(d=0; d< 1<<(z_width/2); d=d+1) |
begin |
zi <= z; |
di <= d; |
zi <= #1 z; |
di <= #1 d; |
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dz[0] <= z; |
dd[0] <= d; |
dz[1] <= #1 z; |
dd[1] <= #1 d; |
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qr = dz[pipeline-1] / dd[pipeline-1]; |
qc = qr; |
sr = dz[pipeline-1] - (dd[pipeline-1] * qc); |
sc = sr; |
qc = dz[pipeline] / dd[pipeline]; |
sc = dz[pipeline] - (dd[pipeline] * (dz[pipeline]/dd[pipeline])); |
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if(!ovf) |
if(!ovf && !div0) |
if ( (qc !== q) || (sc !== s) ) |
begin |
$display("Result error (z/d=%d/%d). Received (q,s) = (%d,%d), expected (%d,%d)", |
dz[pipeline-1], dd[pipeline-1], q, s, qc, sc); |
$display("Result error (z/d=%0d/%0d). Received (q,s) = (%0d,%0d), expected (%0d,%0d)", |
dz[pipeline], dd[pipeline], twos(q), s, twos(qc), sc); |
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err_cnt = err_cnt +1; |
end |
145,11 → 163,11
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if(show_div0) |
if(div0) |
$display("Division by zero (z/d=%0d/%0d)", dz[pipeline-1], dd[pipeline-1]); |
$display("Division by zero (z/d=%0d/%0d)", dz[pipeline], dd[pipeline]); |
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if(show_ovf) |
if(ovf) |
$display("Overflow (z/d=%0d/%0d)", dz[pipeline-1], dd[pipeline-1]); |
$display("Overflow (z/d=%0d/%0d)", dz[pipeline], dd[pipeline]); |
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@(posedge clk); |
end |
/trunk/rtl/verilog/div_uu.v
1,6 → 1,6
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Non-restoring unsinged divider //// |
//// Non-restoring unsigned divider //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
34,10 → 34,10
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// CVS Log |
// |
// $Id: div_uu.v,v 1.2 2002-10-31 13:54:58 rherveille Exp $ |
// $Id: div_uu.v,v 1.3 2003-09-17 13:08:53 rherveille Exp $ |
// |
// $Date: 2002-10-31 13:54:58 $ |
// $Revision: 1.2 $ |
// $Date: 2003-09-17 13:08:53 $ |
// $Revision: 1.3 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
44,6 → 44,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/10/31 13:54:58 rherveille |
// Fixed a bug in the remainder output of div_su.v |
// |
// Revision 1.1.1.1 2002/10/29 20:29:10 rherveille |
// |
// |
110,7 → 113,7
else |
tmp = si; |
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assign_s = tmp[z_width-1:z_width-4]; |
assign_s = tmp[z_width-1:z_width-d_width]; |
end |
endfunction |
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