URL
https://opencores.org/ocsvn/djpeg/djpeg/trunk
Subversion Repositories djpeg
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- from Rev 5 to Rev 6
- ↔ Reverse comparison
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/trunk/c_model/djpeg.c
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/trunk/image/test.jpg
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Index: trunk/src/jpeg_idctx.v
===================================================================
--- trunk/src/jpeg_idctx.v (revision 5)
+++ trunk/src/jpeg_idctx.v (nonexistent)
@@ -1,1241 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_idctx.v
-// Module Name : jpeg_idctx
-// Description : iDCT-X
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/09/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_idctx
- (
- rst,
- clk,
-
- DataInEnable,
- DataInSel,
- Data00In,
- Data01In,
- Data02In,
- Data03In,
- Data04In,
- Data05In,
- Data06In,
- Data07In,
- Data08In,
- Data09In,
- Data10In,
- Data11In,
- Data12In,
- Data13In,
- Data14In,
- Data15In,
- Data16In,
- Data17In,
- Data18In,
- Data19In,
- Data20In,
- Data21In,
- Data22In,
- Data23In,
- Data24In,
- Data25In,
- Data26In,
- Data27In,
- Data28In,
- Data29In,
- Data30In,
- Data31In,
- Data32In,
- Data33In,
- Data34In,
- Data35In,
- Data36In,
- Data37In,
- Data38In,
- Data39In,
- Data40In,
- Data41In,
- Data42In,
- Data43In,
- Data44In,
- Data45In,
- Data46In,
- Data47In,
- Data48In,
- Data49In,
- Data50In,
- Data51In,
- Data52In,
- Data53In,
- Data54In,
- Data55In,
- Data56In,
- Data57In,
- Data58In,
- Data59In,
- Data60In,
- Data61In,
- Data62In,
- Data63In,
- DataInIdle,
- DataInRelease,
-
- DataOutIdle,
- DataOutEnable,
- DataOutPage,
- DataOutCount,
- Data0Out,
- Data1Out
- );
-
- input clk;
- input rst;
-
- input DataInEnable;
- output DataInSel;
- input [15:0] Data00In;
- input [15:0] Data01In;
- input [15:0] Data02In;
- input [15:0] Data03In;
- input [15:0] Data04In;
- input [15:0] Data05In;
- input [15:0] Data06In;
- input [15:0] Data07In;
- input [15:0] Data08In;
- input [15:0] Data09In;
- input [15:0] Data10In;
- input [15:0] Data11In;
- input [15:0] Data12In;
- input [15:0] Data13In;
- input [15:0] Data14In;
- input [15:0] Data15In;
- input [15:0] Data16In;
- input [15:0] Data17In;
- input [15:0] Data18In;
- input [15:0] Data19In;
- input [15:0] Data20In;
- input [15:0] Data21In;
- input [15:0] Data22In;
- input [15:0] Data23In;
- input [15:0] Data24In;
- input [15:0] Data25In;
- input [15:0] Data26In;
- input [15:0] Data27In;
- input [15:0] Data28In;
- input [15:0] Data29In;
- input [15:0] Data30In;
- input [15:0] Data31In;
- input [15:0] Data32In;
- input [15:0] Data33In;
- input [15:0] Data34In;
- input [15:0] Data35In;
- input [15:0] Data36In;
- input [15:0] Data37In;
- input [15:0] Data38In;
- input [15:0] Data39In;
- input [15:0] Data40In;
- input [15:0] Data41In;
- input [15:0] Data42In;
- input [15:0] Data43In;
- input [15:0] Data44In;
- input [15:0] Data45In;
- input [15:0] Data46In;
- input [15:0] Data47In;
- input [15:0] Data48In;
- input [15:0] Data49In;
- input [15:0] Data50In;
- input [15:0] Data51In;
- input [15:0] Data52In;
- input [15:0] Data53In;
- input [15:0] Data54In;
- input [15:0] Data55In;
- input [15:0] Data56In;
- input [15:0] Data57In;
- input [15:0] Data58In;
- input [15:0] Data59In;
- input [15:0] Data60In;
- input [15:0] Data61In;
- input [15:0] Data62In;
- input [15:0] Data63In;
- output DataInIdle;
- output DataInRelease;
-
- input DataOutIdle;
- output DataOutEnable;
- output [2:0] DataOutPage;
- output [1:0] DataOutCount;
- output [15:0] Data0Out;
- output [15:0] Data1Out;
-
- //-------------------------------------------------------------------------
- // Phase1
- //-------------------------------------------------------------------------
- reg Phase1Enable;
- reg [2:0] Phase1Page;
- reg [2:0] Phase1Count;
- //reg Phase1EnableD;
- //reg [2:0] Phase1PageD;
- //reg [2:0] Phase1CountD;
- reg DataInBank;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase1Enable <= 1'b0;
- Phase1Page <= 3'd0;
- Phase1Count <= 3'd0;
- //Phase1EnableD <= 1'b0;
- //Phase1PageD <= 3'd0;
- //Phase1CountD <= 3'd0;
- DataInBank <= 1'b0;
- end else begin
- if(Phase1Enable == 1'b0) begin
- if(DataInEnable == 1'b1) begin
- Phase1Enable <= 1'b1;
- Phase1Page <= 3'd0;
- Phase1Count <= 3'd0;
- end
- end else begin
- if(Phase1Count == 3'd6) begin
- if(Phase1Page == 3'd7) begin
- Phase1Enable <= 1'b0;
- Phase1Page <= 3'd0;
- DataInBank <= ~DataInBank;
- end else begin
- Phase1Page <= Phase1Page + 3'd1;
- end
- Phase1Count <= 3'd0;
- end else begin
- Phase1Count <= Phase1Count + 3'd1;
- end // else: !if(Phase1Count == 3'd6)
- end // else: !if(Phase1Enable == 1'b0)
- //Phase1EnableD <= Phase1Enable;
- //Phase1PageD <= Phase1Page;
- //Phase1CountD <= Phase1Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign DataInSel = DataInBank;
- assign DataInIdle = Phase1Enable == 1'b0 & DataOutIdle == 1'b1;
- assign DataInRelease = Phase1Enable == 1'b1 & Phase1Count == 3'd6 & Phase1Page == 3'd7;
-
- wire signed [15:0] Phase1R0w;
- wire signed [15:0] Phase1R1w;
- wire signed [15:0] Phase1C0w;
- wire signed [15:0] Phase1C1w;
- wire signed [15:0] Phase1C2w;
- wire signed [15:0] Phase1C3w;
-
-/*
- always @(*) begin
- case(Phase1Page)
- 3'd0:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data00In;
- Phase1R1w <= Data04In;
- end
- 3'd1: begin
- Phase1R0w <= Data02In;
- Phase1R1w <= Data06In;
- end
- 3'd2: begin
- Phase1R0w <= Data01In;
- Phase1R1w <= Data07In;
- end
- 3'd3: begin
- Phase1R0w <= Data05In;
- Phase1R1w <= Data03In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd0
- 3'd1:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data08In;
- Phase1R1w <= Data12In;
- end
- 3'd1: begin
- Phase1R0w <= Data10In;
- Phase1R1w <= Data14In;
- end
- 3'd2: begin
- Phase1R0w <= Data09In;
- Phase1R1w <= Data15In;
- end
- 3'd3: begin
- Phase1R0w <= Data13In;
- Phase1R1w <= Data11In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd1
- 3'd2:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data16In;
- Phase1R1w <= Data20In;
- end
- 3'd1: begin
- Phase1R0w <= Data18In;
- Phase1R1w <= Data22In;
- end
- 3'd2: begin
- Phase1R0w <= Data17In;
- Phase1R1w <= Data23In;
- end
- 3'd3: begin
- Phase1R0w <= Data21In;
- Phase1R1w <= Data19In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd2
- 3'd3:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data24In;
- Phase1R1w <= Data28In;
- end
- 3'd1: begin
- Phase1R0w <= Data26In;
- Phase1R1w <= Data30In;
- end
- 3'd2: begin
- Phase1R0w <= Data25In;
- Phase1R1w <= Data31In;
- end
- 3'd3: begin
- Phase1R0w <= Data29In;
- Phase1R1w <= Data27In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd3
- 3'd4:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data32In;
- Phase1R1w <= Data36In;
- end
- 3'd1: begin
- Phase1R0w <= Data34In;
- Phase1R1w <= Data38In;
- end
- 3'd2: begin
- Phase1R0w <= Data33In;
- Phase1R1w <= Data39In;
- end
- 3'd3: begin
- Phase1R0w <= Data37In;
- Phase1R1w <= Data35In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd4
- 3'd5:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data40In;
- Phase1R1w <= Data44In;
- end
- 3'd1: begin
- Phase1R0w <= Data42In;
- Phase1R1w <= Data46In;
- end
- 3'd2: begin
- Phase1R0w <= Data41In;
- Phase1R1w <= Data47In;
- end
- 3'd3: begin
- Phase1R0w <= Data45In;
- Phase1R1w <= Data43In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd5
- 3'd6:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data48In;
- Phase1R1w <= Data52In;
- end
- 3'd1: begin
- Phase1R0w <= Data50In;
- Phase1R1w <= Data54In;
- end
- 3'd2: begin
- Phase1R0w <= Data49In;
- Phase1R1w <= Data55In;
- end
- 3'd3: begin
- Phase1R0w <= Data53In;
- Phase1R1w <= Data51In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd6
- 3'd7:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data56In;
- Phase1R1w <= Data60In;
- end
- 3'd1: begin
- Phase1R0w <= Data58In;
- Phase1R1w <= Data62In;
- end
- 3'd2: begin
- Phase1R0w <= Data57In;
- Phase1R1w <= Data63In;
- end
- 3'd3: begin
- Phase1R0w <= Data61In;
- Phase1R1w <= Data59In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd7
- endcase // case(Phase1Page)
- end // always @ (*)
-*/
- function [15:0] Phase1R0wSel;
- input [2:0] Phase1Page;
- input [2:0] Phase1Count;
- input [15:0] Data00In;
- input [15:0] Data01In;
- input [15:0] Data02In;
- input [15:0] Data03In;
- input [15:0] Data04In;
- input [15:0] Data05In;
- input [15:0] Data06In;
- input [15:0] Data07In;
- input [15:0] Data08In;
- input [15:0] Data09In;
- input [15:0] Data10In;
- input [15:0] Data11In;
- input [15:0] Data12In;
- input [15:0] Data13In;
- input [15:0] Data14In;
- input [15:0] Data15In;
- input [15:0] Data16In;
- input [15:0] Data17In;
- input [15:0] Data18In;
- input [15:0] Data19In;
- input [15:0] Data20In;
- input [15:0] Data21In;
- input [15:0] Data22In;
- input [15:0] Data23In;
- input [15:0] Data24In;
- input [15:0] Data25In;
- input [15:0] Data26In;
- input [15:0] Data27In;
- input [15:0] Data28In;
- input [15:0] Data29In;
- input [15:0] Data30In;
- input [15:0] Data31In;
- input [15:0] Data32In;
- input [15:0] Data33In;
- input [15:0] Data34In;
- input [15:0] Data35In;
- input [15:0] Data36In;
- input [15:0] Data37In;
- input [15:0] Data38In;
- input [15:0] Data39In;
- input [15:0] Data40In;
- input [15:0] Data41In;
- input [15:0] Data42In;
- input [15:0] Data43In;
- input [15:0] Data44In;
- input [15:0] Data45In;
- input [15:0] Data46In;
- input [15:0] Data47In;
- input [15:0] Data48In;
- input [15:0] Data49In;
- input [15:0] Data50In;
- input [15:0] Data51In;
- input [15:0] Data52In;
- input [15:0] Data53In;
- input [15:0] Data54In;
- input [15:0] Data55In;
- input [15:0] Data56In;
- input [15:0] Data57In;
- input [15:0] Data58In;
- input [15:0] Data59In;
- input [15:0] Data60In;
- input [15:0] Data61In;
- input [15:0] Data62In;
- input [15:0] Data63In;
- begin
- case(Phase1Page)
- 3'd0:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data00In;
- end
- 3'd1: begin
- Phase1R0wSel = Data02In;
- end
- 3'd2: begin
- Phase1R0wSel = Data01In;
- end
- 3'd3: begin
- Phase1R0wSel = Data05In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd0
- 3'd1:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data08In;
- end
- 3'd1: begin
- Phase1R0wSel = Data10In;
- end
- 3'd2: begin
- Phase1R0wSel = Data09In;
- end
- 3'd3: begin
- Phase1R0wSel = Data13In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd1
- 3'd2:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data16In;
- end
- 3'd1: begin
- Phase1R0wSel = Data18In;
- end
- 3'd2: begin
- Phase1R0wSel = Data17In;
- end
- 3'd3: begin
- Phase1R0wSel = Data21In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd2
- 3'd3:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data24In;
- end
- 3'd1: begin
- Phase1R0wSel = Data26In;
- end
- 3'd2: begin
- Phase1R0wSel = Data25In;
- end
- 3'd3: begin
- Phase1R0wSel = Data29In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd3
- 3'd4:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data32In;
- end
- 3'd1: begin
- Phase1R0wSel = Data34In;
- end
- 3'd2: begin
- Phase1R0wSel = Data33In;
- end
- 3'd3: begin
- Phase1R0wSel = Data37In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd4
- 3'd5:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data40In;
- end
- 3'd1: begin
- Phase1R0wSel = Data42In;
- end
- 3'd2: begin
- Phase1R0wSel = Data41In;
- end
- 3'd3: begin
- Phase1R0wSel = Data45In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd5
- 3'd6:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data48In;
- end
- 3'd1: begin
- Phase1R0wSel = Data50In;
- end
- 3'd2: begin
- Phase1R0wSel = Data49In;
- end
- 3'd3: begin
- Phase1R0wSel = Data53In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd6
- 3'd7:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data56In;
- end
- 3'd1: begin
- Phase1R0wSel = Data58In;
- end
- 3'd2: begin
- Phase1R0wSel = Data57In;
- end
- 3'd3: begin
- Phase1R0wSel = Data61In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd7
- endcase // case(Phase1Page)
- end
- endfunction
- function [15:0] Phase1R1wSel;
- input [2:0] Phase1Page;
- input [2:0] Phase1Count;
- input [15:0] Data00In;
- input [15:0] Data01In;
- input [15:0] Data02In;
- input [15:0] Data03In;
- input [15:0] Data04In;
- input [15:0] Data05In;
- input [15:0] Data06In;
- input [15:0] Data07In;
- input [15:0] Data08In;
- input [15:0] Data09In;
- input [15:0] Data10In;
- input [15:0] Data11In;
- input [15:0] Data12In;
- input [15:0] Data13In;
- input [15:0] Data14In;
- input [15:0] Data15In;
- input [15:0] Data16In;
- input [15:0] Data17In;
- input [15:0] Data18In;
- input [15:0] Data19In;
- input [15:0] Data20In;
- input [15:0] Data21In;
- input [15:0] Data22In;
- input [15:0] Data23In;
- input [15:0] Data24In;
- input [15:0] Data25In;
- input [15:0] Data26In;
- input [15:0] Data27In;
- input [15:0] Data28In;
- input [15:0] Data29In;
- input [15:0] Data30In;
- input [15:0] Data31In;
- input [15:0] Data32In;
- input [15:0] Data33In;
- input [15:0] Data34In;
- input [15:0] Data35In;
- input [15:0] Data36In;
- input [15:0] Data37In;
- input [15:0] Data38In;
- input [15:0] Data39In;
- input [15:0] Data40In;
- input [15:0] Data41In;
- input [15:0] Data42In;
- input [15:0] Data43In;
- input [15:0] Data44In;
- input [15:0] Data45In;
- input [15:0] Data46In;
- input [15:0] Data47In;
- input [15:0] Data48In;
- input [15:0] Data49In;
- input [15:0] Data50In;
- input [15:0] Data51In;
- input [15:0] Data52In;
- input [15:0] Data53In;
- input [15:0] Data54In;
- input [15:0] Data55In;
- input [15:0] Data56In;
- input [15:0] Data57In;
- input [15:0] Data58In;
- input [15:0] Data59In;
- input [15:0] Data60In;
- input [15:0] Data61In;
- input [15:0] Data62In;
- input [15:0] Data63In;
- begin
- case(Phase1Page)
- 3'd0:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data04In;
- end
- 3'd1: begin
- Phase1R1wSel = Data06In;
- end
- 3'd2: begin
- Phase1R1wSel = Data07In;
- end
- 3'd3: begin
- Phase1R1wSel = Data03In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd0
- 3'd1:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data12In;
- end
- 3'd1: begin
- Phase1R1wSel = Data14In;
- end
- 3'd2: begin
- Phase1R1wSel = Data15In;
- end
- 3'd3: begin
- Phase1R1wSel = Data11In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd1
- 3'd2:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data20In;
- end
- 3'd1: begin
- Phase1R1wSel = Data22In;
- end
- 3'd2: begin
- Phase1R1wSel = Data23In;
- end
- 3'd3: begin
- Phase1R1wSel = Data19In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd2
- 3'd3:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data28In;
- end
- 3'd1: begin
- Phase1R1wSel = Data30In;
- end
- 3'd2: begin
- Phase1R1wSel = Data31In;
- end
- 3'd3: begin
- Phase1R1wSel = Data27In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd3
- 3'd4:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data36In;
- end
- 3'd1: begin
- Phase1R1wSel = Data38In;
- end
- 3'd2: begin
- Phase1R1wSel = Data39In;
- end
- 3'd3: begin
- Phase1R1wSel = Data35In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd4
- 3'd5:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data44In;
- end
- 3'd1: begin
- Phase1R1wSel = Data46In;
- end
- 3'd2: begin
- Phase1R1wSel = Data47In;
- end
- 3'd3: begin
- Phase1R1wSel = Data43In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd5
- 3'd6:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data52In;
- end
- 3'd1: begin
- Phase1R1wSel = Data54In;
- end
- 3'd2: begin
- Phase1R1wSel = Data55In;
- end
- 3'd3: begin
- Phase1R1wSel = Data51In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd6
- 3'd7:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data60In;
- end
- 3'd1: begin
- Phase1R1wSel = Data62In;
- end
- 3'd2: begin
- Phase1R1wSel = Data63In;
- end
- 3'd3: begin
- Phase1R1wSel = Data59In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd7
- endcase // case(Phase1Page)
- end
- endfunction
-
- assign Phase1R0w = Phase1R0wSel(Phase1Page, Phase1Count,
- Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In,
- Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In,
- Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In,
- Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In,
- Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In,
- Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In,
- Data60In, Data61In, Data62In, Data63In
- );
- assign Phase1R1w = Phase1R1wSel(Phase1Page, Phase1Count,
- Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In,
- Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In,
- Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In,
- Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In,
- Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In,
- Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In,
- Data60In, Data61In, Data62In, Data63In
- );
-/*
- always @(*) begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C0w <= 16'd2896; // C4_16
- Phase1C1w <= 16'd2896; // C4_16
- Phase1C2w <= 16'd2896; // C4_16
- Phase1C3w <= 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C0w <= 16'd3784; // C2_16
- Phase1C1w <= 16'd1567; // C6_16
- Phase1C2w <= 16'd1567; // C6_16
- Phase1C3w <= 16'd3784; // C2_16
- end
- 3'd2: begin
- Phase1C0w <= 16'd4017; // C1_16
- Phase1C1w <= 16'd799; // C7_16
- Phase1C2w <= 16'd799; // C7_16
- Phase1C3w <= 16'd4017; // C1_16
- end
- 3'd3: begin
- Phase1C0w <= 16'd2276; // C5_16
- Phase1C1w <= 16'd3406; // C3_16
- Phase1C2w <= 16'd3406; // C3_16
- Phase1C3w <= 16'd2276; // C5_16
- end
- endcase // case(Phase1Count)
- end // always @ (*)
-*/
- function [15:0] Phase1C0wSel;
- input [2:0] Phase1Count;
- begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C0wSel = 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C0wSel = 16'd3784; // C2_16
- end
- 3'd2: begin
- Phase1C0wSel = 16'd4017; // C1_16
- end
- 3'd3: begin
- Phase1C0wSel = 16'd2276; // C5_16
- end
- endcase // case(Phase1Count)
- end
- endfunction
-
- function [15:0] Phase1C1wSel;
- input [2:0] Phase1Count;
- begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C1wSel = 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C1wSel = 16'd1567; // C6_16
- end
- 3'd2: begin
- Phase1C1wSel = 16'd799; // C7_16
- end
- 3'd3: begin
- Phase1C1wSel = 16'd3406; // C3_16
- end
- endcase // case(Phase1Count)
- end
- endfunction
-
- function [15:0] Phase1C2wSel;
- input [2:0] Phase1Count;
- begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C2wSel = 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C2wSel = 16'd1567; // C6_16
- end
- 3'd2: begin
- Phase1C2wSel = 16'd799; // C7_16
- end
- 3'd3: begin
- Phase1C2wSel = 16'd3406; // C3_16
- end
- endcase // case(Phase1Count)
- end
- endfunction
-
- function [15:0] Phase1C3wSel;
- input [2:0] Phase1Count;
- begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C3wSel = 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C3wSel = 16'd3784; // C2_16
- end
- 3'd2: begin
- Phase1C3wSel = 16'd4017; // C1_16
- end
- 3'd3: begin
- Phase1C3wSel = 16'd2276; // C5_16
- end
- endcase // case(Phase1Count)
- end
- endfunction
-
- assign Phase1C0w = Phase1C0wSel(Phase1Count);
- assign Phase1C1w = Phase1C1wSel(Phase1Count);
- assign Phase1C2w = Phase1C2wSel(Phase1Count);
- assign Phase1C3w = Phase1C3wSel(Phase1Count);
-
- reg signed [31:0] Phase1R0r;
- reg signed [31:0] Phase1R1r;
- reg signed [31:0] Phase1R2r;
- reg signed [31:0] Phase1R3r;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase1R0r <= 0;
- Phase1R1r <= 0;
- Phase1R2r <= 0;
- Phase1R3r <= 0;
- end else begin
- Phase1R0r <= Phase1R0w * Phase1C0w;
- Phase1R1r <= Phase1R1w * Phase1C1w;
- Phase1R2r <= Phase1R0w * Phase1C2w;
- Phase1R3r <= Phase1R1w * Phase1C3w;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //-------------------------------------------------------------------------
- // Phase2
- // R0: s0,s3,s7,s6
- // R1: s1,s2,s4,s5
- //-------------------------------------------------------------------------
- reg Phase2Enable;
- reg signed [2:0] Phase2Page;
- reg signed [2:0] Phase2Count;
- reg Phase2EnableD;
- reg signed [2:0] Phase2PageD;
- reg signed [2:0] Phase2CountD;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase2Enable <= 1'b0;
- Phase2Page <= 3'd0;
- Phase2Count <= 3'd0;
- Phase2EnableD <= 1'b0;
- Phase2PageD <= 3'd0;
- Phase2CountD <= 3'd0;
- end else begin
- Phase2Enable <= Phase1Enable;
- Phase2Page <= Phase1Page;
- Phase2Count <= Phase1Count;
- Phase2EnableD <= Phase2Enable;
- Phase2PageD <= Phase2Page;
- Phase2CountD <= Phase2Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- wire signed [31:0] Phase2A0w;
- wire signed [31:0] Phase2A1w;
-/*
- always @(*) begin
- Phase2A0w <= Phase1R0r + Phase1R1r;
- Phase2A1w <= Phase1R2r - Phase1R3r;
- end
-*/
- assign Phase2A0w = Phase1R0r + Phase1R1r;
- assign Phase2A1w = Phase1R2r - Phase1R3r;
-
- reg signed [31:0] Phase2Reg [0:7];
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase2Reg[0] <= 0;
- Phase2Reg[1] <= 0;
- Phase2Reg[2] <= 0;
- Phase2Reg[3] <= 0;
- Phase2Reg[4] <= 0;
- Phase2Reg[5] <= 0;
- Phase2Reg[6] <= 0;
- Phase2Reg[7] <= 0;
- end else begin
- case(Phase2Count)
- 3'd0: begin
- Phase2Reg[0] <= Phase2A0w;
- Phase2Reg[1] <= Phase2A1w;
- end
- 3'd1: begin
- Phase2Reg[3] <= Phase2A0w;
- Phase2Reg[2] <= Phase2A1w;
- end
- 3'd2: begin
- Phase2Reg[7] <= Phase2A0w;
- Phase2Reg[4] <= Phase2A1w;
- end
- 3'd3: begin
- Phase2Reg[6] <= Phase2A0w;
- Phase2Reg[5] <= Phase2A1w;
- end
- endcase // case(Phase2Count)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //-------------------------------------------------------------------------
- // Phase3
- // R0: t0,t1,t4,t7
- // R1: t3,t2,t5,t6
- //-------------------------------------------------------------------------
- reg Phase3Enable;
- reg [2:0] Phase3Page;
- reg [2:0] Phase3Count;
- reg Phase3EnableD;
- reg [2:0] Phase3PageD;
- reg [2:0] Phase3CountD;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase3Enable <= 1'b0;
- Phase3Page <= 3'd0;
- Phase3Count <= 3'd0;
- Phase3EnableD <= 1'b0;
- Phase3PageD <= 3'd0;
- Phase3CountD <= 3'd0;
- end else begin
- Phase3Enable <= Phase2EnableD;
- Phase3Page <= Phase2PageD;
- Phase3Count <= Phase2CountD;
- Phase3EnableD <= Phase3Enable;
- Phase3PageD <= Phase3Page;
- Phase3CountD <= Phase3Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //reg signed [31:0] Phase3R0w;
- //reg signed [31:0] Phase3R1w;
- wire signed [31:0] Phase3R0w;
- wire signed [31:0] Phase3R1w;
-
- assign Phase3R0w = (Phase3Count == 3'd0)?Phase2Reg[0]:
- (Phase3Count == 3'd1)?Phase2Reg[1]:
- (Phase3Count == 3'd2)?Phase2Reg[4]:
- (Phase3Count == 3'd3)?Phase2Reg[7]:
- 32'd0;
- assign Phase3R1w = (Phase3Count == 3'd0)?Phase2Reg[3]:
- (Phase3Count == 3'd1)?Phase2Reg[2]:
- (Phase3Count == 3'd2)?Phase2Reg[5]:
- (Phase3Count == 3'd3)?Phase2Reg[6]:
- 32'd0;
-
-
-
- wire signed [31:0] Phase3A0w;
- wire signed [31:0] Phase3A1w;
-/*
- always @(*) begin
- Phase3A0w <= Phase3R0w + Phase3R1w;
- Phase3A1w <= Phase3R0w - Phase3R1w;
- end
-*/
- assign Phase3A0w = Phase3R0w + Phase3R1w;
- assign Phase3A1w = Phase3R0w - Phase3R1w;
-
- reg signed [31:0] Phase3Reg [0:7];
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase3Reg[0] <= 0;
- Phase3Reg[1] <= 0;
- Phase3Reg[2] <= 0;
- Phase3Reg[3] <= 0;
- Phase3Reg[4] <= 0;
- Phase3Reg[5] <= 0;
- Phase3Reg[6] <= 0;
- Phase3Reg[7] <= 0;
- end else begin
- case(Phase3Count)
- 3'd0: begin
- Phase3Reg[0] <= Phase3A0w;
- Phase3Reg[3] <= Phase3A1w;
- end
- 3'd1: begin
- Phase3Reg[1] <= Phase3A0w;
- Phase3Reg[2] <= Phase3A1w;
- end
- 3'd2: begin
- Phase3Reg[4] <= Phase3A0w;
- Phase3Reg[5] <= Phase3A1w;
- end
- 3'd3: begin
- Phase3Reg[7] <= Phase3A0w;
- Phase3Reg[6] <= Phase3A1w;
- end
- endcase // case(Phase3Count)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //-------------------------------------------------------------------------
- // Phase4
- // R0: s6
- // R1: s5
- //-------------------------------------------------------------------------
- reg Phase4Enable;
- reg [2:0] Phase4Page;
- reg [2:0] Phase4Count;
- reg Phase4EnableD;
- reg [2:0] Phase4PageD;
- reg [2:0] Phase4CountD;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase4Enable <= 1'b0;
- Phase4Page <= 3'd0;
- Phase4Count <= 3'd0;
- Phase4EnableD <= 1'b0;
- Phase4PageD <= 3'd0;
- Phase4CountD <= 3'd0;
- end else begin
- Phase4Enable <= Phase3EnableD;
- Phase4Page <= Phase3PageD;
- Phase4Count <= Phase3CountD;
- Phase4EnableD <= Phase4Enable;
- Phase4PageD <= Phase4Page;
- Phase4CountD <= Phase4Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- reg signed [42:0] Phase4R0r;
- reg signed [42:0] Phase4R1r;
-
- wire signed [8:0] C_181;
- assign C_181 = 9'h0B5;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase4R0r <= 0;
- Phase4R1r <= 0;
- end else begin
- case(Phase4Count)
- 3'd2: begin
- Phase4R0r <= (Phase3Reg[6] + Phase3Reg[5]) * C_181;
- Phase4R1r <= (Phase3Reg[6] - Phase3Reg[5]) * C_181;
- end
- endcase // case(Phase4Count)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //-------------------------------------------------------------------------
- // Phase5
- // R0: B0,B1,B2,B3
- // R1: B7,B6,B5,B4
- //-------------------------------------------------------------------------
- reg Phase5Enable;
- reg [2:0] Phase5Page;
- reg [2:0] Phase5Count;
- reg Phase5EnableD;
- reg [2:0] Phase5PageD;
- reg [2:0] Phase5CountD;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase5Enable <= 1'b0;
- Phase5Page <= 3'd0;
- Phase5Count <= 3'd0;
- Phase5EnableD <= 1'b0;
- Phase5PageD <= 3'd0;
- Phase5CountD <= 3'd0;
- end else begin
- Phase5Enable <= Phase4EnableD;
- Phase5Page <= Phase4PageD;
- Phase5Count <= Phase4CountD;
- Phase5EnableD <= Phase5Enable;
- Phase5PageD <= Phase5Page;
- Phase5CountD <= Phase5Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- wire signed [31:0] Phase5R0w;
- wire signed [31:0] Phase5R1w;
- assign Phase5R0w = (Phase5Count == 3'd0)?Phase3Reg[0]:
- (Phase5Count == 3'd1)?Phase3Reg[1]:
- (Phase5Count == 3'd2)?Phase3Reg[2]:
- (Phase5Count == 3'd3)?Phase3Reg[3]:
- 32'd0;
- assign Phase5R1w = (Phase5Count == 3'd0)?Phase3Reg[7]:
- (Phase5Count == 3'd1)?Phase4R0r >> 8:
- (Phase5Count == 3'd2)?Phase4R1r >> 8:
- (Phase5Count == 3'd3)?Phase3Reg[4]:
- 32'd0;
-
-
- reg signed [31:0] Phase5R0r;
- reg signed [31:0] Phase5R1r;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase5R0r <= 0;
- Phase5R1r <= 0;
- end else begin
- Phase5R0r <= Phase5R0w + Phase5R1w;
- Phase5R1r <= Phase5R0w - Phase5R1w;
- end
- end
-
- assign DataOutEnable = Phase5EnableD == 1'b1 & Phase5CountD[2] == 1'b0;
- assign DataOutPage = Phase5PageD;
- assign DataOutCount = Phase5CountD[1:0];
-
- assign Data0Out = Phase5R0r[26:11];
- assign Data1Out = Phase5R1r[26:11];
-
-endmodule // jpeg_idctx
Index: trunk/src/jpeg_idcty.v
===================================================================
--- trunk/src/jpeg_idcty.v (revision 5)
+++ trunk/src/jpeg_idcty.v (nonexistent)
@@ -1,1240 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_idcty.v
-// Module Name : jpeg_idcty
-// Description : iDCT-Y
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_idcty
- (
- rst,
- clk,
-
- DataInEnable,
- DataInBank,
- DataInSel,
- Data00In,
- Data01In,
- Data02In,
- Data03In,
- Data04In,
- Data05In,
- Data06In,
- Data07In,
- Data08In,
- Data09In,
- Data10In,
- Data11In,
- Data12In,
- Data13In,
- Data14In,
- Data15In,
- Data16In,
- Data17In,
- Data18In,
- Data19In,
- Data20In,
- Data21In,
- Data22In,
- Data23In,
- Data24In,
- Data25In,
- Data26In,
- Data27In,
- Data28In,
- Data29In,
- Data30In,
- Data31In,
- Data32In,
- Data33In,
- Data34In,
- Data35In,
- Data36In,
- Data37In,
- Data38In,
- Data39In,
- Data40In,
- Data41In,
- Data42In,
- Data43In,
- Data44In,
- Data45In,
- Data46In,
- Data47In,
- Data48In,
- Data49In,
- Data50In,
- Data51In,
- Data52In,
- Data53In,
- Data54In,
- Data55In,
- Data56In,
- Data57In,
- Data58In,
- Data59In,
- Data60In,
- Data61In,
- Data62In,
- Data63In,
- DataInIdle,
- DataInRelease,
-
- DataOutEnable,
- DataOutPage,
- DataOutCount,
- Data0Out,
- Data1Out
- );
-
- input clk;
- input rst;
-
- input DataInEnable;
- output DataInBank;
- output DataInSel;
- input [15:0] Data00In;
- input [15:0] Data01In;
- input [15:0] Data02In;
- input [15:0] Data03In;
- input [15:0] Data04In;
- input [15:0] Data05In;
- input [15:0] Data06In;
- input [15:0] Data07In;
- input [15:0] Data08In;
- input [15:0] Data09In;
- input [15:0] Data10In;
- input [15:0] Data11In;
- input [15:0] Data12In;
- input [15:0] Data13In;
- input [15:0] Data14In;
- input [15:0] Data15In;
- input [15:0] Data16In;
- input [15:0] Data17In;
- input [15:0] Data18In;
- input [15:0] Data19In;
- input [15:0] Data20In;
- input [15:0] Data21In;
- input [15:0] Data22In;
- input [15:0] Data23In;
- input [15:0] Data24In;
- input [15:0] Data25In;
- input [15:0] Data26In;
- input [15:0] Data27In;
- input [15:0] Data28In;
- input [15:0] Data29In;
- input [15:0] Data30In;
- input [15:0] Data31In;
- input [15:0] Data32In;
- input [15:0] Data33In;
- input [15:0] Data34In;
- input [15:0] Data35In;
- input [15:0] Data36In;
- input [15:0] Data37In;
- input [15:0] Data38In;
- input [15:0] Data39In;
- input [15:0] Data40In;
- input [15:0] Data41In;
- input [15:0] Data42In;
- input [15:0] Data43In;
- input [15:0] Data44In;
- input [15:0] Data45In;
- input [15:0] Data46In;
- input [15:0] Data47In;
- input [15:0] Data48In;
- input [15:0] Data49In;
- input [15:0] Data50In;
- input [15:0] Data51In;
- input [15:0] Data52In;
- input [15:0] Data53In;
- input [15:0] Data54In;
- input [15:0] Data55In;
- input [15:0] Data56In;
- input [15:0] Data57In;
- input [15:0] Data58In;
- input [15:0] Data59In;
- input [15:0] Data60In;
- input [15:0] Data61In;
- input [15:0] Data62In;
- input [15:0] Data63In;
- output DataInIdle;
- output DataInRelease;
-
- output DataOutEnable;
- output [2:0] DataOutPage;
- output [1:0] DataOutCount;
- output [8:0] Data0Out;
- output [8:0] Data1Out;
-
- //-------------------------------------------------------------------------
- // Phase1
- //-------------------------------------------------------------------------
- reg Phase1Enable;
- reg [2:0] Phase1Page;
- reg [2:0] Phase1Count;
- //reg Phase1EnableD;
- //reg [2:0] Phase1PageD;
- //reg [2:0] Phase1CountD;
- reg DataInBank;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase1Enable <= 1'b0;
- Phase1Page <= 3'd0;
- Phase1Count <= 3'd0;
- //Phase1EnableD <= 1'b0;
- //Phase1PageD <= 3'd0;
- //Phase1CountD <= 3'd0;
- DataInBank <= 1'b0;
- end else begin
- if(Phase1Enable == 1'b0) begin
- if(DataInEnable == 1'b1) begin
- Phase1Enable <= 1'b1;
- Phase1Page <= 3'd0;
- Phase1Count <= 3'd0;
- end
- end else begin
- if(Phase1Count == 3'd6) begin
- if(Phase1Page == 3'd7) begin
- Phase1Enable <= 1'b0;
- Phase1Page <= 3'd0;
- DataInBank <= ~DataInBank;
- end else begin
- Phase1Page <= Phase1Page + 3'd1;
- end
- Phase1Count <= 3'd0;
- end else begin
- Phase1Count <= Phase1Count + 3'd1;
- end // else: !if(Phase1Count == 3'd6)
- end // else: !if(Phase1Enable == 1'b0)
- //Phase1EnableD <= Phase1Enable;
- //Phase1PageD <= Phase1Page;
- //Phase1CountD <= Phase1Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign DataInSel = DataInBank;
- assign DataInIdle = Phase1Enable == 1'b0;
- assign DataInRelease = Phase1Enable == 1'b1 & Phase1Count == 3'd6 & Phase1Page == 3'd7;
-
- wire signed [15:0] Phase1R0w;
- wire signed [15:0] Phase1R1w;
- wire signed [15:0] Phase1C0w;
- wire signed [15:0] Phase1C1w;
- wire signed [15:0] Phase1C2w;
- wire signed [15:0] Phase1C3w;
-/*
- always @(*) begin
- case(Phase1Page)
- 3'd0:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data00In;
- Phase1R1w <= Data04In;
- end
- 3'd1: begin
- Phase1R0w <= Data02In;
- Phase1R1w <= Data06In;
- end
- 3'd2: begin
- Phase1R0w <= Data01In;
- Phase1R1w <= Data07In;
- end
- 3'd3: begin
- Phase1R0w <= Data05In;
- Phase1R1w <= Data03In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd0
- 3'd1:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data08In;
- Phase1R1w <= Data12In;
- end
- 3'd1: begin
- Phase1R0w <= Data10In;
- Phase1R1w <= Data14In;
- end
- 3'd2: begin
- Phase1R0w <= Data09In;
- Phase1R1w <= Data15In;
- end
- 3'd3: begin
- Phase1R0w <= Data13In;
- Phase1R1w <= Data11In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd1
- 3'd2:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data16In;
- Phase1R1w <= Data20In;
- end
- 3'd1: begin
- Phase1R0w <= Data18In;
- Phase1R1w <= Data22In;
- end
- 3'd2: begin
- Phase1R0w <= Data17In;
- Phase1R1w <= Data23In;
- end
- 3'd3: begin
- Phase1R0w <= Data21In;
- Phase1R1w <= Data19In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd2
- 3'd3:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data24In;
- Phase1R1w <= Data28In;
- end
- 3'd1: begin
- Phase1R0w <= Data26In;
- Phase1R1w <= Data30In;
- end
- 3'd2: begin
- Phase1R0w <= Data25In;
- Phase1R1w <= Data31In;
- end
- 3'd3: begin
- Phase1R0w <= Data29In;
- Phase1R1w <= Data27In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd3
- 3'd4:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data32In;
- Phase1R1w <= Data36In;
- end
- 3'd1: begin
- Phase1R0w <= Data34In;
- Phase1R1w <= Data38In;
- end
- 3'd2: begin
- Phase1R0w <= Data33In;
- Phase1R1w <= Data39In;
- end
- 3'd3: begin
- Phase1R0w <= Data37In;
- Phase1R1w <= Data35In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd4
- 3'd5:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data40In;
- Phase1R1w <= Data44In;
- end
- 3'd1: begin
- Phase1R0w <= Data42In;
- Phase1R1w <= Data46In;
- end
- 3'd2: begin
- Phase1R0w <= Data41In;
- Phase1R1w <= Data47In;
- end
- 3'd3: begin
- Phase1R0w <= Data45In;
- Phase1R1w <= Data43In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd5
- 3'd6:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data48In;
- Phase1R1w <= Data52In;
- end
- 3'd1: begin
- Phase1R0w <= Data50In;
- Phase1R1w <= Data54In;
- end
- 3'd2: begin
- Phase1R0w <= Data49In;
- Phase1R1w <= Data55In;
- end
- 3'd3: begin
- Phase1R0w <= Data53In;
- Phase1R1w <= Data51In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd6
- 3'd7:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0w <= Data56In;
- Phase1R1w <= Data60In;
- end
- 3'd1: begin
- Phase1R0w <= Data58In;
- Phase1R1w <= Data62In;
- end
- 3'd2: begin
- Phase1R0w <= Data57In;
- Phase1R1w <= Data63In;
- end
- 3'd3: begin
- Phase1R0w <= Data61In;
- Phase1R1w <= Data59In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd7
- endcase // case(Phase1Page)
- end // always @ (*)
-*/
- function [15:0] Phase1R0wSel;
- input [2:0] Phase1Page;
- input [2:0] Phase1Count;
- input [15:0] Data00In;
- input [15:0] Data01In;
- input [15:0] Data02In;
- input [15:0] Data03In;
- input [15:0] Data04In;
- input [15:0] Data05In;
- input [15:0] Data06In;
- input [15:0] Data07In;
- input [15:0] Data08In;
- input [15:0] Data09In;
- input [15:0] Data10In;
- input [15:0] Data11In;
- input [15:0] Data12In;
- input [15:0] Data13In;
- input [15:0] Data14In;
- input [15:0] Data15In;
- input [15:0] Data16In;
- input [15:0] Data17In;
- input [15:0] Data18In;
- input [15:0] Data19In;
- input [15:0] Data20In;
- input [15:0] Data21In;
- input [15:0] Data22In;
- input [15:0] Data23In;
- input [15:0] Data24In;
- input [15:0] Data25In;
- input [15:0] Data26In;
- input [15:0] Data27In;
- input [15:0] Data28In;
- input [15:0] Data29In;
- input [15:0] Data30In;
- input [15:0] Data31In;
- input [15:0] Data32In;
- input [15:0] Data33In;
- input [15:0] Data34In;
- input [15:0] Data35In;
- input [15:0] Data36In;
- input [15:0] Data37In;
- input [15:0] Data38In;
- input [15:0] Data39In;
- input [15:0] Data40In;
- input [15:0] Data41In;
- input [15:0] Data42In;
- input [15:0] Data43In;
- input [15:0] Data44In;
- input [15:0] Data45In;
- input [15:0] Data46In;
- input [15:0] Data47In;
- input [15:0] Data48In;
- input [15:0] Data49In;
- input [15:0] Data50In;
- input [15:0] Data51In;
- input [15:0] Data52In;
- input [15:0] Data53In;
- input [15:0] Data54In;
- input [15:0] Data55In;
- input [15:0] Data56In;
- input [15:0] Data57In;
- input [15:0] Data58In;
- input [15:0] Data59In;
- input [15:0] Data60In;
- input [15:0] Data61In;
- input [15:0] Data62In;
- input [15:0] Data63In;
- begin
- case(Phase1Page)
- 3'd0:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data00In;
- end
- 3'd1: begin
- Phase1R0wSel = Data02In;
- end
- 3'd2: begin
- Phase1R0wSel = Data01In;
- end
- 3'd3: begin
- Phase1R0wSel = Data05In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd0
- 3'd1:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data08In;
- end
- 3'd1: begin
- Phase1R0wSel = Data10In;
- end
- 3'd2: begin
- Phase1R0wSel = Data09In;
- end
- 3'd3: begin
- Phase1R0wSel = Data13In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd1
- 3'd2:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data16In;
- end
- 3'd1: begin
- Phase1R0wSel = Data18In;
- end
- 3'd2: begin
- Phase1R0wSel = Data17In;
- end
- 3'd3: begin
- Phase1R0wSel = Data21In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd2
- 3'd3:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data24In;
- end
- 3'd1: begin
- Phase1R0wSel = Data26In;
- end
- 3'd2: begin
- Phase1R0wSel = Data25In;
- end
- 3'd3: begin
- Phase1R0wSel = Data29In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd3
- 3'd4:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data32In;
- end
- 3'd1: begin
- Phase1R0wSel = Data34In;
- end
- 3'd2: begin
- Phase1R0wSel = Data33In;
- end
- 3'd3: begin
- Phase1R0wSel = Data37In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd4
- 3'd5:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data40In;
- end
- 3'd1: begin
- Phase1R0wSel = Data42In;
- end
- 3'd2: begin
- Phase1R0wSel = Data41In;
- end
- 3'd3: begin
- Phase1R0wSel = Data45In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd5
- 3'd6:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data48In;
- end
- 3'd1: begin
- Phase1R0wSel = Data50In;
- end
- 3'd2: begin
- Phase1R0wSel = Data49In;
- end
- 3'd3: begin
- Phase1R0wSel = Data53In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd6
- 3'd7:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R0wSel = Data56In;
- end
- 3'd1: begin
- Phase1R0wSel = Data58In;
- end
- 3'd2: begin
- Phase1R0wSel = Data57In;
- end
- 3'd3: begin
- Phase1R0wSel = Data61In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd7
- endcase // case(Phase1Page)
- end
- endfunction
- function [15:0] Phase1R1wSel;
- input [2:0] Phase1Page;
- input [2:0] Phase1Count;
- input [15:0] Data00In;
- input [15:0] Data01In;
- input [15:0] Data02In;
- input [15:0] Data03In;
- input [15:0] Data04In;
- input [15:0] Data05In;
- input [15:0] Data06In;
- input [15:0] Data07In;
- input [15:0] Data08In;
- input [15:0] Data09In;
- input [15:0] Data10In;
- input [15:0] Data11In;
- input [15:0] Data12In;
- input [15:0] Data13In;
- input [15:0] Data14In;
- input [15:0] Data15In;
- input [15:0] Data16In;
- input [15:0] Data17In;
- input [15:0] Data18In;
- input [15:0] Data19In;
- input [15:0] Data20In;
- input [15:0] Data21In;
- input [15:0] Data22In;
- input [15:0] Data23In;
- input [15:0] Data24In;
- input [15:0] Data25In;
- input [15:0] Data26In;
- input [15:0] Data27In;
- input [15:0] Data28In;
- input [15:0] Data29In;
- input [15:0] Data30In;
- input [15:0] Data31In;
- input [15:0] Data32In;
- input [15:0] Data33In;
- input [15:0] Data34In;
- input [15:0] Data35In;
- input [15:0] Data36In;
- input [15:0] Data37In;
- input [15:0] Data38In;
- input [15:0] Data39In;
- input [15:0] Data40In;
- input [15:0] Data41In;
- input [15:0] Data42In;
- input [15:0] Data43In;
- input [15:0] Data44In;
- input [15:0] Data45In;
- input [15:0] Data46In;
- input [15:0] Data47In;
- input [15:0] Data48In;
- input [15:0] Data49In;
- input [15:0] Data50In;
- input [15:0] Data51In;
- input [15:0] Data52In;
- input [15:0] Data53In;
- input [15:0] Data54In;
- input [15:0] Data55In;
- input [15:0] Data56In;
- input [15:0] Data57In;
- input [15:0] Data58In;
- input [15:0] Data59In;
- input [15:0] Data60In;
- input [15:0] Data61In;
- input [15:0] Data62In;
- input [15:0] Data63In;
- begin
- case(Phase1Page)
- 3'd0:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data04In;
- end
- 3'd1: begin
- Phase1R1wSel = Data06In;
- end
- 3'd2: begin
- Phase1R1wSel = Data07In;
- end
- 3'd3: begin
- Phase1R1wSel = Data03In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd0
- 3'd1:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data12In;
- end
- 3'd1: begin
- Phase1R1wSel = Data14In;
- end
- 3'd2: begin
- Phase1R1wSel = Data15In;
- end
- 3'd3: begin
- Phase1R1wSel = Data11In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd1
- 3'd2:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data20In;
- end
- 3'd1: begin
- Phase1R1wSel = Data22In;
- end
- 3'd2: begin
- Phase1R1wSel = Data23In;
- end
- 3'd3: begin
- Phase1R1wSel = Data19In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd2
- 3'd3:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data28In;
- end
- 3'd1: begin
- Phase1R1wSel = Data30In;
- end
- 3'd2: begin
- Phase1R1wSel = Data31In;
- end
- 3'd3: begin
- Phase1R1wSel = Data27In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd3
- 3'd4:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data36In;
- end
- 3'd1: begin
- Phase1R1wSel = Data38In;
- end
- 3'd2: begin
- Phase1R1wSel = Data39In;
- end
- 3'd3: begin
- Phase1R1wSel = Data35In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd4
- 3'd5:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data44In;
- end
- 3'd1: begin
- Phase1R1wSel = Data46In;
- end
- 3'd2: begin
- Phase1R1wSel = Data47In;
- end
- 3'd3: begin
- Phase1R1wSel = Data43In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd5
- 3'd6:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data52In;
- end
- 3'd1: begin
- Phase1R1wSel = Data54In;
- end
- 3'd2: begin
- Phase1R1wSel = Data55In;
- end
- 3'd3: begin
- Phase1R1wSel = Data51In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd6
- 3'd7:begin
- case(Phase1Count)
- 3'd0: begin
- Phase1R1wSel = Data60In;
- end
- 3'd1: begin
- Phase1R1wSel = Data62In;
- end
- 3'd2: begin
- Phase1R1wSel = Data63In;
- end
- 3'd3: begin
- Phase1R1wSel = Data59In;
- end
- endcase // case(Phase1Count)
- end // case: 3'd7
- endcase // case(Phase1Page)
- end
- endfunction
-
- assign Phase1R0w = Phase1R0wSel(Phase1Page, Phase1Count,
- Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In,
- Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In,
- Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In,
- Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In,
- Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In,
- Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In,
- Data60In, Data61In, Data62In, Data63In
- );
- assign Phase1R1w = Phase1R1wSel(Phase1Page, Phase1Count,
- Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In,
- Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In,
- Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In,
- Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In,
- Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In,
- Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In,
- Data60In, Data61In, Data62In, Data63In
- );
-/*
- always @(*) begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C0w <= 16'd2896; // C4_16
- Phase1C1w <= 16'd2896; // C4_16
- Phase1C2w <= 16'd2896; // C4_16
- Phase1C3w <= 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C0w <= 16'd3784; // C2_16
- Phase1C1w <= 16'd1567; // C6_16
- Phase1C2w <= 16'd1567; // C6_16
- Phase1C3w <= 16'd3784; // C2_16
- end
- 3'd2: begin
- Phase1C0w <= 16'd4017; // C1_16
- Phase1C1w <= 16'd799; // C7_16
- Phase1C2w <= 16'd799; // C7_16
- Phase1C3w <= 16'd4017; // C1_16
- end
- 3'd3: begin
- Phase1C0w <= 16'd2276; // C5_16
- Phase1C1w <= 16'd3406; // C3_16
- Phase1C2w <= 16'd3406; // C3_16
- Phase1C3w <= 16'd2276; // C5_16
- end
-
- endcase // case(Phase1Count)
-
- end // always @ (*)
-*/
-
- function [15:0] Phase1C0wSel;
- input [2:0] Phase1Count;
- begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C0wSel = 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C0wSel = 16'd3784; // C2_16
- end
- 3'd2: begin
- Phase1C0wSel = 16'd4017; // C1_16
- end
- 3'd3: begin
- Phase1C0wSel = 16'd2276; // C5_16
- end
- endcase // case(Phase1Count)
- end
- endfunction
-
- function [15:0] Phase1C1wSel;
- input [2:0] Phase1Count;
- begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C1wSel = 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C1wSel = 16'd1567; // C6_16
- end
- 3'd2: begin
- Phase1C1wSel = 16'd799; // C7_16
- end
- 3'd3: begin
- Phase1C1wSel = 16'd3406; // C3_16
- end
- endcase // case(Phase1Count)
- end
- endfunction
-
- function [15:0] Phase1C2wSel;
- input [2:0] Phase1Count;
- begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C2wSel = 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C2wSel = 16'd1567; // C6_16
- end
- 3'd2: begin
- Phase1C2wSel = 16'd799; // C7_16
- end
- 3'd3: begin
- Phase1C2wSel = 16'd3406; // C3_16
- end
- endcase // case(Phase1Count)
- end
- endfunction
-
- function [15:0] Phase1C3wSel;
- input [2:0] Phase1Count;
- begin
- case(Phase1Count)
- 3'd0: begin
- Phase1C3wSel = 16'd2896; // C4_16
- end
- 3'd1: begin
- Phase1C3wSel = 16'd3784; // C2_16
- end
- 3'd2: begin
- Phase1C3wSel = 16'd4017; // C1_16
- end
- 3'd3: begin
- Phase1C3wSel = 16'd2276; // C5_16
- end
- endcase // case(Phase1Count)
- end
- endfunction
-
- assign Phase1C0w = Phase1C0wSel(Phase1Count);
- assign Phase1C1w = Phase1C1wSel(Phase1Count);
- assign Phase1C2w = Phase1C2wSel(Phase1Count);
- assign Phase1C3w = Phase1C3wSel(Phase1Count);
-
- reg signed [31:0] Phase1R0r;
- reg signed [31:0] Phase1R1r;
- reg signed [31:0] Phase1R2r;
- reg signed [31:0] Phase1R3r;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase1R0r <= 0;
- Phase1R1r <= 0;
- Phase1R2r <= 0;
- Phase1R3r <= 0;
- end else begin
- Phase1R0r <= Phase1R0w * Phase1C0w;
- Phase1R1r <= Phase1R1w * Phase1C1w;
- Phase1R2r <= Phase1R0w * Phase1C2w;
- Phase1R3r <= Phase1R1w * Phase1C3w;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //-------------------------------------------------------------------------
- // Phase2
- // R0: s0,s3,s7,s6
- // R1: s1,s2,s4,s5
- //-------------------------------------------------------------------------
- reg Phase2Enable;
- reg [2:0] Phase2Page;
- reg [2:0] Phase2Count;
- reg Phase2EnableD;
- reg [2:0] Phase2PageD;
- reg [2:0] Phase2CountD;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase2Enable <= 1'b0;
- Phase2Page <= 3'd0;
- Phase2Count <= 3'd0;
- Phase2EnableD <= 1'b0;
- Phase2PageD <= 3'd0;
- Phase2CountD <= 3'd0;
- end else begin
- Phase2Enable <= Phase1Enable;
- Phase2Page <= Phase1Page;
- Phase2Count <= Phase1Count;
- Phase2EnableD <= Phase2Enable;
- Phase2PageD <= Phase2Page;
- Phase2CountD <= Phase2Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- wire signed [31:0] Phase2A0w;
- wire signed [31:0] Phase2A1w;
-/*
- always @(*) begin
- Phase2A0w <= Phase1R0r + Phase1R1r;
- Phase2A1w <= Phase1R2r - Phase1R3r;
- end
-*/
-
- assign Phase2A0w = Phase1R0r + Phase1R1r;
- assign Phase2A1w = Phase1R2r - Phase1R3r;
-
- reg signed [31:0] Phase2Reg [0:7];
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase2Reg[0] <= 0;
- Phase2Reg[1] <= 0;
- Phase2Reg[2] <= 0;
- Phase2Reg[3] <= 0;
- Phase2Reg[4] <= 0;
- Phase2Reg[5] <= 0;
- Phase2Reg[6] <= 0;
- Phase2Reg[7] <= 0;
- end else begin
- case(Phase2Count)
- 3'd0: begin
- Phase2Reg[0] <= Phase2A0w;
- Phase2Reg[1] <= Phase2A1w;
- end
- 3'd1: begin
- Phase2Reg[3] <= Phase2A0w;
- Phase2Reg[2] <= Phase2A1w;
- end
- 3'd2: begin
- Phase2Reg[7] <= Phase2A0w;
- Phase2Reg[4] <= Phase2A1w;
- end
- 3'd3: begin
- Phase2Reg[6] <= Phase2A0w;
- Phase2Reg[5] <= Phase2A1w;
- end
- endcase // case(Phase2Count)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //-------------------------------------------------------------------------
- // Phase3
- // R0: t0,t1,t4,t7
- // R1: t3,t2,t5,t6
- //-------------------------------------------------------------------------
- reg Phase3Enable;
- reg [2:0] Phase3Page;
- reg [2:0] Phase3Count;
- reg Phase3EnableD;
- reg [2:0] Phase3PageD;
- reg [2:0] Phase3CountD;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase3Enable <= 1'b0;
- Phase3Page <= 3'd0;
- Phase3Count <= 3'd0;
- Phase3EnableD <= 1'b0;
- Phase3PageD <= 3'd0;
- Phase3CountD <= 3'd0;
- end else begin
- Phase3Enable <= Phase2EnableD;
- Phase3Page <= Phase2PageD;
- Phase3Count <= Phase2CountD;
- Phase3EnableD <= Phase3Enable;
- Phase3PageD <= Phase3Page;
- Phase3CountD <= Phase3Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- wire signed [31:0] Phase3R0w;
- wire signed [31:0] Phase3R1w;
-
- assign Phase3R0w = (Phase3Count == 3'd0)?Phase2Reg[0]:
- (Phase3Count == 3'd1)?Phase2Reg[1]:
- (Phase3Count == 3'd2)?Phase2Reg[4]:
- (Phase3Count == 3'd3)?Phase2Reg[7]:
- 32'd0;
- assign Phase3R1w = (Phase3Count == 3'd0)?Phase2Reg[3]:
- (Phase3Count == 3'd1)?Phase2Reg[2]:
- (Phase3Count == 3'd2)?Phase2Reg[5]:
- (Phase3Count == 3'd3)?Phase2Reg[6]:
- 32'd0;
-
- wire signed [31:0] Phase3A0w;
- wire signed [31:0] Phase3A1w;
-/*
- always @(*) begin
- Phase3A0w <= Phase3R0w + Phase3R1w;
- Phase3A1w <= Phase3R0w - Phase3R1w;
- end
-*/
-
- assign Phase3A0w = Phase3R0w + Phase3R1w;
- assign Phase3A1w = Phase3R0w - Phase3R1w;
-
- reg signed [31:0] Phase3Reg [0:7];
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase3Reg[0] <= 0;
- Phase3Reg[1] <= 0;
- Phase3Reg[2] <= 0;
- Phase3Reg[3] <= 0;
- Phase3Reg[4] <= 0;
- Phase3Reg[5] <= 0;
- Phase3Reg[6] <= 0;
- Phase3Reg[7] <= 0;
- end else begin
- case(Phase3Count)
- 3'd0: begin
- Phase3Reg[0] <= Phase3A0w;
- Phase3Reg[3] <= Phase3A1w;
- end
- 3'd1: begin
- Phase3Reg[1] <= Phase3A0w;
- Phase3Reg[2] <= Phase3A1w;
- end
- 3'd2: begin
- Phase3Reg[4] <= Phase3A0w;
- Phase3Reg[5] <= Phase3A1w;
- end
- 3'd3: begin
- Phase3Reg[7] <= Phase3A0w;
- Phase3Reg[6] <= Phase3A1w;
- end
- endcase // case(Phase3Count)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //-------------------------------------------------------------------------
- // Phase4
- // R0: s5
- // R1: s6
- //-------------------------------------------------------------------------
- reg Phase4Enable;
- reg [2:0] Phase4Page;
- reg [2:0] Phase4Count;
- reg Phase4EnableD;
- reg [2:0] Phase4PageD;
- reg [2:0] Phase4CountD;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase4Enable <= 1'b0;
- Phase4Page <= 3'd0;
- Phase4Count <= 3'd0;
- Phase4EnableD <= 1'b0;
- Phase4PageD <= 3'd0;
- Phase4CountD <= 3'd0;
- end else begin
- Phase4Enable <= Phase3EnableD;
- Phase4Page <= Phase3PageD;
- Phase4Count <= Phase3CountD;
- Phase4EnableD <= Phase4Enable;
- Phase4PageD <= Phase4Page;
- Phase4CountD <= Phase4Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- reg signed [42:0] Phase4R0r;
- reg signed [42:0] Phase4R1r;
-
- wire signed [8:0] C_181;
- assign C_181 = 9'h0B5;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase4R0r <= 0;
- Phase4R1r <= 0;
- end else begin
- case(Phase4Count)
- 3'd2: begin
- Phase4R0r <= (Phase3Reg[6] + Phase3Reg[5]) * C_181;
- Phase4R1r <= (Phase3Reg[6] - Phase3Reg[5]) * C_181;
- end
- endcase // case(Phase4Count)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //-------------------------------------------------------------------------
- // Phase5
- // R0: B0,B1,B2,B3
- // R1: B7,B6,B5,B4
- //-------------------------------------------------------------------------
- reg Phase5Enable;
- reg [2:0] Phase5Page;
- reg [2:0] Phase5Count;
- reg Phase5EnableD;
- reg [2:0] Phase5PageD;
- reg [2:0] Phase5CountD;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase5Enable <= 1'b0;
- Phase5Page <= 3'd0;
- Phase5Count <= 3'd0;
- Phase5EnableD <= 1'b0;
- Phase5PageD <= 3'd0;
- Phase5CountD <= 3'd0;
- end else begin
- Phase5Enable <= Phase4EnableD;
- Phase5Page <= Phase4PageD;
- Phase5Count <= Phase4CountD;
- Phase5EnableD <= Phase5Enable;
- Phase5PageD <= Phase5Page;
- Phase5CountD <= Phase5Count;
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- wire signed [31:0] Phase5R0w;
- wire signed [31:0] Phase5R1w;
- assign Phase5R0w = (Phase5Count == 3'd0)?Phase3Reg[0]:
- (Phase5Count == 3'd1)?Phase3Reg[1]:
- (Phase5Count == 3'd2)?Phase3Reg[2]:
- (Phase5Count == 3'd3)?Phase3Reg[3]:
- 32'd0;
- assign Phase5R1w = (Phase5Count == 3'd0)?Phase3Reg[7]:
- (Phase5Count == 3'd1)?Phase4R0r >> 8:
- (Phase5Count == 3'd2)?Phase4R1r >> 8:
- (Phase5Count == 3'd3)?Phase3Reg[4]:
- 32'd0;
-
- reg signed [31:0] Phase5R0r;
- reg signed [31:0] Phase5R1r;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Phase5R0r <= 0;
- Phase5R1r <= 0;
- end else begin
- Phase5R0r <= Phase5R0w + Phase5R1w;
- Phase5R1r <= Phase5R0w - Phase5R1w;
- end
- end
-
- assign DataOutEnable = Phase5EnableD == 1'b1 & Phase5CountD[2] == 1'b0;
- assign DataOutPage = Phase5PageD;
- assign DataOutCount = Phase5CountD[1:0];
-
- assign Data0Out = Phase5R0r[30:15];
- assign Data1Out = Phase5R1r[30:15];
-
-endmodule // jpeg_idcty
Index: trunk/src/jpeg_dht.v
===================================================================
--- trunk/src/jpeg_dht.v (revision 5)
+++ trunk/src/jpeg_dht.v (nonexistent)
@@ -1,118 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_dht.v
-// Module Name : jpeg_dht
-// Description : DHT space
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_dht
- (
- rst,
- clk,
-
- DataInEnable,
- DataInColor,
- DataInCount,
- DataIn,
-
- ColorNumber,
- TableNumber,
- ZeroTable,
- WidhtTable
- );
-
- input rst;
- input clk;
-
- input DataInEnable;
- input [1:0] DataInColor;
- input [7:0] DataInCount;
- input [7:0] DataIn;
-
- input [1:0] ColorNumber;
- input [7:0] TableNumber;
- output [3:0] ZeroTable;
- output [3:0] WidhtTable;
-
- // RAM
- reg [7:0] DHT_Ydc [0:15];
- reg [7:0] DHT_Yac [0:255];
- reg [7:0] DHT_Cdc [0:15];
- reg [7:0] DHT_Cac [0:255];
-
- reg [7:0] ReadDataYdc;
- reg [7:0] ReadDataYac;
- reg [7:0] ReadDataCdc;
- reg [7:0] ReadDataCac;
-
- wire [7:0] ReadData;
-
- // RAM
- always @(posedge clk) begin
- if(DataInEnable ==1'b1 & DataInColor ==2'b00) begin
- DHT_Ydc[DataInCount[3:0]] <= DataIn;
- end
- if(DataInEnable ==1'b1 & DataInColor ==2'b01) begin
- DHT_Yac[DataInCount] <= DataIn;
- end
- if(DataInEnable ==1'b1 & DataInColor ==2'b10) begin
- DHT_Cdc[DataInCount[3:0]] <= DataIn;
- end
- if(DataInEnable ==1'b1 & DataInColor ==2'b11) begin
- DHT_Cac[DataInCount] <= DataIn;
- end
- end // always @ (posedge clk)
-
- always @(posedge clk) begin
- ReadDataYdc <= DHT_Ydc[TableNumber[3:0]];
- ReadDataYac <= DHT_Yac[TableNumber];
- ReadDataCdc <= DHT_Cdc[TableNumber[3:0]];
- ReadDataCac <= DHT_Cac[TableNumber];
- end // always @ (posedge clk or negedge rst)
-
- // Selector
-/*
- always @(*) begin
- case (ColorNumber)
- 2'b00: ReadData <= ReadDataYdc;
- 2'b01: ReadData <= ReadDataYac;
- 2'b10: ReadData <= ReadDataCdc;
- 2'b11: ReadData <= ReadDataCac;
- endcase // case(ColorNumber)
- end
-*/
- function [7:0] ReadDataSel;
- input [1:0] ColorNumber;
- input [7:0] ReadDataYdc;
- input [7:0] ReadDataYac;
- input [7:0] ReadDataCdc;
- input [7:0] ReadDataCac;
- begin
- case (ColorNumber)
- 2'b00: ReadDataSel = ReadDataYdc;
- 2'b01: ReadDataSel = ReadDataYac;
- 2'b10: ReadDataSel = ReadDataCdc;
- 2'b11: ReadDataSel = ReadDataCac;
- endcase
- end
- endfunction
-
- assign ReadData = ReadDataSel(ColorNumber, ReadDataYdc, ReadDataYac, ReadDataCdc, ReadDataCac);
-
- assign ZeroTable = ReadData[7:4];
- assign WidhtTable = ReadData[3:0];
-
-endmodule // jpeg_dht
Index: trunk/src/jpeg_ycbcr2rgb.v
===================================================================
--- trunk/src/jpeg_ycbcr2rgb.v (revision 5)
+++ trunk/src/jpeg_ycbcr2rgb.v (nonexistent)
@@ -1,245 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_ycbcr2rgb.v
-// Module Name : jpeg_ycbcr2rgb
-// Description : YCbCr2RGB
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-//----------------------------------------------------------------------------
-// JPEG YCbCr -> RGB Conveter
-//----------------------------------------------------------------------------
-module jpeg_ycbcbr2rgb
- (
- rst,
- clk,
-
- InEnable,
- InBlockX,
- InBlockY,
- InIdle,
- InBank,
- InAddress,
- InY,
- InCb,
- InCr,
-
- OutEnable,
- OutPixelX,
- OutPixelY,
- OutR,
- OutG,
- OutB
- );
-
- input clk;
- input rst;
-
- input InEnable;
- input [11:0] InBlockX;
- input [11:0] InBlockY;
- output InIdle;
- output InBank;
- output [7:0] InAddress;
- input [8:0] InY;
- input [8:0] InCb;
- input [8:0] InCr;
-
- output OutEnable;
- output [15:0] OutPixelX;
- output [15:0] OutPixelY;
- output [7:0] OutR;
- output [7:0] OutG;
- output [7:0] OutB;
-
- reg RunActive;
- reg [7:0] RunCount;
- reg [11:0] RunBlockX;
- reg [11:0] RunBlockY;
- reg RunBank;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- RunActive <= 1'b0;
- RunBank <= 1'b0;
- RunCount <= 8'h00;
- RunBlockX <= 12'h000;
- RunBlockY <= 12'h000;
- end else begin
- if(RunActive == 1'b0) begin
- if(InEnable == 1'b1) begin
- RunActive <= 1'b1;
- RunBlockX <= InBlockX;
- RunBlockY <= InBlockY;
- end
- RunCount <= 8'h00;
- end else begin
- if(RunCount == 8'hFF) begin
- RunActive <= 1'b0;
- RunBank <= ~RunBank;
- RunCount <= 8'h00;
- end else begin
- RunCount <= RunCount +1;
- end
- end // else: !if(RunActive == 1'b0)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign InIdle = RunActive == 1'b0 | (RunActive == 1'b1 & RunCount == 8'hFF);
- assign InAddress = RunCount;
- assign InBank = RunBank;
-
- reg PreEnable;
- reg [15:0] PreCountX;
- reg [15:0] PreCountY;
- reg Phase0Enable;
- reg [15:0] Phase0CountX;
- reg [15:0] Phase0CountY;
- reg Phase1Enable;
- reg [15:0] Phase1CountX;
- reg [15:0] Phase1CountY;
- reg Phase2Enable;
- reg [15:0] Phase2CountX;
- reg [15:0] Phase2CountY;
- reg Phase3Enable;
- reg [15:0] Phase3CountX;
- reg [15:0] Phase3CountY;
-
- reg signed [31:0] rgb00r;
- reg signed [31:0] r00r;
- reg signed [31:0] g00r;
- reg signed [31:0] g01r;
- reg signed [31:0] b00r;
- reg signed [31:0] r10r;
- reg signed [31:0] g10r;
- reg signed [31:0] g11r;
- reg signed [31:0] b10r;
- reg signed [31:0] r20r;
- reg signed [31:0] g20r;
- reg signed [31:0] b20r;
-
- wire signed [8:0] DataY;
- wire signed [8:0] DataCb;
- wire signed [8:0] DataCr;
-
- reg signed [8:0] Phase0Y;
- reg signed [8:0] Phase0Cb;
- reg signed [8:0] Phase0Cr;
-
- wire signed [19:0] C_RR = 20'h59BA5; // R_Cr: 1.402 * 0x4000
- wire signed [19:0] C_GB = 20'h16066; // G_Cb: 0.34414 * 0x4000
- wire signed [19:0] C_GR = 20'h2DB47; // G_Cr: 0.71414 * 0x4000
- wire signed [19:0] C_BB = 20'h71687; // B_Cb: 1.772 * 0x4000
-
- assign DataY = InY;
- assign DataCb = InCb;
- assign DataCr = InCr;
-
- reg signed [8:0] Phase1Y,Phase1Cb,Phase1Cr;
- reg signed [8:0] Phase2Y,Phase2Cb,Phase2Cr;
- reg signed [8:0] Phase3Y,Phase3Cb,Phase3Cr;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- rgb00r <= 0;
- r00r <= 0;
- g00r <= 0;
- g01r <= 0;
- b00r <= 0;
-
- r10r <= 0;
- g10r <= 0;
- g11r <= 0;
- b10r <= 0;
-
- r20r <= 0;
- g20r <= 0;
- b20r <= 0;
-
- Phase0Enable <= 1'b0;
- Phase0CountX <= 16'h0000;
- Phase0CountY <= 16'h0000;
- Phase1Enable <= 1'b0;
- Phase1CountX <= 16'h0000;
- Phase1CountY <= 16'h0000;
- Phase2Enable <= 1'b0;
- Phase2CountX <= 16'h0000;
- Phase2CountY <= 16'h0000;
- Phase3Enable <= 1'b0;
- Phase3CountX <= 16'h0000;
- Phase3CountY <= 16'h0000;
- end else begin // if (!rst)
- // Pre
- PreEnable <= RunActive;
- PreCountX <= {RunBlockX,RunCount[3:0]};
- PreCountY <= {RunBlockY,RunCount[7:4]};
- // Phase0
- Phase0Enable <= PreEnable;
- Phase0CountX <= PreCountX;
- Phase0CountY <= PreCountY;
- Phase0Y <= DataY;
- Phase0Cb <= DataCb;
- Phase0Cr <= DataCr;
- // Phase1
- Phase1Enable <= Phase0Enable;
- Phase1CountX <= Phase0CountX;
- Phase1CountY <= Phase0CountY;
- rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};
- r00r <= Phase0Cr * C_RR;
- g00r <= Phase0Cb * C_GB;
- g01r <= Phase0Cr * C_GR;
- b00r <= Phase0Cb * C_BB;
-
- Phase1Y <= Phase0Y;
- Phase1Cb <= Phase0Cb;
- Phase1Cr <= Phase0Cr;
-
-
- // Phase2
- Phase2Enable <= Phase1Enable;
- Phase2CountX <= Phase1CountX;
- Phase2CountY <= Phase1CountY;
- r10r <= rgb00r + r00r;
- g10r <= rgb00r - g00r;
- g11r <= g01r;
- b10r <= rgb00r + b00r;
-
- Phase2Y <= Phase1Y;
- Phase2Cb <= Phase1Cb;
- Phase2Cr <= Phase1Cr;
-
- // Phase3
- Phase3Enable <= Phase2Enable;
- Phase3CountX <= Phase2CountX;
- Phase3CountY <= Phase2CountY;
- r20r <= r10r;
- g20r <= g10r - g11r;
- b20r <= b10r;
-
- Phase3Y <= Phase2Y;
- Phase3Cb <= Phase2Cb;
- Phase3Cr <= Phase2Cr;
-
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign OutEnable = Phase3Enable;
- assign OutPixelX = Phase3CountX;
- assign OutPixelY = Phase3CountY;
- assign OutR = (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];
- assign OutG = (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];
- assign OutB = (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];
-
-endmodule // jpeg_ycbcbr2rgb
Index: trunk/src/jpeg_idct.v
===================================================================
--- trunk/src/jpeg_idct.v (revision 5)
+++ trunk/src/jpeg_idct.v (nonexistent)
@@ -1,505 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_idct.v
-// Module Name : jpeg_idct
-// Description : iDCT top module
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_idct
- (
- rst,
- clk,
-
- DataInEnable,
- DataInSel,
- Data00In,
- Data01In,
- Data02In,
- Data03In,
- Data04In,
- Data05In,
- Data06In,
- Data07In,
- Data08In,
- Data09In,
- Data10In,
- Data11In,
- Data12In,
- Data13In,
- Data14In,
- Data15In,
- Data16In,
- Data17In,
- Data18In,
- Data19In,
- Data20In,
- Data21In,
- Data22In,
- Data23In,
- Data24In,
- Data25In,
- Data26In,
- Data27In,
- Data28In,
- Data29In,
- Data30In,
- Data31In,
- Data32In,
- Data33In,
- Data34In,
- Data35In,
- Data36In,
- Data37In,
- Data38In,
- Data39In,
- Data40In,
- Data41In,
- Data42In,
- Data43In,
- Data44In,
- Data45In,
- Data46In,
- Data47In,
- Data48In,
- Data49In,
- Data50In,
- Data51In,
- Data52In,
- Data53In,
- Data54In,
- Data55In,
- Data56In,
- Data57In,
- Data58In,
- Data59In,
- Data60In,
- Data61In,
- Data62In,
- Data63In,
- DataInIdle,
- DataInRelease,
-
- DataOutEnable,
- DataOutPage,
- DataOutCount,
- Data0Out,
- Data1Out
- );
-
- input rst;
- input clk;
-
- input DataInEnable;
- output DataInSel;
- input [15:0] Data00In;
- input [15:0] Data01In;
- input [15:0] Data02In;
- input [15:0] Data03In;
- input [15:0] Data04In;
- input [15:0] Data05In;
- input [15:0] Data06In;
- input [15:0] Data07In;
- input [15:0] Data08In;
- input [15:0] Data09In;
- input [15:0] Data10In;
- input [15:0] Data11In;
- input [15:0] Data12In;
- input [15:0] Data13In;
- input [15:0] Data14In;
- input [15:0] Data15In;
- input [15:0] Data16In;
- input [15:0] Data17In;
- input [15:0] Data18In;
- input [15:0] Data19In;
- input [15:0] Data20In;
- input [15:0] Data21In;
- input [15:0] Data22In;
- input [15:0] Data23In;
- input [15:0] Data24In;
- input [15:0] Data25In;
- input [15:0] Data26In;
- input [15:0] Data27In;
- input [15:0] Data28In;
- input [15:0] Data29In;
- input [15:0] Data30In;
- input [15:0] Data31In;
- input [15:0] Data32In;
- input [15:0] Data33In;
- input [15:0] Data34In;
- input [15:0] Data35In;
- input [15:0] Data36In;
- input [15:0] Data37In;
- input [15:0] Data38In;
- input [15:0] Data39In;
- input [15:0] Data40In;
- input [15:0] Data41In;
- input [15:0] Data42In;
- input [15:0] Data43In;
- input [15:0] Data44In;
- input [15:0] Data45In;
- input [15:0] Data46In;
- input [15:0] Data47In;
- input [15:0] Data48In;
- input [15:0] Data49In;
- input [15:0] Data50In;
- input [15:0] Data51In;
- input [15:0] Data52In;
- input [15:0] Data53In;
- input [15:0] Data54In;
- input [15:0] Data55In;
- input [15:0] Data56In;
- input [15:0] Data57In;
- input [15:0] Data58In;
- input [15:0] Data59In;
- input [15:0] Data60In;
- input [15:0] Data61In;
- input [15:0] Data62In;
- input [15:0] Data63In;
- output DataInIdle;
- output DataInRelease;
-
- output DataOutEnable;
- output [2:0] DataOutPage;
- output [1:0] DataOutCount;
- output [8:0] Data0Out;
- output [8:0] Data1Out;
-
- wire DctXEnable;
- wire [2:0] DctXPage;
- wire [1:0] DctXCount;
- wire [15:0] DctXData0r;
- wire [15:0] DctXData1r;
-
- wire DctBBank;
- wire DctBIdle;
-
- jpeg_idctx u_jpeg_idctx(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable( DataInEnable ),
- .DataInSel( DataInSel ),
- .Data00In( Data00In ),
- .Data01In( Data01In ),
- .Data02In( Data02In ),
- .Data03In( Data03In ),
- .Data04In( Data04In ),
- .Data05In( Data05In ),
- .Data06In( Data06In ),
- .Data07In( Data07In ),
- .Data08In( Data08In ),
- .Data09In( Data09In ),
- .Data10In( Data10In ),
- .Data11In( Data11In ),
- .Data12In( Data12In ),
- .Data13In( Data13In ),
- .Data14In( Data14In ),
- .Data15In( Data15In ),
- .Data16In( Data16In ),
- .Data17In( Data17In ),
- .Data18In( Data18In ),
- .Data19In( Data19In ),
- .Data20In( Data20In ),
- .Data21In( Data21In ),
- .Data22In( Data22In ),
- .Data23In( Data23In ),
- .Data24In( Data24In ),
- .Data25In( Data25In ),
- .Data26In( Data26In ),
- .Data27In( Data27In ),
- .Data28In( Data28In ),
- .Data29In( Data29In ),
- .Data30In( Data30In ),
- .Data31In( Data31In ),
- .Data32In( Data32In ),
- .Data33In( Data33In ),
- .Data34In( Data34In ),
- .Data35In( Data35In ),
- .Data36In( Data36In ),
- .Data37In( Data37In ),
- .Data38In( Data38In ),
- .Data39In( Data39In ),
- .Data40In( Data40In ),
- .Data41In( Data41In ),
- .Data42In( Data42In ),
- .Data43In( Data43In ),
- .Data44In( Data44In ),
- .Data45In( Data45In ),
- .Data46In( Data46In ),
- .Data47In( Data47In ),
- .Data48In( Data48In ),
- .Data49In( Data49In ),
- .Data50In( Data50In ),
- .Data51In( Data51In ),
- .Data52In( Data52In ),
- .Data53In( Data53In ),
- .Data54In( Data54In ),
- .Data55In( Data55In ),
- .Data56In( Data56In ),
- .Data57In( Data57In ),
- .Data58In( Data58In ),
- .Data59In( Data59In ),
- .Data60In( Data60In ),
- .Data61In( Data61In ),
- .Data62In( Data62In ),
- .Data63In( Data63In ),
- .DataInIdle( DataInIdle),
- .DataInRelease( DataInRelease ),
-
- .DataOutIdle ( DctBIdle ),
- .DataOutEnable ( DctXEnable ),
- .DataOutPage ( DctXPage ),
- .DataOutCount ( DctXCount ),
- .Data0Out ( DctXData0r ),
- .Data1Out ( DctXData1r )
- );
-
- wire [15:0] DctB00r;
- wire [15:0] DctB01r;
- wire [15:0] DctB02r;
- wire [15:0] DctB03r;
- wire [15:0] DctB04r;
- wire [15:0] DctB05r;
- wire [15:0] DctB06r;
- wire [15:0] DctB07r;
- wire [15:0] DctB08r;
- wire [15:0] DctB09r;
- wire [15:0] DctB10r;
- wire [15:0] DctB11r;
- wire [15:0] DctB12r;
- wire [15:0] DctB13r;
- wire [15:0] DctB14r;
- wire [15:0] DctB15r;
- wire [15:0] DctB16r;
- wire [15:0] DctB17r;
- wire [15:0] DctB18r;
- wire [15:0] DctB19r;
- wire [15:0] DctB20r;
- wire [15:0] DctB21r;
- wire [15:0] DctB22r;
- wire [15:0] DctB23r;
- wire [15:0] DctB24r;
- wire [15:0] DctB25r;
- wire [15:0] DctB26r;
- wire [15:0] DctB27r;
- wire [15:0] DctB28r;
- wire [15:0] DctB29r;
- wire [15:0] DctB30r;
- wire [15:0] DctB31r;
- wire [15:0] DctB32r;
- wire [15:0] DctB33r;
- wire [15:0] DctB34r;
- wire [15:0] DctB35r;
- wire [15:0] DctB36r;
- wire [15:0] DctB37r;
- wire [15:0] DctB38r;
- wire [15:0] DctB39r;
- wire [15:0] DctB40r;
- wire [15:0] DctB41r;
- wire [15:0] DctB42r;
- wire [15:0] DctB43r;
- wire [15:0] DctB44r;
- wire [15:0] DctB45r;
- wire [15:0] DctB46r;
- wire [15:0] DctB47r;
- wire [15:0] DctB48r;
- wire [15:0] DctB49r;
- wire [15:0] DctB50r;
- wire [15:0] DctB51r;
- wire [15:0] DctB52r;
- wire [15:0] DctB53r;
- wire [15:0] DctB54r;
- wire [15:0] DctB55r;
- wire [15:0] DctB56r;
- wire [15:0] DctB57r;
- wire [15:0] DctB58r;
- wire [15:0] DctB59r;
- wire [15:0] DctB60r;
- wire [15:0] DctB61r;
- wire [15:0] DctB62r;
- wire [15:0] DctB63r;
-
- wire DctBReleaseA;
- wire DctBReleaseB;
- wire DctBRelease;
-
- jpeg_idctb u_jpeg_idctb(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable ( DctXEnable ),
- .DataInPage ( DctXPage ),
- .DataInCount ( DctXCount ),
- .DataInIdle ( DctBIdle ),
- .Data0In ( DctXData0r ),
- .Data1In ( DctXData1r ),
-
- .DataOutEnable ( DctBEnable ),
- .DataOutSel( DctBSel),
- .Data00Out( DctB00r ),
- .Data01Out( DctB01r ),
- .Data02Out( DctB02r ),
- .Data03Out( DctB03r ),
- .Data04Out( DctB04r ),
- .Data05Out( DctB05r ),
- .Data06Out( DctB06r ),
- .Data07Out( DctB07r ),
- .Data08Out( DctB08r ),
- .Data09Out( DctB09r ),
- .Data10Out( DctB10r ),
- .Data11Out( DctB11r ),
- .Data12Out( DctB12r ),
- .Data13Out( DctB13r ),
- .Data14Out( DctB14r ),
- .Data15Out( DctB15r ),
- .Data16Out( DctB16r ),
- .Data17Out( DctB17r ),
- .Data18Out( DctB18r ),
- .Data19Out( DctB19r ),
- .Data20Out( DctB20r ),
- .Data21Out( DctB21r ),
- .Data22Out( DctB22r ),
- .Data23Out( DctB23r ),
- .Data24Out( DctB24r ),
- .Data25Out( DctB25r ),
- .Data26Out( DctB26r ),
- .Data27Out( DctB27r ),
- .Data28Out( DctB28r ),
- .Data29Out( DctB29r ),
- .Data30Out( DctB30r ),
- .Data31Out( DctB31r ),
- .Data32Out( DctB32r ),
- .Data33Out( DctB33r ),
- .Data34Out( DctB34r ),
- .Data35Out( DctB35r ),
- .Data36Out( DctB36r ),
- .Data37Out( DctB37r ),
- .Data38Out( DctB38r ),
- .Data39Out( DctB39r ),
- .Data40Out( DctB40r ),
- .Data41Out( DctB41r ),
- .Data42Out( DctB42r ),
- .Data43Out( DctB43r ),
- .Data44Out( DctB44r ),
- .Data45Out( DctB45r ),
- .Data46Out( DctB46r ),
- .Data47Out( DctB47r ),
- .Data48Out( DctB48r ),
- .Data49Out( DctB49r ),
- .Data50Out( DctB50r ),
- .Data51Out( DctB51r ),
- .Data52Out( DctB52r ),
- .Data53Out( DctB53r ),
- .Data54Out( DctB54r ),
- .Data55Out( DctB55r ),
- .Data56Out( DctB56r ),
- .Data57Out( DctB57r ),
- .Data58Out( DctB58r ),
- .Data59Out( DctB59r ),
- .Data60Out( DctB60r ),
- .Data61Out( DctB61r ),
- .Data62Out( DctB62r ),
- .Data63Out( DctB63r ),
-
- .BankARelease( DctBReleaseA ),
- .BankBRelease( DctBReleaseB )
- );
-
- assign DctBReleaseA = DctBSel == 1'b0 & DctBRelease;
- assign DctBReleaseB = DctBSel == 1'b1 & DctBRelease;
-
- jpeg_idcty u_jpeg_idcty(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable(DctBEnable),
- .DataInBank(DctBBank),
- .DataInSel(DctBSel),
- .Data00In( DctB00r ),
- .Data01In( DctB01r ),
- .Data02In( DctB02r ),
- .Data03In( DctB03r ),
- .Data04In( DctB04r ),
- .Data05In( DctB05r ),
- .Data06In( DctB06r ),
- .Data07In( DctB07r ),
- .Data08In( DctB08r ),
- .Data09In( DctB09r ),
- .Data10In( DctB10r ),
- .Data11In( DctB11r ),
- .Data12In( DctB12r ),
- .Data13In( DctB13r ),
- .Data14In( DctB14r ),
- .Data15In( DctB15r ),
- .Data16In( DctB16r ),
- .Data17In( DctB17r ),
- .Data18In( DctB18r ),
- .Data19In( DctB19r ),
- .Data20In( DctB20r ),
- .Data21In( DctB21r ),
- .Data22In( DctB22r ),
- .Data23In( DctB23r ),
- .Data24In( DctB24r ),
- .Data25In( DctB25r ),
- .Data26In( DctB26r ),
- .Data27In( DctB27r ),
- .Data28In( DctB28r ),
- .Data29In( DctB29r ),
- .Data30In( DctB30r ),
- .Data31In( DctB31r ),
- .Data32In( DctB32r ),
- .Data33In( DctB33r ),
- .Data34In( DctB34r ),
- .Data35In( DctB35r ),
- .Data36In( DctB36r ),
- .Data37In( DctB37r ),
- .Data38In( DctB38r ),
- .Data39In( DctB39r ),
- .Data40In( DctB40r ),
- .Data41In( DctB41r ),
- .Data42In( DctB42r ),
- .Data43In( DctB43r ),
- .Data44In( DctB44r ),
- .Data45In( DctB45r ),
- .Data46In( DctB46r ),
- .Data47In( DctB47r ),
- .Data48In( DctB48r ),
- .Data49In( DctB49r ),
- .Data50In( DctB50r ),
- .Data51In( DctB51r ),
- .Data52In( DctB52r ),
- .Data53In( DctB53r ),
- .Data54In( DctB54r ),
- .Data55In( DctB55r ),
- .Data56In( DctB56r ),
- .Data57In( DctB57r ),
- .Data58In( DctB58r ),
- .Data59In( DctB59r ),
- .Data60In( DctB60r ),
- .Data61In( DctB61r ),
- .Data62In( DctB62r ),
- .Data63In( DctB63r ),
- .DataInIdle( DctYIdle ),
- .DataInRelease( DctBRelease),
-
- .DataOutEnable ( DataOutEnable ),
- .DataOutPage ( DataOutPage ),
- .DataOutCount ( DataOutCount ),
- .Data0Out ( Data0Out ),
- .Data1Out ( Data1Out )
- );
-
-endmodule // jpeg_idct
Index: trunk/src/jpeg_decode.v
===================================================================
--- trunk/src/jpeg_decode.v (revision 5)
+++ trunk/src/jpeg_decode.v (nonexistent)
@@ -1,474 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_decode.v
-// Module Name : jpeg_decode
-// Description : JPEG Deocder top module
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2007/04/11
-// Rev. : 2.0
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-// 1.02 2006/10/04 add ProcessIdle register
-// 2.00 2007/04/11
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_decode
- (
- rst,
- clk,
-
- // From FIFO
- DataIn,
- DataInEnable,
- DataInRead,
-
- JpegDecodeIdle, // Deocdeer Process Idle(1:Idle, 0:Run)
-
- OutEnable,
- OutWidth,
- OutHeight,
- OutPixelX,
- OutPixelY,
- OutR,
- OutG,
- OutB
-
- );
-
- input rst;
- input clk;
-
- input [31:0] DataIn;
- input DataInEnable;
- output DataInRead;
-
- output JpegDecodeIdle;
-
- output OutEnable;
- output [15:0] OutWidth;
- output [15:0] OutHeight;
- output [15:0] OutPixelX;
- output [15:0] OutPixelY;
- output [7:0] OutR;
- output [7:0] OutG;
- output [7:0] OutB;
-
- wire [31:0] JpegData;
- wire JpegDataEnable;
- wire JpegDecodeIdle;
-
- wire UseBit;
- wire [6:0] UseWidth;
- wire UseByte;
- wire UseWord;
-
- wire ImageEnable;
- wire EnableFF00;
- wire DecodeFinish;
-
-// reg ProcessIdle;
-
- //--------------------------------------------------------------------------
- // Read JPEG Data from FIFO
- //--------------------------------------------------------------------------
- jpeg_regdata u_jpeg_regdata(
- .rst(rst),
- .clk(clk),
-
- // Read Data
- .DataIn ( DataIn ),
- .DataInEnable ( DataInEnable ),
- .DataInRead ( DataInRead ),
-
- // DataOut
- .DataOut ( JpegData ),
- .DataOutEnable ( JpegDataEnable ),
-
- //
- .ImageEnable ( EnableFF00 ),
- .ProcessIdle ( JpegDecodeIdle ),
-
- // UseData
- .UseBit ( UseBit ),
- .UseWidth ( UseWidth ),
- .UseByte ( UseByte ),
- .UseWord ( UseWord )
- );
-
- //--------------------------------------------------------------------------
- // Read Maker from Jpeg Data
- //--------------------------------------------------------------------------
- wire DqtEnable;
- wire DqtTable;
- wire [5:0] DqtCount;
- wire [7:0] DqtData;
-
- wire DhtEnable;
- wire [1:0] DhtTable;
- wire [7:0] DhtCount;
- wire [7:0] DhtData;
-
- //
- wire HaffumanEnable;
- wire [1:0] HaffumanTable;
- wire [3:0] HaffumanCount;
- wire [15:0] HaffumanData;
- wire [7:0] HaffumanStart;
-
- wire [11:0] JpegBlockWidth;
-
- jpeg_decode_fsm u_jpeg_decode_fsm(
- .rst(rst),
- .clk(clk),
-
- // From FIFO
- .DataInEnable ( JpegDataEnable ),
- .DataIn ( JpegData ),
-
- .JpegDecodeIdle ( JpegDecodeIdle ),
-
- .OutWidth ( OutWidth ),
- .OutHeight ( OutHeight ),
- .OutBlockWidth ( JpegBlockWidth ),
- .OutEnable ( OutEnable ),
- .OutPixelX ( OutPixelX ),
- .OutPixelY ( OutPixelY ),
-
- //
- .DqtEnable ( DqtEnable ),
- .DqtTable ( DqtTable ),
- .DqtCount ( DqtCount ),
- .DqtData ( DqtData ),
-
- //
- .DhtEnable ( DhtEnable ),
- .DhtTable ( DhtTable ),
- .DhtCount ( DhtCount ),
- .DhtData ( DhtData ),
-
- //
- .HaffumanEnable ( HaffumanEnable ),
- .HaffumanTable ( HaffumanTable ),
- .HaffumanCount ( HaffumanCount ),
- .HaffumanData ( HaffumanData ),
- .HaffumanStart ( HaffumanStart ),
-
- //
- .ImageEnable ( ImageEnable ),
- .ImageEnd ( DecodeFinish ),
- .EnableFF00 ( EnableFF00 ),
-
- //
- .UseByte ( UseByte ),
- .UseWord ( UseWord )
- );
-
-
- wire HmDecEnable;
- wire [2:0] HmDecColor;
-
- wire HmDecSel;
- wire HmDecRelease;
-
- wire [15:0] Hm00Data;
- wire [15:0] Hm01Data;
- wire [15:0] Hm02Data;
- wire [15:0] Hm03Data;
- wire [15:0] Hm04Data;
- wire [15:0] Hm05Data;
- wire [15:0] Hm06Data;
- wire [15:0] Hm07Data;
- wire [15:0] Hm08Data;
- wire [15:0] Hm09Data;
- wire [15:0] Hm10Data;
- wire [15:0] Hm11Data;
- wire [15:0] Hm12Data;
- wire [15:0] Hm13Data;
- wire [15:0] Hm14Data;
- wire [15:0] Hm15Data;
- wire [15:0] Hm16Data;
- wire [15:0] Hm17Data;
- wire [15:0] Hm18Data;
- wire [15:0] Hm19Data;
- wire [15:0] Hm20Data;
- wire [15:0] Hm21Data;
- wire [15:0] Hm22Data;
- wire [15:0] Hm23Data;
- wire [15:0] Hm24Data;
- wire [15:0] Hm25Data;
- wire [15:0] Hm26Data;
- wire [15:0] Hm27Data;
- wire [15:0] Hm28Data;
- wire [15:0] Hm29Data;
- wire [15:0] Hm30Data;
- wire [15:0] Hm31Data;
- wire [15:0] Hm32Data;
- wire [15:0] Hm33Data;
- wire [15:0] Hm34Data;
- wire [15:0] Hm35Data;
- wire [15:0] Hm36Data;
- wire [15:0] Hm37Data;
- wire [15:0] Hm38Data;
- wire [15:0] Hm39Data;
- wire [15:0] Hm40Data;
- wire [15:0] Hm41Data;
- wire [15:0] Hm42Data;
- wire [15:0] Hm43Data;
- wire [15:0] Hm44Data;
- wire [15:0] Hm45Data;
- wire [15:0] Hm46Data;
- wire [15:0] Hm47Data;
- wire [15:0] Hm48Data;
- wire [15:0] Hm49Data;
- wire [15:0] Hm50Data;
- wire [15:0] Hm51Data;
- wire [15:0] Hm52Data;
- wire [15:0] Hm53Data;
- wire [15:0] Hm54Data;
- wire [15:0] Hm55Data;
- wire [15:0] Hm56Data;
- wire [15:0] Hm57Data;
- wire [15:0] Hm58Data;
- wire [15:0] Hm59Data;
- wire [15:0] Hm60Data;
- wire [15:0] Hm61Data;
- wire [15:0] Hm62Data;
- wire [15:0] Hm63Data;
-
- wire DctIdle;
-
- jpeg_haffuman u_jpeg_haffuman(
- .rst(rst),
- .clk(clk),
-
- // DQT Table
- .DqtInEnable ( DqtEnable ),
- .DqtInColor ( DqtTable ),
- .DqtInCount ( DqtCount[5:0] ),
- .DqtInData ( DqtData ),
-
- // DHT Table
- .DhtInEnable ( DhtEnable ),
- .DhtInColor ( DhtTable ),
- .DhtInCount ( DhtCount ),
- .DhtInData ( DhtData ),
-
- // Haffuman Table
- .HaffumanTableEnable ( HaffumanEnable ),
- .HaffumanTableColor ( HaffumanTable ),
- .HaffumanTableCount ( HaffumanCount ),
- .HaffumanTableCode ( HaffumanData ),
- .HaffumanTableStart ( HaffumanStart ),
-
- // Haffuman Decode
- .DataInRun ( ImageEnable ),
- .DataInEnable ( JpegDataEnable ),
- .DataIn ( JpegData ),
-
- // Output decode data
- .DecodeUseBit ( UseBit ),
- .DecodeUseWidth ( UseWidth ),
-
- // Data Out
- .DataOutIdle ( DctIdle ),
- .DataOutEnable ( HmDecEnable ),
- .DataOutColor ( HmDecColor ),
- .DataOutSel ( HmDecSel ),
- .Data00Reg ( Hm00Data ),
- .Data01Reg ( Hm01Data ),
- .Data02Reg ( Hm02Data ),
- .Data03Reg ( Hm03Data ),
- .Data04Reg ( Hm04Data ),
- .Data05Reg ( Hm05Data ),
- .Data06Reg ( Hm06Data ),
- .Data07Reg ( Hm07Data ),
- .Data08Reg ( Hm08Data ),
- .Data09Reg ( Hm09Data ),
- .Data10Reg ( Hm10Data ),
- .Data11Reg ( Hm11Data ),
- .Data12Reg ( Hm12Data ),
- .Data13Reg ( Hm13Data ),
- .Data14Reg ( Hm14Data ),
- .Data15Reg ( Hm15Data ),
- .Data16Reg ( Hm16Data ),
- .Data17Reg ( Hm17Data ),
- .Data18Reg ( Hm18Data ),
- .Data19Reg ( Hm19Data ),
- .Data20Reg ( Hm20Data ),
- .Data21Reg ( Hm21Data ),
- .Data22Reg ( Hm22Data ),
- .Data23Reg ( Hm23Data ),
- .Data24Reg ( Hm24Data ),
- .Data25Reg ( Hm25Data ),
- .Data26Reg ( Hm26Data ),
- .Data27Reg ( Hm27Data ),
- .Data28Reg ( Hm28Data ),
- .Data29Reg ( Hm29Data ),
- .Data30Reg ( Hm30Data ),
- .Data31Reg ( Hm31Data ),
- .Data32Reg ( Hm32Data ),
- .Data33Reg ( Hm33Data ),
- .Data34Reg ( Hm34Data ),
- .Data35Reg ( Hm35Data ),
- .Data36Reg ( Hm36Data ),
- .Data37Reg ( Hm37Data ),
- .Data38Reg ( Hm38Data ),
- .Data39Reg ( Hm39Data ),
- .Data40Reg ( Hm40Data ),
- .Data41Reg ( Hm41Data ),
- .Data42Reg ( Hm42Data ),
- .Data43Reg ( Hm43Data ),
- .Data44Reg ( Hm44Data ),
- .Data45Reg ( Hm45Data ),
- .Data46Reg ( Hm46Data ),
- .Data47Reg ( Hm47Data ),
- .Data48Reg ( Hm48Data ),
- .Data49Reg ( Hm49Data ),
- .Data50Reg ( Hm50Data ),
- .Data51Reg ( Hm51Data ),
- .Data52Reg ( Hm52Data ),
- .Data53Reg ( Hm53Data ),
- .Data54Reg ( Hm54Data ),
- .Data55Reg ( Hm55Data ),
- .Data56Reg ( Hm56Data ),
- .Data57Reg ( Hm57Data ),
- .Data58Reg ( Hm58Data ),
- .Data59Reg ( Hm59Data ),
- .Data60Reg ( Hm60Data ),
- .Data61Reg ( Hm61Data ),
- .Data62Reg ( Hm62Data ),
- .Data63Reg ( Hm63Data ),
- .DataOutRelease (HmDecRelase)
- );
-
- wire DctEnable;
- wire [2:0] DctColor;
- wire [2:0] DctPage;
- wire [1:0] DctCount;
- wire [8:0] Dct0Data;
- wire [8:0] Dct1Data;
-
- wire [15:0] DctWidth;
- wire [15:0] DctHeight;
- wire [11:0] DctBlockX;
- wire [11:0] DctBlockY;
-
- wire YCbCrIdle;
-
- jpeg_idct u_jpeg_idct(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable( HmDecEnable ),
- .DataInSel( HmDecSel ),
- .Data00In( Hm00Data ),
- .Data01In( Hm01Data ),
- .Data02In( Hm02Data ),
- .Data03In( Hm03Data ),
- .Data04In( Hm04Data ),
- .Data05In( Hm05Data ),
- .Data06In( Hm06Data ),
- .Data07In( Hm07Data ),
- .Data08In( Hm08Data ),
- .Data09In( Hm09Data ),
- .Data10In( Hm10Data ),
- .Data11In( Hm11Data ),
- .Data12In( Hm12Data ),
- .Data13In( Hm13Data ),
- .Data14In( Hm14Data ),
- .Data15In( Hm15Data ),
- .Data16In( Hm16Data ),
- .Data17In( Hm17Data ),
- .Data18In( Hm18Data ),
- .Data19In( Hm19Data ),
- .Data20In( Hm20Data ),
- .Data21In( Hm21Data ),
- .Data22In( Hm22Data ),
- .Data23In( Hm23Data ),
- .Data24In( Hm24Data ),
- .Data25In( Hm25Data ),
- .Data26In( Hm26Data ),
- .Data27In( Hm27Data ),
- .Data28In( Hm28Data ),
- .Data29In( Hm29Data ),
- .Data30In( Hm30Data ),
- .Data31In( Hm31Data ),
- .Data32In( Hm32Data ),
- .Data33In( Hm33Data ),
- .Data34In( Hm34Data ),
- .Data35In( Hm35Data ),
- .Data36In( Hm36Data ),
- .Data37In( Hm37Data ),
- .Data38In( Hm38Data ),
- .Data39In( Hm39Data ),
- .Data40In( Hm40Data ),
- .Data41In( Hm41Data ),
- .Data42In( Hm42Data ),
- .Data43In( Hm43Data ),
- .Data44In( Hm44Data ),
- .Data45In( Hm45Data ),
- .Data46In( Hm46Data ),
- .Data47In( Hm47Data ),
- .Data48In( Hm48Data ),
- .Data49In( Hm49Data ),
- .Data50In( Hm50Data ),
- .Data51In( Hm51Data ),
- .Data52In( Hm52Data ),
- .Data53In( Hm53Data ),
- .Data54In( Hm54Data ),
- .Data55In( Hm55Data ),
- .Data56In( Hm56Data ),
- .Data57In( Hm57Data ),
- .Data58In( Hm58Data ),
- .Data59In( Hm59Data ),
- .Data60In( Hm60Data ),
- .Data61In( Hm61Data ),
- .Data62In( Hm62Data ),
- .Data63In( Hm63Data ),
- .DataInIdle( DctIdle ),
- .DataInRelease( HmDecRelase ),
-
- .DataOutEnable ( DctEnable ),
- .DataOutPage ( DctPage ),
- .DataOutCount ( DctCount ),
- .Data0Out ( Dct0Data ),
- .Data1Out ( Dct1Data )
- );
-
- wire ColorEnable;
- wire [15:0] ColorPixelX, ColorPixelY;
- wire [7:0] ColorR, ColorG, ColorB;
- jpeg_ycbcr u_jpeg_ycbcr(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable ( DctEnable ),
- .DataInPage ( DctPage ),
- .DataInCount ( DctCount ),
- .DataInIdle ( YCbCrIdle ),
- .Data0In ( Dct0Data ),
- .Data1In ( Dct1Data ),
- .DataInBlockWidth ( JpegBlockWidth ),
-
- .OutEnable ( ColorEnable ),
- .OutPixelX ( ColorPixelX ),
- .OutPixelY ( ColorPixelY ),
- .OutR ( ColorR ),
- .OutG ( ColorG ),
- .OutB ( ColorB )
- );
- // OutData
- assign OutEnable = (ImageEnable)?ColorEnable:1'b0;
- assign OutPixelX = (ImageEnable)?ColorPixelX:16'd0;
- assign OutPixelY = (ImageEnable)?ColorPixelY:16'd0;
- assign OutR = (ImageEnable)?ColorR:8'd0;
- assign OutG = (ImageEnable)?ColorG:8'd0;
- assign OutB = (ImageEnable)?ColorB:8'd0;
-
-endmodule // jpeg_decode
Index: trunk/src/jpeg_haffuman.v
===================================================================
--- trunk/src/jpeg_haffuman.v (revision 5)
+++ trunk/src/jpeg_haffuman.v (nonexistent)
@@ -1,404 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_haffuman.v
-// Module Name : jpeg_haffuman
-// Description : Haffuam top module
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_haffuman
- (
- rst,
- clk,
-
- // DQT Table
- DqtInEnable,
- DqtInColor,
- DqtInCount,
- DqtInData,
-
- // DHT Table
- DhtInEnable,
- DhtInColor,
- DhtInCount,
- DhtInData,
-
- // Haffuman Table
- HaffumanTableEnable, // Table Data In Enable
- HaffumanTableColor, // Haffuman Table Color Number
- HaffumanTableCount, // Table Number
- HaffumanTableCode, // Haffuman Table Code
- HaffumanTableStart, // Haffuman Table Start Number
-
- // Haffuman Decode
- DataInRun, // Data In Start
- DataInEnable, // Data In Enable
- DataIn, // Data In
-
- DecodeUseBit, // Used Data Bit
- DecodeUseWidth, // Used Data Width
-
- // Data Out
- DataOutIdle,
- DataOutEnable,
- DataOutColor,
- DataOutSel,
- Data00Reg,
- Data01Reg,
- Data02Reg,
- Data03Reg,
- Data04Reg,
- Data05Reg,
- Data06Reg,
- Data07Reg,
- Data08Reg,
- Data09Reg,
- Data10Reg,
- Data11Reg,
- Data12Reg,
- Data13Reg,
- Data14Reg,
- Data15Reg,
- Data16Reg,
- Data17Reg,
- Data18Reg,
- Data19Reg,
- Data20Reg,
- Data21Reg,
- Data22Reg,
- Data23Reg,
- Data24Reg,
- Data25Reg,
- Data26Reg,
- Data27Reg,
- Data28Reg,
- Data29Reg,
- Data30Reg,
- Data31Reg,
- Data32Reg,
- Data33Reg,
- Data34Reg,
- Data35Reg,
- Data36Reg,
- Data37Reg,
- Data38Reg,
- Data39Reg,
- Data40Reg,
- Data41Reg,
- Data42Reg,
- Data43Reg,
- Data44Reg,
- Data45Reg,
- Data46Reg,
- Data47Reg,
- Data48Reg,
- Data49Reg,
- Data50Reg,
- Data51Reg,
- Data52Reg,
- Data53Reg,
- Data54Reg,
- Data55Reg,
- Data56Reg,
- Data57Reg,
- Data58Reg,
- Data59Reg,
- Data60Reg,
- Data61Reg,
- Data62Reg,
- Data63Reg,
- DataOutRelease
-
- );
-
- input rst;
- input clk;
-
- // DQT Table
- input DqtInEnable;
- input DqtInColor;
- input [5:0] DqtInCount;
- input [7:0] DqtInData;
-
- // DHT Table
- input DhtInEnable;
- input [1:0] DhtInColor;
- input [7:0] DhtInCount;
- input [7:0] DhtInData;
-
- input HaffumanTableEnable; // Table Data In Enable
- input [1:0] HaffumanTableColor;
- input [3:0] HaffumanTableCount; // Table Number
- input [15:0] HaffumanTableCode; // Haffuman Table Data
- input [7:0] HaffumanTableStart; // Haffuman Table Start Number
-
- input DataInRun;
- input DataInEnable; // Data In Enable
- input [31:0] DataIn; // Data In
-
- output DecodeUseBit;
- output [6:0] DecodeUseWidth;
-
- // Data Out
- input DataOutIdle;
- output DataOutEnable;
- output [2:0] DataOutColor;
- input DataOutSel;
- output [15:0] Data00Reg;
- output [15:0] Data01Reg;
- output [15:0] Data02Reg;
- output [15:0] Data03Reg;
- output [15:0] Data04Reg;
- output [15:0] Data05Reg;
- output [15:0] Data06Reg;
- output [15:0] Data07Reg;
- output [15:0] Data08Reg;
- output [15:0] Data09Reg;
- output [15:0] Data10Reg;
- output [15:0] Data11Reg;
- output [15:0] Data12Reg;
- output [15:0] Data13Reg;
- output [15:0] Data14Reg;
- output [15:0] Data15Reg;
- output [15:0] Data16Reg;
- output [15:0] Data17Reg;
- output [15:0] Data18Reg;
- output [15:0] Data19Reg;
- output [15:0] Data20Reg;
- output [15:0] Data21Reg;
- output [15:0] Data22Reg;
- output [15:0] Data23Reg;
- output [15:0] Data24Reg;
- output [15:0] Data25Reg;
- output [15:0] Data26Reg;
- output [15:0] Data27Reg;
- output [15:0] Data28Reg;
- output [15:0] Data29Reg;
- output [15:0] Data30Reg;
- output [15:0] Data31Reg;
- output [15:0] Data32Reg;
- output [15:0] Data33Reg;
- output [15:0] Data34Reg;
- output [15:0] Data35Reg;
- output [15:0] Data36Reg;
- output [15:0] Data37Reg;
- output [15:0] Data38Reg;
- output [15:0] Data39Reg;
- output [15:0] Data40Reg;
- output [15:0] Data41Reg;
- output [15:0] Data42Reg;
- output [15:0] Data43Reg;
- output [15:0] Data44Reg;
- output [15:0] Data45Reg;
- output [15:0] Data46Reg;
- output [15:0] Data47Reg;
- output [15:0] Data48Reg;
- output [15:0] Data49Reg;
- output [15:0] Data50Reg;
- output [15:0] Data51Reg;
- output [15:0] Data52Reg;
- output [15:0] Data53Reg;
- output [15:0] Data54Reg;
- output [15:0] Data55Reg;
- output [15:0] Data56Reg;
- output [15:0] Data57Reg;
- output [15:0] Data58Reg;
- output [15:0] Data59Reg;
- output [15:0] Data60Reg;
- output [15:0] Data61Reg;
- output [15:0] Data62Reg;
- output [15:0] Data63Reg;
- input DataOutRelease;
-
- wire HmDqtColor;
- wire [5:0] HmDqtNumber;
- wire [7:0] HmDqtData;
-
- // DQT Table
- jpeg_dqt u_jpeg_dqt(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable ( DqtInEnable ),
- .DataInColor ( DqtInColor ),
- .DataInCount ( DqtInCount[5:0] ),
- .DataIn ( DqtInData ),
-
- .TableColor ( HmDqtColor ),
- .TableNumber ( HmDqtNumber ),
- .TableData ( HmDqtData )
- );
-
- wire [1:0] HmDhtColor;
- wire [7:0] HmDhtNumber;
- wire [3:0] HmDhtZero;
- wire [3:0] HmDhtWidth;
-
- jpeg_dht u_jpeg_dht(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable ( DhtInEnable ),
- .DataInColor ( DhtInColor ),
- .DataInCount ( DhtInCount ),
- .DataIn ( DhtInData ),
-
- .ColorNumber ( HmDhtColor ),
- .TableNumber ( HmDhtNumber ),
- .ZeroTable ( HmDhtZero ),
- .WidhtTable ( HmDhtWidth )
- );
-
- //wire [2:0] HmDecColor;
- wire [5:0] HmDecCount;
- wire [15:0] HmDecData;
-
- wire HmOutEnable;
- wire [2:0] HmOutColor;
-
- jpeg_hm_decode u_jpeg_hm_decode(
- .rst(rst),
- .clk(clk),
-
- // Haffuman Table
- .HaffumanTableEnable ( HaffumanTableEnable ),
- .HaffumanTableColor ( HaffumanTableColor ),
- .HaffumanTableCount ( HaffumanTableCount ),
- .HaffumanTableCode ( HaffumanTableCode ),
- .HaffumanTableStart ( HaffumanTableStart ),
-
- // Haffuman Decode
- .DataInRun ( DataInRun ),
- .DataInEnable ( DataInEnable ),
- .DataIn ( DataIn ),
-
- // Haffuman Table List
- .DhtColor ( HmDhtColor ),
- .DhtNumber ( HmDhtNumber ),
- .DhtZero ( HmDhtZero ),
- .DhtWidth ( HmDhtWidth ),
-
- // DQT Table
- .DqtColor ( HmDqtColor ),
- .DqtNumber ( HmDqtNumber ),
- .DqtData ( HmDqtData ),
-
- .DataOutIdle ( HmOutIdle ),
- .DataOutEnable ( HmOutEnable ),
- .DataOutColor ( HmOutColor ),
-
- // Output decode data
- .DecodeUseBit ( DecodeUseBit ),
- .DecodeUseWidth ( DecodeUseWidth ),
-
- .DecodeEnable ( HmDecEnable ),
- .DecodeColor ( ),
- .DecodeCount ( HmDecCount ),
- .DecodeZero ( ),
- .DecodeCode ( HmDecData )
- );
-
- wire BankARelease;
- wire BankBRelease;
-
- assign BankARelease = DataOutSel == 1'b0 & DataOutRelease;
- assign BankBRelease = DataOutSel == 1'b1 & DataOutRelease;
-
-
- jpeg_ziguzagu u_jpeg_ziguzagu(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable ( HmDecEnable ),
- .DataInAddress ( HmDecCount ),
- .DataInColor ( HmOutColor ),
- .DataInIdle ( HmOutIdle ),
- .DataIn ( HmDecData ),
-
- .HaffumanEndEnable(HmOutEnable),
-
- .DataOutEnable( DataOutEnable),
- .DataOutColor ( DataOutColor),
- .DataOutSel(DataOutSel),
- .Data00Reg( Data00Reg ),
- .Data01Reg( Data01Reg ),
- .Data02Reg( Data02Reg ),
- .Data03Reg( Data03Reg ),
- .Data04Reg( Data04Reg ),
- .Data05Reg( Data05Reg ),
- .Data06Reg( Data06Reg ),
- .Data07Reg( Data07Reg ),
- .Data08Reg( Data08Reg ),
- .Data09Reg( Data09Reg ),
- .Data10Reg( Data10Reg ),
- .Data11Reg( Data11Reg ),
- .Data12Reg( Data12Reg ),
- .Data13Reg( Data13Reg ),
- .Data14Reg( Data14Reg ),
- .Data15Reg( Data15Reg ),
- .Data16Reg( Data16Reg ),
- .Data17Reg( Data17Reg ),
- .Data18Reg( Data18Reg ),
- .Data19Reg( Data19Reg ),
- .Data20Reg( Data20Reg ),
- .Data21Reg( Data21Reg ),
- .Data22Reg( Data22Reg ),
- .Data23Reg( Data23Reg ),
- .Data24Reg( Data24Reg ),
- .Data25Reg( Data25Reg ),
- .Data26Reg( Data26Reg ),
- .Data27Reg( Data27Reg ),
- .Data28Reg( Data28Reg ),
- .Data29Reg( Data29Reg ),
- .Data30Reg( Data30Reg ),
- .Data31Reg( Data31Reg ),
- .Data32Reg( Data32Reg ),
- .Data33Reg( Data33Reg ),
- .Data34Reg( Data34Reg ),
- .Data35Reg( Data35Reg ),
- .Data36Reg( Data36Reg ),
- .Data37Reg( Data37Reg ),
- .Data38Reg( Data38Reg ),
- .Data39Reg( Data39Reg ),
- .Data40Reg( Data40Reg ),
- .Data41Reg( Data41Reg ),
- .Data42Reg( Data42Reg ),
- .Data43Reg( Data43Reg ),
- .Data44Reg( Data44Reg ),
- .Data45Reg( Data45Reg ),
- .Data46Reg( Data46Reg ),
- .Data47Reg( Data47Reg ),
- .Data48Reg( Data48Reg ),
- .Data49Reg( Data49Reg ),
- .Data50Reg( Data50Reg ),
- .Data51Reg( Data51Reg ),
- .Data52Reg( Data52Reg ),
- .Data53Reg( Data53Reg ),
- .Data54Reg( Data54Reg ),
- .Data55Reg( Data55Reg ),
- .Data56Reg( Data56Reg ),
- .Data57Reg( Data57Reg ),
- .Data58Reg( Data58Reg ),
- .Data59Reg( Data59Reg ),
- .Data60Reg( Data60Reg ),
- .Data61Reg( Data61Reg ),
- .Data62Reg( Data62Reg ),
- .Data63Reg( Data63Reg ),
-
- .BankARelease(BankARelease),
- .BankBRelease(BankBRelease)
- );
-
-endmodule // jpeg_haffuman
Index: trunk/src/jpeg_idctb.v
===================================================================
--- trunk/src/jpeg_idctb.v (revision 5)
+++ trunk/src/jpeg_idctb.v (nonexistent)
@@ -1,763 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_idctb.v
-// Module Name : jpeg_idctb
-// Description : data register for iDCT
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_idctb
- (
- rst,
- clk,
-
- DataInEnable,
- DataInPage,
- DataInCount,
- DataInIdle,
- Data0In,
- Data1In,
-
- DataOutEnable,
- DataOutSel,
- Data00Out,
- Data01Out,
- Data02Out,
- Data03Out,
- Data04Out,
- Data05Out,
- Data06Out,
- Data07Out,
- Data08Out,
- Data09Out,
- Data10Out,
- Data11Out,
- Data12Out,
- Data13Out,
- Data14Out,
- Data15Out,
- Data16Out,
- Data17Out,
- Data18Out,
- Data19Out,
- Data20Out,
- Data21Out,
- Data22Out,
- Data23Out,
- Data24Out,
- Data25Out,
- Data26Out,
- Data27Out,
- Data28Out,
- Data29Out,
- Data30Out,
- Data31Out,
- Data32Out,
- Data33Out,
- Data34Out,
- Data35Out,
- Data36Out,
- Data37Out,
- Data38Out,
- Data39Out,
- Data40Out,
- Data41Out,
- Data42Out,
- Data43Out,
- Data44Out,
- Data45Out,
- Data46Out,
- Data47Out,
- Data48Out,
- Data49Out,
- Data50Out,
- Data51Out,
- Data52Out,
- Data53Out,
- Data54Out,
- Data55Out,
- Data56Out,
- Data57Out,
- Data58Out,
- Data59Out,
- Data60Out,
- Data61Out,
- Data62Out,
- Data63Out,
-
- BankARelease,
- BankBRelease
- );
-
- input clk;
- input rst;
-
- input DataInEnable;
- input [2:0] DataInPage;
- input [1:0] DataInCount;
- output DataInIdle;
- input [15:0] Data0In;
- input [15:0] Data1In;
-
- output DataOutEnable;
- input DataOutSel;
- output [15:0] Data00Out;
- output [15:0] Data01Out;
- output [15:0] Data02Out;
- output [15:0] Data03Out;
- output [15:0] Data04Out;
- output [15:0] Data05Out;
- output [15:0] Data06Out;
- output [15:0] Data07Out;
- output [15:0] Data08Out;
- output [15:0] Data09Out;
- output [15:0] Data10Out;
- output [15:0] Data11Out;
- output [15:0] Data12Out;
- output [15:0] Data13Out;
- output [15:0] Data14Out;
- output [15:0] Data15Out;
- output [15:0] Data16Out;
- output [15:0] Data17Out;
- output [15:0] Data18Out;
- output [15:0] Data19Out;
- output [15:0] Data20Out;
- output [15:0] Data21Out;
- output [15:0] Data22Out;
- output [15:0] Data23Out;
- output [15:0] Data24Out;
- output [15:0] Data25Out;
- output [15:0] Data26Out;
- output [15:0] Data27Out;
- output [15:0] Data28Out;
- output [15:0] Data29Out;
- output [15:0] Data30Out;
- output [15:0] Data31Out;
- output [15:0] Data32Out;
- output [15:0] Data33Out;
- output [15:0] Data34Out;
- output [15:0] Data35Out;
- output [15:0] Data36Out;
- output [15:0] Data37Out;
- output [15:0] Data38Out;
- output [15:0] Data39Out;
- output [15:0] Data40Out;
- output [15:0] Data41Out;
- output [15:0] Data42Out;
- output [15:0] Data43Out;
- output [15:0] Data44Out;
- output [15:0] Data45Out;
- output [15:0] Data46Out;
- output [15:0] Data47Out;
- output [15:0] Data48Out;
- output [15:0] Data49Out;
- output [15:0] Data50Out;
- output [15:0] Data51Out;
- output [15:0] Data52Out;
- output [15:0] Data53Out;
- output [15:0] Data54Out;
- output [15:0] Data55Out;
- output [15:0] Data56Out;
- output [15:0] Data57Out;
- output [15:0] Data58Out;
- output [15:0] Data59Out;
- output [15:0] Data60Out;
- output [15:0] Data61Out;
- output [15:0] Data62Out;
- output [15:0] Data63Out;
-
- input BankARelease;
- input BankBRelease;
-
- reg BankAEnable;
- reg BankBEnable;
- reg DataInBank;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- BankAEnable <= 1'b0;
- BankBEnable <= 1'b0;
- DataInBank <= 1'b0;
- end else begin
- if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
- if(DataInEnable == 1'b1 &
- DataInPage == 3'd7 & DataInCount == 2'd3) begin
- BankAEnable <= 1'b1;
- end
- end else begin
- if(BankARelease == 1'b1) begin
- BankAEnable <= 1'b0;
- end
- end
- if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
- if(DataInEnable == 1'b1 &
- DataInPage == 3'd7 & DataInCount == 2'd3) begin
- BankBEnable <= 1'b1;
- end
- end else begin
- if(BankBRelease == 1'b1) begin
- BankBEnable <= 1'b0;
- end
- end
- if(DataInEnable == 1'b1 &
- DataInPage == 3'd7 & DataInCount == 2'd3) begin
- DataInBank <= ~DataInBank;
- end
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;
-
- assign DataOutEnable = DataInEnable == 1'b1 & DataInPage == 3'b111 &
- DataInCount == 2'b11;
-
- reg [15:0] BankAReg [0:63];
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- BankAReg[0] <= 12'h000;
- BankAReg[1] <= 12'h000;
- BankAReg[2] <= 12'h000;
- BankAReg[3] <= 12'h000;
- BankAReg[4] <= 12'h000;
- BankAReg[5] <= 12'h000;
- BankAReg[6] <= 12'h000;
- BankAReg[7] <= 12'h000;
- BankAReg[8] <= 12'h000;
- BankAReg[9] <= 12'h000;
- BankAReg[10] <= 12'h000;
- BankAReg[11] <= 12'h000;
- BankAReg[12] <= 12'h000;
- BankAReg[13] <= 12'h000;
- BankAReg[14] <= 12'h000;
- BankAReg[15] <= 12'h000;
- BankAReg[16] <= 12'h000;
- BankAReg[17] <= 12'h000;
- BankAReg[18] <= 12'h000;
- BankAReg[19] <= 12'h000;
- BankAReg[20] <= 12'h000;
- BankAReg[21] <= 12'h000;
- BankAReg[22] <= 12'h000;
- BankAReg[23] <= 12'h000;
- BankAReg[24] <= 12'h000;
- BankAReg[25] <= 12'h000;
- BankAReg[26] <= 12'h000;
- BankAReg[27] <= 12'h000;
- BankAReg[28] <= 12'h000;
- BankAReg[29] <= 12'h000;
- BankAReg[30] <= 12'h000;
- BankAReg[31] <= 12'h000;
- BankAReg[32] <= 12'h000;
- BankAReg[33] <= 12'h000;
- BankAReg[34] <= 12'h000;
- BankAReg[35] <= 12'h000;
- BankAReg[36] <= 12'h000;
- BankAReg[37] <= 12'h000;
- BankAReg[38] <= 12'h000;
- BankAReg[39] <= 12'h000;
- BankAReg[40] <= 12'h000;
- BankAReg[41] <= 12'h000;
- BankAReg[42] <= 12'h000;
- BankAReg[43] <= 12'h000;
- BankAReg[44] <= 12'h000;
- BankAReg[45] <= 12'h000;
- BankAReg[46] <= 12'h000;
- BankAReg[47] <= 12'h000;
- BankAReg[48] <= 12'h000;
- BankAReg[49] <= 12'h000;
- BankAReg[50] <= 12'h000;
- BankAReg[51] <= 12'h000;
- BankAReg[52] <= 12'h000;
- BankAReg[53] <= 12'h000;
- BankAReg[54] <= 12'h000;
- BankAReg[55] <= 12'h000;
- BankAReg[56] <= 12'h000;
- BankAReg[57] <= 12'h000;
- BankAReg[58] <= 12'h000;
- BankAReg[59] <= 12'h000;
- BankAReg[60] <= 12'h000;
- BankAReg[61] <= 12'h000;
- BankAReg[62] <= 12'h000;
- BankAReg[63] <= 12'h000;
- end else begin // if (!rst)
- if(DataInEnable == 1'b1 & DataInBank == 1'b0) begin
- case(DataInPage)
- 3'd0: begin
- case(DataInCount)
- 2'd0: begin
- BankAReg[0] <= Data0In;
- BankAReg[7] <= Data1In;
- end
- 2'd1: begin
- BankAReg[1] <= Data0In;
- BankAReg[6] <= Data1In;
- end
- 2'd2: begin
- BankAReg[2] <= Data0In;
- BankAReg[5] <= Data1In;
- end
- 2'd3: begin
- BankAReg[3] <= Data0In;
- BankAReg[4] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd0
- 3'd1: begin
- case(DataInCount)
- 2'd0: begin
- BankAReg[8] <= Data0In;
- BankAReg[15] <= Data1In;
- end
- 2'd1: begin
- BankAReg[9] <= Data0In;
- BankAReg[14] <= Data1In;
- end
- 2'd2: begin
- BankAReg[10] <= Data0In;
- BankAReg[13] <= Data1In;
- end
- 2'd3: begin
- BankAReg[11] <= Data0In;
- BankAReg[12] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd1
- 3'd2: begin
- case(DataInCount)
- 2'd0: begin
- BankAReg[16] <= Data0In;
- BankAReg[23] <= Data1In;
- end
- 2'd1: begin
- BankAReg[17] <= Data0In;
- BankAReg[22] <= Data1In;
- end
- 2'd2: begin
- BankAReg[18] <= Data0In;
- BankAReg[21] <= Data1In;
- end
- 2'd3: begin
- BankAReg[19] <= Data0In;
- BankAReg[20] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd2
- 3'd3: begin
- case(DataInCount)
- 2'd0: begin
- BankAReg[24] <= Data0In;
- BankAReg[31] <= Data1In;
- end
- 2'd1: begin
- BankAReg[25] <= Data0In;
- BankAReg[30] <= Data1In;
- end
- 2'd2: begin
- BankAReg[26] <= Data0In;
- BankAReg[29] <= Data1In;
- end
- 2'd3: begin
- BankAReg[27] <= Data0In;
- BankAReg[28] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd3
- 3'd4: begin
- case(DataInCount)
- 2'd0: begin
- BankAReg[32] <= Data0In;
- BankAReg[39] <= Data1In;
- end
- 2'd1: begin
- BankAReg[33] <= Data0In;
- BankAReg[38] <= Data1In;
- end
- 2'd2: begin
- BankAReg[34] <= Data0In;
- BankAReg[37] <= Data1In;
- end
- 2'd3: begin
- BankAReg[35] <= Data0In;
- BankAReg[36] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd4
- 3'd5: begin
- case(DataInCount)
- 2'd0: begin
- BankAReg[40] <= Data0In;
- BankAReg[47] <= Data1In;
- end
- 2'd1: begin
- BankAReg[41] <= Data0In;
- BankAReg[46] <= Data1In;
- end
- 2'd2: begin
- BankAReg[42] <= Data0In;
- BankAReg[45] <= Data1In;
- end
- 2'd3: begin
- BankAReg[43] <= Data0In;
- BankAReg[44] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd5
- 3'd6: begin
- case(DataInCount)
- 2'd0: begin
- BankAReg[48] <= Data0In;
- BankAReg[55] <= Data1In;
- end
- 2'd1: begin
- BankAReg[49] <= Data0In;
- BankAReg[54] <= Data1In;
- end
- 2'd2: begin
- BankAReg[50] <= Data0In;
- BankAReg[53] <= Data1In;
- end
- 2'd3: begin
- BankAReg[51] <= Data0In;
- BankAReg[52] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd6
- 3'd7: begin
- case(DataInCount)
- 2'd0: begin
- BankAReg[56] <= Data0In;
- BankAReg[63] <= Data1In;
- end
- 2'd1: begin
- BankAReg[57] <= Data0In;
- BankAReg[62] <= Data1In;
- end
- 2'd2: begin
- BankAReg[58] <= Data0In;
- BankAReg[61] <= Data1In;
- end
- 2'd3: begin
- BankAReg[59] <= Data0In;
- BankAReg[60] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd7
- endcase // case(DataInPage)
- end // if (DataInEnable == 1'b1 & DataInBank == 1'b0)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- reg [15:0] BankBReg [0:63];
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- BankBReg[0] <= 12'h000;
- BankBReg[1] <= 12'h000;
- BankBReg[2] <= 12'h000;
- BankBReg[3] <= 12'h000;
- BankBReg[4] <= 12'h000;
- BankBReg[5] <= 12'h000;
- BankBReg[6] <= 12'h000;
- BankBReg[7] <= 12'h000;
- BankBReg[8] <= 12'h000;
- BankBReg[9] <= 12'h000;
- BankBReg[10] <= 12'h000;
- BankBReg[11] <= 12'h000;
- BankBReg[12] <= 12'h000;
- BankBReg[13] <= 12'h000;
- BankBReg[14] <= 12'h000;
- BankBReg[15] <= 12'h000;
- BankBReg[16] <= 12'h000;
- BankBReg[17] <= 12'h000;
- BankBReg[18] <= 12'h000;
- BankBReg[19] <= 12'h000;
- BankBReg[20] <= 12'h000;
- BankBReg[21] <= 12'h000;
- BankBReg[22] <= 12'h000;
- BankBReg[23] <= 12'h000;
- BankBReg[24] <= 12'h000;
- BankBReg[25] <= 12'h000;
- BankBReg[26] <= 12'h000;
- BankBReg[27] <= 12'h000;
- BankBReg[28] <= 12'h000;
- BankBReg[29] <= 12'h000;
- BankBReg[30] <= 12'h000;
- BankBReg[31] <= 12'h000;
- BankBReg[32] <= 12'h000;
- BankBReg[33] <= 12'h000;
- BankBReg[34] <= 12'h000;
- BankBReg[35] <= 12'h000;
- BankBReg[36] <= 12'h000;
- BankBReg[37] <= 12'h000;
- BankBReg[38] <= 12'h000;
- BankBReg[39] <= 12'h000;
- BankBReg[40] <= 12'h000;
- BankBReg[41] <= 12'h000;
- BankBReg[42] <= 12'h000;
- BankBReg[43] <= 12'h000;
- BankBReg[44] <= 12'h000;
- BankBReg[45] <= 12'h000;
- BankBReg[46] <= 12'h000;
- BankBReg[47] <= 12'h000;
- BankBReg[48] <= 12'h000;
- BankBReg[49] <= 12'h000;
- BankBReg[50] <= 12'h000;
- BankBReg[51] <= 12'h000;
- BankBReg[52] <= 12'h000;
- BankBReg[53] <= 12'h000;
- BankBReg[54] <= 12'h000;
- BankBReg[55] <= 12'h000;
- BankBReg[56] <= 12'h000;
- BankBReg[57] <= 12'h000;
- BankBReg[58] <= 12'h000;
- BankBReg[59] <= 12'h000;
- BankBReg[60] <= 12'h000;
- BankBReg[61] <= 12'h000;
- BankBReg[62] <= 12'h000;
- BankBReg[63] <= 12'h000;
- end else begin // if (!rst)
- if(DataInEnable == 1'b1 & DataInBank == 1'b1) begin
- case(DataInPage)
- 3'd0: begin
- case(DataInCount)
- 2'd0: begin
- BankBReg[0] <= Data0In;
- BankBReg[7] <= Data1In;
- end
- 2'd1: begin
- BankBReg[1] <= Data0In;
- BankBReg[6] <= Data1In;
- end
- 2'd2: begin
- BankBReg[2] <= Data0In;
- BankBReg[5] <= Data1In;
- end
- 2'd3: begin
- BankBReg[3] <= Data0In;
- BankBReg[4] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd0
- 3'd1: begin
- case(DataInCount)
- 2'd0: begin
- BankBReg[8] <= Data0In;
- BankBReg[15] <= Data1In;
- end
- 2'd1: begin
- BankBReg[9] <= Data0In;
- BankBReg[14] <= Data1In;
- end
- 2'd2: begin
- BankBReg[10] <= Data0In;
- BankBReg[13] <= Data1In;
- end
- 2'd3: begin
- BankBReg[11] <= Data0In;
- BankBReg[12] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd1
- 3'd2: begin
- case(DataInCount)
- 2'd0: begin
- BankBReg[16] <= Data0In;
- BankBReg[23] <= Data1In;
- end
- 2'd1: begin
- BankBReg[17] <= Data0In;
- BankBReg[22] <= Data1In;
- end
- 2'd2: begin
- BankBReg[18] <= Data0In;
- BankBReg[21] <= Data1In;
- end
- 2'd3: begin
- BankBReg[19] <= Data0In;
- BankBReg[20] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd2
- 3'd3: begin
- case(DataInCount)
- 2'd0: begin
- BankBReg[24] <= Data0In;
- BankBReg[31] <= Data1In;
- end
- 2'd1: begin
- BankBReg[25] <= Data0In;
- BankBReg[30] <= Data1In;
- end
- 2'd2: begin
- BankBReg[26] <= Data0In;
- BankBReg[29] <= Data1In;
- end
- 2'd3: begin
- BankBReg[27] <= Data0In;
- BankBReg[28] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd3
- 3'd4: begin
- case(DataInCount)
- 2'd0: begin
- BankBReg[32] <= Data0In;
- BankBReg[39] <= Data1In;
- end
- 2'd1: begin
- BankBReg[33] <= Data0In;
- BankBReg[38] <= Data1In;
- end
- 2'd2: begin
- BankBReg[34] <= Data0In;
- BankBReg[37] <= Data1In;
- end
- 2'd3: begin
- BankBReg[35] <= Data0In;
- BankBReg[36] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd4
- 3'd5: begin
- case(DataInCount)
- 2'd0: begin
- BankBReg[40] <= Data0In;
- BankBReg[47] <= Data1In;
- end
- 2'd1: begin
- BankBReg[41] <= Data0In;
- BankBReg[46] <= Data1In;
- end
- 2'd2: begin
- BankBReg[42] <= Data0In;
- BankBReg[45] <= Data1In;
- end
- 2'd3: begin
- BankBReg[43] <= Data0In;
- BankBReg[44] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd5
- 3'd6: begin
- case(DataInCount)
- 2'd0: begin
- BankBReg[48] <= Data0In;
- BankBReg[55] <= Data1In;
- end
- 2'd1: begin
- BankBReg[49] <= Data0In;
- BankBReg[54] <= Data1In;
- end
- 2'd2: begin
- BankBReg[50] <= Data0In;
- BankBReg[53] <= Data1In;
- end
- 2'd3: begin
- BankBReg[51] <= Data0In;
- BankBReg[52] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd6
- 3'd7: begin
- case(DataInCount)
- 2'd0: begin
- BankBReg[56] <= Data0In;
- BankBReg[63] <= Data1In;
- end
- 2'd1: begin
- BankBReg[57] <= Data0In;
- BankBReg[62] <= Data1In;
- end
- 2'd2: begin
- BankBReg[58] <= Data0In;
- BankBReg[61] <= Data1In;
- end
- 2'd3: begin
- BankBReg[59] <= Data0In;
- BankBReg[60] <= Data1In;
- end
- endcase // case(DataInCount)
- end // case: 3'd7
- endcase // case(DataInPage)
- end // if (DataInEnable == 1'b1 & DataInBank == 1'b1)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign Data00Out = (DataOutSel)?BankBReg[00]:BankAReg[00];
- assign Data01Out = (DataOutSel)?BankBReg[08]:BankAReg[08];
- assign Data02Out = (DataOutSel)?BankBReg[16]:BankAReg[16];
- assign Data03Out = (DataOutSel)?BankBReg[24]:BankAReg[24];
- assign Data04Out = (DataOutSel)?BankBReg[32]:BankAReg[32];
- assign Data05Out = (DataOutSel)?BankBReg[40]:BankAReg[40];
- assign Data06Out = (DataOutSel)?BankBReg[48]:BankAReg[48];
- assign Data07Out = (DataOutSel)?BankBReg[56]:BankAReg[56];
- assign Data08Out = (DataOutSel)?BankBReg[01]:BankAReg[01];
- assign Data09Out = (DataOutSel)?BankBReg[09]:BankAReg[09];
- assign Data10Out = (DataOutSel)?BankBReg[17]:BankAReg[17];
- assign Data11Out = (DataOutSel)?BankBReg[25]:BankAReg[25];
- assign Data12Out = (DataOutSel)?BankBReg[33]:BankAReg[33];
- assign Data13Out = (DataOutSel)?BankBReg[41]:BankAReg[41];
- assign Data14Out = (DataOutSel)?BankBReg[49]:BankAReg[49];
- assign Data15Out = (DataOutSel)?BankBReg[57]:BankAReg[57];
- assign Data16Out = (DataOutSel)?BankBReg[02]:BankAReg[02];
- assign Data17Out = (DataOutSel)?BankBReg[10]:BankAReg[10];
- assign Data18Out = (DataOutSel)?BankBReg[18]:BankAReg[18];
- assign Data19Out = (DataOutSel)?BankBReg[26]:BankAReg[26];
- assign Data20Out = (DataOutSel)?BankBReg[34]:BankAReg[34];
- assign Data21Out = (DataOutSel)?BankBReg[42]:BankAReg[42];
- assign Data22Out = (DataOutSel)?BankBReg[50]:BankAReg[50];
- assign Data23Out = (DataOutSel)?BankBReg[58]:BankAReg[58];
- assign Data24Out = (DataOutSel)?BankBReg[03]:BankAReg[03];
- assign Data25Out = (DataOutSel)?BankBReg[11]:BankAReg[11];
- assign Data26Out = (DataOutSel)?BankBReg[19]:BankAReg[19];
- assign Data27Out = (DataOutSel)?BankBReg[27]:BankAReg[27];
- assign Data28Out = (DataOutSel)?BankBReg[35]:BankAReg[35];
- assign Data29Out = (DataOutSel)?BankBReg[43]:BankAReg[43];
- assign Data30Out = (DataOutSel)?BankBReg[51]:BankAReg[51];
- assign Data31Out = (DataOutSel)?BankBReg[59]:BankAReg[59];
- assign Data32Out = (DataOutSel)?BankBReg[04]:BankAReg[04];
- assign Data33Out = (DataOutSel)?BankBReg[12]:BankAReg[12];
- assign Data34Out = (DataOutSel)?BankBReg[20]:BankAReg[20];
- assign Data35Out = (DataOutSel)?BankBReg[28]:BankAReg[28];
- assign Data36Out = (DataOutSel)?BankBReg[36]:BankAReg[36];
- assign Data37Out = (DataOutSel)?BankBReg[44]:BankAReg[44];
- assign Data38Out = (DataOutSel)?BankBReg[52]:BankAReg[52];
- assign Data39Out = (DataOutSel)?BankBReg[60]:BankAReg[60];
- assign Data40Out = (DataOutSel)?BankBReg[05]:BankAReg[05];
- assign Data41Out = (DataOutSel)?BankBReg[13]:BankAReg[13];
- assign Data42Out = (DataOutSel)?BankBReg[21]:BankAReg[21];
- assign Data43Out = (DataOutSel)?BankBReg[29]:BankAReg[29];
- assign Data44Out = (DataOutSel)?BankBReg[37]:BankAReg[37];
- assign Data45Out = (DataOutSel)?BankBReg[45]:BankAReg[45];
- assign Data46Out = (DataOutSel)?BankBReg[53]:BankAReg[53];
- assign Data47Out = (DataOutSel)?BankBReg[61]:BankAReg[61];
- assign Data48Out = (DataOutSel)?BankBReg[06]:BankAReg[06];
- assign Data49Out = (DataOutSel)?BankBReg[14]:BankAReg[14];
- assign Data50Out = (DataOutSel)?BankBReg[22]:BankAReg[22];
- assign Data51Out = (DataOutSel)?BankBReg[30]:BankAReg[30];
- assign Data52Out = (DataOutSel)?BankBReg[38]:BankAReg[38];
- assign Data53Out = (DataOutSel)?BankBReg[46]:BankAReg[46];
- assign Data54Out = (DataOutSel)?BankBReg[54]:BankAReg[54];
- assign Data55Out = (DataOutSel)?BankBReg[62]:BankAReg[62];
- assign Data56Out = (DataOutSel)?BankBReg[07]:BankAReg[07];
- assign Data57Out = (DataOutSel)?BankBReg[15]:BankAReg[15];
- assign Data58Out = (DataOutSel)?BankBReg[23]:BankAReg[23];
- assign Data59Out = (DataOutSel)?BankBReg[31]:BankAReg[31];
- assign Data60Out = (DataOutSel)?BankBReg[39]:BankAReg[39];
- assign Data61Out = (DataOutSel)?BankBReg[47]:BankAReg[47];
- assign Data62Out = (DataOutSel)?BankBReg[55]:BankAReg[55];
- assign Data63Out = (DataOutSel)?BankBReg[63]:BankAReg[63];
-
-endmodule // jpeg_idctb
Index: trunk/src/jpeg_dqt.v
===================================================================
--- trunk/src/jpeg_dqt.v (revision 5)
+++ trunk/src/jpeg_dqt.v (nonexistent)
@@ -1,76 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_dqt.v
-// Module Name : jpeg_dqt
-// Description : DQT spcae
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_dqt
- (
- rst,
- clk,
-
- DataInEnable,
- DataInColor,
- DataInCount,
- DataIn,
-
- TableColor,
- TableNumber,
- TableData
- );
-
- input rst;
- input clk;
-
- input DataInEnable;
- input DataInColor;
- input [5:0] DataInCount;
- input [7:0] DataIn;
-
- input TableColor;
- input [5:0] TableNumber;
- output [7:0] TableData;
-
- // RAM
- reg [7:0] DQT_Y [0:63];
- reg [7:0] DQT_C [0:63];
-
- // RAM
- always @(posedge clk)
- begin
- if(DataInEnable ==1'b1 && DataInColor ==1'b0) begin
- DQT_Y[DataInCount] <= DataIn;
- end
- if(DataInEnable ==1'b1 && DataInColor ==1'b1) begin
- DQT_C[DataInCount] <= DataIn;
- end
- end
-
- reg [7:0] TableDataY;
- reg [7:0] TableDataC;
-
- // RAM out
- always @(posedge clk) begin
- TableDataY <= DQT_Y[TableNumber];
- TableDataC <= DQT_C[TableNumber];
- end
-
- // Selector
- assign TableData = (TableColor)?TableDataC:TableDataY;
-
-endmodule // jpeg_dqt
-
Index: trunk/src/jpeg_decode_fsm.v
===================================================================
--- trunk/src/jpeg_decode_fsm.v (revision 5)
+++ trunk/src/jpeg_decode_fsm.v (nonexistent)
@@ -1,640 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_decode_fsm.v
-// Module Name : jpeg_decode_fsm
-// Description : Decode Maker
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2007/04/11
-// Rev. : 1.03
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-// 1.02 2006/10/04 Remove a HmOldData register.
-// When reset, clear a ReadDqtTable register.
-// 1.03 2007/04/11 Remove JpegDecodeStart
-// Exchange StateMachine(Add ImageData)
-// Remove JpegDecodeStart
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_decode_fsm
- (
- rst,
- clk,
-
- // From FIFO
- DataInEnable,
- DataIn,
-
- JpegDecodeIdle, // Deocdeer Process Idle(1:Idle, 0:Run)
-
- OutWidth,
- OutHeight,
- OutBlockWidth,
- OutEnable,
- OutPixelX,
- OutPixelY,
-
- //
- DqtEnable,
- DqtTable,
- DqtCount,
- DqtData,
-
- //
- DhtEnable,
- DhtTable,
- DhtCount,
- DhtData,
-
- //
- HaffumanEnable,
- HaffumanTable,
- HaffumanCount,
- HaffumanData,
- HaffumanStart,
-
- //
- ImageEnable,
- ImageEnd,
- EnableFF00,
-
- //
- UseByte,
- UseWord
- );
-
- input rst;
- input clk;
-
- input DataInEnable;
- input [31:0] DataIn;
-
- output JpegDecodeIdle;
-
- output [15:0] OutWidth;
- output [15:0] OutHeight;
- output [11:0] OutBlockWidth;
- input OutEnable;
- input [15:0] OutPixelX;
- input [15:0] OutPixelY;
-
- output DqtEnable;
- output DqtTable;
- output [5:0] DqtCount;
- output [7:0] DqtData;
-
- output DhtEnable;
- output [1:0] DhtTable;
- output [7:0] DhtCount;
- output [7:0] DhtData;
-
- //
- output HaffumanEnable;
- output [1:0] HaffumanTable;
- output [3:0] HaffumanCount;
- output [15:0] HaffumanData;
- output [7:0] HaffumanStart;
-
- //
- output ImageEnable;
- input ImageEnd;
- output EnableFF00;
-
- //
- output UseByte;
- output UseWord;
-
-
- //--------------------------------------------------------------------------
- // Read Maker from Jpeg Data
- //--------------------------------------------------------------------------
- reg [1:0] State;
- reg [3:0] Process;
- wire StateReadByte;
- wire StateReadWord;
- wire ImageEnable;
-
- wire ReadSegmentEnd;
-
- parameter Idle = 2'b00;
- parameter GetMarker = 2'b01;
- parameter ReadSegment = 2'b10;
- parameter ImageData = 2'b11;
-
- parameter NoProcess = 4'h0;
- parameter SegSOI = 4'h1;
- parameter SegAPP = 4'h2;
- parameter SegDQT = 4'h3;
- parameter SegDHT = 4'h4;
- parameter SegSOF0 = 4'h5;
- parameter SegSOS = 4'h6;
- parameter SegDRI = 4'h7;
- parameter SegRST = 4'h8;
- parameter SegEOI = 4'h9;
-
- reg [15:0] JpegWidth;
- reg [15:0] JpegHeight;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- State <= Idle;
- Process <= NoProcess;
- end else begin
- case(State)
- Idle: begin
- if(DataInEnable == 1'b1) begin
- State <= GetMarker;
- end
- Process <= NoProcess;
- end
- GetMarker: begin
- if(DataInEnable == 1'b1) begin
- State <= ReadSegment;
- case(DataIn[31:16])
- 16'hFFD8: begin // SOI Segment
- Process <= SegSOI;
- end
- 16'hFFE0: begin // APP0 Segment
- Process <= SegAPP;
- end
- 16'hFFDB: begin // DQT Segment
- Process <= SegDQT;
- end
- 16'hFFC4: begin // DHT Segment
- Process <= SegDHT;
- end
- 16'hFFC0: begin // SOF0 Segment
- Process <= SegSOF0;
- end
- 16'hFFDA: begin // SOS Segment
- Process <= SegSOS;
- end
- //16'hFFDD: begin // DRI Segment
- // Process <= SegDRI;
- //end
- //16'hFFDx: begin // RSTn Segment
- // Process <= SegRST;
- //end
- //16'hFFD9: begin // EOI Segment
- // Process <= SegEOI;
- //end
- default: begin
- Process <= SegAPP;
- end
- endcase
- end
- end
- ReadSegment: begin
- if(ReadSegmentEnd == 1'b1) begin
- Process <= NoProcess;
- if(Process == SegSOS) begin
- State <= ImageData;
- end else begin
- State <= GetMarker;
- end
- end
- end
- ImageData: begin
- if(OutEnable & (JpegWidth == OutPixelX +1) & (JpegHeight == OutPixelY +1)) begin
- State <= Idle;
- end
- end
- endcase
- end
- end
-
- assign JpegDecodeIdle = (State == Idle);
- assign StateReadByte = 1'b0;
- assign StateReadWord = ((State == GetMarker) & (DataInEnable == 1'b1));
- assign ImageEnable = (State == ImageData);
-
- wire ReadNopEnd;
-
- assign ReadNopEnd = ((Process == SegSOI) | (Process == SegRST));
-
- //--------------------------------------------------------------------------
- // APP Segment
- // Skip read data!
- //--------------------------------------------------------------------------
-
- reg [1:0] StateAPP;
- reg [15:0] ReadAppCount;
- wire ReadAppByte;
- wire ReadAppWord;
- wire ReadAppEnd;
-
- parameter AppIdle = 2'd0;
- parameter AppLength = 2'd1;
- parameter AppRead = 2'd2;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- StateAPP <= AppIdle;
- ReadAppCount <= 16'd0;
- end else begin
- case(StateAPP)
- AppIdle: begin
- if(Process == SegAPP) StateAPP <= AppLength;
- ReadAppCount <= 16'd0;
- end
- AppLength: begin
- if(DataInEnable == 1'b1) begin
- ReadAppCount <= DataIn[31:16] -2;
- StateAPP <= AppRead;
- end
- end
- AppRead: begin
- if(DataInEnable == 1'b1) begin
- if(ReadAppCount == 1) begin
- StateAPP <= AppIdle;
- end else begin
- ReadAppCount <= ReadAppCount -1;
- end
- end
- end
- endcase
- end
- end
- assign ReadAppByte = (StateAPP == AppRead);
- assign ReadAppWord = (StateAPP == AppLength);
- assign ReadAppEnd = ((StateAPP == AppRead) & (DataInEnable == 1'b1) & (ReadAppCount == 1));
-
- //--------------------------------------------------------------------------
- // DQT Segment
- //--------------------------------------------------------------------------
-
- reg [1:0] StateDQT;
- reg [15:0] ReadDqtCount;
- wire ReadDqtByte;
- wire ReadDqtWord;
- wire ReadDqtEnd;
- wire ReadDqtEnable;
- wire [7:0] ReadDqtData;
- reg ReadDqtTable;
-
- parameter DQTIdle = 2'b00;
- parameter DQTLength = 2'b01;
- parameter DQTTable = 2'b10;
- parameter DQTRead = 2'b11;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- StateDQT <= DQTIdle;
- ReadDqtCount <= 16'h0000;
- ReadDqtTable <= 1'b0;
- end else begin
- case(StateDQT)
- DQTIdle: begin
- if(Process == SegDQT) begin
- StateDQT <= DQTLength;
- end
- ReadDqtCount <= 16'h0000;
- end
- DQTLength: begin
- if(DataInEnable == 1'b1) begin
- StateDQT <= DQTTable;
- ReadDqtCount <= DataIn[31:16] -2;
- end
- end
- DQTTable: begin
- if(DataInEnable == 1'b1) begin
- StateDQT <= DQTRead;
- ReadDqtTable <= DataIn[24];
- ReadDqtCount <= 16'd0;
- end
- end
- DQTRead: begin
- if(DataInEnable == 1'b1) begin
- if(ReadDqtCount ==63) begin
- StateDQT <= DQTIdle;
- end
- ReadDqtCount <= ReadDqtCount +1;
- end
- end
- endcase
- end
- end
-
- assign ReadDqtEnable = StateDQT == DQTRead;
- assign ReadDqtData = DataIn[31:24];
-
- assign ReadDqtByte = StateDQT == DQTRead | StateDQT == DQTTable;
- assign ReadDqtWord = StateDQT == DQTLength;
- assign ReadDqtEnd = StateDQT == DQTRead & DataInEnable == 1'b1 & ReadDqtCount ==63;
-
- //--------------------------------------------------------------------------
- // DHT Segment
- //--------------------------------------------------------------------------
- reg [2:0] StateDHT;
- reg [15:0] ReadDhtCount;
- wire ReadDhtByte;
- wire ReadDhtWord;
- wire ReadDhtEnd;
- wire ReadDhtEnable;
- wire [7:0] ReadDhtData;
- reg [1:0] ReadDhtTable;
-
- reg [15:0] HmShift;
- reg [15:0] HmData;
- reg [7:0] HmMax;
- reg [7:0] HmCount;
- reg HmEnable;
-
- parameter DHTIdle = 3'h0;
- parameter DHTLength = 3'h1;
- parameter DHTTable = 3'h2;
- parameter DHTMakeHm0 = 3'h3;
- parameter DHTMakeHm1 = 3'h4;
- parameter DHTMakeHm2 = 3'h5;
- parameter DHTReadTable = 3'h6;
-
- always @(posedge clk or negedge rst)
- begin
- if(!rst) begin
- StateDHT <= DHTIdle;
- ReadDhtCount <= 16'h0000;
- ReadDhtTable <= 2'b00;
- HmEnable <= 1'b0;
- HmShift <= 16'h8000;
- HmData <= 16'h0000;
- HmMax <= 8'h00;
- HmCount <= 8'h00;
- end else begin // if (!rst)
- case(StateDHT)
- DHTIdle: begin
- if(Process == SegDHT) begin
- StateDHT <= DHTLength;
- end
- HmEnable <= 1'b0;
- end
- DHTLength: begin
- if(DataInEnable == 1'b1) begin
- StateDHT <= DHTTable;
- ReadDhtCount <= DataIn[31:16];
- end
- end
- DHTTable: begin
- if(DataInEnable == 1'b1) begin
- StateDHT <= DHTMakeHm0;
- case(DataIn[31:24])
- 8'h00: ReadDhtTable <= 2'b00;
- 8'h10: ReadDhtTable <= 2'b01;
- 8'h01: ReadDhtTable <= 2'b10;
- 8'h11: ReadDhtTable <= 2'b11;
- endcase
- end
- HmShift <= 16'h8000;
- HmData <= 16'h0000;
- HmMax <= 8'h00;
- ReadDhtCount <= 0;
- end // case: DHTTable
- DHTMakeHm0: begin
- if(DataInEnable == 1'b1) begin
- StateDHT <= DHTMakeHm1;
- HmCount <= DataIn[31:24];
- end
- HmEnable <= 1'b0;
- end
- DHTMakeHm1: begin
- StateDHT <= DHTMakeHm2;
- HmMax <= HmMax + HmCount;
- end
- DHTMakeHm2: begin
- if(HmCount != 0) begin
- HmData <= HmData + HmShift;
- HmCount <= HmCount -1;
- end else begin
- if(ReadDhtCount == 15) begin
- StateDHT <= DHTReadTable;
- HmCount <= 8'h00;
- //HmMax <= HmMax -1;
- end else begin
- HmEnable <= 1'b1;
- StateDHT <= DHTMakeHm0;
- ReadDhtCount <= ReadDhtCount +1;
- end
- HmShift <= HmShift >> 1;
- end
- end
- DHTReadTable: begin
- HmEnable <= 1'b0;
- if(DataInEnable == 1'b1) begin
- if(HmMax == HmCount +1) begin
- StateDHT <= DHTIdle;
- end
- HmCount <= HmCount +1;
- end
- end
- endcase
- end
- end
-
- assign ReadDhtEnable = StateDHT == DHTReadTable;
- assign ReadDhtData = DataIn[31:24];
-
- assign ReadDhtByte = StateDHT == DHTTable | StateDHT == DHTMakeHm0 |
- StateDHT == DHTReadTable;
- assign ReadDhtWord = StateDHT == DHTLength;
- assign ReadDhtEnd = StateDHT == DHTReadTable & DataInEnable == 1'b1 & HmMax == HmCount +1;
-
- //--------------------------------------------------------------------------
- // SOS Segment
- //--------------------------------------------------------------------------
- reg [3:0] StateSOS;
- reg [15:0] ReadSosCount;
- wire ReadSosByte;
- wire ReadSosWord;
- wire ReadSosEnd;
-
- parameter SOSIdle = 4'h0;
- parameter SOSLength = 4'h1;
- parameter SOSRead0 = 4'h2;
- parameter SOSRead1 = 4'h3;
- parameter SOSRead2 = 4'h4;
- parameter SOSRead3 = 4'h5;
- parameter SOSRead4 = 4'h6;
-
- reg EnableFF00;
-
- always @(posedge clk or negedge rst)
- begin
- if(!rst) begin
- StateSOS <= SOSIdle;
- ReadSosCount <= 16'h0000;
- EnableFF00 <= 1'b0;
- end else begin
- case(StateSOS)
- SOSIdle: begin
- if(Process == SegSOS) begin
- StateSOS <= SOSLength;
- EnableFF00 <= 1'b1;
- end
- end
- SOSLength: begin
- if(DataInEnable == 1'b1) begin
- StateSOS <= SOSRead0;
- ReadSosCount <= DataIn[31:16];
- end
- end
- SOSRead0: begin
- if(DataInEnable == 1'b1) begin
- StateSOS <= SOSRead1;
- ReadSosCount <= {8'h00,DataIn[31:24]};
- end
- end
- SOSRead1: begin
- if(DataInEnable == 1'b1) begin
- if(ReadSosCount == 1) begin
- StateSOS <= SOSRead2;
- end else begin
- ReadSosCount <= ReadSosCount -1;
- end
- end
- end
- SOSRead2: begin
- if(DataInEnable == 1'b1) begin
- StateSOS <= SOSRead3;
- end
- end
- SOSRead3: begin
- if(DataInEnable == 1'b1) begin
- StateSOS <= SOSRead4;
- end
- end
- SOSRead4: begin
- if(DataInEnable == 1'b1) begin
- StateSOS <= SOSIdle;
- end
- end
- endcase
- end
- end
- assign ReadSosByte = StateSOS == SOSRead0 | StateSOS == SOSRead2 | StateSOS == SOSRead3 | StateSOS == SOSRead4;
- assign ReadSosWord = StateSOS == SOSLength | StateSOS == SOSRead1;
- assign ReadSosEnd = DataInEnable == 1'b1 & StateSOS == SOSRead4;
-
- //--------------------------------------------------------------------------
- // SOF0 Segment
- //--------------------------------------------------------------------------
- reg [3:0] StateSOF;
- reg [15:0] ReadSofCount;
- wire ReadSofByte;
- wire ReadSofWord;
- wire ReadSofEnd;
-
- reg [15:0] JpegBlockWidth;
- reg [15:0] JpegBlockHeight;
-
- parameter SOFIdle = 4'h0;
- parameter SOFLength = 4'h1;
- parameter SOFRead0 = 4'h2;
- parameter SOFReadY = 4'h3;
- parameter SOFReadX = 4'h4;
- parameter SOFReadComp = 4'h5;
- parameter SOFMakeBlock0 = 4'H6;
- parameter SOFMakeBlock1 = 4'h7;
-
- always @(posedge clk or negedge rst)
- begin
- if(!rst) begin
- StateSOF <= SOFIdle;
- ReadSofCount <= 16'h0000;
- JpegWidth <= 16'h0000;
- JpegHeight <= 16'h0000;
- JpegBlockWidth <= 16'h0000;
- JpegBlockHeight <= 16'h0000;
- end else begin
- case(StateSOF)
- SOFIdle: begin
- if(Process == SegSOF0) begin
- StateSOF <= SOFLength;
- end
- end
- SOFLength: begin
- if(DataInEnable == 1'b1) begin
- StateSOF <= SOFRead0;
- ReadSofCount <= DataIn[31:16];
- end
- end
- SOFRead0: begin
- if(DataInEnable == 1'b1) begin
- StateSOF <= SOFReadY;
- end
- end
- SOFReadY: begin
- if(DataInEnable == 1'b1) begin
- StateSOF <= SOFReadX;
- JpegHeight <= DataIn[31:16];
- JpegBlockHeight <= DataIn[31:16];
- end
- end
- SOFReadX: begin
- if(DataInEnable == 1'b1) begin
- StateSOF <= SOFReadComp;
- JpegWidth <= DataIn[31:16];
- JpegBlockWidth <= DataIn[31:16];
- ReadSofCount <= 16'h0000;
- end
- end
- SOFReadComp: begin
- if(DataInEnable == 1'b1) begin
- if(ReadSofCount == 9) begin
- StateSOF <= SOFMakeBlock0;
- end else begin
- ReadSofCount <= ReadSofCount +1;
- end
- end
- end
- SOFMakeBlock0:begin
- StateSOF <= SOFMakeBlock1;
- JpegBlockWidth <= JpegBlockWidth +15;
- JpegBlockHeight <= JpegBlockHeight +15;
- end
- SOFMakeBlock1:begin
- StateSOF <= SOFIdle;
- JpegBlockWidth <= JpegBlockWidth >> 4;
- JpegBlockHeight <= JpegBlockHeight >> 4;
- end
- endcase
- end
- end
- assign ReadSofByte = StateSOF == SOFRead0 | StateSOF == SOFReadComp;
- assign ReadSofWord = StateSOF == SOFLength | StateSOF == SOFReadX | StateSOF == SOFReadY ;
- assign ReadSofEnd = StateSOF == SOFMakeBlock1;
-
- assign OutWidth = JpegWidth;
- assign OutHeight = JpegHeight;
- assign OutBlockWidth = JpegBlockWidth[11:0];
-
- //
- assign UseByte = DataInEnable == 1'b1 & (StateReadByte | ReadAppByte | ReadDqtByte | ReadDhtByte | ReadSosByte | ReadSofByte) ;
- assign UseWord = DataInEnable == 1'b1 & (StateReadWord | ReadAppWord | ReadDqtWord | ReadDhtWord | ReadSosWord | ReadSofWord) ;
- assign ReadSegmentEnd = ReadNopEnd | ReadAppEnd | ReadDqtEnd | ReadDhtEnd | ReadSosEnd | ReadSofEnd ;
-
- //
- assign DqtEnable = ReadDqtEnable;
- assign DqtTable = ReadDqtTable;
- assign DqtCount = ReadDqtCount[5:0];
- assign DqtData = ReadDqtData;
-
- //
- assign DhtEnable = ReadDhtEnable;
- assign DhtTable = ReadDhtTable;
- assign DhtCount = HmCount;
- assign DhtData = ReadDhtData;
-
- //
- assign HaffumanEnable = HmEnable;
- assign HaffumanTable = ReadDhtTable;
- assign HaffumanCount = ReadDhtCount[3:0];
- assign HaffumanData = HmData;
- assign HaffumanStart = HmMax;
-
-endmodule
Index: trunk/src/jpeg_ycbcr_mem.v
===================================================================
--- trunk/src/jpeg_ycbcr_mem.v (revision 5)
+++ trunk/src/jpeg_ycbcr_mem.v (nonexistent)
@@ -1,175 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_ycbcr_mem.v
-// Module Name : jpeg_ycbcr_mem
-// Description : Memory for YCbCr2RGB
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-// 1.02 2006/10/04 remove a WriteData,WriteDataA,WriteDataB wires.
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_ycbcr_mem
- (
- clk,
-
- DataInEnable,
- DataInColor,
- DataInPage,
- DataInCount,
- Data0In,
- Data1In,
-
- DataOutAddress,
- DataOutY,
- DataOutCb,
- DataOutCr
- );
-
- input clk;
-
- input DataInEnable;
- input [2:0] DataInColor;
- input [2:0] DataInPage;
- input [1:0] DataInCount;
- input [8:0] Data0In;
- input [8:0] Data1In;
-
- input [7:0] DataOutAddress;
- output [8:0] DataOutY;
- output [8:0] DataOutCb;
- output [8:0] DataOutCr;
-
- reg [8:0] MemYA [0:127];
- reg [8:0] MemYB [0:127];
- reg [8:0] MemCbA [0:31];
- reg [8:0] MemCbB [0:31];
- reg [8:0] MemCrA [0:31];
- reg [8:0] MemCrB [0:31];
-
- reg [6:0] WriteAddressA;
- reg [6:0] WriteAddressB;
-
- always @(DataInColor or DataInPage or DataInCount) begin
- WriteAddressA[6] <= DataInColor[1];
- WriteAddressB[6] <= DataInColor[1];
- if(DataInColor[2] == 1'b0) begin
- if(DataInColor[0] == 1'b0) begin
- case(DataInCount)
- 2'h0: begin
- WriteAddressA[5:0] <= DataInPage + 0;
- WriteAddressB[5:0] <= DataInPage +112 -64;
- end
- 2'h1: begin
- WriteAddressA[5:0] <= DataInPage + 16;
- WriteAddressB[5:0] <= DataInPage + 96 -64;
- end
- 2'h2: begin
- WriteAddressA[5:0] <= DataInPage + 32;
- WriteAddressB[5:0] <= DataInPage + 80 -64;
- end
- 2'h3: begin
- WriteAddressA[5:0] <= DataInPage + 48;
- WriteAddressB[5:0] <= DataInPage + 64 -64;
- end
- endcase // case(DataInCount)
- end else begin // if (DataInColor[0] == 1'b0)
- case(DataInCount)
- 2'h0: begin
- WriteAddressA[5:0] <= DataInPage + 0 +8;
- WriteAddressB[5:0] <= DataInPage +112 +8 -64;
- end
- 2'h1: begin
- WriteAddressA[5:0] <= DataInPage + 16 +8;
- WriteAddressB[5:0] <= DataInPage + 96 +8 -64;
- end
- 2'h2: begin
- WriteAddressA[5:0] <= DataInPage + 32 +8;
- WriteAddressB[5:0] <= DataInPage + 80 +8 -64;
- end
- 2'h3: begin
- WriteAddressA[5:0] <= DataInPage + 48 +8;
- WriteAddressB[5:0] <= DataInPage + 64 +8 -64;
- end
- endcase // case(DataInCount)
- end // else: !if(DataInColor[0] == 1'b0)
- end else begin // if (DataInColor[2] == 1'b0)
- case(DataInCount)
- 2'h0: begin
- WriteAddressA[5:0] <= DataInPage + 0;
- WriteAddressB[5:0] <= DataInPage + 56 -32;
- end
- 2'h1: begin
- WriteAddressA[5:0] <= DataInPage + 8;
- WriteAddressB[5:0] <= DataInPage + 48 -32;
- end
- 2'h2: begin
- WriteAddressA[5:0] <= DataInPage + 16;
- WriteAddressB[5:0] <= DataInPage + 40 -32;
- end
- 2'h3: begin
- WriteAddressA[5:0] <= DataInPage + 24;
- WriteAddressB[5:0] <= DataInPage + 32 -32;
- end
- endcase // case(DataInCount)
- end // else: !if(DataInColor[2] == 1'b0)
- end // always @ (DataInColor or DataInPage or DataInCount)
-
- always @(posedge clk) begin
- if(DataInColor[2] == 1'b0 & DataInEnable == 1'b1) begin
- MemYA[WriteAddressA] <= Data0In;
- MemYB[WriteAddressB] <= Data1In;
- end
- end
-
- always @(posedge clk) begin
- if(DataInColor == 3'b100 & DataInEnable == 1'b1) begin
- MemCbA[WriteAddressA[4:0]] <= Data0In;
- MemCbB[WriteAddressB[4:0]] <= Data1In;
- end
- end
-
- always @(posedge clk) begin
- if(DataInColor == 3'b101 & DataInEnable == 1'b1) begin
- MemCrA[WriteAddressA[4:0]] <= Data0In;
- MemCrB[WriteAddressB[4:0]] <= Data1In;
- end
- end
-
- reg [8:0] ReadYA;
- reg [8:0] ReadYB;
- reg [8:0] ReadCbA;
- reg [8:0] ReadCbB;
- reg [8:0] ReadCrA;
- reg [8:0] ReadCrB;
-
- reg [7:0] RegAdrs;
-
- always @(posedge clk) begin
- RegAdrs <= DataOutAddress;
-
- ReadYA <= MemYA[{DataOutAddress[7],DataOutAddress[5:0]}];
- ReadYB <= MemYB[{DataOutAddress[7],DataOutAddress[5:0]}];
-
- ReadCbA <= MemCbA[{DataOutAddress[6:5],DataOutAddress[3:1]}];
- ReadCrA <= MemCrA[{DataOutAddress[6:5],DataOutAddress[3:1]}];
-
- ReadCbB <= MemCbB[{DataOutAddress[6:5],DataOutAddress[3:1]}];
- ReadCrB <= MemCrB[{DataOutAddress[6:5],DataOutAddress[3:1]}];
- end // always @ (posedge clk)
-
- assign DataOutY = (RegAdrs[6] ==1'b0)?ReadYA:ReadYB;
- assign DataOutCb = (RegAdrs[7] ==1'b0)?ReadCbA:ReadCbB;
- assign DataOutCr = (RegAdrs[7] ==1'b0)?ReadCrA:ReadCrB;
-
-endmodule // jpeg_ycbcr_mem
Index: trunk/src/jpeg_ziguzagu_reg.v
===================================================================
--- trunk/src/jpeg_ziguzagu_reg.v (revision 5)
+++ trunk/src/jpeg_ziguzagu_reg.v (nonexistent)
@@ -1,519 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_ziguzagu_reg.v
-// Module Name : jpeg_ziguzagu_reg
-// Description : Register for ziguzagu
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_ziguzagu_reg
- (
- rst,
- clk,
-
- DataInEnable,
- DataInAddress,
- DataIn,
-
- Data00Reg,
- Data01Reg,
- Data02Reg,
- Data03Reg,
- Data04Reg,
- Data05Reg,
- Data06Reg,
- Data07Reg,
- Data08Reg,
- Data09Reg,
- Data10Reg,
- Data11Reg,
- Data12Reg,
- Data13Reg,
- Data14Reg,
- Data15Reg,
- Data16Reg,
- Data17Reg,
- Data18Reg,
- Data19Reg,
- Data20Reg,
- Data21Reg,
- Data22Reg,
- Data23Reg,
- Data24Reg,
- Data25Reg,
- Data26Reg,
- Data27Reg,
- Data28Reg,
- Data29Reg,
- Data30Reg,
- Data31Reg,
- Data32Reg,
- Data33Reg,
- Data34Reg,
- Data35Reg,
- Data36Reg,
- Data37Reg,
- Data38Reg,
- Data39Reg,
- Data40Reg,
- Data41Reg,
- Data42Reg,
- Data43Reg,
- Data44Reg,
- Data45Reg,
- Data46Reg,
- Data47Reg,
- Data48Reg,
- Data49Reg,
- Data50Reg,
- Data51Reg,
- Data52Reg,
- Data53Reg,
- Data54Reg,
- Data55Reg,
- Data56Reg,
- Data57Reg,
- Data58Reg,
- Data59Reg,
- Data60Reg,
- Data61Reg,
- Data62Reg,
- Data63Reg
- );
-
- input clk;
- input rst;
-
- input DataInEnable;
- input [5:0] DataInAddress;
- input [15:0] DataIn;
-
- output [15:0] Data00Reg;
- output [15:0] Data01Reg;
- output [15:0] Data02Reg;
- output [15:0] Data03Reg;
- output [15:0] Data04Reg;
- output [15:0] Data05Reg;
- output [15:0] Data06Reg;
- output [15:0] Data07Reg;
- output [15:0] Data08Reg;
- output [15:0] Data09Reg;
- output [15:0] Data10Reg;
- output [15:0] Data11Reg;
- output [15:0] Data12Reg;
- output [15:0] Data13Reg;
- output [15:0] Data14Reg;
- output [15:0] Data15Reg;
- output [15:0] Data16Reg;
- output [15:0] Data17Reg;
- output [15:0] Data18Reg;
- output [15:0] Data19Reg;
- output [15:0] Data20Reg;
- output [15:0] Data21Reg;
- output [15:0] Data22Reg;
- output [15:0] Data23Reg;
- output [15:0] Data24Reg;
- output [15:0] Data25Reg;
- output [15:0] Data26Reg;
- output [15:0] Data27Reg;
- output [15:0] Data28Reg;
- output [15:0] Data29Reg;
- output [15:0] Data30Reg;
- output [15:0] Data31Reg;
- output [15:0] Data32Reg;
- output [15:0] Data33Reg;
- output [15:0] Data34Reg;
- output [15:0] Data35Reg;
- output [15:0] Data36Reg;
- output [15:0] Data37Reg;
- output [15:0] Data38Reg;
- output [15:0] Data39Reg;
- output [15:0] Data40Reg;
- output [15:0] Data41Reg;
- output [15:0] Data42Reg;
- output [15:0] Data43Reg;
- output [15:0] Data44Reg;
- output [15:0] Data45Reg;
- output [15:0] Data46Reg;
- output [15:0] Data47Reg;
- output [15:0] Data48Reg;
- output [15:0] Data49Reg;
- output [15:0] Data50Reg;
- output [15:0] Data51Reg;
- output [15:0] Data52Reg;
- output [15:0] Data53Reg;
- output [15:0] Data54Reg;
- output [15:0] Data55Reg;
- output [15:0] Data56Reg;
- output [15:0] Data57Reg;
- output [15:0] Data58Reg;
- output [15:0] Data59Reg;
- output [15:0] Data60Reg;
- output [15:0] Data61Reg;
- output [15:0] Data62Reg;
- output [15:0] Data63Reg;
-
- reg [15:0] RegData [0:63]; // Register Memory
-
- integer i;
-
-/*
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- RegData[0] <= 16'h0000;
- RegData[1] <= 16'h0000;
- RegData[2] <= 16'h0000;
- RegData[3] <= 16'h0000;
- RegData[4] <= 16'h0000;
- RegData[5] <= 16'h0000;
- RegData[6] <= 16'h0000;
- RegData[7] <= 16'h0000;
- RegData[8] <= 16'h0000;
- RegData[9] <= 16'h0000;
- RegData[10] <= 16'h0000;
- RegData[11] <= 16'h0000;
- RegData[12] <= 16'h0000;
- RegData[13] <= 16'h0000;
- RegData[14] <= 16'h0000;
- RegData[15] <= 16'h0000;
- RegData[16] <= 16'h0000;
- RegData[17] <= 16'h0000;
- RegData[18] <= 16'h0000;
- RegData[19] <= 16'h0000;
- RegData[20] <= 16'h0000;
- RegData[21] <= 16'h0000;
- RegData[22] <= 16'h0000;
- RegData[23] <= 16'h0000;
- RegData[24] <= 16'h0000;
- RegData[25] <= 16'h0000;
- RegData[26] <= 16'h0000;
- RegData[27] <= 16'h0000;
- RegData[28] <= 16'h0000;
- RegData[29] <= 16'h0000;
- RegData[30] <= 16'h0000;
- RegData[31] <= 16'h0000;
- RegData[32] <= 16'h0000;
- RegData[33] <= 16'h0000;
- RegData[34] <= 16'h0000;
- RegData[35] <= 16'h0000;
- RegData[36] <= 16'h0000;
- RegData[37] <= 16'h0000;
- RegData[38] <= 16'h0000;
- RegData[39] <= 16'h0000;
- RegData[40] <= 16'h0000;
- RegData[41] <= 16'h0000;
- RegData[42] <= 16'h0000;
- RegData[43] <= 16'h0000;
- RegData[44] <= 16'h0000;
- RegData[45] <= 16'h0000;
- RegData[46] <= 16'h0000;
- RegData[47] <= 16'h0000;
- RegData[48] <= 16'h0000;
- RegData[49] <= 16'h0000;
- RegData[50] <= 16'h0000;
- RegData[51] <= 16'h0000;
- RegData[52] <= 16'h0000;
- RegData[53] <= 16'h0000;
- RegData[54] <= 16'h0000;
- RegData[55] <= 16'h0000;
- RegData[56] <= 16'h0000;
- RegData[57] <= 16'h0000;
- RegData[58] <= 16'h0000;
- RegData[59] <= 16'h0000;
- RegData[60] <= 16'h0000;
- RegData[61] <= 16'h0000;
- RegData[62] <= 16'h0000;
- RegData[63] <= 16'h0000;
- end else begin // if (!rst)
- if(DataInEnable == 1'b1) begin
- RegData[DataInAddress] <= DataIn;
- if(DataInAddress == 6'h00) begin
- for(i=1;i<64;i=i+1) begin
- RegData[i] <= 16'h0000;
- end
- end
- end
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-*/
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- RegData[0] <= 16'h0000;
- RegData[1] <= 16'h0000;
- RegData[2] <= 16'h0000;
- RegData[3] <= 16'h0000;
- RegData[4] <= 16'h0000;
- RegData[5] <= 16'h0000;
- RegData[6] <= 16'h0000;
- RegData[7] <= 16'h0000;
- RegData[8] <= 16'h0000;
- RegData[9] <= 16'h0000;
- RegData[10] <= 16'h0000;
- RegData[11] <= 16'h0000;
- RegData[12] <= 16'h0000;
- RegData[13] <= 16'h0000;
- RegData[14] <= 16'h0000;
- RegData[15] <= 16'h0000;
- RegData[16] <= 16'h0000;
- RegData[17] <= 16'h0000;
- RegData[18] <= 16'h0000;
- RegData[19] <= 16'h0000;
- RegData[20] <= 16'h0000;
- RegData[21] <= 16'h0000;
- RegData[22] <= 16'h0000;
- RegData[23] <= 16'h0000;
- RegData[24] <= 16'h0000;
- RegData[25] <= 16'h0000;
- RegData[26] <= 16'h0000;
- RegData[27] <= 16'h0000;
- RegData[28] <= 16'h0000;
- RegData[29] <= 16'h0000;
- RegData[30] <= 16'h0000;
- RegData[31] <= 16'h0000;
- RegData[32] <= 16'h0000;
- RegData[33] <= 16'h0000;
- RegData[34] <= 16'h0000;
- RegData[35] <= 16'h0000;
- RegData[36] <= 16'h0000;
- RegData[37] <= 16'h0000;
- RegData[38] <= 16'h0000;
- RegData[39] <= 16'h0000;
- RegData[40] <= 16'h0000;
- RegData[41] <= 16'h0000;
- RegData[42] <= 16'h0000;
- RegData[43] <= 16'h0000;
- RegData[44] <= 16'h0000;
- RegData[45] <= 16'h0000;
- RegData[46] <= 16'h0000;
- RegData[47] <= 16'h0000;
- RegData[48] <= 16'h0000;
- RegData[49] <= 16'h0000;
- RegData[50] <= 16'h0000;
- RegData[51] <= 16'h0000;
- RegData[52] <= 16'h0000;
- RegData[53] <= 16'h0000;
- RegData[54] <= 16'h0000;
- RegData[55] <= 16'h0000;
- RegData[56] <= 16'h0000;
- RegData[57] <= 16'h0000;
- RegData[58] <= 16'h0000;
- RegData[59] <= 16'h0000;
- RegData[60] <= 16'h0000;
- RegData[61] <= 16'h0000;
- RegData[62] <= 16'h0000;
- RegData[63] <= 16'h0000;
- end else begin
- if(DataInEnable == 1'b1) begin
- case(DataInAddress)
- 6'd0: begin
- RegData[0] <= DataIn;
- RegData[1] <= 16'h0000;
- RegData[2] <= 16'h0000;
- RegData[3] <= 16'h0000;
- RegData[4] <= 16'h0000;
- RegData[5] <= 16'h0000;
- RegData[6] <= 16'h0000;
- RegData[7] <= 16'h0000;
- RegData[8] <= 16'h0000;
- RegData[9] <= 16'h0000;
- RegData[10] <= 16'h0000;
- RegData[11] <= 16'h0000;
- RegData[12] <= 16'h0000;
- RegData[13] <= 16'h0000;
- RegData[14] <= 16'h0000;
- RegData[15] <= 16'h0000;
- RegData[16] <= 16'h0000;
- RegData[17] <= 16'h0000;
- RegData[18] <= 16'h0000;
- RegData[19] <= 16'h0000;
- RegData[20] <= 16'h0000;
- RegData[21] <= 16'h0000;
- RegData[22] <= 16'h0000;
- RegData[23] <= 16'h0000;
- RegData[24] <= 16'h0000;
- RegData[25] <= 16'h0000;
- RegData[26] <= 16'h0000;
- RegData[27] <= 16'h0000;
- RegData[28] <= 16'h0000;
- RegData[29] <= 16'h0000;
- RegData[30] <= 16'h0000;
- RegData[31] <= 16'h0000;
- RegData[32] <= 16'h0000;
- RegData[33] <= 16'h0000;
- RegData[34] <= 16'h0000;
- RegData[35] <= 16'h0000;
- RegData[36] <= 16'h0000;
- RegData[37] <= 16'h0000;
- RegData[38] <= 16'h0000;
- RegData[39] <= 16'h0000;
- RegData[40] <= 16'h0000;
- RegData[41] <= 16'h0000;
- RegData[42] <= 16'h0000;
- RegData[43] <= 16'h0000;
- RegData[44] <= 16'h0000;
- RegData[45] <= 16'h0000;
- RegData[46] <= 16'h0000;
- RegData[47] <= 16'h0000;
- RegData[48] <= 16'h0000;
- RegData[49] <= 16'h0000;
- RegData[50] <= 16'h0000;
- RegData[51] <= 16'h0000;
- RegData[52] <= 16'h0000;
- RegData[53] <= 16'h0000;
- RegData[54] <= 16'h0000;
- RegData[55] <= 16'h0000;
- RegData[56] <= 16'h0000;
- RegData[57] <= 16'h0000;
- RegData[58] <= 16'h0000;
- RegData[59] <= 16'h0000;
- RegData[60] <= 16'h0000;
- RegData[61] <= 16'h0000;
- RegData[62] <= 16'h0000;
- RegData[63] <= 16'h0000;
- end
- 6'd1: RegData[1] <= DataIn;
- 6'd2: RegData[2] <= DataIn;
- 6'd3: RegData[3] <= DataIn;
- 6'd4: RegData[4] <= DataIn;
- 6'd5: RegData[5] <= DataIn;
- 6'd6: RegData[6] <= DataIn;
- 6'd7: RegData[7] <= DataIn;
- 6'd8: RegData[8] <= DataIn;
- 6'd9: RegData[9] <= DataIn;
- 6'd10: RegData[10] <= DataIn;
- 6'd11: RegData[11] <= DataIn;
- 6'd12: RegData[12] <= DataIn;
- 6'd13: RegData[13] <= DataIn;
- 6'd14: RegData[14] <= DataIn;
- 6'd15: RegData[15] <= DataIn;
- 6'd16: RegData[16] <= DataIn;
- 6'd17: RegData[17] <= DataIn;
- 6'd18: RegData[18] <= DataIn;
- 6'd19: RegData[19] <= DataIn;
- 6'd20: RegData[20] <= DataIn;
- 6'd21: RegData[21] <= DataIn;
- 6'd22: RegData[22] <= DataIn;
- 6'd23: RegData[23] <= DataIn;
- 6'd24: RegData[24] <= DataIn;
- 6'd25: RegData[25] <= DataIn;
- 6'd26: RegData[26] <= DataIn;
- 6'd27: RegData[27] <= DataIn;
- 6'd28: RegData[28] <= DataIn;
- 6'd29: RegData[29] <= DataIn;
- 6'd30: RegData[30] <= DataIn;
- 6'd31: RegData[31] <= DataIn;
- 6'd32: RegData[32] <= DataIn;
- 6'd33: RegData[33] <= DataIn;
- 6'd34: RegData[34] <= DataIn;
- 6'd35: RegData[35] <= DataIn;
- 6'd36: RegData[36] <= DataIn;
- 6'd37: RegData[37] <= DataIn;
- 6'd38: RegData[38] <= DataIn;
- 6'd39: RegData[39] <= DataIn;
- 6'd40: RegData[40] <= DataIn;
- 6'd41: RegData[41] <= DataIn;
- 6'd42: RegData[42] <= DataIn;
- 6'd43: RegData[43] <= DataIn;
- 6'd44: RegData[44] <= DataIn;
- 6'd45: RegData[45] <= DataIn;
- 6'd46: RegData[46] <= DataIn;
- 6'd47: RegData[47] <= DataIn;
- 6'd48: RegData[48] <= DataIn;
- 6'd49: RegData[49] <= DataIn;
- 6'd50: RegData[50] <= DataIn;
- 6'd51: RegData[51] <= DataIn;
- 6'd52: RegData[52] <= DataIn;
- 6'd53: RegData[53] <= DataIn;
- 6'd54: RegData[54] <= DataIn;
- 6'd55: RegData[55] <= DataIn;
- 6'd56: RegData[56] <= DataIn;
- 6'd57: RegData[57] <= DataIn;
- 6'd58: RegData[58] <= DataIn;
- 6'd59: RegData[59] <= DataIn;
- 6'd60: RegData[60] <= DataIn;
- 6'd61: RegData[61] <= DataIn;
- 6'd62: RegData[62] <= DataIn;
- 6'd63: RegData[63] <= DataIn;
- endcase
- end
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign Data00Reg = RegData[00];
- assign Data01Reg = RegData[01];
- assign Data08Reg = RegData[02];
- assign Data16Reg = RegData[03];
- assign Data09Reg = RegData[04];
- assign Data02Reg = RegData[05];
- assign Data03Reg = RegData[06];
- assign Data10Reg = RegData[07];
- assign Data17Reg = RegData[08];
- assign Data24Reg = RegData[09];
- assign Data32Reg = RegData[10];
- assign Data25Reg = RegData[11];
- assign Data18Reg = RegData[12];
- assign Data11Reg = RegData[13];
- assign Data04Reg = RegData[14];
- assign Data05Reg = RegData[15];
- assign Data12Reg = RegData[16];
- assign Data19Reg = RegData[17];
- assign Data26Reg = RegData[18];
- assign Data33Reg = RegData[19];
- assign Data40Reg = RegData[20];
- assign Data48Reg = RegData[21];
- assign Data41Reg = RegData[22];
- assign Data34Reg = RegData[23];
- assign Data27Reg = RegData[24];
- assign Data20Reg = RegData[25];
- assign Data13Reg = RegData[26];
- assign Data06Reg = RegData[27];
- assign Data07Reg = RegData[28];
- assign Data14Reg = RegData[29];
- assign Data21Reg = RegData[30];
- assign Data28Reg = RegData[31];
- assign Data35Reg = RegData[32];
- assign Data42Reg = RegData[33];
- assign Data49Reg = RegData[34];
- assign Data56Reg = RegData[35];
- assign Data57Reg = RegData[36];
- assign Data50Reg = RegData[37];
- assign Data43Reg = RegData[38];
- assign Data36Reg = RegData[39];
- assign Data29Reg = RegData[40];
- assign Data22Reg = RegData[41];
- assign Data15Reg = RegData[42];
- assign Data23Reg = RegData[43];
- assign Data30Reg = RegData[44];
- assign Data37Reg = RegData[45];
- assign Data44Reg = RegData[46];
- assign Data51Reg = RegData[47];
- assign Data58Reg = RegData[48];
- assign Data59Reg = RegData[49];
- assign Data52Reg = RegData[50];
- assign Data45Reg = RegData[51];
- assign Data38Reg = RegData[52];
- assign Data31Reg = RegData[53];
- assign Data39Reg = RegData[54];
- assign Data46Reg = RegData[55];
- assign Data53Reg = RegData[56];
- assign Data60Reg = RegData[57];
- assign Data61Reg = RegData[58];
- assign Data54Reg = RegData[59];
- assign Data47Reg = RegData[60];
- assign Data55Reg = RegData[61];
- assign Data62Reg = RegData[62];
- assign Data63Reg = RegData[63];
-
-endmodule // jpeg_ziguzagu_reg
Index: trunk/src/jpeg_ycbcr.v
===================================================================
--- trunk/src/jpeg_ycbcr.v (revision 5)
+++ trunk/src/jpeg_ycbcr.v (nonexistent)
@@ -1,228 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_ycbcr.v
-// Module Name : jpeg_ycbcr
-// Description : Convert to RGB from YCbCr
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_ycbcr
- (
- rst,
- clk,
-
- DataInEnable,
- DataInPage,
- DataInCount,
- DataInIdle,
- Data0In,
- Data1In,
- DataInBlockWidth,
-
- OutEnable,
- OutPixelX,
- OutPixelY,
- OutR,
- OutG,
- OutB
- );
-
- input rst;
- input clk;
-
- input DataInEnable;
- input [2:0] DataInPage;
- input [1:0] DataInCount;
- output DataInIdle;
- input [8:0] Data0In;
- input [8:0] Data1In;
- input [11:0] DataInBlockWidth;
-
- output OutEnable;
- output [15:0] OutPixelX;
- output [15:0] OutPixelY;
- output [7:0] OutR;
- output [7:0] OutG;
- output [7:0] OutB;
-
- reg DataInBank;
- reg [2:0] DataInColor;
- reg [11:0] DataInBlockX;
- reg [11:0] DataInBlockY;
- reg BankAActive;
- reg BankBActive;
- wire BankAEnable;
- wire BankBEnable;
-
- wire [8:0] BankAY;
- wire [8:0] BankACb;
- wire [8:0] BankACr;
- wire [8:0] BankBY;
- wire [8:0] BankBCb;
- wire [8:0] BankBCr;
-
- reg [11:0] BankABlockX;
- reg [11:0] BankABlockY;
- reg [11:0] BankBBlockX;
- reg [11:0] BankBBlockY;
-
- wire ConvertEnable;
- wire ConvertBank;
- wire [7:0] ConvertAddress;
- wire [8:0] DataY;
- wire [8:0] DataCb;
- wire [8:0] DataCr;
- wire [11:0] ConvertBlockX;
- wire [11:0] ConvertBlockY;
-
- wire BankAIdle;
- wire BankBIdle;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- DataInBank <= 1'b0;
- DataInColor <= 3'b000;
- DataInBlockX <= 12'h000;
- DataInBlockY <= 12'h000;
- BankAActive <= 1'b0;
- BankBActive <= 1'b0;
- BankABlockX <= 12'h000;
- BankABlockY <= 12'h000;
- BankBBlockX <= 12'h000;
- BankBBlockY <= 12'h000;
- end else begin // if (!rst)
- if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
- DataInPage == 3'b111 & DataInCount == 2'b11) begin
- end
- if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
- DataInPage == 3'b111 & DataInCount == 2'b11 &
- DataInBank == 1'b0 & BankAActive == 1'b0) begin
- BankAActive <= 1'b1;
- BankABlockX <= DataInBlockX;
- BankABlockY <= DataInBlockY;
- end else if(ConvertBank == 1'b0 & ConvertAddress == 7'b111) begin
- BankAActive <= 1'b0;
- end
- if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
- DataInPage == 3'b111 & DataInCount == 2'b11 &
- DataInBank == 1'b1 & BankBActive == 1'b0) begin
- BankBActive <= 1'b1;
- BankBBlockX <= DataInBlockX;
- BankBBlockY <= DataInBlockY;
- end else if(ConvertBank == 1'b1 & ConvertAddress == 7'b111) begin
- BankBActive <= 1'b0;
- end
- if(DataInEnable == 1'b1 &
- DataInPage == 3'b111 & DataInCount == 2'b11) begin
- if(DataInColor == 3'b101) begin
- DataInColor <= 3'b000;
- DataInBank <= ~DataInBank;
- if(DataInBlockWidth == DataInBlockX +1) begin
- DataInBlockX <= 12'h000;
- DataInBlockY <= DataInBlockY + 12'h001;
- end else begin
- DataInBlockX <= DataInBlockX + 12'h001;
- end
- end else begin
- DataInColor <= DataInColor + 3'b001;
- end // else: !if(DataInColor == 3'b101)
- end // if (DataInEnable == 1'b1 &...
-
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign BankAEnable = DataInEnable == 1'b1 & DataInBank == 1'b0;
- assign BankBEnable = DataInEnable == 1'b1 & DataInBank == 1'b1;
-
- /*
- assign ConvertBlockX = (ConvertBank)?BankBBlockX:BankABlockX;
- assign ConvertBlockY = (ConvertBank)?BankBBlockY:BankABlockY;
- */
-
- assign ConvertEnable = DataInEnable == 1'b1 & DataInColor == 3'b101 &
- DataInPage == 3'b111 & DataInCount == 2'b11;
-
- assign DataInIdle = BankAActive == 1'b0 | BankBActive == 1'b0;
-
- //------------------------------------------------------------------------
- // YCbCr Memory
- //------------------------------------------------------------------------
- jpeg_ycbcr_mem u_jpeg_ycbcr_mem0(
- .clk(clk),
-
- .DataInEnable (BankAEnable),
- .DataInColor (DataInColor),
- .DataInPage (DataInPage),
- .DataInCount (DataInCount),
- .Data0In (Data0In),
- .Data1In (Data1In),
-
- .DataOutAddress (ConvertAddress),
- .DataOutY (BankAY),
- .DataOutCb (BankACb),
- .DataOutCr (BankACr)
- );
- jpeg_ycbcr_mem u_jpeg_ycbcr_mem1(
- .clk(clk),
-
- .DataInEnable (BankBEnable),
- .DataInColor (DataInColor),
- .DataInPage (DataInPage),
- .DataInCount (DataInCount),
- .Data0In (Data0In),
- .Data1In (Data1In),
-
- .DataOutAddress (ConvertAddress),
- .DataOutY (BankBY),
- .DataOutCb (BankBCb),
- .DataOutCr (BankBCr)
- );
-
- reg ConvertBankD;
- always @(posedge clk or negedge rst) begin
- if(!rst) ConvertBankD <= 1'b0;
- else ConvertBankD <= ConvertBank;
- end
-
-
- assign DataY = (ConvertBankD)?BankBY :BankAY;
- assign DataCb = (ConvertBankD)?BankBCb:BankACb;
- assign DataCr = (ConvertBankD)?BankBCr:BankACr;
-
- //------------------------------------------------------------------------
- // YCbCr to RGB
- //------------------------------------------------------------------------
- jpeg_ycbcbr2rgb u_jpeg_ycbcr2rgb(
- .rst(rst),
- .clk(clk),
-
- .InEnable ( ConvertEnable ),
- .InBlockX ( DataInBlockX ),
- .InBlockY ( DataInBlockY ),
- .InIdle ( ConvertIdle ),
- .InBank ( ConvertBank ),
- .InAddress ( ConvertAddress ),
- .InY ( DataY ),
- .InCb ( DataCb ),
- .InCr ( DataCr ),
-
- .OutEnable ( OutEnable ),
- .OutPixelX ( OutPixelX ),
- .OutPixelY ( OutPixelY ),
- .OutR ( OutR ),
- .OutG ( OutG ),
- .OutB ( OutB )
- );
-endmodule // jpeg_ycbcr
Index: trunk/src/jpeg_ziguzagu.v
===================================================================
--- trunk/src/jpeg_ziguzagu.v (revision 5)
+++ trunk/src/jpeg_ziguzagu.v (nonexistent)
@@ -1,581 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_ziguzagu.v
-// Module Name : jpeg_ziguzagu
-// Description : Ziguzagu
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_ziguzagu
- (
- rst,
- clk,
-
- DataInEnable,
- DataInAddress,
- DataInColor,
- DataInIdle,
- DataIn,
-
- HaffumanEndEnable,
-
- DataOutEnable,
- DataOutColor,
- DataOutSel,
- Data00Reg,
- Data01Reg,
- Data02Reg,
- Data03Reg,
- Data04Reg,
- Data05Reg,
- Data06Reg,
- Data07Reg,
- Data08Reg,
- Data09Reg,
- Data10Reg,
- Data11Reg,
- Data12Reg,
- Data13Reg,
- Data14Reg,
- Data15Reg,
- Data16Reg,
- Data17Reg,
- Data18Reg,
- Data19Reg,
- Data20Reg,
- Data21Reg,
- Data22Reg,
- Data23Reg,
- Data24Reg,
- Data25Reg,
- Data26Reg,
- Data27Reg,
- Data28Reg,
- Data29Reg,
- Data30Reg,
- Data31Reg,
- Data32Reg,
- Data33Reg,
- Data34Reg,
- Data35Reg,
- Data36Reg,
- Data37Reg,
- Data38Reg,
- Data39Reg,
- Data40Reg,
- Data41Reg,
- Data42Reg,
- Data43Reg,
- Data44Reg,
- Data45Reg,
- Data46Reg,
- Data47Reg,
- Data48Reg,
- Data49Reg,
- Data50Reg,
- Data51Reg,
- Data52Reg,
- Data53Reg,
- Data54Reg,
- Data55Reg,
- Data56Reg,
- Data57Reg,
- Data58Reg,
- Data59Reg,
- Data60Reg,
- Data61Reg,
- Data62Reg,
- Data63Reg,
-
- BankARelease,
- BankBRelease
- );
-
- input clk;
- input rst;
-
- input DataInEnable;
- input [5:0] DataInAddress;
- input [2:0] DataInColor;
- output DataInIdle;
- input [15:0] DataIn;
-
- input HaffumanEndEnable;
-
- output DataOutEnable;
- output [2:0] DataOutColor;
- input DataOutSel;
- output [15:0] Data00Reg;
- output [15:0] Data01Reg;
- output [15:0] Data02Reg;
- output [15:0] Data03Reg;
- output [15:0] Data04Reg;
- output [15:0] Data05Reg;
- output [15:0] Data06Reg;
- output [15:0] Data07Reg;
- output [15:0] Data08Reg;
- output [15:0] Data09Reg;
- output [15:0] Data10Reg;
- output [15:0] Data11Reg;
- output [15:0] Data12Reg;
- output [15:0] Data13Reg;
- output [15:0] Data14Reg;
- output [15:0] Data15Reg;
- output [15:0] Data16Reg;
- output [15:0] Data17Reg;
- output [15:0] Data18Reg;
- output [15:0] Data19Reg;
- output [15:0] Data20Reg;
- output [15:0] Data21Reg;
- output [15:0] Data22Reg;
- output [15:0] Data23Reg;
- output [15:0] Data24Reg;
- output [15:0] Data25Reg;
- output [15:0] Data26Reg;
- output [15:0] Data27Reg;
- output [15:0] Data28Reg;
- output [15:0] Data29Reg;
- output [15:0] Data30Reg;
- output [15:0] Data31Reg;
- output [15:0] Data32Reg;
- output [15:0] Data33Reg;
- output [15:0] Data34Reg;
- output [15:0] Data35Reg;
- output [15:0] Data36Reg;
- output [15:0] Data37Reg;
- output [15:0] Data38Reg;
- output [15:0] Data39Reg;
- output [15:0] Data40Reg;
- output [15:0] Data41Reg;
- output [15:0] Data42Reg;
- output [15:0] Data43Reg;
- output [15:0] Data44Reg;
- output [15:0] Data45Reg;
- output [15:0] Data46Reg;
- output [15:0] Data47Reg;
- output [15:0] Data48Reg;
- output [15:0] Data49Reg;
- output [15:0] Data50Reg;
- output [15:0] Data51Reg;
- output [15:0] Data52Reg;
- output [15:0] Data53Reg;
- output [15:0] Data54Reg;
- output [15:0] Data55Reg;
- output [15:0] Data56Reg;
- output [15:0] Data57Reg;
- output [15:0] Data58Reg;
- output [15:0] Data59Reg;
- output [15:0] Data60Reg;
- output [15:0] Data61Reg;
- output [15:0] Data62Reg;
- output [15:0] Data63Reg;
- input BankARelease;
- input BankBRelease;
-
- reg BankAEnable;
- reg BankBEnable;
- reg DataInBank;
-
- reg [2:0] BankAColor;
- reg [2:0] BankBColor;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- BankAEnable <= 1'b0;
- BankBEnable <= 1'b0;
- BankAColor <= 3'b000;
- BankBColor <= 3'b000;
- DataInBank <= 1'b0;
- end else begin
- if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
- if(HaffumanEndEnable == 1'b1 & DataInIdle == 1'b1) begin
- BankAEnable <= 1'b1;
- BankAColor <= DataInColor;
- end
- end else begin
- if(BankARelease == 1'b1) begin
- BankAEnable <= 1'b0;
- end
- end
- if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
- if(HaffumanEndEnable == 1'b1 & DataInIdle == 1'b1) begin
- BankBEnable <= 1'b1;
- BankBColor <= DataInColor;
- end
- end else begin
- if(BankBRelease == 1'b1) begin
- BankBEnable <= 1'b0;
- end
- end
- if(HaffumanEndEnable == 1'b1) begin
- DataInBank <= ~DataInBank;
- end
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;
- assign DataOutEnable = BankAEnable == 1'b1 | BankBEnable == 1'b1;
- assign DataOutColor = (DataInBank)?BankBColor:BankAColor;
-
- wire ZigAEnable;
- wire ZigBEnable;
-
- wire [15:0] BankA00Reg;
- wire [15:0] BankA01Reg;
- wire [15:0] BankA02Reg;
- wire [15:0] BankA03Reg;
- wire [15:0] BankA04Reg;
- wire [15:0] BankA05Reg;
- wire [15:0] BankA06Reg;
- wire [15:0] BankA07Reg;
- wire [15:0] BankA08Reg;
- wire [15:0] BankA09Reg;
- wire [15:0] BankA10Reg;
- wire [15:0] BankA11Reg;
- wire [15:0] BankA12Reg;
- wire [15:0] BankA13Reg;
- wire [15:0] BankA14Reg;
- wire [15:0] BankA15Reg;
- wire [15:0] BankA16Reg;
- wire [15:0] BankA17Reg;
- wire [15:0] BankA18Reg;
- wire [15:0] BankA19Reg;
- wire [15:0] BankA20Reg;
- wire [15:0] BankA21Reg;
- wire [15:0] BankA22Reg;
- wire [15:0] BankA23Reg;
- wire [15:0] BankA24Reg;
- wire [15:0] BankA25Reg;
- wire [15:0] BankA26Reg;
- wire [15:0] BankA27Reg;
- wire [15:0] BankA28Reg;
- wire [15:0] BankA29Reg;
- wire [15:0] BankA30Reg;
- wire [15:0] BankA31Reg;
- wire [15:0] BankA32Reg;
- wire [15:0] BankA33Reg;
- wire [15:0] BankA34Reg;
- wire [15:0] BankA35Reg;
- wire [15:0] BankA36Reg;
- wire [15:0] BankA37Reg;
- wire [15:0] BankA38Reg;
- wire [15:0] BankA39Reg;
- wire [15:0] BankA40Reg;
- wire [15:0] BankA41Reg;
- wire [15:0] BankA42Reg;
- wire [15:0] BankA43Reg;
- wire [15:0] BankA44Reg;
- wire [15:0] BankA45Reg;
- wire [15:0] BankA46Reg;
- wire [15:0] BankA47Reg;
- wire [15:0] BankA48Reg;
- wire [15:0] BankA49Reg;
- wire [15:0] BankA50Reg;
- wire [15:0] BankA51Reg;
- wire [15:0] BankA52Reg;
- wire [15:0] BankA53Reg;
- wire [15:0] BankA54Reg;
- wire [15:0] BankA55Reg;
- wire [15:0] BankA56Reg;
- wire [15:0] BankA57Reg;
- wire [15:0] BankA58Reg;
- wire [15:0] BankA59Reg;
- wire [15:0] BankA60Reg;
- wire [15:0] BankA61Reg;
- wire [15:0] BankA62Reg;
- wire [15:0] BankA63Reg;
-
- wire [15:0] BankB00Reg;
- wire [15:0] BankB01Reg;
- wire [15:0] BankB02Reg;
- wire [15:0] BankB03Reg;
- wire [15:0] BankB04Reg;
- wire [15:0] BankB05Reg;
- wire [15:0] BankB06Reg;
- wire [15:0] BankB07Reg;
- wire [15:0] BankB08Reg;
- wire [15:0] BankB09Reg;
- wire [15:0] BankB10Reg;
- wire [15:0] BankB11Reg;
- wire [15:0] BankB12Reg;
- wire [15:0] BankB13Reg;
- wire [15:0] BankB14Reg;
- wire [15:0] BankB15Reg;
- wire [15:0] BankB16Reg;
- wire [15:0] BankB17Reg;
- wire [15:0] BankB18Reg;
- wire [15:0] BankB19Reg;
- wire [15:0] BankB20Reg;
- wire [15:0] BankB21Reg;
- wire [15:0] BankB22Reg;
- wire [15:0] BankB23Reg;
- wire [15:0] BankB24Reg;
- wire [15:0] BankB25Reg;
- wire [15:0] BankB26Reg;
- wire [15:0] BankB27Reg;
- wire [15:0] BankB28Reg;
- wire [15:0] BankB29Reg;
- wire [15:0] BankB30Reg;
- wire [15:0] BankB31Reg;
- wire [15:0] BankB32Reg;
- wire [15:0] BankB33Reg;
- wire [15:0] BankB34Reg;
- wire [15:0] BankB35Reg;
- wire [15:0] BankB36Reg;
- wire [15:0] BankB37Reg;
- wire [15:0] BankB38Reg;
- wire [15:0] BankB39Reg;
- wire [15:0] BankB40Reg;
- wire [15:0] BankB41Reg;
- wire [15:0] BankB42Reg;
- wire [15:0] BankB43Reg;
- wire [15:0] BankB44Reg;
- wire [15:0] BankB45Reg;
- wire [15:0] BankB46Reg;
- wire [15:0] BankB47Reg;
- wire [15:0] BankB48Reg;
- wire [15:0] BankB49Reg;
- wire [15:0] BankB50Reg;
- wire [15:0] BankB51Reg;
- wire [15:0] BankB52Reg;
- wire [15:0] BankB53Reg;
- wire [15:0] BankB54Reg;
- wire [15:0] BankB55Reg;
- wire [15:0] BankB56Reg;
- wire [15:0] BankB57Reg;
- wire [15:0] BankB58Reg;
- wire [15:0] BankB59Reg;
- wire [15:0] BankB60Reg;
- wire [15:0] BankB61Reg;
- wire [15:0] BankB62Reg;
- wire [15:0] BankB63Reg;
-
- assign ZigAEnable = DataInEnable == 1'b1 & DataInBank == 1'b0;
- assign ZigBEnable = DataInEnable == 1'b1 & DataInBank == 1'b1;
-
- jpeg_ziguzagu_reg u_jpeg_ziguzagu_reg0(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable ( ZigAEnable ),
- .DataInAddress ( DataInAddress ),
- .DataIn ( DataIn ),
-
- .Data00Reg( BankA00Reg ),
- .Data01Reg( BankA01Reg ),
- .Data02Reg( BankA02Reg ),
- .Data03Reg( BankA03Reg ),
- .Data04Reg( BankA04Reg ),
- .Data05Reg( BankA05Reg ),
- .Data06Reg( BankA06Reg ),
- .Data07Reg( BankA07Reg ),
- .Data08Reg( BankA08Reg ),
- .Data09Reg( BankA09Reg ),
- .Data10Reg( BankA10Reg ),
- .Data11Reg( BankA11Reg ),
- .Data12Reg( BankA12Reg ),
- .Data13Reg( BankA13Reg ),
- .Data14Reg( BankA14Reg ),
- .Data15Reg( BankA15Reg ),
- .Data16Reg( BankA16Reg ),
- .Data17Reg( BankA17Reg ),
- .Data18Reg( BankA18Reg ),
- .Data19Reg( BankA19Reg ),
- .Data20Reg( BankA20Reg ),
- .Data21Reg( BankA21Reg ),
- .Data22Reg( BankA22Reg ),
- .Data23Reg( BankA23Reg ),
- .Data24Reg( BankA24Reg ),
- .Data25Reg( BankA25Reg ),
- .Data26Reg( BankA26Reg ),
- .Data27Reg( BankA27Reg ),
- .Data28Reg( BankA28Reg ),
- .Data29Reg( BankA29Reg ),
- .Data30Reg( BankA30Reg ),
- .Data31Reg( BankA31Reg ),
- .Data32Reg( BankA32Reg ),
- .Data33Reg( BankA33Reg ),
- .Data34Reg( BankA34Reg ),
- .Data35Reg( BankA35Reg ),
- .Data36Reg( BankA36Reg ),
- .Data37Reg( BankA37Reg ),
- .Data38Reg( BankA38Reg ),
- .Data39Reg( BankA39Reg ),
- .Data40Reg( BankA40Reg ),
- .Data41Reg( BankA41Reg ),
- .Data42Reg( BankA42Reg ),
- .Data43Reg( BankA43Reg ),
- .Data44Reg( BankA44Reg ),
- .Data45Reg( BankA45Reg ),
- .Data46Reg( BankA46Reg ),
- .Data47Reg( BankA47Reg ),
- .Data48Reg( BankA48Reg ),
- .Data49Reg( BankA49Reg ),
- .Data50Reg( BankA50Reg ),
- .Data51Reg( BankA51Reg ),
- .Data52Reg( BankA52Reg ),
- .Data53Reg( BankA53Reg ),
- .Data54Reg( BankA54Reg ),
- .Data55Reg( BankA55Reg ),
- .Data56Reg( BankA56Reg ),
- .Data57Reg( BankA57Reg ),
- .Data58Reg( BankA58Reg ),
- .Data59Reg( BankA59Reg ),
- .Data60Reg( BankA60Reg ),
- .Data61Reg( BankA61Reg ),
- .Data62Reg( BankA62Reg ),
- .Data63Reg( BankA63Reg )
- );
-
- jpeg_ziguzagu_reg u_jpeg_ziguzagu_reg1(
- .rst(rst),
- .clk(clk),
-
- .DataInEnable ( ZigBEnable ),
- .DataInAddress ( DataInAddress ),
- .DataIn ( DataIn ),
-
- .Data00Reg( BankB00Reg ),
- .Data01Reg( BankB01Reg ),
- .Data02Reg( BankB02Reg ),
- .Data03Reg( BankB03Reg ),
- .Data04Reg( BankB04Reg ),
- .Data05Reg( BankB05Reg ),
- .Data06Reg( BankB06Reg ),
- .Data07Reg( BankB07Reg ),
- .Data08Reg( BankB08Reg ),
- .Data09Reg( BankB09Reg ),
- .Data10Reg( BankB10Reg ),
- .Data11Reg( BankB11Reg ),
- .Data12Reg( BankB12Reg ),
- .Data13Reg( BankB13Reg ),
- .Data14Reg( BankB14Reg ),
- .Data15Reg( BankB15Reg ),
- .Data16Reg( BankB16Reg ),
- .Data17Reg( BankB17Reg ),
- .Data18Reg( BankB18Reg ),
- .Data19Reg( BankB19Reg ),
- .Data20Reg( BankB20Reg ),
- .Data21Reg( BankB21Reg ),
- .Data22Reg( BankB22Reg ),
- .Data23Reg( BankB23Reg ),
- .Data24Reg( BankB24Reg ),
- .Data25Reg( BankB25Reg ),
- .Data26Reg( BankB26Reg ),
- .Data27Reg( BankB27Reg ),
- .Data28Reg( BankB28Reg ),
- .Data29Reg( BankB29Reg ),
- .Data30Reg( BankB30Reg ),
- .Data31Reg( BankB31Reg ),
- .Data32Reg( BankB32Reg ),
- .Data33Reg( BankB33Reg ),
- .Data34Reg( BankB34Reg ),
- .Data35Reg( BankB35Reg ),
- .Data36Reg( BankB36Reg ),
- .Data37Reg( BankB37Reg ),
- .Data38Reg( BankB38Reg ),
- .Data39Reg( BankB39Reg ),
- .Data40Reg( BankB40Reg ),
- .Data41Reg( BankB41Reg ),
- .Data42Reg( BankB42Reg ),
- .Data43Reg( BankB43Reg ),
- .Data44Reg( BankB44Reg ),
- .Data45Reg( BankB45Reg ),
- .Data46Reg( BankB46Reg ),
- .Data47Reg( BankB47Reg ),
- .Data48Reg( BankB48Reg ),
- .Data49Reg( BankB49Reg ),
- .Data50Reg( BankB50Reg ),
- .Data51Reg( BankB51Reg ),
- .Data52Reg( BankB52Reg ),
- .Data53Reg( BankB53Reg ),
- .Data54Reg( BankB54Reg ),
- .Data55Reg( BankB55Reg ),
- .Data56Reg( BankB56Reg ),
- .Data57Reg( BankB57Reg ),
- .Data58Reg( BankB58Reg ),
- .Data59Reg( BankB59Reg ),
- .Data60Reg( BankB60Reg ),
- .Data61Reg( BankB61Reg ),
- .Data62Reg( BankB62Reg ),
- .Data63Reg( BankB63Reg )
- );
-
- assign Data00Reg = (DataOutSel)?BankB00Reg:BankA00Reg;
- assign Data01Reg = (DataOutSel)?BankB01Reg:BankA01Reg;
- assign Data02Reg = (DataOutSel)?BankB02Reg:BankA02Reg;
- assign Data03Reg = (DataOutSel)?BankB03Reg:BankA03Reg;
- assign Data04Reg = (DataOutSel)?BankB04Reg:BankA04Reg;
- assign Data05Reg = (DataOutSel)?BankB05Reg:BankA05Reg;
- assign Data06Reg = (DataOutSel)?BankB06Reg:BankA06Reg;
- assign Data07Reg = (DataOutSel)?BankB07Reg:BankA07Reg;
- assign Data08Reg = (DataOutSel)?BankB08Reg:BankA08Reg;
- assign Data09Reg = (DataOutSel)?BankB09Reg:BankA09Reg;
- assign Data10Reg = (DataOutSel)?BankB10Reg:BankA10Reg;
- assign Data11Reg = (DataOutSel)?BankB11Reg:BankA11Reg;
- assign Data12Reg = (DataOutSel)?BankB12Reg:BankA12Reg;
- assign Data13Reg = (DataOutSel)?BankB13Reg:BankA13Reg;
- assign Data14Reg = (DataOutSel)?BankB14Reg:BankA14Reg;
- assign Data15Reg = (DataOutSel)?BankB15Reg:BankA15Reg;
- assign Data16Reg = (DataOutSel)?BankB16Reg:BankA16Reg;
- assign Data17Reg = (DataOutSel)?BankB17Reg:BankA17Reg;
- assign Data18Reg = (DataOutSel)?BankB18Reg:BankA18Reg;
- assign Data19Reg = (DataOutSel)?BankB19Reg:BankA19Reg;
- assign Data20Reg = (DataOutSel)?BankB20Reg:BankA20Reg;
- assign Data21Reg = (DataOutSel)?BankB21Reg:BankA21Reg;
- assign Data22Reg = (DataOutSel)?BankB22Reg:BankA22Reg;
- assign Data23Reg = (DataOutSel)?BankB23Reg:BankA23Reg;
- assign Data24Reg = (DataOutSel)?BankB24Reg:BankA24Reg;
- assign Data25Reg = (DataOutSel)?BankB25Reg:BankA25Reg;
- assign Data26Reg = (DataOutSel)?BankB26Reg:BankA26Reg;
- assign Data27Reg = (DataOutSel)?BankB27Reg:BankA27Reg;
- assign Data28Reg = (DataOutSel)?BankB28Reg:BankA28Reg;
- assign Data29Reg = (DataOutSel)?BankB29Reg:BankA29Reg;
- assign Data30Reg = (DataOutSel)?BankB30Reg:BankA30Reg;
- assign Data31Reg = (DataOutSel)?BankB31Reg:BankA31Reg;
- assign Data32Reg = (DataOutSel)?BankB32Reg:BankA32Reg;
- assign Data33Reg = (DataOutSel)?BankB33Reg:BankA33Reg;
- assign Data34Reg = (DataOutSel)?BankB34Reg:BankA34Reg;
- assign Data35Reg = (DataOutSel)?BankB35Reg:BankA35Reg;
- assign Data36Reg = (DataOutSel)?BankB36Reg:BankA36Reg;
- assign Data37Reg = (DataOutSel)?BankB37Reg:BankA37Reg;
- assign Data38Reg = (DataOutSel)?BankB38Reg:BankA38Reg;
- assign Data39Reg = (DataOutSel)?BankB39Reg:BankA39Reg;
- assign Data40Reg = (DataOutSel)?BankB40Reg:BankA40Reg;
- assign Data41Reg = (DataOutSel)?BankB41Reg:BankA41Reg;
- assign Data42Reg = (DataOutSel)?BankB42Reg:BankA42Reg;
- assign Data43Reg = (DataOutSel)?BankB43Reg:BankA43Reg;
- assign Data44Reg = (DataOutSel)?BankB44Reg:BankA44Reg;
- assign Data45Reg = (DataOutSel)?BankB45Reg:BankA45Reg;
- assign Data46Reg = (DataOutSel)?BankB46Reg:BankA46Reg;
- assign Data47Reg = (DataOutSel)?BankB47Reg:BankA47Reg;
- assign Data48Reg = (DataOutSel)?BankB48Reg:BankA48Reg;
- assign Data49Reg = (DataOutSel)?BankB49Reg:BankA49Reg;
- assign Data50Reg = (DataOutSel)?BankB50Reg:BankA50Reg;
- assign Data51Reg = (DataOutSel)?BankB51Reg:BankA51Reg;
- assign Data52Reg = (DataOutSel)?BankB52Reg:BankA52Reg;
- assign Data53Reg = (DataOutSel)?BankB53Reg:BankA53Reg;
- assign Data54Reg = (DataOutSel)?BankB54Reg:BankA54Reg;
- assign Data55Reg = (DataOutSel)?BankB55Reg:BankA55Reg;
- assign Data56Reg = (DataOutSel)?BankB56Reg:BankA56Reg;
- assign Data57Reg = (DataOutSel)?BankB57Reg:BankA57Reg;
- assign Data58Reg = (DataOutSel)?BankB58Reg:BankA58Reg;
- assign Data59Reg = (DataOutSel)?BankB59Reg:BankA59Reg;
- assign Data60Reg = (DataOutSel)?BankB60Reg:BankA60Reg;
- assign Data61Reg = (DataOutSel)?BankB61Reg:BankA61Reg;
- assign Data62Reg = (DataOutSel)?BankB62Reg:BankA62Reg;
- assign Data63Reg = (DataOutSel)?BankB63Reg:BankA63Reg;
-
-endmodule // jpeg_ziguzagu
Index: trunk/src/jpeg_regdata.v
===================================================================
--- trunk/src/jpeg_regdata.v (revision 5)
+++ trunk/src/jpeg_regdata.v (nonexistent)
@@ -1,209 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_regdata.v
-// Module Name : jpeg_regdata
-// Description : get Data
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2007/04/11
-// Rev. : 1.03
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-// 1.02 2006/10/04 Remove a RegEnd register.
-// When reset, clear on OutEnable,PreEnable,DataOut registers.
-// Remove some comments.
-// 1.03 2007/04/11 Don't OutEnable, ImageEnable == 1 and DataOut == 0xFFD9XXXX
-// Stop ReadEnable with DataEnd(after 0xFFD9 of ImageData)
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_regdata(
- rst,
- clk,
-
- // Read Data
- DataIn, //
- DataInEnable, // Data Enable
- DataInRead, // Data Read
-
- // DataOut
- DataOut, // Data Out
- DataOutEnable, // Data Out Enable
-
- //
- ImageEnable,
- ProcessIdle,
-
- // UseData
- UseBit, // Used data bit
- UseWidth, // Used data bit width
- UseByte, // Used data byte
- UseWord // Used data word
- );
-
- input rst;
- input clk;
-
- input [31:0] DataIn;
- input DataInEnable;
- output DataInRead;
-
- output [31:0] DataOut;
- output DataOutEnable;
-
- input ImageEnable;
- input ProcessIdle;
-
- input UseBit;
- input [6:0] UseWidth;
- input UseByte;
- input UseWord;
-
- wire RegValid;
- reg [95:0] RegData;
- reg [7:0] RegWidth;
-
- reg DataEnd;
-
- assign RegValid = RegWidth > 64;
- assign DataInRead = RegValid == 1'b0 & DataInEnable == 1'b1;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- RegData <= 96'd0;
- RegWidth <= 8'h00;
- end else begin
- if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin
- if(ImageEnable == 1'b1) begin
- if(RegData[39: 8] == 32'hFF00FF00) begin
- RegWidth <= RegWidth + 16;
- RegData[95:64] <= {8'h00,RegData[71:48]};
- RegData[63:32] <= {RegData[47:40],16'hFFFF,RegData[7:0]};
- end else if(RegData[39:24] == 16'hFF00 &
- RegData[15: 0] == 16'hFF00) begin
- RegWidth <= RegWidth + 16;
- RegData[95:64] <= {8'h00,RegData[71:48]};
- RegData[63:32] <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF};
- end else if(RegData[31: 0] == 32'hFF00FF00) begin
- RegWidth <= RegWidth + 16;
- RegData[95:64] <= {16'h0000,RegData[71:56]};
- RegData[63:32] <= {RegData[55:40],16'hFFFF};
- end else if(RegData[39:24] == 16'hFF00) begin
- RegWidth <= RegWidth + 24;
- RegData[95:64] <= {RegData[71:40]};
- RegData[63:32] <= {8'hFF,RegData[23:0]};
- end else if(RegData[31:16] == 16'hFF00) begin
- RegWidth <= RegWidth + 24;
- RegData[95:64] <= {RegData[71:40]};
- RegData[63:32] <= {RegData[39:32],8'hFF,RegData[15:0]};
- end else if(RegData[23: 8] == 16'hFF00) begin
- RegWidth <= RegWidth + 24;
- RegData[95:64] <= {RegData[71:40]};
- RegData[63:32] <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]};
- end else if(RegData[15: 0] == 16'hFF00) begin
- RegWidth <= RegWidth + 24;
- RegData[95:64] <= {RegData[71:40]};
- RegData[63:32] <= {RegData[39:32],RegData[31:16],8'hFF};
- end else begin
- RegWidth <= RegWidth + 32;
- RegData[95:64] <= RegData[63:32];
- RegData[63:32] <= RegData[31:0];
- end
- end else begin
- RegWidth <= RegWidth + 32;
- RegData[95:64] <= RegData[63:32];
- RegData[63:32] <= RegData[31:0];
- end
- RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]};
- end else if(UseBit == 1'b1) begin
- RegWidth <= RegWidth - UseWidth;
- end else if(UseByte == 1'b1) begin
- RegWidth <= RegWidth - 8;
- end else if(UseWord == 1'b1) begin
- RegWidth <= RegWidth - 16;
- end
- end
- end
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- DataEnd <= 1'b0;
- end else begin
- if(ProcessIdle) begin
- DataEnd <= 1'b0;
- end else if(ImageEnable == 1'b1 & (RegData[39:24] == 16'hFFD9 | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin
- DataEnd <= 1'b1;
- end
- end
- end
-
- function [31:0] SliceData;
- input [95:0] RegData;
- input [7:0] RegWidth;
-
- case(RegWidth)
- 8'd65: SliceData = RegData[64:33];
- 8'd66: SliceData = RegData[65:34];
- 8'd67: SliceData = RegData[66:35];
- 8'd68: SliceData = RegData[67:36];
- 8'd69: SliceData = RegData[68:37];
- 8'd70: SliceData = RegData[69:38];
- 8'd71: SliceData = RegData[70:39];
- 8'd72: SliceData = RegData[71:40];
- 8'd73: SliceData = RegData[72:41];
- 8'd74: SliceData = RegData[73:42];
- 8'd75: SliceData = RegData[74:43];
- 8'd76: SliceData = RegData[75:44];
- 8'd77: SliceData = RegData[76:45];
- 8'd78: SliceData = RegData[77:46];
- 8'd79: SliceData = RegData[78:47];
- 8'd80: SliceData = RegData[79:48];
- 8'd81: SliceData = RegData[80:49];
- 8'd82: SliceData = RegData[81:50];
- 8'd83: SliceData = RegData[82:51];
- 8'd84: SliceData = RegData[83:52];
- 8'd85: SliceData = RegData[84:53];
- 8'd86: SliceData = RegData[85:54];
- 8'd87: SliceData = RegData[86:55];
- 8'd88: SliceData = RegData[87:56];
- 8'd89: SliceData = RegData[88:57];
- 8'd90: SliceData = RegData[89:58];
- 8'd91: SliceData = RegData[90:59];
- 8'd92: SliceData = RegData[91:60];
- 8'd93: SliceData = RegData[92:61];
- 8'd94: SliceData = RegData[93:62];
- 8'd95: SliceData = RegData[94:63];
- 8'd96: SliceData = RegData[95:64];
- default: SliceData = 32'h00000000;
- endcase
- endfunction
-
- reg OutEnable;
- reg PreEnable;
-
- reg [31:0] DataOut;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- OutEnable <= 1'b0;
- PreEnable <= 1'b0;
- DataOut <= 32'h00000000;
- end else begin
- OutEnable <= RegWidth >64;
- PreEnable <= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1);
- DataOut <= SliceData(RegData,RegWidth);
- end
- end
-
- assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0;
-
-endmodule
-
-
-
\ No newline at end of file
Index: trunk/src/jpeg_hm_decode.v
===================================================================
--- trunk/src/jpeg_hm_decode.v (revision 5)
+++ trunk/src/jpeg_hm_decode.v (nonexistent)
@@ -1,860 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_hm_decode.v
-// Module Name : jpeg_hm_decode
-// Description : Decode of Haffuman data
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-// 1.02 2006/10/04 move for a comment widh OutData,OutDhtNumber register.
-// remove a ProcessColorNumber,tempPlace register.
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_hm_decode
- (
- rst, // Reset
- clk, // Clock
-
- // Haffuman Table
- HaffumanTableEnable, // Table Data In Enable
- HaffumanTableColor, // Haffuman Table Color Number
- HaffumanTableCount, // Table Number
- HaffumanTableCode, // Haffuman Table Code
- HaffumanTableStart, // Haffuman Table Start Number
-
- // Haffuman Decode
- DataInRun, // Data In Start
- DataInEnable, // Data In Enable
- DataIn, // Data In
-
- // DHT table
- DhtColor, // Color Number
- DhtNumber, // Decode Dht Number
- DhtZero, // Zero Count of Dht Number
- DhtWidth, // Data Width of Dht Number
-
- // DQT Table
- DqtColor, // Color Number
- DqtNumber, // Dqt Number
- DqtData, // Dqt Data
-
- //
- DataOutIdle,
- DataOutEnable,
- DataOutColor,
-
- // Output decode data
- DecodeUseBit, // Used Data Bit
- DecodeUseWidth, // Used Data Width
- DecodeEnable, // Data Out Enable
- DecodeColor, // Data Out Enable
- DecodeCount, // Data Out Enable
- DecodeZero, // Data Out with Zero Count
- DecodeCode // Data Out with Code
- );
-
- //--------------------------------------------------------------------------
- // Input/Output
- //--------------------------------------------------------------------------
- input rst,clk; // Reset and Clock
- input HaffumanTableEnable; // Table Data In Enable
- input [1:0] HaffumanTableColor;
- input [3:0] HaffumanTableCount; // Table Number
- input [15:0] HaffumanTableCode; // Haffuman Table Data
- input [7:0] HaffumanTableStart; // Haffuman Table Start Number
-
- input DataInRun;
- input DataInEnable; // Data In Enable
- input [31:0] DataIn; // Data In
-
- output [1:0] DhtColor;
- output [7:0] DhtNumber; // Decode Dht Number
- input [3:0] DhtZero; // Zero Count of Dht Number
- input [3:0] DhtWidth; // Data Width of Dht Number
-
- output DqtColor;
- output [5:0] DqtNumber;
- input [7:0] DqtData;
-
- input DataOutIdle;
- output DataOutEnable;
- output [2:0] DataOutColor;
-
-
- output DecodeUseBit;
- output [6:0] DecodeUseWidth; // Used Data Width
- output DecodeEnable; // Data Out Enable
- output [2:0] DecodeColor;
- output [5:0] DecodeCount;
- output [3:0] DecodeZero; // Data Out with Zero Count
- output [15:0] DecodeCode; // Data Out with Code
-
- //--------------------------------------------------------------------------
- // Register Haffuman Table(YCbCr)
- //--------------------------------------------------------------------------
- // Y-DC Haffuman Table
- reg [15:0] HaffumanTable0r [0:15]; // Y-DC Haffuman Table
- reg [15:0] HaffumanTable1r [0:15]; // Y-AC Haffuman Table
- reg [15:0] HaffumanTable2r [0:15]; // C-DC Haffuman Table
- reg [15:0] HaffumanTable3r [0:15]; // C-AC Haffuman Table
-
- reg [15:0] HaffumanNumber0r [0:15]; // Y-DC Haffuman Number
- reg [15:0] HaffumanNumber1r [0:15]; // Y-AC Haffuman Number
- reg [15:0] HaffumanNumber2r [0:15]; // C-DC Haffuman Number
- reg [15:0] HaffumanNumber3r [0:15]; // C-AC Haffuman Number
-
- integer i;
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- HaffumanTable0r[0] <= 16'h0000;
- HaffumanNumber0r[0] <= 8'h00;
- HaffumanTable1r[0] <= 16'h0000;
- HaffumanNumber1r[0] <= 8'h00;
- HaffumanTable2r[0] <= 16'h0000;
- HaffumanNumber2r[0] <= 8'h00;
- HaffumanTable3r[0] <= 16'h0000;
- HaffumanNumber3r[0] <= 8'h00;
-
- HaffumanTable0r[1] <= 16'h0000;
- HaffumanNumber0r[1] <= 8'h00;
- HaffumanTable1r[1] <= 16'h0000;
- HaffumanNumber1r[1] <= 8'h00;
- HaffumanTable2r[1] <= 16'h0000;
- HaffumanNumber2r[1] <= 8'h00;
- HaffumanTable3r[1] <= 16'h0000;
- HaffumanNumber3r[1] <= 8'h00;
-
- HaffumanTable0r[2] <= 16'h0000;
- HaffumanNumber0r[2] <= 8'h00;
- HaffumanTable1r[2] <= 16'h0000;
- HaffumanNumber1r[2] <= 8'h00;
- HaffumanTable2r[2] <= 16'h0000;
- HaffumanNumber2r[2] <= 8'h00;
- HaffumanTable3r[2] <= 16'h0000;
- HaffumanNumber3r[2] <= 8'h00;
-
- HaffumanTable0r[3] <= 16'h0000;
- HaffumanNumber0r[3] <= 8'h00;
- HaffumanTable1r[3] <= 16'h0000;
- HaffumanNumber1r[3] <= 8'h00;
- HaffumanTable2r[3] <= 16'h0000;
- HaffumanNumber2r[3] <= 8'h00;
- HaffumanTable3r[3] <= 16'h0000;
- HaffumanNumber3r[3] <= 8'h00;
-
- HaffumanTable0r[4] <= 16'h0000;
- HaffumanNumber0r[4] <= 8'h00;
- HaffumanTable1r[4] <= 16'h0000;
- HaffumanNumber1r[4] <= 8'h00;
- HaffumanTable2r[4] <= 16'h0000;
- HaffumanNumber2r[4] <= 8'h00;
- HaffumanTable3r[4] <= 16'h0000;
- HaffumanNumber3r[4] <= 8'h00;
-
- HaffumanTable0r[5] <= 16'h0000;
- HaffumanNumber0r[5] <= 8'h00;
- HaffumanTable1r[5] <= 16'h0000;
- HaffumanNumber1r[5] <= 8'h00;
- HaffumanTable2r[5] <= 16'h0000;
- HaffumanNumber2r[5] <= 8'h00;
- HaffumanTable3r[5] <= 16'h0000;
- HaffumanNumber3r[5] <= 8'h00;
-
- HaffumanTable0r[6] <= 16'h0000;
- HaffumanNumber0r[6] <= 8'h00;
- HaffumanTable1r[6] <= 16'h0000;
- HaffumanNumber1r[6] <= 8'h00;
- HaffumanTable2r[6] <= 16'h0000;
- HaffumanNumber2r[6] <= 8'h00;
- HaffumanTable3r[6] <= 16'h0000;
- HaffumanNumber3r[6] <= 8'h00;
-
- HaffumanTable0r[7] <= 16'h0000;
- HaffumanNumber0r[7] <= 8'h00;
- HaffumanTable1r[7] <= 16'h0000;
- HaffumanNumber1r[7] <= 8'h00;
- HaffumanTable2r[7] <= 16'h0000;
- HaffumanNumber2r[7] <= 8'h00;
- HaffumanTable3r[7] <= 16'h0000;
- HaffumanNumber3r[7] <= 8'h00;
-
- HaffumanTable0r[8] <= 16'h0000;
- HaffumanNumber0r[8] <= 8'h00;
- HaffumanTable1r[8] <= 16'h0000;
- HaffumanNumber1r[8] <= 8'h00;
- HaffumanTable2r[8] <= 16'h0000;
- HaffumanNumber2r[8] <= 8'h00;
- HaffumanTable3r[8] <= 16'h0000;
- HaffumanNumber3r[8] <= 8'h00;
-
- HaffumanTable0r[9] <= 16'h0000;
- HaffumanNumber0r[9] <= 8'h00;
- HaffumanTable1r[9] <= 16'h0000;
- HaffumanNumber1r[9] <= 8'h00;
- HaffumanTable2r[9] <= 16'h0000;
- HaffumanNumber2r[9] <= 8'h00;
- HaffumanTable3r[9] <= 16'h0000;
- HaffumanNumber3r[9] <= 8'h00;
-
- HaffumanTable0r[10] <= 16'h0000;
- HaffumanNumber0r[10] <= 8'h00;
- HaffumanTable1r[10] <= 16'h0000;
- HaffumanNumber1r[10] <= 8'h00;
- HaffumanTable2r[10] <= 16'h0000;
- HaffumanNumber2r[10] <= 8'h00;
- HaffumanTable3r[10] <= 16'h0000;
- HaffumanNumber3r[10] <= 8'h00;
-
- HaffumanTable0r[11] <= 16'h0000;
- HaffumanNumber0r[11] <= 8'h00;
- HaffumanTable1r[11] <= 16'h0000;
- HaffumanNumber1r[11] <= 8'h00;
- HaffumanTable2r[11] <= 16'h0000;
- HaffumanNumber2r[11] <= 8'h00;
- HaffumanTable3r[11] <= 16'h0000;
- HaffumanNumber3r[11] <= 8'h00;
-
- HaffumanTable0r[12] <= 16'h0000;
- HaffumanNumber0r[12] <= 8'h00;
- HaffumanTable1r[12] <= 16'h0000;
- HaffumanNumber1r[12] <= 8'h00;
- HaffumanTable2r[12] <= 16'h0000;
- HaffumanNumber2r[12] <= 8'h00;
- HaffumanTable3r[12] <= 16'h0000;
- HaffumanNumber3r[12] <= 8'h00;
-
- HaffumanTable0r[13] <= 16'h0000;
- HaffumanNumber0r[13] <= 8'h00;
- HaffumanTable1r[13] <= 16'h0000;
- HaffumanNumber1r[13] <= 8'h00;
- HaffumanTable2r[13] <= 16'h0000;
- HaffumanNumber2r[13] <= 8'h00;
- HaffumanTable3r[13] <= 16'h0000;
- HaffumanNumber3r[13] <= 8'h00;
-
- HaffumanTable0r[14] <= 16'h0000;
- HaffumanNumber0r[14] <= 8'h00;
- HaffumanTable1r[14] <= 16'h0000;
- HaffumanNumber1r[14] <= 8'h00;
- HaffumanTable2r[14] <= 16'h0000;
- HaffumanNumber2r[14] <= 8'h00;
- HaffumanTable3r[14] <= 16'h0000;
- HaffumanNumber3r[14] <= 8'h00;
-
- HaffumanTable0r[15] <= 16'h0000;
- HaffumanNumber0r[15] <= 8'h00;
- HaffumanTable1r[15] <= 16'h0000;
- HaffumanNumber1r[15] <= 8'h00;
- HaffumanTable2r[15] <= 16'h0000;
- HaffumanNumber2r[15] <= 8'h00;
- HaffumanTable3r[15] <= 16'h0000;
- HaffumanNumber3r[15] <= 8'h00;
- end else begin // if (!rst)
- if(HaffumanTableEnable ==2'b1) begin
- if(HaffumanTableColor ==2'b00) begin
- HaffumanTable0r[HaffumanTableCount] <= HaffumanTableCode;
- HaffumanNumber0r[HaffumanTableCount] <= HaffumanTableStart;
- end else if(HaffumanTableColor ==2'b01) begin
- HaffumanTable1r[HaffumanTableCount] <= HaffumanTableCode;
- HaffumanNumber1r[HaffumanTableCount] <= HaffumanTableStart;
- end else if(HaffumanTableColor ==2'b10) begin
- HaffumanTable2r[HaffumanTableCount] <= HaffumanTableCode;
- HaffumanNumber2r[HaffumanTableCount] <= HaffumanTableStart;
- end else begin
- HaffumanTable3r[HaffumanTableCount] <= HaffumanTableCode;
- HaffumanNumber3r[HaffumanTableCount] <= HaffumanTableStart;
- end
- end // if (HaffumanTableEnable ==2'b1)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- //--------------------------------------------------------------------------
- // Decode Process
- //--------------------------------------------------------------------------
- reg [3:0] Process; // Process State
- reg [31:0] ProcessData; // Data
-
- // Haffuman Table
- reg [15:0] HaffumanTable [0:15];
- // Haffuman Table Number
- reg [7:0] HaffumanNumber [0:15];
-
- reg [15:0] Place; // Place bit
- reg [15:0] TableCode; // Table Code
- reg [7:0] NumberCode; // Start Number of Table Code
- reg [3:0] CodeNumber; // Haffuman code width
- reg [15:0] DataNumber; // Haffuman code
- //reg [15:0] SubData; // Haffuman Dht Number
-
- //reg [7:0] OutDhtNumber; // Output Dht Number
-
- reg [2:0] ProcessColor;
- reg [6:0] ProcessCount;
- reg [6:0] NextProcessCount;
-
- reg OutEnable; // Output Enable
- reg [3:0] OutZero; // Output Zero Count
- reg [15:0] OutCode; // Output Data Code
- wire [15:0] OutCodeP; // Output Data Code
-
- reg [4:0] UseWidth; // Output used width
-
- //reg [23:0] OutData;
-
- reg DataOutEnable;
- reg [2:0] DataOutColor;
-
- reg signed [31:0] PreData [0:2];
-
- wire [15:0] SubCode;
-
- parameter ProcIdle = 4'h0;
- parameter Phase1 = 4'h1;
- parameter Phase2 = 4'h2;
- parameter Phase3 = 4'h3;
- parameter Phase4 = 4'h4;
- parameter Phase5 = 4'h5;
- parameter Phase6 = 4'h6;
- parameter Phase7 = 4'h7;
- parameter Phase8 = 4'h8;
- parameter Phase9 = 4'h9;
- parameter Phase10 = 4'hA;
- parameter Phase11 = 4'hB;
-
-/*
- always @(*) begin
- case (DhtWidth)
- 4'h0: OutCodeP <= 16'h0000;
- 4'h1: OutCodeP <= {15'h0000,ProcessData[31]};
- 4'h2: OutCodeP <= {14'h0000,ProcessData[31:30]};
- 4'h3: OutCodeP <= {13'h0000,ProcessData[31:29]};
- 4'h4: OutCodeP <= {12'h000, ProcessData[31:28]};
- 4'h5: OutCodeP <= {11'h000, ProcessData[31:27]};
- 4'h6: OutCodeP <= {10'h000, ProcessData[31:26]};
- 4'h7: OutCodeP <= {9'h000, ProcessData[31:25]};
- 4'h8: OutCodeP <= {8'h00, ProcessData[31:24]};
- 4'h9: OutCodeP <= {7'h00, ProcessData[31:23]};
- 4'hA: OutCodeP <= {6'h00, ProcessData[31:22]};
- 4'hB: OutCodeP <= {5'h00, ProcessData[31:21]};
- 4'hC: OutCodeP <= {4'h0, ProcessData[31:20]};
- 4'hD: OutCodeP <= {3'h0, ProcessData[31:19]};
- 4'hE: OutCodeP <= {2'h0, ProcessData[31:18]};
- 4'hF: OutCodeP <= {1'h0, ProcessData[31:17]};
- endcase // case(DhtWidth)
- case (DhtWidth)
- 4'h0: SubCode <= 16'hFFFF;
- 4'h1: SubCode <= 16'hFFFE;
- 4'h2: SubCode <= 16'hFFFC;
- 4'h3: SubCode <= 16'hFFF8;
- 4'h4: SubCode <= 16'hFFF0;
- 4'h5: SubCode <= 16'hFFE0;
- 4'h6: SubCode <= 16'hFFC0;
- 4'h7: SubCode <= 16'hFF80;
- 4'h8: SubCode <= 16'hFF00;
- 4'h9: SubCode <= 16'hFE00;
- 4'hA: SubCode <= 16'hFC00;
- 4'hB: SubCode <= 16'hF800;
- 4'hC: SubCode <= 16'hF000;
- 4'hD: SubCode <= 16'hE000;
- 4'hE: SubCode <= 16'hC000;
- 4'hF: SubCode <= 16'h8000;
- endcase // case(DhtWidth)
- end // always @ (*)
-*/
-
- function [15:0] OutCodePSel;
- input [3:0] DhtWidth;
- input [31:0] ProcessData;
- begin
- case (DhtWidth)
- 4'h0: OutCodePSel = 16'h0000;
- 4'h1: OutCodePSel = {15'h0000,ProcessData[31]};
- 4'h2: OutCodePSel = {14'h0000,ProcessData[31:30]};
- 4'h3: OutCodePSel = {13'h0000,ProcessData[31:29]};
- 4'h4: OutCodePSel = {12'h000, ProcessData[31:28]};
- 4'h5: OutCodePSel = {11'h000, ProcessData[31:27]};
- 4'h6: OutCodePSel = {10'h000, ProcessData[31:26]};
- 4'h7: OutCodePSel = {9'h000, ProcessData[31:25]};
- 4'h8: OutCodePSel = {8'h00, ProcessData[31:24]};
- 4'h9: OutCodePSel = {7'h00, ProcessData[31:23]};
- 4'hA: OutCodePSel = {6'h00, ProcessData[31:22]};
- 4'hB: OutCodePSel = {5'h00, ProcessData[31:21]};
- 4'hC: OutCodePSel = {4'h0, ProcessData[31:20]};
- 4'hD: OutCodePSel = {3'h0, ProcessData[31:19]};
- 4'hE: OutCodePSel = {2'h0, ProcessData[31:18]};
- 4'hF: OutCodePSel = {1'h0, ProcessData[31:17]};
- endcase // case(DhtWidth)
- end
- endfunction
- assign OutCodeP = OutCodePSel(DhtWidth, ProcessData);
-
- function [15:0] SubCodeSel;
- input [3:0] DhtWidth;
- begin
- case (DhtWidth)
- 4'h0: SubCodeSel = 16'hFFFF;
- 4'h1: SubCodeSel = 16'hFFFE;
- 4'h2: SubCodeSel = 16'hFFFC;
- 4'h3: SubCodeSel = 16'hFFF8;
- 4'h4: SubCodeSel = 16'hFFF0;
- 4'h5: SubCodeSel = 16'hFFE0;
- 4'h6: SubCodeSel = 16'hFFC0;
- 4'h7: SubCodeSel = 16'hFF80;
- 4'h8: SubCodeSel = 16'hFF00;
- 4'h9: SubCodeSel = 16'hFE00;
- 4'hA: SubCodeSel = 16'hFC00;
- 4'hB: SubCodeSel = 16'hF800;
- 4'hC: SubCodeSel = 16'hF000;
- 4'hD: SubCodeSel = 16'hE000;
- 4'hE: SubCodeSel = 16'hC000;
- 4'hF: SubCodeSel = 16'h8000;
- endcase // case(DhtWidth)
- end
- endfunction
- assign SubCode = SubCodeSel(DhtWidth);
-
- always @(posedge clk or negedge rst) begin
- if(!rst) begin
- Process <= ProcIdle;
- ProcessData <= 32'h00000000;
- OutEnable <= 1'b0;
- DataOutEnable <= 1'b0;
- DataOutColor <= 3'b000;
- PreData[0] <= 32'h00000000;
- PreData[1] <= 32'h00000000;
- PreData[2] <= 32'h00000000;
- UseWidth <= 7'h00;
- CodeNumber <= 4'd0;
- end else begin // if (!rst)
- case (Process)
- ProcIdle: begin
- if(DataInRun == 1'b1) begin
- Process <= Phase1;
- end else begin
- // Reset DC code
- PreData[0] <= 32'h00000000;
- PreData[1] <= 32'h00000000;
- PreData[2] <= 32'h00000000;
- end
- OutEnable <= 1'b0;
- ProcessColor <= 3'b000;
- ProcessCount <= 0;
- DataOutEnable <= 1'b0;
- DataOutColor <= 3'b000;
- end // case: ProcIdle
- // get a table-data and table-number
- Phase1: begin
- if(DataInEnable ==1'b1 & DataOutIdle == 1'b1) begin
- Process <= Phase2;
- ProcessData <= DataIn;
- end
- OutEnable <= 1'b0;
- DataOutEnable <= 1'b0;
- if(ProcessColor[2] == 1'b0) begin
- if(ProcessCount == 0) begin
- HaffumanTable[0] <= HaffumanTable0r[0];
- HaffumanNumber[0] <= HaffumanNumber0r[0];
- HaffumanTable[1] <= HaffumanTable0r[1];
- HaffumanNumber[1] <= HaffumanNumber0r[1];
- HaffumanTable[2] <= HaffumanTable0r[2];
- HaffumanNumber[2] <= HaffumanNumber0r[2];
- HaffumanTable[3] <= HaffumanTable0r[3];
- HaffumanNumber[3] <= HaffumanNumber0r[3];
- HaffumanTable[4] <= HaffumanTable0r[4];
- HaffumanNumber[4] <= HaffumanNumber0r[4];
- HaffumanTable[5] <= HaffumanTable0r[5];
- HaffumanNumber[5] <= HaffumanNumber0r[5];
- HaffumanTable[6] <= HaffumanTable0r[6];
- HaffumanNumber[6] <= HaffumanNumber0r[6];
- HaffumanTable[7] <= HaffumanTable0r[7];
- HaffumanNumber[7] <= HaffumanNumber0r[7];
- HaffumanTable[8] <= HaffumanTable0r[8];
- HaffumanNumber[8] <= HaffumanNumber0r[8];
- HaffumanTable[9] <= HaffumanTable0r[9];
- HaffumanNumber[9] <= HaffumanNumber0r[9];
- HaffumanTable[10] <= HaffumanTable0r[10];
- HaffumanNumber[10] <= HaffumanNumber0r[10];
- HaffumanTable[11] <= HaffumanTable0r[11];
- HaffumanNumber[11] <= HaffumanNumber0r[11];
- HaffumanTable[12] <= HaffumanTable0r[12];
- HaffumanNumber[12] <= HaffumanNumber0r[12];
- HaffumanTable[13] <= HaffumanTable0r[13];
- HaffumanNumber[13] <= HaffumanNumber0r[13];
- HaffumanTable[14] <= HaffumanTable0r[14];
- HaffumanNumber[14] <= HaffumanNumber0r[14];
- HaffumanTable[15] <= HaffumanTable0r[15];
- HaffumanNumber[15] <= HaffumanNumber0r[15];
- end else begin
- HaffumanTable[0] <= HaffumanTable1r[0];
- HaffumanNumber[0] <= HaffumanNumber1r[0];
- HaffumanTable[1] <= HaffumanTable1r[1];
- HaffumanNumber[1] <= HaffumanNumber1r[1];
- HaffumanTable[2] <= HaffumanTable1r[2];
- HaffumanNumber[2] <= HaffumanNumber1r[2];
- HaffumanTable[3] <= HaffumanTable1r[3];
- HaffumanNumber[3] <= HaffumanNumber1r[3];
- HaffumanTable[4] <= HaffumanTable1r[4];
- HaffumanNumber[4] <= HaffumanNumber1r[4];
- HaffumanTable[5] <= HaffumanTable1r[5];
- HaffumanNumber[5] <= HaffumanNumber1r[5];
- HaffumanTable[6] <= HaffumanTable1r[6];
- HaffumanNumber[6] <= HaffumanNumber1r[6];
- HaffumanTable[7] <= HaffumanTable1r[7];
- HaffumanNumber[7] <= HaffumanNumber1r[7];
- HaffumanTable[8] <= HaffumanTable1r[8];
- HaffumanNumber[8] <= HaffumanNumber1r[8];
- HaffumanTable[9] <= HaffumanTable1r[9];
- HaffumanNumber[9] <= HaffumanNumber1r[9];
- HaffumanTable[10] <= HaffumanTable1r[10];
- HaffumanNumber[10] <= HaffumanNumber1r[10];
- HaffumanTable[11] <= HaffumanTable1r[11];
- HaffumanNumber[11] <= HaffumanNumber1r[11];
- HaffumanTable[12] <= HaffumanTable1r[12];
- HaffumanNumber[12] <= HaffumanNumber1r[12];
- HaffumanTable[13] <= HaffumanTable1r[13];
- HaffumanNumber[13] <= HaffumanNumber1r[13];
- HaffumanTable[14] <= HaffumanTable1r[14];
- HaffumanNumber[14] <= HaffumanNumber1r[14];
- HaffumanTable[15] <= HaffumanTable1r[15];
- HaffumanNumber[15] <= HaffumanNumber1r[15];
- end // else: !if(ProcessCount == 0)
- end else begin // if (ProcessColor[2] == 1'b0)
- if(ProcessCount == 0) begin
- HaffumanTable[0] <= HaffumanTable2r[0];
- HaffumanNumber[0] <= HaffumanNumber2r[0];
- HaffumanTable[1] <= HaffumanTable2r[1];
- HaffumanNumber[1] <= HaffumanNumber2r[1];
- HaffumanTable[2] <= HaffumanTable2r[2];
- HaffumanNumber[2] <= HaffumanNumber2r[2];
- HaffumanTable[3] <= HaffumanTable2r[3];
- HaffumanNumber[3] <= HaffumanNumber2r[3];
- HaffumanTable[4] <= HaffumanTable2r[4];
- HaffumanNumber[4] <= HaffumanNumber2r[4];
- HaffumanTable[5] <= HaffumanTable2r[5];
- HaffumanNumber[5] <= HaffumanNumber2r[5];
- HaffumanTable[6] <= HaffumanTable2r[6];
- HaffumanNumber[6] <= HaffumanNumber2r[6];
- HaffumanTable[7] <= HaffumanTable2r[7];
- HaffumanNumber[7] <= HaffumanNumber2r[7];
- HaffumanTable[8] <= HaffumanTable2r[8];
- HaffumanNumber[8] <= HaffumanNumber2r[8];
- HaffumanTable[9] <= HaffumanTable2r[9];
- HaffumanNumber[9] <= HaffumanNumber2r[9];
- HaffumanTable[10] <= HaffumanTable2r[10];
- HaffumanNumber[10] <= HaffumanNumber2r[10];
- HaffumanTable[11] <= HaffumanTable2r[11];
- HaffumanNumber[11] <= HaffumanNumber2r[11];
- HaffumanTable[12] <= HaffumanTable2r[12];
- HaffumanNumber[12] <= HaffumanNumber2r[12];
- HaffumanTable[13] <= HaffumanTable2r[13];
- HaffumanNumber[13] <= HaffumanNumber2r[13];
- HaffumanTable[14] <= HaffumanTable2r[14];
- HaffumanNumber[14] <= HaffumanNumber2r[14];
- HaffumanTable[15] <= HaffumanTable2r[15];
- HaffumanNumber[15] <= HaffumanNumber2r[15];
- end else begin
- HaffumanTable[0] <= HaffumanTable3r[0];
- HaffumanNumber[0] <= HaffumanNumber3r[0];
- HaffumanTable[1] <= HaffumanTable3r[1];
- HaffumanNumber[1] <= HaffumanNumber3r[1];
- HaffumanTable[2] <= HaffumanTable3r[2];
- HaffumanNumber[2] <= HaffumanNumber3r[2];
- HaffumanTable[3] <= HaffumanTable3r[3];
- HaffumanNumber[3] <= HaffumanNumber3r[3];
- HaffumanTable[4] <= HaffumanTable3r[4];
- HaffumanNumber[4] <= HaffumanNumber3r[4];
- HaffumanTable[5] <= HaffumanTable3r[5];
- HaffumanNumber[5] <= HaffumanNumber3r[5];
- HaffumanTable[6] <= HaffumanTable3r[6];
- HaffumanNumber[6] <= HaffumanNumber3r[6];
- HaffumanTable[7] <= HaffumanTable3r[7];
- HaffumanNumber[7] <= HaffumanNumber3r[7];
- HaffumanTable[8] <= HaffumanTable3r[8];
- HaffumanNumber[8] <= HaffumanNumber3r[8];
- HaffumanTable[9] <= HaffumanTable3r[9];
- HaffumanNumber[9] <= HaffumanNumber3r[9];
- HaffumanTable[10] <= HaffumanTable3r[10];
- HaffumanNumber[10] <= HaffumanNumber3r[10];
- HaffumanTable[11] <= HaffumanTable3r[11];
- HaffumanNumber[11] <= HaffumanNumber3r[11];
- HaffumanTable[12] <= HaffumanTable3r[12];
- HaffumanNumber[12] <= HaffumanNumber3r[12];
- HaffumanTable[13] <= HaffumanTable3r[13];
- HaffumanNumber[13] <= HaffumanNumber3r[13];
- HaffumanTable[14] <= HaffumanTable3r[14];
- HaffumanNumber[14] <= HaffumanNumber3r[14];
- HaffumanTable[15] <= HaffumanTable3r[15];
- HaffumanNumber[15] <= HaffumanNumber3r[15];
- end // else: !if(ProcessCount == 0)
- end // else: !if(ProcessColor[2] == 1'b0)
- end // case: Phase1
- // compare table
- Phase2: begin
- Process <= Phase4;
- if(ProcessData[31:16] >= HaffumanTable[0]) Place[0] <= 1'b1;
- else Place[0] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[1]) Place[1] <= 1'b1;
- else Place[1] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[2]) Place[2] <= 1'b1;
- else Place[2] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[3]) Place[3] <= 1'b1;
- else Place[3] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[4]) Place[4] <= 1'b1;
- else Place[4] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[5]) Place[5] <= 1'b1;
- else Place[5] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[6]) Place[6] <= 1'b1;
- else Place[6] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[7]) Place[7] <= 1'b1;
- else Place[7] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[8]) Place[8] <= 1'b1;
- else Place[8] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[9]) Place[9] <= 1'b1;
- else Place[9] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[10]) Place[10] <= 1'b1;
- else Place[10] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[11]) Place[11] <= 1'b1;
- else Place[11] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[12]) Place[12] <= 1'b1;
- else Place[12] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[13]) Place[13] <= 1'b1;
- else Place[13] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[14]) Place[14] <= 1'b1;
- else Place[14] <= 1'b0;
- if(ProcessData[31:16] >= HaffumanTable[15]) Place[15] <= 1'b1;
- else Place[15] <= 1'b0;
- end
- // shift code
- Phase4: begin
- Process <= Phase6;
- case (Place)
- 16'b0000000000000001: begin
- TableCode <= {15'h0000,HaffumanTable[0][15]};
- NumberCode <= HaffumanNumber[0];
- CodeNumber <= 4'h0;
- DataNumber <= {15'h0000,ProcessData[31]};
- ProcessData <= {ProcessData[30:0],1'b0};
- end
- 16'b0000000000000011: begin
- TableCode <= {14'h0000,HaffumanTable[1][15:14]};
- NumberCode <= HaffumanNumber[1];
- CodeNumber <= 4'h1;
- DataNumber <= {14'h0000,ProcessData[31:30]};
- ProcessData <= {ProcessData[29:0],2'b00};
- end
- 16'b0000000000000111: begin
- TableCode <= {13'h0000,HaffumanTable[2][15:13]};
- NumberCode <= HaffumanNumber[2];
- CodeNumber <= 4'h2;
- DataNumber <= {13'h0000,ProcessData[31:29]};
- ProcessData <= {ProcessData[28:0],3'b000};
- end
- 16'b0000000000001111: begin
- TableCode <= {12'h000,HaffumanTable[3][15:12]};
- NumberCode <= HaffumanNumber[3];
- CodeNumber <= 4'h3;
- DataNumber <= {12'h000,ProcessData[31:28]};
- ProcessData <= {ProcessData[27:0],4'h0};
- end
- 16'b0000000000011111: begin
- TableCode <= {11'h000,HaffumanTable[4][15:11]};
- NumberCode <= HaffumanNumber[4];
- CodeNumber <= 4'h4;
- DataNumber <= {11'h000,ProcessData[31:27]};
- ProcessData <= {ProcessData[26:0],5'h00};
- end
- 16'b0000000000111111: begin
- TableCode <= {10'h000,HaffumanTable[5][15:10]};
- NumberCode <= HaffumanNumber[5];
- CodeNumber <= 4'h5;
- DataNumber <= {10'h000,ProcessData[31:26]};
- ProcessData <= {ProcessData[25:0],6'h00};
- end
- 16'b0000000001111111: begin
- TableCode <= {9'h000,HaffumanTable[6][15:9]};
- NumberCode <= HaffumanNumber[6];
- CodeNumber <= 4'h6;
- DataNumber <= {9'h000,ProcessData[31:25]};
- ProcessData <= {ProcessData[24:0],7'h00};
- end
- 16'b0000000011111111: begin
- TableCode <= {8'h00,HaffumanTable[7][15:8]};
- NumberCode <= HaffumanNumber[7];
- CodeNumber <= 4'h7;
- DataNumber <= {8'h00,ProcessData[31:24]};
- ProcessData <= {ProcessData[23:0],8'h00};
- end
- 16'b0000000111111111: begin
- TableCode <= {7'h00,HaffumanTable[8][15:7]};
- NumberCode <= HaffumanNumber[8];
- CodeNumber <= 4'h8;
- DataNumber <= {7'h00,ProcessData[31:23]};
- ProcessData <= {ProcessData[22:0],9'h000};
- end
- 16'b0000001111111111: begin
- TableCode <= {6'h00,HaffumanTable[9][15:6]};
- NumberCode <= HaffumanNumber[9];
- CodeNumber <= 4'h9;
- DataNumber <= {6'h00,ProcessData[31:22]};
- ProcessData <= {ProcessData[21:0],10'h000};
- end
- 16'b0000011111111111: begin
- TableCode <= {5'h00,HaffumanTable[10][15:5]};
- NumberCode <= HaffumanNumber[10];
- CodeNumber <= 4'hA;
- DataNumber <= {5'h00,ProcessData[31:21]};
- ProcessData <= {ProcessData[20:0],11'h000};
- end
- 16'b0000111111111111: begin
- TableCode <= {4'h0,HaffumanTable[11][15:4]};
- NumberCode <= HaffumanNumber[11];
- CodeNumber <= 4'hB;
- DataNumber <= {4'h0,ProcessData[31:20]};
- ProcessData <= {ProcessData[19:0],12'h000};
- end
- 16'b0001111111111111: begin
- TableCode <= {3'h0,HaffumanTable[12][15:3]};
- NumberCode <= HaffumanNumber[12];
- CodeNumber <= 4'hC;
- DataNumber <= {3'h0,ProcessData[31:19]};
- ProcessData <= {ProcessData[18:0],13'h0000};
- end
- 16'b0011111111111111: begin
- TableCode <= {2'h0,HaffumanTable[13][15:2]};
- NumberCode <= HaffumanNumber[13];
- CodeNumber <= 4'hD;
- DataNumber <= {2'h0,ProcessData[31:18]};
- ProcessData <= {ProcessData[17:0],14'h0000};
- end
- 16'b0111111111111111: begin
- TableCode <= {1'h0,HaffumanTable[14][15:1]};
- NumberCode <= HaffumanNumber[14];
- CodeNumber <= 4'hE;
- DataNumber <= {1'h0,ProcessData[31:17]};
- ProcessData <= {ProcessData[16:0],15'h0000};
- end
- 16'b1111111111111111: begin
- TableCode <= HaffumanTable[15];
- NumberCode <= HaffumanNumber[15];
- CodeNumber <= 4'hF;
- DataNumber <= ProcessData[31:16] ;
- ProcessData <= {ProcessData[15:0],16'h0000};
- end
- endcase // case(Place)
- end // case: Phase4
- Phase5: begin
- Process <= Phase6;
- //SubData <= DataNumber - TableCode;
- //OutDhtNumber <= DataNumber - TableCode + NumberCode;
- end
- Phase6: begin
- if(DataOutIdle == 1'b1) Process <= Phase7;
- //DhtNumber <= SubData[7:0] + NumberCode;
- end
- Phase7: begin
- Process <= Phase9;
- OutZero <= DhtZero;
- UseWidth <= CodeNumber + DhtWidth +1;
- if(ProcessCount == 0) begin
- NextProcessCount <= 7'd1;
- OutEnable <= 1'b1;
- end else begin
- if(DhtZero == 4'h0 & DhtWidth == 4'h0) begin
- ProcessCount <= 7'd64;
- NextProcessCount <= 7'd64;
- OutEnable <= 1'b0;
- end else if(DhtZero == 4'hF & DhtWidth == 4'h0) begin
- ProcessCount <= ProcessCount + 4'hF;
- NextProcessCount <= ProcessCount + 4'hF;
- OutEnable <= 1'b0;
- end else begin
- ProcessCount <= ProcessCount + DhtZero;
- NextProcessCount <= ProcessCount + DhtZero +1;
- OutEnable <= 1'b1;
- end
- end // else: !if(ProcessCount == 0)
-
- if(ProcessData[31] == 1'b0 & DhtWidth != 0) begin
- OutCode <= (OutCodeP | SubCode) + 16'h0001;
- end else begin
- OutCode <= OutCodeP;
- end
- end // case: Phase7
- Phase8: begin
- Process <= Phase9;
- end
- Phase9: begin
- Process <= Phase11;
- if(ProcessCount == 0) begin
- if(ProcessColor[2] == 1'b0) begin
- OutCode <= OutCode + PreData[0];
- PreData[0] <= OutCode + PreData[0];
- end else begin
- if(ProcessColor[0] == 1'b0) begin
- OutCode <= OutCode + PreData[1];
- PreData[1] <= OutCode + PreData[1];
- end else begin
- OutCode <= OutCode + PreData[2];
- PreData[2] <= OutCode + PreData[2];
- end
- end // else: !if(ProcessColor[2] == 1'b0)
- end // if (ProcessCount == 0)
- end // case: Phase9
- Phase10: begin
- Process <= Phase11;
- //OutData <= DqtData * OutCode;
- end
- Phase11: begin
- OutEnable <= 1'b0;
- if(NextProcessCount <64) begin
- Process <= Phase1;
- ProcessCount <= NextProcessCount;
- end else begin
- ProcessCount <= 7'd0;
- DataOutEnable <= 1'b1;
- DataOutColor <= ProcessColor;
- if(ProcessColor == 5) begin
- ProcessColor <= 3'b000;
- if(DataInRun == 1'b0) Process <= ProcIdle;
- else Process <= Phase1;
- end else begin
- Process <= Phase1;
- ProcessColor <= ProcessColor +1;
- end
- end // else: !if(NextProcessCount <64)
- end // case: Phase11
- endcase // case(Process)
- end // else: !if(!rst)
- end // always @ (posedge clk or negedge rst)
-
- assign DhtColor[1] = ProcessColor[2];
- assign DhtColor[0] = ProcessCount != 0;
- //assign DhtNumber = OutDhtNumber[7:0];
- assign DhtNumber = DataNumber - TableCode + NumberCode;
-
- assign DqtColor = ProcessColor[2];
- assign DqtNumber = ProcessCount[5:0];
-
- //assign DecodeUseBit = Process == Phase8;
- assign DecodeUseBit = Process == Phase9;
- assign DecodeUseWidth = UseWidth;
-
- assign DecodeEnable = OutEnable == 1'b1 & Process == Phase11;
- assign DecodeColor = ProcessColor;
- assign DecodeCount = ProcessCount[5:0];
- assign DecodeZero = OutZero;
- //assign DecodeCode = OutData[15:0];
- assign DecodeCode = DqtData * OutCode;
-
-endmodule // jpeg_hm_decode
Index: trunk/readme.txt
===================================================================
--- trunk/readme.txt (revision 5)
+++ trunk/readme.txt (nonexistent)
@@ -1,14 +0,0 @@
-JPEG Decoder
-
-[Product Name] JPEG Decoder
-[Update Date ] 2007/04/18
-[Version ] Ver 1.03
-[License ] LGPL
-[Langage ] Verilog
-[Author ] Hidemi Ishihara(E-Mail:hidemi@sweetcafe.jp)
-
-Specification for Japanese
-http://claude.sweetcafe.jp//index.php?option=com_content&task=view&id=38&Itemid=88888896
-
-Specification for English
-http://translate.google.com/translate?u=http%3A%2F%2Fclaude.sweetcafe.jp%2F%2Findex.php%3Foption%3Dcom_content%26task%3Dview%26id%3D38%26Itemid%3D88888896&langpair=ja%7Cen&hl=ja&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools
Index: trunk/testbench/convbtoh
===================================================================
--- trunk/testbench/convbtoh (revision 5)
+++ trunk/testbench/convbtoh (nonexistent)
@@ -1,14 +0,0 @@
-ELF `4 D
- 4 ( 4 44 @ @ @ @@ T TTﾈ ﾈ ( (( Q蚯d /lib/ld-linux.so.2 GNU
-
- 5 . : p H ﾊ V [ 2 a @ 4 O X _Jv_RegisterClasses __gmon_start__ libc.so.6 perror feof fread sprintf fclose fwrite exit fopen _IO_stdin_used __libc_start_main GLIBC_2.1 GLIBC_2.0 $ ii
- ii
- , 0 4 8 < @ D H L
- P U牙鞦 8 # ﾉﾃ 5$%( %,h 鰲%0h 鰔%4h 鯊%8h 魏%<h 鬆%@h( 髏%Dh0 騾%Hh8 駱%Lh@ 饒%PhH 餘1^蚊蓿PTRhhhpQVh鑰瑞U牙S [ﾃ 挙ﾒt隱X[ﾉﾃ瑞瑞瑞U牙=\ t β｣Xﾒ｡Xﾒuﾆ\ﾉﾃ振牙｡Pﾀtｸ ﾀt ﾇ$Pﾐﾉﾃ錐L$蓿qU牙SQ0 燕虚毅β ﾇD$$$鞳右マ uﾇ$ 閙ﾇ$ 雋虚毅β ﾇD$'$隍右マ ｡ ﾇ$ ;ﾇ$ 鑰畿吋$ ﾇD$ ﾇD$ 孔$ ｶEｶﾈｶEｶﾘｶEｶﾐｶEｶﾀ鵜$噂$欝$ 吋$ﾇD$*劫$+畿吋$ ﾇD$ ﾇD$ 劫$畿$闍ﾀd畿$雕畿$隴ｸ ﾄ0 Y[]溝ﾃ瑞振牙ﾉﾃ貢 U牙WVS [ﾃ｢ 鴻 酷 )ﾐﾁ右t 1茄Puu uGθζ9}u闕e[^_ﾉﾃ瑞瑞瑞瑞瑞瑞U牙S｡@t1ﾛﾐ泣<uζ[]ﾃ瑞振牙S [ﾃ 陷Y[ﾉﾃ rb wb %02X%02X%02X%02X
- $
- H ` 吹
- P H @ oo o T ﾆﾖ諠&6FV L GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.1 20060525 (Red Hat 4.1.1-1) GCC: (GNU) 4.1.1 20060525 (Red Hat 4.1.1-1) GCC: (GNU) 4.1.1 20060525 (Red Hat 4.1.1-1) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) .symtab .strtab .shstrtab .interp .note.ABI-tag .hash .dynsym .dynstr .gnu.version .gnu.version_r .rel.dyn .rel.plt .init .text .fini .rodata .eh_frame .ctors .dtors .jcr .dynamic .got .got.plt .data .bss .comment # (( 1 HH H 7 吹 ﾐ ? `` G o T o 0 c @@ l HH P u p ｰｰ ｰ { `` $ << @@ HH ｧ PP ｬ TT ﾈ ｵ ｺ 4 ﾃ TT ﾉ \\ ﾎ \ j ﾗ ､ ﾐ 4 t ｹ ( H 吹 ` @ H
- ｰ `
- < @ H P T T \ т @ * H 8 P E \ T X [ ｰ q 焙 } D L < ･ P ｱ ﾐ ﾇ ﾒ T ﾛ @ @ @ @ $ : @ M @ c s z h ｩ
- ｯ ﾀ ` ﾇ pT ﾗ \ a T
- ﾊ ( 8 \ ? ` D 2 U d 4 w X T ｪ call_gmon_start crtstuff.c __CTOR_LIST__ __DTOR_LIST__ __JCR_LIST__ completed.5754 p.5752 __do_global_dtors_aux frame_dummy __CTOR_END__ __DTOR_END__ __FRAME_END__ __JCR_END__ __do_global_ctors_aux convbtoh.c _DYNAMIC __fini_array_end __fini_array_start __init_array_end __preinit_array_end _GLOBAL_OFFSET_TABLE_ __init_array_start __preinit_array_start feof@@GLIBC_2.0 _fp_hw perror@@GLIBC_2.0 __dso_handle __libc_csu_fini _init fread@@GLIBC_2.0 _start __libc_csu_init __bss_start main __libc_start_main@@GLIBC_2.0 data_start _fini fclose@@GLIBC_2.1 exit@@GLIBC_2.0 _edata _end fopen@@GLIBC_2.1 _IO_stdin_used sprintf@@GLIBC_2.0 fwrite@@GLIBC_2.0 __data_start _Jv_RegisterClasses __gmon_start__
\ No newline at end of file
trunk/testbench/convbtoh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/testbench/run.ms
===================================================================
--- trunk/testbench/run.ms (revision 5)
+++ trunk/testbench/run.ms (nonexistent)
@@ -1,51 +0,0 @@
-#!/bin/csh
-
-if($#argv == 0) then
- echo Usage: run.ms IMAGENAME
- exit
-endif
-
-../c_model/convbtoh ../image/$argv[1].jpg test.mem
-
-if(-d ./work) rm -rf work
-
-vlib work
-vlog \
-../src/jpeg_regdata.v \
-../src/jpeg_ziguzagu_reg.v \
-../src/jpeg_ziguzagu.v \
-../src/jpeg_dqt.v \
-../src/jpeg_dht.v \
-../src/jpeg_hm_decode.v \
-../src/jpeg_haffuman.v \
-../src/jpeg_idctb.v \
-../src/jpeg_idctx.v \
-../src/jpeg_idcty.v \
-../src/jpeg_idct.v \
-../src/jpeg_ycbcr_mem.v \
-../src/jpeg_ycbcr2rgb.v \
-../src/jpeg_ycbcr.v \
-../src/jpeg_decode_fsm.v \
-../src/jpeg_decode.v \
-jpeg_test.v
-#jpeg_test
-#-cover \
-
-
-#echo "vsim -coverage -t 1ps -lib work jpeg_test" > modelsim.fdo
-echo "vsim -t 1ps -lib work jpeg_test" > modelsim.fdo
-echo "view wave" >> modelsim.fdo
-#echo "do wave.do" >> modelsim.fdo
-#echo "vcd file vcd/jpeg_test.vcd" >> modelsim.fdo
-#echo "vcd add -r *" >> modelsim.fdo
-echo "run 100 ms" >> modelsim.fdo
-echo "quit" >> modelsim.fdo
-
-#vsim -c -do modelsim.fdo
-vsim -do modelsim.fdo
-
-../c_model/convsim sim.dat sim.bmp
-
-rm -rf ./work
-rm transcript
-rm modelsim.fdo
trunk/testbench/run.ms
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/testbench/convbtoh.c
===================================================================
--- trunk/testbench/convbtoh.c (revision 5)
+++ trunk/testbench/convbtoh.c (nonexistent)
@@ -1,31 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-#include
-#include
-
-//////////////////////////////////////////////////////////////////////////////
-// メイン関数
-//////////////////////////////////////////////////////////////////////////////
-int main(int argc, char *argv[])
-{
- unsigned char buff[4];
- char data[256];
- FILE *rfp,*wfp;
-
- if((rfp = fopen(argv[1],"rb")) == NULL){
- perror(0);
- exit(0);
- }
- if((wfp = fopen(argv[2],"wb")) == NULL){
- perror(0);
- exit(0);
- }
- while(!feof(rfp)){
- fread(buff,1,4,rfp);
- sprintf(data,"%02X%02X%02X%02X\n",buff[3],buff[2],buff[1],buff[0]);
- fwrite(data,1,9,wfp);
- }
- fclose(rfp);
- fclose(wfp);
-
- return 0;
-}
trunk/testbench/convbtoh.c
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/testbench/jpeg_test.v
===================================================================
--- trunk/testbench/jpeg_test.v (revision 5)
+++ trunk/testbench/jpeg_test.v (nonexistent)
@@ -1,360 +0,0 @@
-//---------------------------------------------------------------------------
-// File Name : jpeg_test.v
-// Module Name : jpeg_test
-// Description : TestBench
-// Project : JPEG Decoder
-// Belong to :
-// Author : H.Ishihara
-// E-Mail : hidemi@sweetcafe.jp
-// HomePage : http://www.sweetcafe.jp/
-// Date : 2006/10/01
-// Rev. : 1.1
-//---------------------------------------------------------------------------
-// Rev. Date Description
-//---------------------------------------------------------------------------
-// 1.01 2006/10/01 1st Release
-//---------------------------------------------------------------------------
-// $Id:
-//---------------------------------------------------------------------------
-`timescale 1ps / 1ps
-
-module jpeg_test;
- reg rst;
- reg clk;
-
- reg [31:0] JPEG_MEM [0:1*1024*1024-1];
-
- integer DATA_COUNT;
-
- parameter clkP = 10000; // 100MHz
- parameter clkH = clkP /2;
- parameter clkL = clkP - clkH;
-
- wire [31:0] JPEG_DATA;
- reg DATA_ENABLE;
- wire READ_ENABLE;
- wire JPEG_IDLE;
-
- wire OutEnable;
- wire [15:0] OutWidth;
- wire [15:0] OutHeight;
- wire [15:0] OutPixelX;
- wire [15:0] OutPixelY;
- wire [7:0] OutR;
- wire [7:0] OutG;
- wire [7:0] OutB;
-
- integer count;
- reg [23:0] rgb_mem [0:1920*1080-1];
-
- initial begin
- count = 0;
- while(1) begin
- @(posedge clk);
- count = count +1;
- end
- end
-
- jpeg_decode u_jpeg_decode
- (
- .rst(rst),
- .clk(clk),
-
- .DataIn (JPEG_DATA),
- .DataInEnable (DATA_ENABLE),
- .DataInRead (READ_ENABLE),
- .JpegDecodeIdle (JPEG_IDLE),
-
- .OutEnable ( OutEnable ),
- .OutWidth ( OutWidth ),
- .OutHeight ( OutHeight ),
- .OutPixelX ( OutPixelX ),
- .OutPixelY ( OutPixelY ),
- .OutR ( OutR ),
- .OutG ( OutG ),
- .OutB ( OutB )
- );
-
-
- // Clock
- always begin
- #clkH clk = 0;
- #clkL clk = 1;
- end
-
- initial begin
- rst = 1'b0;
- repeat (3) @(posedge clk);
- rst = 1'b1;
- end
-
- // Read JPEG File
- initial begin
- $readmemh("test.mem",JPEG_MEM);
- end
-
- // Initial
- initial begin
- DATA_COUNT <= 0;
- DATA_ENABLE <= 1'b0;
- wait (rst == 1'b1);
- @(posedge clk);
- $display(" Start Clock: %d",count);
- @(posedge clk);
- @(posedge clk);
- DATA_ENABLE <= 1'b1;
- forever begin
- if(READ_ENABLE == 1'b1) begin
- DATA_COUNT <= DATA_COUNT +1;
- end
- @(posedge clk);
- end
- end // initial begin
-
- assign JPEG_DATA = JPEG_MEM[DATA_COUNT];
-
- integer i;
-
-/*
- initial begin
- @(posedge u_jpeg_decode.ImageEnable);
-
- $display("------------------------------");
- $display("Image Run");
- $display("------------------------------");
- $display(" DQT Y Table");
- for(i=0;i<64;i=i+1) begin
- $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dqt.DQT_Y[i]);
- end
-
- $display("------------------------------");
- $display(" DQT Cb/Cr Table");
- for(i=0;i<64;i=i+1) begin
- $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dqt.DQT_C[i]);
- end
- $display("------------------------------");
-
- $display("------------------------------");
- $display(" Haffuman Y-DC Code/Number");
- for(i=0;i<16;i=i+1) begin
- $display(" %2d: %2x,%2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable0r[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber0r[i]);
- end
- $display("------------------------------");
-
- $display("------------------------------");
- $display(" Haffuman Y-DC Table");
- for(i=0;i<16;i=i+1) begin
- $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dht.DHT_Ydc[i]);
- end
- $display("------------------------------");
-
- $display("------------------------------");
- $display(" Haffuman Y-AC Code/Number");
- for(i=0;i<16;i=i+1) begin
- $display(" %2d: %2x,%2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable1r[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber1r[i]);
- end
- $display("------------------------------");
-
- $display("------------------------------");
- $display(" Haffuman Y-AC Table");
- for(i=0;i<162;i=i+1) begin
- $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dht.DHT_Yac[i]);
- end
- $display("------------------------------");
-
- $display("------------------------------");
- $display(" Haffuman C-DC Table");
- for(i=0;i<16;i=i+1) begin
- $display(" %2d: %2x,%2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable2r[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber2r[i]);
- end
- $display("------------------------------");
-
- $display("------------------------------");
- $display(" Haffuman C-DC Table");
- for(i=0;i<16;i=i+1) begin
- $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dht.DHT_Cdc[i]);
- end
- $display("------------------------------");
-
- $display("------------------------------");
- $display(" Haffuman C-AC Table");
- for(i=0;i<16;i=i+1) begin
- $display(" %2d: %2x,%2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable3r[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber3r[i]);
- end
- $display("------------------------------");
-
- $display("------------------------------");
- $display(" Haffuman C-AC Table");
- for(i=0;i<162;i=i+1) begin
- $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dht.DHT_Cac[i]);
- end
- $display("------------------------------");
- end
-*/
-/*
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'h2)
- $display(" Color: %d,%d",u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessColor,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessCount);
- end
- end
-
-
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'h4)
- for(i=0;i<16;i=i+1) begin
- $display(" Data Code: %8x,%8x",u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber[i]);
- end
- end
- end
-*/
-
-/*
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'h6)
- $display(" Wait for RAM");
- end
- end
-*/
-/*
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'h4)
- $display(" Data Code: %8x",u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessData);
- end
- end
-*/
-/*
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'hB)
- $display(" Data Code: %d,%d,%4x,%4x,%4x,%4x,%2x,%4x,%4x,%4x,%8x",
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.CodeNumber,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessCount,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.DhtNumber,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.DhtZero,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.DataNumber,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.TableCode,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.NumberCode,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.DqtData,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.OutCode,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.OutData,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessData);
- end
- end
-
-
-
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_haffuman.HmDecEnable == 1'b1)
- $display(" HmDec Code: %d,%4x",
- u_jpeg_decode.u_jpeg_haffuman.HmDecCount,
- u_jpeg_decode.u_jpeg_haffuman.HmDecData);
- end
- end
-*/
-
-/*
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_haffuman.HmOutEnable == 1'b1)
- for(i=0;i<64;i=i+1) begin
- $display(" Data Code: %d,%4x",i,
- u_jpeg_decode.u_jpeg_haffuman.u_jpeg_ziguzagu.RegData[i]);
- end
- end
- end
-*/
-
-/*
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_idct.DctXEnable == 1'b1)
- $display(" Dct Data[X]: %d,%4x,%4x",u_jpeg_decode.u_jpeg_idct.DctXCount,u_jpeg_decode.u_jpeg_idct.DctXData0r,u_jpeg_decode.u_jpeg_idct.DctXData1r);
- end
- end
-
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Enable == 1'b1)
- $display(" Dct Data[Y2]: %d,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x",u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Count,u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[0],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[1],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[2],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[3],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[4],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[5],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[6],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[7]);
- end
- end
-
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase5Enable == 1'b1)
- $display(" Dct Data[Y5]: %d,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x",u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase5Count,u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase5R0w,u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase5R1w,u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[0],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[1],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[2],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[3],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[4],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[5],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[6],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[7]);
- end
- end
-
-
-
- initial begin
- while(1) begin
- @(posedge clk);
- if(u_jpeg_decode.DctEnable == 1'b1)
- $display(" Dct Data[Y]: %d,%4x,%4x",u_jpeg_decode.DctCount,u_jpeg_decode.Dct0Data,u_jpeg_decode.Dct1Data);
- end
- end
-*/
-
- integer address;
- integer fp;
-
- initial begin
-
- while(1) begin
- if(u_jpeg_decode.OutEnable == 1'b1) begin
- address = u_jpeg_decode.OutWidth * u_jpeg_decode.OutPixelY +
- u_jpeg_decode.OutPixelX;
- /*
- $display(" RGB[%4d,%4d,%4d,%4d](%d): %3x,%3x,%3x = %2x,%2x,%2x",OutPixelX,OutPixelY,u_jpeg_decode.OutWidth,u_jpeg_decode.OutHeight,
- address,
- u_jpeg_decode.u_jpeg_ycbcr.u_jpeg_ycbcr2rgb.Phase3Y,
- u_jpeg_decode.u_jpeg_ycbcr.u_jpeg_ycbcr2rgb.Phase3Cb,
- u_jpeg_decode.u_jpeg_ycbcr.u_jpeg_ycbcr2rgb.Phase3Cr,
- OutR,OutG,OutB);
- */
- rgb_mem[address] = {OutR,OutG,OutB};
- end
- @(posedge clk);
- end
- end
-
-
- initial begin
- wait(!JPEG_IDLE);
- wait(JPEG_IDLE);
-
- $display(" End Clock %d",count);
- fp = $fopen("sim.dat");
- $fwrite(fp,"%0d\n",OutWidth);
- $fwrite(fp,"%0d\n",OutHeight);
-
- for(i=0;iN^n~私桷ｮｾ GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2) .symtab .strtab .shstrtab .interp .note.ABI-tag .hash .dynsym .dynstr .gnu.version .gnu.version_r .rel.dyn .rel.plt .init .text .fini .rodata .eh_frame .ctors .dtors .jcr .dynamic .got .got.plt .data .bss .comment # (( 1 HH P 7 ? ｡ G o ** T o HH 0 c xx l ` u 焜 p ﾐ { ﾐﾐ ﾌﾌ
- 闃
-
-
- ｧ ｬ ﾈ ｵ ﾘﾘ ｺ ﾜﾜ < ﾃ ﾉ $$ ﾎ $ 2
- ﾗ l 4 \ ﾙ ( H * H x 焜
- ﾐ ﾌ
- 闃 ﾘ ﾜ $ * 8 E $ T [ q P } ･ ｱ ﾇ ﾑ ﾚ # ﾜ 9 L b r 闃 y 8 ｨ 焜
- ｮ ~ ﾀ ﾐ ﾇ r ﾘ F @T $ tﾄ ( 3 ﾌ
- 9 ﾎ K [ $ b ､ r ( w 2 [ ｩ ｶ ﾊ call_gmon_start crtstuff.c __CTOR_LIST__ __DTOR_LIST__ __JCR_LIST__ completed.5751 p.5749 __do_global_dtors_aux frame_dummy __CTOR_END__ __DTOR_END__ __FRAME_END__ __JCR_END__ __do_global_ctors_aux convsim.c _DYNAMIC __fini_array_end __fini_array_start __init_array_end __preinit_array_end _GLOBAL_OFFSET_TABLE_ __init_array_start __preinit_array_start feof@@GLIBC_2.0 _fp_hw perror@@GLIBC_2.0 __dso_handle __libc_csu_fini _init malloc@@GLIBC_2.0 _start fgets@@GLIBC_2.0 strtol@@GLIBC_2.0 __libc_csu_init __bss_start main __libc_start_main@@GLIBC_2.0 data_start _fini fclose@@GLIBC_2.1 exit@@GLIBC_2.0 _edata free@@GLIBC_2.0 _end fopen@@GLIBC_2.1 _IO_stdin_used fwrite@@GLIBC_2.0 __data_start _Jv_RegisterClasses __gmon_start__
\ No newline at end of file
trunk/testbench/convsim
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/testbench/convsim.c
===================================================================
--- trunk/testbench/convsim.c (revision 5)
+++ trunk/testbench/convsim.c (nonexistent)
@@ -1,108 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-#include
-#include
-
-typedef unsigned short WORD;
-typedef unsigned long DWORD;
-typedef long LONG;
-
-typedef struct tagBITMAPINFOHEADER{
- DWORD biSize;
- LONG biWidth;
- LONG biHeight;
- WORD biPlanes;
- WORD biBitCount;
- DWORD biCompression;
- DWORD biSizeImage;
- LONG biXPelsPerMeter;
- LONG biYPelsPerMeter;
- DWORD biClrUsed;
- DWORD biClrImportant;
-} BITMAPINFOHEADER, *PBITMAPINFOHEADER;
-
-//////////////////////////////////////////////////////////////////////////////
-// メイン関数
-//////////////////////////////////////////////////////////////////////////////
-int main(int argc, char *argv[])
-{
- unsigned char buff[4];
- char data[256];
- FILE *rfp,*wfp;
-
- unsigned long width;
- unsigned long height;
- unsigned long bitdata;
- unsigned char tbuff[4];
- BITMAPINFOHEADER lpBi;
-
- unsigned char *image;
- unsigned int i;
-
- if((rfp = fopen(argv[1],"rb")) == NULL){
- perror(0);
- exit(0);
- }
-
- if((wfp = fopen(argv[2],"wb")) == NULL){
- perror(0);
- exit(0);
- }
-
-
- fgets(data,256,rfp);
- width = (unsigned int)strtol(data,NULL,10);
- fgets(data,256,rfp);
- height = (unsigned int)strtol(data,NULL,10);
-
- image = (unsigned char *)malloc(height*width*3);
-
- // ファイルヘッダの設定
- tbuff[0] = 'B';
- tbuff[1] = 'M';
- fwrite(tbuff,2,1,wfp);
- tbuff[3] = ((14 +40 +width * height * 3) >> 24) & 0xff;
- tbuff[2] = ((14 +40 +width * height * 3) >> 16) & 0xff;
- tbuff[1] = ((14 +40 +width * height * 3) >> 8) & 0xff;
- tbuff[0] = ((14 +40 +width * height * 3) >> 0) & 0xff;
- fwrite(tbuff,4,1,wfp);
- tbuff[1] = 0;
- tbuff[0] = 0;
- fwrite(tbuff,2,1,wfp);
- fwrite(tbuff,2,1,wfp);
- tbuff[3] = 0;
- tbuff[2] = 0;
- tbuff[1] = 0;
- tbuff[0] = 54;
- fwrite(tbuff,4,1,wfp);
-
- // インフォメーションの設定
- lpBi.biSize = 40;
- lpBi.biWidth = width;
- lpBi.biHeight = height;
- lpBi.biPlanes = 1;
- lpBi.biBitCount = 3*8;
- lpBi.biCompression = 0;
- lpBi.biSizeImage = width*height*3;
- lpBi.biXPelsPerMeter = 300;
- lpBi.biYPelsPerMeter = 300;
- lpBi.biClrUsed = 0;
- lpBi.biClrImportant = 0;
- fwrite(&lpBi,1,40,wfp);
-
- i = 0;
- while(!feof(rfp)){
- if(i>=width*height) break;
- fgets(data,256,rfp);
- bitdata=strtol(data,NULL,16);
- image[((height-i/width-1)*width*3)+(i%width)*3+0] = (bitdata >> 0) & 0xff;
- image[((height-i/width-1)*width*3)+(i%width)*3+1] = (bitdata >> 8) & 0xff;
- image[((height-i/width-1)*width*3)+(i%width)*3+2] = (bitdata >> 16) & 0xff;
- i++;
- }
- fwrite(image,1,width*height*3,wfp);
- fclose(rfp);
- fclose(wfp);
- free(image);
-
- return 0;
-}
trunk/testbench/convsim.c
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: djpeg/trunk/testbench/run.ms
===================================================================
--- djpeg/trunk/testbench/run.ms (nonexistent)
+++ djpeg/trunk/testbench/run.ms (revision 6)
@@ -0,0 +1,51 @@
+#!/bin/csh
+
+if($#argv == 0) then
+ echo Usage: run.ms IMAGENAME
+ exit
+endif
+
+../c_model/convbtoh ../image/$argv[1].jpg test.mem
+
+if(-d ./work) rm -rf work
+
+vlib work
+vlog \
+../src/jpeg_regdata.v \
+../src/jpeg_ziguzagu_reg.v \
+../src/jpeg_ziguzagu.v \
+../src/jpeg_dqt.v \
+../src/jpeg_dht.v \
+../src/jpeg_hm_decode.v \
+../src/jpeg_haffuman.v \
+../src/jpeg_idctb.v \
+../src/jpeg_idctx.v \
+../src/jpeg_idcty.v \
+../src/jpeg_idct.v \
+../src/jpeg_ycbcr_mem.v \
+../src/jpeg_ycbcr2rgb.v \
+../src/jpeg_ycbcr.v \
+../src/jpeg_decode_fsm.v \
+../src/jpeg_decode.v \
+jpeg_test.v
+#jpeg_test
+#-cover \
+
+
+#echo "vsim -coverage -t 1ps -lib work jpeg_test" > modelsim.fdo
+echo "vsim -t 1ps -lib work jpeg_test" > modelsim.fdo
+echo "view wave" >> modelsim.fdo
+#echo "do wave.do" >> modelsim.fdo
+#echo "vcd file vcd/jpeg_test.vcd" >> modelsim.fdo
+#echo "vcd add -r *" >> modelsim.fdo
+echo "run 100 ms" >> modelsim.fdo
+echo "quit" >> modelsim.fdo
+
+#vsim -c -do modelsim.fdo
+vsim -do modelsim.fdo
+
+../c_model/convsim sim.dat sim.bmp
+
+rm -rf ./work
+rm transcript
+rm modelsim.fdo
djpeg/trunk/testbench/run.ms
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: djpeg/trunk/testbench/jpeg_test.v
===================================================================
--- djpeg/trunk/testbench/jpeg_test.v (nonexistent)
+++ djpeg/trunk/testbench/jpeg_test.v (revision 6)
@@ -0,0 +1,360 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_test.v
+// Module Name : jpeg_test
+// Description : TestBench
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_test;
+ reg rst;
+ reg clk;
+
+ reg [31:0] JPEG_MEM [0:1*1024*1024-1];
+
+ integer DATA_COUNT;
+
+ parameter clkP = 10000; // 100MHz
+ parameter clkH = clkP /2;
+ parameter clkL = clkP - clkH;
+
+ wire [31:0] JPEG_DATA;
+ reg DATA_ENABLE;
+ wire READ_ENABLE;
+ wire JPEG_IDLE;
+
+ wire OutEnable;
+ wire [15:0] OutWidth;
+ wire [15:0] OutHeight;
+ wire [15:0] OutPixelX;
+ wire [15:0] OutPixelY;
+ wire [7:0] OutR;
+ wire [7:0] OutG;
+ wire [7:0] OutB;
+
+ integer count;
+ reg [23:0] rgb_mem [0:1920*1080-1];
+
+ initial begin
+ count = 0;
+ while(1) begin
+ @(posedge clk);
+ count = count +1;
+ end
+ end
+
+ jpeg_decode u_jpeg_decode
+ (
+ .rst(rst),
+ .clk(clk),
+
+ .DataIn (JPEG_DATA),
+ .DataInEnable (DATA_ENABLE),
+ .DataInRead (READ_ENABLE),
+ .JpegDecodeIdle (JPEG_IDLE),
+
+ .OutEnable ( OutEnable ),
+ .OutWidth ( OutWidth ),
+ .OutHeight ( OutHeight ),
+ .OutPixelX ( OutPixelX ),
+ .OutPixelY ( OutPixelY ),
+ .OutR ( OutR ),
+ .OutG ( OutG ),
+ .OutB ( OutB )
+ );
+
+
+ // Clock
+ always begin
+ #clkH clk = 0;
+ #clkL clk = 1;
+ end
+
+ initial begin
+ rst = 1'b0;
+ repeat (3) @(posedge clk);
+ rst = 1'b1;
+ end
+
+ // Read JPEG File
+ initial begin
+ $readmemh("test.mem",JPEG_MEM);
+ end
+
+ // Initial
+ initial begin
+ DATA_COUNT <= 0;
+ DATA_ENABLE <= 1'b0;
+ wait (rst == 1'b1);
+ @(posedge clk);
+ $display(" Start Clock: %d",count);
+ @(posedge clk);
+ @(posedge clk);
+ DATA_ENABLE <= 1'b1;
+ forever begin
+ if(READ_ENABLE == 1'b1) begin
+ DATA_COUNT <= DATA_COUNT +1;
+ end
+ @(posedge clk);
+ end
+ end // initial begin
+
+ assign JPEG_DATA = JPEG_MEM[DATA_COUNT];
+
+ integer i;
+
+/*
+ initial begin
+ @(posedge u_jpeg_decode.ImageEnable);
+
+ $display("------------------------------");
+ $display("Image Run");
+ $display("------------------------------");
+ $display(" DQT Y Table");
+ for(i=0;i<64;i=i+1) begin
+ $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dqt.DQT_Y[i]);
+ end
+
+ $display("------------------------------");
+ $display(" DQT Cb/Cr Table");
+ for(i=0;i<64;i=i+1) begin
+ $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dqt.DQT_C[i]);
+ end
+ $display("------------------------------");
+
+ $display("------------------------------");
+ $display(" Haffuman Y-DC Code/Number");
+ for(i=0;i<16;i=i+1) begin
+ $display(" %2d: %2x,%2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable0r[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber0r[i]);
+ end
+ $display("------------------------------");
+
+ $display("------------------------------");
+ $display(" Haffuman Y-DC Table");
+ for(i=0;i<16;i=i+1) begin
+ $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dht.DHT_Ydc[i]);
+ end
+ $display("------------------------------");
+
+ $display("------------------------------");
+ $display(" Haffuman Y-AC Code/Number");
+ for(i=0;i<16;i=i+1) begin
+ $display(" %2d: %2x,%2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable1r[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber1r[i]);
+ end
+ $display("------------------------------");
+
+ $display("------------------------------");
+ $display(" Haffuman Y-AC Table");
+ for(i=0;i<162;i=i+1) begin
+ $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dht.DHT_Yac[i]);
+ end
+ $display("------------------------------");
+
+ $display("------------------------------");
+ $display(" Haffuman C-DC Table");
+ for(i=0;i<16;i=i+1) begin
+ $display(" %2d: %2x,%2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable2r[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber2r[i]);
+ end
+ $display("------------------------------");
+
+ $display("------------------------------");
+ $display(" Haffuman C-DC Table");
+ for(i=0;i<16;i=i+1) begin
+ $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dht.DHT_Cdc[i]);
+ end
+ $display("------------------------------");
+
+ $display("------------------------------");
+ $display(" Haffuman C-AC Table");
+ for(i=0;i<16;i=i+1) begin
+ $display(" %2d: %2x,%2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable3r[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber3r[i]);
+ end
+ $display("------------------------------");
+
+ $display("------------------------------");
+ $display(" Haffuman C-AC Table");
+ for(i=0;i<162;i=i+1) begin
+ $display(" %2d: %2x",i,u_jpeg_decode.u_jpeg_haffuman.u_jpeg_dht.DHT_Cac[i]);
+ end
+ $display("------------------------------");
+ end
+*/
+/*
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'h2)
+ $display(" Color: %d,%d",u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessColor,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessCount);
+ end
+ end
+
+
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'h4)
+ for(i=0;i<16;i=i+1) begin
+ $display(" Data Code: %8x,%8x",u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanTable[i],u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.HaffumanNumber[i]);
+ end
+ end
+ end
+*/
+
+/*
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'h6)
+ $display(" Wait for RAM");
+ end
+ end
+*/
+/*
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'h4)
+ $display(" Data Code: %8x",u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessData);
+ end
+ end
+*/
+/*
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.Process == 4'hB)
+ $display(" Data Code: %d,%d,%4x,%4x,%4x,%4x,%2x,%4x,%4x,%4x,%8x",
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.CodeNumber,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessCount,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.DhtNumber,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.DhtZero,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.DataNumber,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.TableCode,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.NumberCode,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.DqtData,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.OutCode,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.OutData,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_hm_decode.ProcessData);
+ end
+ end
+
+
+
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_haffuman.HmDecEnable == 1'b1)
+ $display(" HmDec Code: %d,%4x",
+ u_jpeg_decode.u_jpeg_haffuman.HmDecCount,
+ u_jpeg_decode.u_jpeg_haffuman.HmDecData);
+ end
+ end
+*/
+
+/*
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_haffuman.HmOutEnable == 1'b1)
+ for(i=0;i<64;i=i+1) begin
+ $display(" Data Code: %d,%4x",i,
+ u_jpeg_decode.u_jpeg_haffuman.u_jpeg_ziguzagu.RegData[i]);
+ end
+ end
+ end
+*/
+
+/*
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_idct.DctXEnable == 1'b1)
+ $display(" Dct Data[X]: %d,%4x,%4x",u_jpeg_decode.u_jpeg_idct.DctXCount,u_jpeg_decode.u_jpeg_idct.DctXData0r,u_jpeg_decode.u_jpeg_idct.DctXData1r);
+ end
+ end
+
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Enable == 1'b1)
+ $display(" Dct Data[Y2]: %d,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x",u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Count,u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[0],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[1],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[2],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[3],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[4],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[5],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[6],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[7]);
+ end
+ end
+
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase5Enable == 1'b1)
+ $display(" Dct Data[Y5]: %d,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x",u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase5Count,u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase5R0w,u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase5R1w,u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[0],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[1],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[2],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[3],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[4],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[5],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[6],u_jpeg_decode.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[7]);
+ end
+ end
+
+
+
+ initial begin
+ while(1) begin
+ @(posedge clk);
+ if(u_jpeg_decode.DctEnable == 1'b1)
+ $display(" Dct Data[Y]: %d,%4x,%4x",u_jpeg_decode.DctCount,u_jpeg_decode.Dct0Data,u_jpeg_decode.Dct1Data);
+ end
+ end
+*/
+
+ integer address;
+ integer fp;
+
+ initial begin
+
+ while(1) begin
+ if(u_jpeg_decode.OutEnable == 1'b1) begin
+ address = u_jpeg_decode.OutWidth * u_jpeg_decode.OutPixelY +
+ u_jpeg_decode.OutPixelX;
+ /*
+ $display(" RGB[%4d,%4d,%4d,%4d](%d): %3x,%3x,%3x = %2x,%2x,%2x",OutPixelX,OutPixelY,u_jpeg_decode.OutWidth,u_jpeg_decode.OutHeight,
+ address,
+ u_jpeg_decode.u_jpeg_ycbcr.u_jpeg_ycbcr2rgb.Phase3Y,
+ u_jpeg_decode.u_jpeg_ycbcr.u_jpeg_ycbcr2rgb.Phase3Cb,
+ u_jpeg_decode.u_jpeg_ycbcr.u_jpeg_ycbcr2rgb.Phase3Cr,
+ OutR,OutG,OutB);
+ */
+ rgb_mem[address] = {OutR,OutG,OutB};
+ end
+ @(posedge clk);
+ end
+ end
+
+
+ initial begin
+ wait(!JPEG_IDLE);
+ wait(JPEG_IDLE);
+
+ $display(" End Clock %d",count);
+ fp = $fopen("sim.dat");
+ $fwrite(fp,"%0d\n",OutWidth);
+ $fwrite(fp,"%0d\n",OutHeight);
+
+ for(i=0;i
+#include
+
+typedef unsigned short WORD;
+typedef unsigned long DWORD;
+typedef long LONG;
+
+typedef struct tagBITMAPINFOHEADER{
+ DWORD biSize;
+ LONG biWidth;
+ LONG biHeight;
+ WORD biPlanes;
+ WORD biBitCount;
+ DWORD biCompression;
+ DWORD biSizeImage;
+ LONG biXPelsPerMeter;
+ LONG biYPelsPerMeter;
+ DWORD biClrUsed;
+ DWORD biClrImportant;
+} BITMAPINFOHEADER, *PBITMAPINFOHEADER;
+
+//////////////////////////////////////////////////////////////////////////////
+// メイン関数
+//////////////////////////////////////////////////////////////////////////////
+int main(int argc, char *argv[])
+{
+ unsigned char buff[4];
+ char data[256];
+ FILE *rfp,*wfp;
+
+ unsigned long width;
+ unsigned long height;
+ unsigned long bitdata;
+ unsigned char tbuff[4];
+ BITMAPINFOHEADER lpBi;
+
+ unsigned char *image;
+ unsigned int i;
+
+ if((rfp = fopen(argv[1],"rb")) == NULL){
+ perror(0);
+ exit(0);
+ }
+
+ if((wfp = fopen(argv[2],"wb")) == NULL){
+ perror(0);
+ exit(0);
+ }
+
+
+ fgets(data,256,rfp);
+ width = (unsigned int)strtol(data,NULL,10);
+ fgets(data,256,rfp);
+ height = (unsigned int)strtol(data,NULL,10);
+
+ image = (unsigned char *)malloc(height*width*3);
+
+ // ファイルヘッダの設定
+ tbuff[0] = 'B';
+ tbuff[1] = 'M';
+ fwrite(tbuff,2,1,wfp);
+ tbuff[3] = ((14 +40 +width * height * 3) >> 24) & 0xff;
+ tbuff[2] = ((14 +40 +width * height * 3) >> 16) & 0xff;
+ tbuff[1] = ((14 +40 +width * height * 3) >> 8) & 0xff;
+ tbuff[0] = ((14 +40 +width * height * 3) >> 0) & 0xff;
+ fwrite(tbuff,4,1,wfp);
+ tbuff[1] = 0;
+ tbuff[0] = 0;
+ fwrite(tbuff,2,1,wfp);
+ fwrite(tbuff,2,1,wfp);
+ tbuff[3] = 0;
+ tbuff[2] = 0;
+ tbuff[1] = 0;
+ tbuff[0] = 54;
+ fwrite(tbuff,4,1,wfp);
+
+ // インフォメーションの設定
+ lpBi.biSize = 40;
+ lpBi.biWidth = width;
+ lpBi.biHeight = height;
+ lpBi.biPlanes = 1;
+ lpBi.biBitCount = 3*8;
+ lpBi.biCompression = 0;
+ lpBi.biSizeImage = width*height*3;
+ lpBi.biXPelsPerMeter = 300;
+ lpBi.biYPelsPerMeter = 300;
+ lpBi.biClrUsed = 0;
+ lpBi.biClrImportant = 0;
+ fwrite(&lpBi,1,40,wfp);
+
+ i = 0;
+ while(!feof(rfp)){
+ if(i>=width*height) break;
+ fgets(data,256,rfp);
+ bitdata=strtol(data,NULL,16);
+ image[((height-i/width-1)*width*3)+(i%width)*3+0] = (bitdata >> 0) & 0xff;
+ image[((height-i/width-1)*width*3)+(i%width)*3+1] = (bitdata >> 8) & 0xff;
+ image[((height-i/width-1)*width*3)+(i%width)*3+2] = (bitdata >> 16) & 0xff;
+ i++;
+ }
+ fwrite(image,1,width*height*3,wfp);
+ fclose(rfp);
+ fclose(wfp);
+ free(image);
+
+ return 0;
+}
djpeg/trunk/testbench/convsim.c
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: djpeg/trunk/testbench/convbtoh
===================================================================
--- djpeg/trunk/testbench/convbtoh (nonexistent)
+++ djpeg/trunk/testbench/convbtoh (revision 6)
@@ -0,0 +1,14 @@
+ELF `4 D
+ 4 ( 4 44 @ @ @ @@ T TTﾈ ﾈ ( (( Q蚯d /lib/ld-linux.so.2 GNU
+
+ 5 . : p H ﾊ V [ 2 a @ 4 O X _Jv_RegisterClasses __gmon_start__ libc.so.6 perror feof fread sprintf fclose fwrite exit fopen _IO_stdin_used __libc_start_main GLIBC_2.1 GLIBC_2.0 $ ii
+ ii
+ , 0 4 8 < @ D H L
+ P U牙鞦 8 # ﾉﾃ 5$%( %,h 鰲%0h 鰔%4h 鯊%8h 魏%<h 鬆%@h( 髏%Dh0 騾%Hh8 駱%Lh@ 饒%PhH 餘1^蚊蓿PTRhhhpQVh鑰瑞U牙S [ﾃ 挙ﾒt隱X[ﾉﾃ瑞瑞瑞U牙=\ t β｣Xﾒ｡Xﾒuﾆ\ﾉﾃ振牙｡Pﾀtｸ ﾀt ﾇ$Pﾐﾉﾃ錐L$蓿qU牙SQ0 燕虚毅β ﾇD$$$鞳右マ uﾇ$ 閙ﾇ$ 雋虚毅β ﾇD$'$隍右マ ｡ ﾇ$ ;ﾇ$ 鑰畿吋$ ﾇD$ ﾇD$ 孔$ ｶEｶﾈｶEｶﾘｶEｶﾐｶEｶﾀ鵜$噂$欝$ 吋$ﾇD$*劫$+畿吋$ ﾇD$ ﾇD$ 劫$畿$闍ﾀd畿$雕畿$隴ｸ ﾄ0 Y[]溝ﾃ瑞振牙ﾉﾃ貢 U牙WVS [ﾃ｢ 鴻 酷 )ﾐﾁ右t 1茄Puu uGθζ9}u闕e[^_ﾉﾃ瑞瑞瑞瑞瑞瑞U牙S｡@t1ﾛﾐ泣<uζ[]ﾃ瑞振牙S [ﾃ 陷Y[ﾉﾃ rb wb %02X%02X%02X%02X
+ $
+ H ` 吹
+ P H @ oo o T ﾆﾖ諠&6FV L GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.1 20060525 (Red Hat 4.1.1-1) GCC: (GNU) 4.1.1 20060525 (Red Hat 4.1.1-1) GCC: (GNU) 4.1.1 20060525 (Red Hat 4.1.1-1) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) .symtab .strtab .shstrtab .interp .note.ABI-tag .hash .dynsym .dynstr .gnu.version .gnu.version_r .rel.dyn .rel.plt .init .text .fini .rodata .eh_frame .ctors .dtors .jcr .dynamic .got .got.plt .data .bss .comment # (( 1 HH H 7 吹 ﾐ ? `` G o T o 0 c @@ l HH P u p ｰｰ ｰ { `` $ << @@ HH ｧ PP ｬ TT ﾈ ｵ ｺ 4 ﾃ TT ﾉ \\ ﾎ \ j ﾗ ､ ﾐ 4 t ｹ ( H 吹 ` @ H
+ ｰ `
+ < @ H P T T \ т @ * H 8 P E \ T X [ ｰ q 焙 } D L < ･ P ｱ ﾐ ﾇ ﾒ T ﾛ @ @ @ @ $ : @ M @ c s z h ｩ
+ ｯ ﾀ ` ﾇ pT ﾗ \ a T
+ ﾊ ( 8 \ ? ` D 2 U d 4 w X T ｪ call_gmon_start crtstuff.c __CTOR_LIST__ __DTOR_LIST__ __JCR_LIST__ completed.5754 p.5752 __do_global_dtors_aux frame_dummy __CTOR_END__ __DTOR_END__ __FRAME_END__ __JCR_END__ __do_global_ctors_aux convbtoh.c _DYNAMIC __fini_array_end __fini_array_start __init_array_end __preinit_array_end _GLOBAL_OFFSET_TABLE_ __init_array_start __preinit_array_start feof@@GLIBC_2.0 _fp_hw perror@@GLIBC_2.0 __dso_handle __libc_csu_fini _init fread@@GLIBC_2.0 _start __libc_csu_init __bss_start main __libc_start_main@@GLIBC_2.0 data_start _fini fclose@@GLIBC_2.1 exit@@GLIBC_2.0 _edata _end fopen@@GLIBC_2.1 _IO_stdin_used sprintf@@GLIBC_2.0 fwrite@@GLIBC_2.0 __data_start _Jv_RegisterClasses __gmon_start__
\ No newline at end of file
djpeg/trunk/testbench/convbtoh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: djpeg/trunk/testbench/convbtoh.c
===================================================================
--- djpeg/trunk/testbench/convbtoh.c (nonexistent)
+++ djpeg/trunk/testbench/convbtoh.c (revision 6)
@@ -0,0 +1,31 @@
+//////////////////////////////////////////////////////////////////////////////
+#include
+#include
+
+//////////////////////////////////////////////////////////////////////////////
+// メイン関数
+//////////////////////////////////////////////////////////////////////////////
+int main(int argc, char *argv[])
+{
+ unsigned char buff[4];
+ char data[256];
+ FILE *rfp,*wfp;
+
+ if((rfp = fopen(argv[1],"rb")) == NULL){
+ perror(0);
+ exit(0);
+ }
+ if((wfp = fopen(argv[2],"wb")) == NULL){
+ perror(0);
+ exit(0);
+ }
+ while(!feof(rfp)){
+ fread(buff,1,4,rfp);
+ sprintf(data,"%02X%02X%02X%02X\n",buff[3],buff[2],buff[1],buff[0]);
+ fwrite(data,1,9,wfp);
+ }
+ fclose(rfp);
+ fclose(wfp);
+
+ return 0;
+}
djpeg/trunk/testbench/convbtoh.c
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: djpeg/trunk/testbench/convsim
===================================================================
--- djpeg/trunk/testbench/convsim (nonexistent)
+++ djpeg/trunk/testbench/convsim (revision 6)
@@ -0,0 +1,22 @@
+ELF ﾐ4 4 ( 4 44
+
+
+ ( , ﾈ ﾈ ( (( Q蚯d /lib/ld-linux.so.2 GNU
+
+ ; 4 @ ~ . r G F v N ﾎ \ ､ a 2 g U [ _Jv_RegisterClasses __gmon_start__ libc.so.6 fgets perror feof malloc strtol fclose fwrite exit fopen _IO_stdin_used __libc_start_main free GLIBC_2.1 GLIBC_2.0 $ ii
+ ii
+ ﾘ 陋
+ U牙 鐐 隲 ﾉﾃ 5燬%茆 %陋h 鰲%h 鰔%h 鯊%h 魏%h 鬆%h( 髏% h0 騾%h8 駱%h@ 饒% hH 餘%hP 顱%hX 0 1^蚊蓿PTRh8h@QVht鑒瑞U牙S [ﾃﾜ 挙ﾒt陲X[ﾉﾃ瑞瑞瑞U牙=$ t β｣ ﾒ｡ ﾒuﾆ$ﾉﾃ振牙｡ ﾀtｸ ﾀt ﾇ$ ﾐﾉﾃ錐L$蓿qU牙Qd 燕ｨ虚ｨ毅β ﾇD$$韲右焜} uﾇ$ 鏝ﾇ$ 隲牛ｨ帰β ﾇD$$隴右艫} uﾇ$ ﾇ$ 鑞畿煢D$ﾇD$ 劫ﾜ$ﾇD$
+ ﾇD$ 劫ﾜ$右闍E煢D$ﾇD$ 劫ﾜ$靦ﾇD$
+ ﾇD$ 劫ﾜ$霤右畿可ｯU濶ﾐﾀﾐ$濶右ﾆﾘBﾆﾙM畿芍D$ ﾇD$ ﾇD$ 劫ﾘ$勒畿濶ﾂｯU禍ﾀﾐβ6ﾁﾛ畿濶ﾂｯU禍ﾀﾐβ6ﾁﾚ畿濶ﾂｯU禍ﾀﾐβ6ﾁﾙ畿濶ﾂｯU禍ﾀﾐβ6ﾘ畿芍D$ ﾇD$ ﾇD$ 劫ﾘ$錵ﾆﾙ ﾆﾘ 畿芍D$ ﾇD$ ﾇD$ 劫ﾘ$畿芍D$ ﾇD$ ﾇD$ 劫ﾘ$竟ﾆﾛ ﾆﾚ ﾆﾙ ﾆﾘ6畿芍D$ ﾇD$ ﾇD$ 劫ﾘ$隰ﾇｰ( 畿濶ｴ畿怨ｸfﾇｼ fﾇｾ ﾇﾀ 畿濶ﾂｯU禍ﾀﾐ怨ﾄﾇﾈ, ﾇﾌ, ﾇﾐ ﾇﾔ 畿芍D$ ﾇD$( ﾇD$ 劫ｰ$ﾇE # 畿ｯE;E& 畿煢D$ﾇD$ 劫ﾜ$鑛ﾇD$ ﾇD$ 劫ﾜ$鐚右畿ｺ u濶ﾂ畿加)ﾑ果禍ﾀﾐ加ｯM闍Eｺ u濶ﾐﾀﾐ可U畿畿ｺ u濶ﾂ畿加)ﾑ果禍ﾀﾐ加ｯM闍Eｺ u濶ﾐﾀﾐE恒畿ﾁ畿ｺ u濶ﾂ畿加)ﾑ果禍ﾀﾐ加ｯM闍Eｺ u濶ﾐﾀﾐE恒畿ﾁウ畿煢$8ﾀﾊ畿濶ﾂｯU禍ﾀ畿芍D$ 欝$ﾇD$ 畿$陲畿煢$鏝畿芍$鎰畿$鐶ｸ ﾄd Y]溝ﾃU牙ﾉﾃ貢 U牙WVS [ﾃ 閹鴻 酷 )ﾐﾁ右t 1茄Puu uGθζ9}u闕e[^_ﾉﾃ瑞瑞瑞瑞瑞瑞U牙S｡t1ﾛﾐ泣uζ[]ﾃ瑞振牙S [ﾃ N^n~私桷ｮｾ GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-3) GCC: (GNU) 4.1.0 20060304 (Red Hat 4.1.0-2) .symtab .strtab .shstrtab .interp .note.ABI-tag .hash .dynsym .dynstr .gnu.version .gnu.version_r .rel.dyn .rel.plt .init .text .fini .rodata .eh_frame .ctors .dtors .jcr .dynamic .got .got.plt .data .bss .comment # (( 1 HH P 7 ? ｡ G o ** T o HH 0 c xx l ` u 焜 p ﾐ { ﾐﾐ ﾌﾌ
+ 闃
+
+
+ ｧ ｬ ﾈ ｵ ﾘﾘ ｺ ﾜﾜ < ﾃ ﾉ $$ ﾎ $ 2
+ ﾗ l 4 \ ﾙ ( H * H x 焜
+ ﾐ ﾌ
+ 闃 ﾘ ﾜ $ * 8 E $ T [ q P } ･ ｱ ﾇ ﾑ ﾚ # ﾜ 9 L b r 闃 y 8 ｨ 焜
+ ｮ ~ ﾀ ﾐ ﾇ r ﾘ F @T $ tﾄ ( 3 ﾌ
+ 9 ﾎ K [ $ b ､ r ( w 2 [ ｩ ｶ ﾊ call_gmon_start crtstuff.c __CTOR_LIST__ __DTOR_LIST__ __JCR_LIST__ completed.5751 p.5749 __do_global_dtors_aux frame_dummy __CTOR_END__ __DTOR_END__ __FRAME_END__ __JCR_END__ __do_global_ctors_aux convsim.c _DYNAMIC __fini_array_end __fini_array_start __init_array_end __preinit_array_end _GLOBAL_OFFSET_TABLE_ __init_array_start __preinit_array_start feof@@GLIBC_2.0 _fp_hw perror@@GLIBC_2.0 __dso_handle __libc_csu_fini _init malloc@@GLIBC_2.0 _start fgets@@GLIBC_2.0 strtol@@GLIBC_2.0 __libc_csu_init __bss_start main __libc_start_main@@GLIBC_2.0 data_start _fini fclose@@GLIBC_2.1 exit@@GLIBC_2.0 _edata free@@GLIBC_2.0 _end fopen@@GLIBC_2.1 _IO_stdin_used fwrite@@GLIBC_2.0 __data_start _Jv_RegisterClasses __gmon_start__
\ No newline at end of file
djpeg/trunk/testbench/convsim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: djpeg/trunk/src/jpeg_hm_decode.v
===================================================================
--- djpeg/trunk/src/jpeg_hm_decode.v (nonexistent)
+++ djpeg/trunk/src/jpeg_hm_decode.v (revision 6)
@@ -0,0 +1,860 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_hm_decode.v
+// Module Name : jpeg_hm_decode
+// Description : Decode of Haffuman data
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+// 1.02 2006/10/04 move for a comment widh OutData,OutDhtNumber register.
+// remove a ProcessColorNumber,tempPlace register.
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_hm_decode
+ (
+ rst, // Reset
+ clk, // Clock
+
+ // Haffuman Table
+ HaffumanTableEnable, // Table Data In Enable
+ HaffumanTableColor, // Haffuman Table Color Number
+ HaffumanTableCount, // Table Number
+ HaffumanTableCode, // Haffuman Table Code
+ HaffumanTableStart, // Haffuman Table Start Number
+
+ // Haffuman Decode
+ DataInRun, // Data In Start
+ DataInEnable, // Data In Enable
+ DataIn, // Data In
+
+ // DHT table
+ DhtColor, // Color Number
+ DhtNumber, // Decode Dht Number
+ DhtZero, // Zero Count of Dht Number
+ DhtWidth, // Data Width of Dht Number
+
+ // DQT Table
+ DqtColor, // Color Number
+ DqtNumber, // Dqt Number
+ DqtData, // Dqt Data
+
+ //
+ DataOutIdle,
+ DataOutEnable,
+ DataOutColor,
+
+ // Output decode data
+ DecodeUseBit, // Used Data Bit
+ DecodeUseWidth, // Used Data Width
+ DecodeEnable, // Data Out Enable
+ DecodeColor, // Data Out Enable
+ DecodeCount, // Data Out Enable
+ DecodeZero, // Data Out with Zero Count
+ DecodeCode // Data Out with Code
+ );
+
+ //--------------------------------------------------------------------------
+ // Input/Output
+ //--------------------------------------------------------------------------
+ input rst,clk; // Reset and Clock
+ input HaffumanTableEnable; // Table Data In Enable
+ input [1:0] HaffumanTableColor;
+ input [3:0] HaffumanTableCount; // Table Number
+ input [15:0] HaffumanTableCode; // Haffuman Table Data
+ input [7:0] HaffumanTableStart; // Haffuman Table Start Number
+
+ input DataInRun;
+ input DataInEnable; // Data In Enable
+ input [31:0] DataIn; // Data In
+
+ output [1:0] DhtColor;
+ output [7:0] DhtNumber; // Decode Dht Number
+ input [3:0] DhtZero; // Zero Count of Dht Number
+ input [3:0] DhtWidth; // Data Width of Dht Number
+
+ output DqtColor;
+ output [5:0] DqtNumber;
+ input [7:0] DqtData;
+
+ input DataOutIdle;
+ output DataOutEnable;
+ output [2:0] DataOutColor;
+
+
+ output DecodeUseBit;
+ output [6:0] DecodeUseWidth; // Used Data Width
+ output DecodeEnable; // Data Out Enable
+ output [2:0] DecodeColor;
+ output [5:0] DecodeCount;
+ output [3:0] DecodeZero; // Data Out with Zero Count
+ output [15:0] DecodeCode; // Data Out with Code
+
+ //--------------------------------------------------------------------------
+ // Register Haffuman Table(YCbCr)
+ //--------------------------------------------------------------------------
+ // Y-DC Haffuman Table
+ reg [15:0] HaffumanTable0r [0:15]; // Y-DC Haffuman Table
+ reg [15:0] HaffumanTable1r [0:15]; // Y-AC Haffuman Table
+ reg [15:0] HaffumanTable2r [0:15]; // C-DC Haffuman Table
+ reg [15:0] HaffumanTable3r [0:15]; // C-AC Haffuman Table
+
+ reg [15:0] HaffumanNumber0r [0:15]; // Y-DC Haffuman Number
+ reg [15:0] HaffumanNumber1r [0:15]; // Y-AC Haffuman Number
+ reg [15:0] HaffumanNumber2r [0:15]; // C-DC Haffuman Number
+ reg [15:0] HaffumanNumber3r [0:15]; // C-AC Haffuman Number
+
+ integer i;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ HaffumanTable0r[0] <= 16'h0000;
+ HaffumanNumber0r[0] <= 8'h00;
+ HaffumanTable1r[0] <= 16'h0000;
+ HaffumanNumber1r[0] <= 8'h00;
+ HaffumanTable2r[0] <= 16'h0000;
+ HaffumanNumber2r[0] <= 8'h00;
+ HaffumanTable3r[0] <= 16'h0000;
+ HaffumanNumber3r[0] <= 8'h00;
+
+ HaffumanTable0r[1] <= 16'h0000;
+ HaffumanNumber0r[1] <= 8'h00;
+ HaffumanTable1r[1] <= 16'h0000;
+ HaffumanNumber1r[1] <= 8'h00;
+ HaffumanTable2r[1] <= 16'h0000;
+ HaffumanNumber2r[1] <= 8'h00;
+ HaffumanTable3r[1] <= 16'h0000;
+ HaffumanNumber3r[1] <= 8'h00;
+
+ HaffumanTable0r[2] <= 16'h0000;
+ HaffumanNumber0r[2] <= 8'h00;
+ HaffumanTable1r[2] <= 16'h0000;
+ HaffumanNumber1r[2] <= 8'h00;
+ HaffumanTable2r[2] <= 16'h0000;
+ HaffumanNumber2r[2] <= 8'h00;
+ HaffumanTable3r[2] <= 16'h0000;
+ HaffumanNumber3r[2] <= 8'h00;
+
+ HaffumanTable0r[3] <= 16'h0000;
+ HaffumanNumber0r[3] <= 8'h00;
+ HaffumanTable1r[3] <= 16'h0000;
+ HaffumanNumber1r[3] <= 8'h00;
+ HaffumanTable2r[3] <= 16'h0000;
+ HaffumanNumber2r[3] <= 8'h00;
+ HaffumanTable3r[3] <= 16'h0000;
+ HaffumanNumber3r[3] <= 8'h00;
+
+ HaffumanTable0r[4] <= 16'h0000;
+ HaffumanNumber0r[4] <= 8'h00;
+ HaffumanTable1r[4] <= 16'h0000;
+ HaffumanNumber1r[4] <= 8'h00;
+ HaffumanTable2r[4] <= 16'h0000;
+ HaffumanNumber2r[4] <= 8'h00;
+ HaffumanTable3r[4] <= 16'h0000;
+ HaffumanNumber3r[4] <= 8'h00;
+
+ HaffumanTable0r[5] <= 16'h0000;
+ HaffumanNumber0r[5] <= 8'h00;
+ HaffumanTable1r[5] <= 16'h0000;
+ HaffumanNumber1r[5] <= 8'h00;
+ HaffumanTable2r[5] <= 16'h0000;
+ HaffumanNumber2r[5] <= 8'h00;
+ HaffumanTable3r[5] <= 16'h0000;
+ HaffumanNumber3r[5] <= 8'h00;
+
+ HaffumanTable0r[6] <= 16'h0000;
+ HaffumanNumber0r[6] <= 8'h00;
+ HaffumanTable1r[6] <= 16'h0000;
+ HaffumanNumber1r[6] <= 8'h00;
+ HaffumanTable2r[6] <= 16'h0000;
+ HaffumanNumber2r[6] <= 8'h00;
+ HaffumanTable3r[6] <= 16'h0000;
+ HaffumanNumber3r[6] <= 8'h00;
+
+ HaffumanTable0r[7] <= 16'h0000;
+ HaffumanNumber0r[7] <= 8'h00;
+ HaffumanTable1r[7] <= 16'h0000;
+ HaffumanNumber1r[7] <= 8'h00;
+ HaffumanTable2r[7] <= 16'h0000;
+ HaffumanNumber2r[7] <= 8'h00;
+ HaffumanTable3r[7] <= 16'h0000;
+ HaffumanNumber3r[7] <= 8'h00;
+
+ HaffumanTable0r[8] <= 16'h0000;
+ HaffumanNumber0r[8] <= 8'h00;
+ HaffumanTable1r[8] <= 16'h0000;
+ HaffumanNumber1r[8] <= 8'h00;
+ HaffumanTable2r[8] <= 16'h0000;
+ HaffumanNumber2r[8] <= 8'h00;
+ HaffumanTable3r[8] <= 16'h0000;
+ HaffumanNumber3r[8] <= 8'h00;
+
+ HaffumanTable0r[9] <= 16'h0000;
+ HaffumanNumber0r[9] <= 8'h00;
+ HaffumanTable1r[9] <= 16'h0000;
+ HaffumanNumber1r[9] <= 8'h00;
+ HaffumanTable2r[9] <= 16'h0000;
+ HaffumanNumber2r[9] <= 8'h00;
+ HaffumanTable3r[9] <= 16'h0000;
+ HaffumanNumber3r[9] <= 8'h00;
+
+ HaffumanTable0r[10] <= 16'h0000;
+ HaffumanNumber0r[10] <= 8'h00;
+ HaffumanTable1r[10] <= 16'h0000;
+ HaffumanNumber1r[10] <= 8'h00;
+ HaffumanTable2r[10] <= 16'h0000;
+ HaffumanNumber2r[10] <= 8'h00;
+ HaffumanTable3r[10] <= 16'h0000;
+ HaffumanNumber3r[10] <= 8'h00;
+
+ HaffumanTable0r[11] <= 16'h0000;
+ HaffumanNumber0r[11] <= 8'h00;
+ HaffumanTable1r[11] <= 16'h0000;
+ HaffumanNumber1r[11] <= 8'h00;
+ HaffumanTable2r[11] <= 16'h0000;
+ HaffumanNumber2r[11] <= 8'h00;
+ HaffumanTable3r[11] <= 16'h0000;
+ HaffumanNumber3r[11] <= 8'h00;
+
+ HaffumanTable0r[12] <= 16'h0000;
+ HaffumanNumber0r[12] <= 8'h00;
+ HaffumanTable1r[12] <= 16'h0000;
+ HaffumanNumber1r[12] <= 8'h00;
+ HaffumanTable2r[12] <= 16'h0000;
+ HaffumanNumber2r[12] <= 8'h00;
+ HaffumanTable3r[12] <= 16'h0000;
+ HaffumanNumber3r[12] <= 8'h00;
+
+ HaffumanTable0r[13] <= 16'h0000;
+ HaffumanNumber0r[13] <= 8'h00;
+ HaffumanTable1r[13] <= 16'h0000;
+ HaffumanNumber1r[13] <= 8'h00;
+ HaffumanTable2r[13] <= 16'h0000;
+ HaffumanNumber2r[13] <= 8'h00;
+ HaffumanTable3r[13] <= 16'h0000;
+ HaffumanNumber3r[13] <= 8'h00;
+
+ HaffumanTable0r[14] <= 16'h0000;
+ HaffumanNumber0r[14] <= 8'h00;
+ HaffumanTable1r[14] <= 16'h0000;
+ HaffumanNumber1r[14] <= 8'h00;
+ HaffumanTable2r[14] <= 16'h0000;
+ HaffumanNumber2r[14] <= 8'h00;
+ HaffumanTable3r[14] <= 16'h0000;
+ HaffumanNumber3r[14] <= 8'h00;
+
+ HaffumanTable0r[15] <= 16'h0000;
+ HaffumanNumber0r[15] <= 8'h00;
+ HaffumanTable1r[15] <= 16'h0000;
+ HaffumanNumber1r[15] <= 8'h00;
+ HaffumanTable2r[15] <= 16'h0000;
+ HaffumanNumber2r[15] <= 8'h00;
+ HaffumanTable3r[15] <= 16'h0000;
+ HaffumanNumber3r[15] <= 8'h00;
+ end else begin // if (!rst)
+ if(HaffumanTableEnable ==2'b1) begin
+ if(HaffumanTableColor ==2'b00) begin
+ HaffumanTable0r[HaffumanTableCount] <= HaffumanTableCode;
+ HaffumanNumber0r[HaffumanTableCount] <= HaffumanTableStart;
+ end else if(HaffumanTableColor ==2'b01) begin
+ HaffumanTable1r[HaffumanTableCount] <= HaffumanTableCode;
+ HaffumanNumber1r[HaffumanTableCount] <= HaffumanTableStart;
+ end else if(HaffumanTableColor ==2'b10) begin
+ HaffumanTable2r[HaffumanTableCount] <= HaffumanTableCode;
+ HaffumanNumber2r[HaffumanTableCount] <= HaffumanTableStart;
+ end else begin
+ HaffumanTable3r[HaffumanTableCount] <= HaffumanTableCode;
+ HaffumanNumber3r[HaffumanTableCount] <= HaffumanTableStart;
+ end
+ end // if (HaffumanTableEnable ==2'b1)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //--------------------------------------------------------------------------
+ // Decode Process
+ //--------------------------------------------------------------------------
+ reg [3:0] Process; // Process State
+ reg [31:0] ProcessData; // Data
+
+ // Haffuman Table
+ reg [15:0] HaffumanTable [0:15];
+ // Haffuman Table Number
+ reg [7:0] HaffumanNumber [0:15];
+
+ reg [15:0] Place; // Place bit
+ reg [15:0] TableCode; // Table Code
+ reg [7:0] NumberCode; // Start Number of Table Code
+ reg [3:0] CodeNumber; // Haffuman code width
+ reg [15:0] DataNumber; // Haffuman code
+ //reg [15:0] SubData; // Haffuman Dht Number
+
+ //reg [7:0] OutDhtNumber; // Output Dht Number
+
+ reg [2:0] ProcessColor;
+ reg [6:0] ProcessCount;
+ reg [6:0] NextProcessCount;
+
+ reg OutEnable; // Output Enable
+ reg [3:0] OutZero; // Output Zero Count
+ reg [15:0] OutCode; // Output Data Code
+ wire [15:0] OutCodeP; // Output Data Code
+
+ reg [4:0] UseWidth; // Output used width
+
+ //reg [23:0] OutData;
+
+ reg DataOutEnable;
+ reg [2:0] DataOutColor;
+
+ reg signed [31:0] PreData [0:2];
+
+ wire [15:0] SubCode;
+
+ parameter ProcIdle = 4'h0;
+ parameter Phase1 = 4'h1;
+ parameter Phase2 = 4'h2;
+ parameter Phase3 = 4'h3;
+ parameter Phase4 = 4'h4;
+ parameter Phase5 = 4'h5;
+ parameter Phase6 = 4'h6;
+ parameter Phase7 = 4'h7;
+ parameter Phase8 = 4'h8;
+ parameter Phase9 = 4'h9;
+ parameter Phase10 = 4'hA;
+ parameter Phase11 = 4'hB;
+
+/*
+ always @(*) begin
+ case (DhtWidth)
+ 4'h0: OutCodeP <= 16'h0000;
+ 4'h1: OutCodeP <= {15'h0000,ProcessData[31]};
+ 4'h2: OutCodeP <= {14'h0000,ProcessData[31:30]};
+ 4'h3: OutCodeP <= {13'h0000,ProcessData[31:29]};
+ 4'h4: OutCodeP <= {12'h000, ProcessData[31:28]};
+ 4'h5: OutCodeP <= {11'h000, ProcessData[31:27]};
+ 4'h6: OutCodeP <= {10'h000, ProcessData[31:26]};
+ 4'h7: OutCodeP <= {9'h000, ProcessData[31:25]};
+ 4'h8: OutCodeP <= {8'h00, ProcessData[31:24]};
+ 4'h9: OutCodeP <= {7'h00, ProcessData[31:23]};
+ 4'hA: OutCodeP <= {6'h00, ProcessData[31:22]};
+ 4'hB: OutCodeP <= {5'h00, ProcessData[31:21]};
+ 4'hC: OutCodeP <= {4'h0, ProcessData[31:20]};
+ 4'hD: OutCodeP <= {3'h0, ProcessData[31:19]};
+ 4'hE: OutCodeP <= {2'h0, ProcessData[31:18]};
+ 4'hF: OutCodeP <= {1'h0, ProcessData[31:17]};
+ endcase // case(DhtWidth)
+ case (DhtWidth)
+ 4'h0: SubCode <= 16'hFFFF;
+ 4'h1: SubCode <= 16'hFFFE;
+ 4'h2: SubCode <= 16'hFFFC;
+ 4'h3: SubCode <= 16'hFFF8;
+ 4'h4: SubCode <= 16'hFFF0;
+ 4'h5: SubCode <= 16'hFFE0;
+ 4'h6: SubCode <= 16'hFFC0;
+ 4'h7: SubCode <= 16'hFF80;
+ 4'h8: SubCode <= 16'hFF00;
+ 4'h9: SubCode <= 16'hFE00;
+ 4'hA: SubCode <= 16'hFC00;
+ 4'hB: SubCode <= 16'hF800;
+ 4'hC: SubCode <= 16'hF000;
+ 4'hD: SubCode <= 16'hE000;
+ 4'hE: SubCode <= 16'hC000;
+ 4'hF: SubCode <= 16'h8000;
+ endcase // case(DhtWidth)
+ end // always @ (*)
+*/
+
+ function [15:0] OutCodePSel;
+ input [3:0] DhtWidth;
+ input [31:0] ProcessData;
+ begin
+ case (DhtWidth)
+ 4'h0: OutCodePSel = 16'h0000;
+ 4'h1: OutCodePSel = {15'h0000,ProcessData[31]};
+ 4'h2: OutCodePSel = {14'h0000,ProcessData[31:30]};
+ 4'h3: OutCodePSel = {13'h0000,ProcessData[31:29]};
+ 4'h4: OutCodePSel = {12'h000, ProcessData[31:28]};
+ 4'h5: OutCodePSel = {11'h000, ProcessData[31:27]};
+ 4'h6: OutCodePSel = {10'h000, ProcessData[31:26]};
+ 4'h7: OutCodePSel = {9'h000, ProcessData[31:25]};
+ 4'h8: OutCodePSel = {8'h00, ProcessData[31:24]};
+ 4'h9: OutCodePSel = {7'h00, ProcessData[31:23]};
+ 4'hA: OutCodePSel = {6'h00, ProcessData[31:22]};
+ 4'hB: OutCodePSel = {5'h00, ProcessData[31:21]};
+ 4'hC: OutCodePSel = {4'h0, ProcessData[31:20]};
+ 4'hD: OutCodePSel = {3'h0, ProcessData[31:19]};
+ 4'hE: OutCodePSel = {2'h0, ProcessData[31:18]};
+ 4'hF: OutCodePSel = {1'h0, ProcessData[31:17]};
+ endcase // case(DhtWidth)
+ end
+ endfunction
+ assign OutCodeP = OutCodePSel(DhtWidth, ProcessData);
+
+ function [15:0] SubCodeSel;
+ input [3:0] DhtWidth;
+ begin
+ case (DhtWidth)
+ 4'h0: SubCodeSel = 16'hFFFF;
+ 4'h1: SubCodeSel = 16'hFFFE;
+ 4'h2: SubCodeSel = 16'hFFFC;
+ 4'h3: SubCodeSel = 16'hFFF8;
+ 4'h4: SubCodeSel = 16'hFFF0;
+ 4'h5: SubCodeSel = 16'hFFE0;
+ 4'h6: SubCodeSel = 16'hFFC0;
+ 4'h7: SubCodeSel = 16'hFF80;
+ 4'h8: SubCodeSel = 16'hFF00;
+ 4'h9: SubCodeSel = 16'hFE00;
+ 4'hA: SubCodeSel = 16'hFC00;
+ 4'hB: SubCodeSel = 16'hF800;
+ 4'hC: SubCodeSel = 16'hF000;
+ 4'hD: SubCodeSel = 16'hE000;
+ 4'hE: SubCodeSel = 16'hC000;
+ 4'hF: SubCodeSel = 16'h8000;
+ endcase // case(DhtWidth)
+ end
+ endfunction
+ assign SubCode = SubCodeSel(DhtWidth);
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Process <= ProcIdle;
+ ProcessData <= 32'h00000000;
+ OutEnable <= 1'b0;
+ DataOutEnable <= 1'b0;
+ DataOutColor <= 3'b000;
+ PreData[0] <= 32'h00000000;
+ PreData[1] <= 32'h00000000;
+ PreData[2] <= 32'h00000000;
+ UseWidth <= 7'h00;
+ CodeNumber <= 4'd0;
+ end else begin // if (!rst)
+ case (Process)
+ ProcIdle: begin
+ if(DataInRun == 1'b1) begin
+ Process <= Phase1;
+ end else begin
+ // Reset DC code
+ PreData[0] <= 32'h00000000;
+ PreData[1] <= 32'h00000000;
+ PreData[2] <= 32'h00000000;
+ end
+ OutEnable <= 1'b0;
+ ProcessColor <= 3'b000;
+ ProcessCount <= 0;
+ DataOutEnable <= 1'b0;
+ DataOutColor <= 3'b000;
+ end // case: ProcIdle
+ // get a table-data and table-number
+ Phase1: begin
+ if(DataInEnable ==1'b1 & DataOutIdle == 1'b1) begin
+ Process <= Phase2;
+ ProcessData <= DataIn;
+ end
+ OutEnable <= 1'b0;
+ DataOutEnable <= 1'b0;
+ if(ProcessColor[2] == 1'b0) begin
+ if(ProcessCount == 0) begin
+ HaffumanTable[0] <= HaffumanTable0r[0];
+ HaffumanNumber[0] <= HaffumanNumber0r[0];
+ HaffumanTable[1] <= HaffumanTable0r[1];
+ HaffumanNumber[1] <= HaffumanNumber0r[1];
+ HaffumanTable[2] <= HaffumanTable0r[2];
+ HaffumanNumber[2] <= HaffumanNumber0r[2];
+ HaffumanTable[3] <= HaffumanTable0r[3];
+ HaffumanNumber[3] <= HaffumanNumber0r[3];
+ HaffumanTable[4] <= HaffumanTable0r[4];
+ HaffumanNumber[4] <= HaffumanNumber0r[4];
+ HaffumanTable[5] <= HaffumanTable0r[5];
+ HaffumanNumber[5] <= HaffumanNumber0r[5];
+ HaffumanTable[6] <= HaffumanTable0r[6];
+ HaffumanNumber[6] <= HaffumanNumber0r[6];
+ HaffumanTable[7] <= HaffumanTable0r[7];
+ HaffumanNumber[7] <= HaffumanNumber0r[7];
+ HaffumanTable[8] <= HaffumanTable0r[8];
+ HaffumanNumber[8] <= HaffumanNumber0r[8];
+ HaffumanTable[9] <= HaffumanTable0r[9];
+ HaffumanNumber[9] <= HaffumanNumber0r[9];
+ HaffumanTable[10] <= HaffumanTable0r[10];
+ HaffumanNumber[10] <= HaffumanNumber0r[10];
+ HaffumanTable[11] <= HaffumanTable0r[11];
+ HaffumanNumber[11] <= HaffumanNumber0r[11];
+ HaffumanTable[12] <= HaffumanTable0r[12];
+ HaffumanNumber[12] <= HaffumanNumber0r[12];
+ HaffumanTable[13] <= HaffumanTable0r[13];
+ HaffumanNumber[13] <= HaffumanNumber0r[13];
+ HaffumanTable[14] <= HaffumanTable0r[14];
+ HaffumanNumber[14] <= HaffumanNumber0r[14];
+ HaffumanTable[15] <= HaffumanTable0r[15];
+ HaffumanNumber[15] <= HaffumanNumber0r[15];
+ end else begin
+ HaffumanTable[0] <= HaffumanTable1r[0];
+ HaffumanNumber[0] <= HaffumanNumber1r[0];
+ HaffumanTable[1] <= HaffumanTable1r[1];
+ HaffumanNumber[1] <= HaffumanNumber1r[1];
+ HaffumanTable[2] <= HaffumanTable1r[2];
+ HaffumanNumber[2] <= HaffumanNumber1r[2];
+ HaffumanTable[3] <= HaffumanTable1r[3];
+ HaffumanNumber[3] <= HaffumanNumber1r[3];
+ HaffumanTable[4] <= HaffumanTable1r[4];
+ HaffumanNumber[4] <= HaffumanNumber1r[4];
+ HaffumanTable[5] <= HaffumanTable1r[5];
+ HaffumanNumber[5] <= HaffumanNumber1r[5];
+ HaffumanTable[6] <= HaffumanTable1r[6];
+ HaffumanNumber[6] <= HaffumanNumber1r[6];
+ HaffumanTable[7] <= HaffumanTable1r[7];
+ HaffumanNumber[7] <= HaffumanNumber1r[7];
+ HaffumanTable[8] <= HaffumanTable1r[8];
+ HaffumanNumber[8] <= HaffumanNumber1r[8];
+ HaffumanTable[9] <= HaffumanTable1r[9];
+ HaffumanNumber[9] <= HaffumanNumber1r[9];
+ HaffumanTable[10] <= HaffumanTable1r[10];
+ HaffumanNumber[10] <= HaffumanNumber1r[10];
+ HaffumanTable[11] <= HaffumanTable1r[11];
+ HaffumanNumber[11] <= HaffumanNumber1r[11];
+ HaffumanTable[12] <= HaffumanTable1r[12];
+ HaffumanNumber[12] <= HaffumanNumber1r[12];
+ HaffumanTable[13] <= HaffumanTable1r[13];
+ HaffumanNumber[13] <= HaffumanNumber1r[13];
+ HaffumanTable[14] <= HaffumanTable1r[14];
+ HaffumanNumber[14] <= HaffumanNumber1r[14];
+ HaffumanTable[15] <= HaffumanTable1r[15];
+ HaffumanNumber[15] <= HaffumanNumber1r[15];
+ end // else: !if(ProcessCount == 0)
+ end else begin // if (ProcessColor[2] == 1'b0)
+ if(ProcessCount == 0) begin
+ HaffumanTable[0] <= HaffumanTable2r[0];
+ HaffumanNumber[0] <= HaffumanNumber2r[0];
+ HaffumanTable[1] <= HaffumanTable2r[1];
+ HaffumanNumber[1] <= HaffumanNumber2r[1];
+ HaffumanTable[2] <= HaffumanTable2r[2];
+ HaffumanNumber[2] <= HaffumanNumber2r[2];
+ HaffumanTable[3] <= HaffumanTable2r[3];
+ HaffumanNumber[3] <= HaffumanNumber2r[3];
+ HaffumanTable[4] <= HaffumanTable2r[4];
+ HaffumanNumber[4] <= HaffumanNumber2r[4];
+ HaffumanTable[5] <= HaffumanTable2r[5];
+ HaffumanNumber[5] <= HaffumanNumber2r[5];
+ HaffumanTable[6] <= HaffumanTable2r[6];
+ HaffumanNumber[6] <= HaffumanNumber2r[6];
+ HaffumanTable[7] <= HaffumanTable2r[7];
+ HaffumanNumber[7] <= HaffumanNumber2r[7];
+ HaffumanTable[8] <= HaffumanTable2r[8];
+ HaffumanNumber[8] <= HaffumanNumber2r[8];
+ HaffumanTable[9] <= HaffumanTable2r[9];
+ HaffumanNumber[9] <= HaffumanNumber2r[9];
+ HaffumanTable[10] <= HaffumanTable2r[10];
+ HaffumanNumber[10] <= HaffumanNumber2r[10];
+ HaffumanTable[11] <= HaffumanTable2r[11];
+ HaffumanNumber[11] <= HaffumanNumber2r[11];
+ HaffumanTable[12] <= HaffumanTable2r[12];
+ HaffumanNumber[12] <= HaffumanNumber2r[12];
+ HaffumanTable[13] <= HaffumanTable2r[13];
+ HaffumanNumber[13] <= HaffumanNumber2r[13];
+ HaffumanTable[14] <= HaffumanTable2r[14];
+ HaffumanNumber[14] <= HaffumanNumber2r[14];
+ HaffumanTable[15] <= HaffumanTable2r[15];
+ HaffumanNumber[15] <= HaffumanNumber2r[15];
+ end else begin
+ HaffumanTable[0] <= HaffumanTable3r[0];
+ HaffumanNumber[0] <= HaffumanNumber3r[0];
+ HaffumanTable[1] <= HaffumanTable3r[1];
+ HaffumanNumber[1] <= HaffumanNumber3r[1];
+ HaffumanTable[2] <= HaffumanTable3r[2];
+ HaffumanNumber[2] <= HaffumanNumber3r[2];
+ HaffumanTable[3] <= HaffumanTable3r[3];
+ HaffumanNumber[3] <= HaffumanNumber3r[3];
+ HaffumanTable[4] <= HaffumanTable3r[4];
+ HaffumanNumber[4] <= HaffumanNumber3r[4];
+ HaffumanTable[5] <= HaffumanTable3r[5];
+ HaffumanNumber[5] <= HaffumanNumber3r[5];
+ HaffumanTable[6] <= HaffumanTable3r[6];
+ HaffumanNumber[6] <= HaffumanNumber3r[6];
+ HaffumanTable[7] <= HaffumanTable3r[7];
+ HaffumanNumber[7] <= HaffumanNumber3r[7];
+ HaffumanTable[8] <= HaffumanTable3r[8];
+ HaffumanNumber[8] <= HaffumanNumber3r[8];
+ HaffumanTable[9] <= HaffumanTable3r[9];
+ HaffumanNumber[9] <= HaffumanNumber3r[9];
+ HaffumanTable[10] <= HaffumanTable3r[10];
+ HaffumanNumber[10] <= HaffumanNumber3r[10];
+ HaffumanTable[11] <= HaffumanTable3r[11];
+ HaffumanNumber[11] <= HaffumanNumber3r[11];
+ HaffumanTable[12] <= HaffumanTable3r[12];
+ HaffumanNumber[12] <= HaffumanNumber3r[12];
+ HaffumanTable[13] <= HaffumanTable3r[13];
+ HaffumanNumber[13] <= HaffumanNumber3r[13];
+ HaffumanTable[14] <= HaffumanTable3r[14];
+ HaffumanNumber[14] <= HaffumanNumber3r[14];
+ HaffumanTable[15] <= HaffumanTable3r[15];
+ HaffumanNumber[15] <= HaffumanNumber3r[15];
+ end // else: !if(ProcessCount == 0)
+ end // else: !if(ProcessColor[2] == 1'b0)
+ end // case: Phase1
+ // compare table
+ Phase2: begin
+ Process <= Phase4;
+ if(ProcessData[31:16] >= HaffumanTable[0]) Place[0] <= 1'b1;
+ else Place[0] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[1]) Place[1] <= 1'b1;
+ else Place[1] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[2]) Place[2] <= 1'b1;
+ else Place[2] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[3]) Place[3] <= 1'b1;
+ else Place[3] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[4]) Place[4] <= 1'b1;
+ else Place[4] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[5]) Place[5] <= 1'b1;
+ else Place[5] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[6]) Place[6] <= 1'b1;
+ else Place[6] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[7]) Place[7] <= 1'b1;
+ else Place[7] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[8]) Place[8] <= 1'b1;
+ else Place[8] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[9]) Place[9] <= 1'b1;
+ else Place[9] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[10]) Place[10] <= 1'b1;
+ else Place[10] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[11]) Place[11] <= 1'b1;
+ else Place[11] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[12]) Place[12] <= 1'b1;
+ else Place[12] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[13]) Place[13] <= 1'b1;
+ else Place[13] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[14]) Place[14] <= 1'b1;
+ else Place[14] <= 1'b0;
+ if(ProcessData[31:16] >= HaffumanTable[15]) Place[15] <= 1'b1;
+ else Place[15] <= 1'b0;
+ end
+ // shift code
+ Phase4: begin
+ Process <= Phase6;
+ case (Place)
+ 16'b0000000000000001: begin
+ TableCode <= {15'h0000,HaffumanTable[0][15]};
+ NumberCode <= HaffumanNumber[0];
+ CodeNumber <= 4'h0;
+ DataNumber <= {15'h0000,ProcessData[31]};
+ ProcessData <= {ProcessData[30:0],1'b0};
+ end
+ 16'b0000000000000011: begin
+ TableCode <= {14'h0000,HaffumanTable[1][15:14]};
+ NumberCode <= HaffumanNumber[1];
+ CodeNumber <= 4'h1;
+ DataNumber <= {14'h0000,ProcessData[31:30]};
+ ProcessData <= {ProcessData[29:0],2'b00};
+ end
+ 16'b0000000000000111: begin
+ TableCode <= {13'h0000,HaffumanTable[2][15:13]};
+ NumberCode <= HaffumanNumber[2];
+ CodeNumber <= 4'h2;
+ DataNumber <= {13'h0000,ProcessData[31:29]};
+ ProcessData <= {ProcessData[28:0],3'b000};
+ end
+ 16'b0000000000001111: begin
+ TableCode <= {12'h000,HaffumanTable[3][15:12]};
+ NumberCode <= HaffumanNumber[3];
+ CodeNumber <= 4'h3;
+ DataNumber <= {12'h000,ProcessData[31:28]};
+ ProcessData <= {ProcessData[27:0],4'h0};
+ end
+ 16'b0000000000011111: begin
+ TableCode <= {11'h000,HaffumanTable[4][15:11]};
+ NumberCode <= HaffumanNumber[4];
+ CodeNumber <= 4'h4;
+ DataNumber <= {11'h000,ProcessData[31:27]};
+ ProcessData <= {ProcessData[26:0],5'h00};
+ end
+ 16'b0000000000111111: begin
+ TableCode <= {10'h000,HaffumanTable[5][15:10]};
+ NumberCode <= HaffumanNumber[5];
+ CodeNumber <= 4'h5;
+ DataNumber <= {10'h000,ProcessData[31:26]};
+ ProcessData <= {ProcessData[25:0],6'h00};
+ end
+ 16'b0000000001111111: begin
+ TableCode <= {9'h000,HaffumanTable[6][15:9]};
+ NumberCode <= HaffumanNumber[6];
+ CodeNumber <= 4'h6;
+ DataNumber <= {9'h000,ProcessData[31:25]};
+ ProcessData <= {ProcessData[24:0],7'h00};
+ end
+ 16'b0000000011111111: begin
+ TableCode <= {8'h00,HaffumanTable[7][15:8]};
+ NumberCode <= HaffumanNumber[7];
+ CodeNumber <= 4'h7;
+ DataNumber <= {8'h00,ProcessData[31:24]};
+ ProcessData <= {ProcessData[23:0],8'h00};
+ end
+ 16'b0000000111111111: begin
+ TableCode <= {7'h00,HaffumanTable[8][15:7]};
+ NumberCode <= HaffumanNumber[8];
+ CodeNumber <= 4'h8;
+ DataNumber <= {7'h00,ProcessData[31:23]};
+ ProcessData <= {ProcessData[22:0],9'h000};
+ end
+ 16'b0000001111111111: begin
+ TableCode <= {6'h00,HaffumanTable[9][15:6]};
+ NumberCode <= HaffumanNumber[9];
+ CodeNumber <= 4'h9;
+ DataNumber <= {6'h00,ProcessData[31:22]};
+ ProcessData <= {ProcessData[21:0],10'h000};
+ end
+ 16'b0000011111111111: begin
+ TableCode <= {5'h00,HaffumanTable[10][15:5]};
+ NumberCode <= HaffumanNumber[10];
+ CodeNumber <= 4'hA;
+ DataNumber <= {5'h00,ProcessData[31:21]};
+ ProcessData <= {ProcessData[20:0],11'h000};
+ end
+ 16'b0000111111111111: begin
+ TableCode <= {4'h0,HaffumanTable[11][15:4]};
+ NumberCode <= HaffumanNumber[11];
+ CodeNumber <= 4'hB;
+ DataNumber <= {4'h0,ProcessData[31:20]};
+ ProcessData <= {ProcessData[19:0],12'h000};
+ end
+ 16'b0001111111111111: begin
+ TableCode <= {3'h0,HaffumanTable[12][15:3]};
+ NumberCode <= HaffumanNumber[12];
+ CodeNumber <= 4'hC;
+ DataNumber <= {3'h0,ProcessData[31:19]};
+ ProcessData <= {ProcessData[18:0],13'h0000};
+ end
+ 16'b0011111111111111: begin
+ TableCode <= {2'h0,HaffumanTable[13][15:2]};
+ NumberCode <= HaffumanNumber[13];
+ CodeNumber <= 4'hD;
+ DataNumber <= {2'h0,ProcessData[31:18]};
+ ProcessData <= {ProcessData[17:0],14'h0000};
+ end
+ 16'b0111111111111111: begin
+ TableCode <= {1'h0,HaffumanTable[14][15:1]};
+ NumberCode <= HaffumanNumber[14];
+ CodeNumber <= 4'hE;
+ DataNumber <= {1'h0,ProcessData[31:17]};
+ ProcessData <= {ProcessData[16:0],15'h0000};
+ end
+ 16'b1111111111111111: begin
+ TableCode <= HaffumanTable[15];
+ NumberCode <= HaffumanNumber[15];
+ CodeNumber <= 4'hF;
+ DataNumber <= ProcessData[31:16] ;
+ ProcessData <= {ProcessData[15:0],16'h0000};
+ end
+ endcase // case(Place)
+ end // case: Phase4
+ Phase5: begin
+ Process <= Phase6;
+ //SubData <= DataNumber - TableCode;
+ //OutDhtNumber <= DataNumber - TableCode + NumberCode;
+ end
+ Phase6: begin
+ if(DataOutIdle == 1'b1) Process <= Phase7;
+ //DhtNumber <= SubData[7:0] + NumberCode;
+ end
+ Phase7: begin
+ Process <= Phase9;
+ OutZero <= DhtZero;
+ UseWidth <= CodeNumber + DhtWidth +1;
+ if(ProcessCount == 0) begin
+ NextProcessCount <= 7'd1;
+ OutEnable <= 1'b1;
+ end else begin
+ if(DhtZero == 4'h0 & DhtWidth == 4'h0) begin
+ ProcessCount <= 7'd64;
+ NextProcessCount <= 7'd64;
+ OutEnable <= 1'b0;
+ end else if(DhtZero == 4'hF & DhtWidth == 4'h0) begin
+ ProcessCount <= ProcessCount + 4'hF;
+ NextProcessCount <= ProcessCount + 4'hF;
+ OutEnable <= 1'b0;
+ end else begin
+ ProcessCount <= ProcessCount + DhtZero;
+ NextProcessCount <= ProcessCount + DhtZero +1;
+ OutEnable <= 1'b1;
+ end
+ end // else: !if(ProcessCount == 0)
+
+ if(ProcessData[31] == 1'b0 & DhtWidth != 0) begin
+ OutCode <= (OutCodeP | SubCode) + 16'h0001;
+ end else begin
+ OutCode <= OutCodeP;
+ end
+ end // case: Phase7
+ Phase8: begin
+ Process <= Phase9;
+ end
+ Phase9: begin
+ Process <= Phase11;
+ if(ProcessCount == 0) begin
+ if(ProcessColor[2] == 1'b0) begin
+ OutCode <= OutCode + PreData[0];
+ PreData[0] <= OutCode + PreData[0];
+ end else begin
+ if(ProcessColor[0] == 1'b0) begin
+ OutCode <= OutCode + PreData[1];
+ PreData[1] <= OutCode + PreData[1];
+ end else begin
+ OutCode <= OutCode + PreData[2];
+ PreData[2] <= OutCode + PreData[2];
+ end
+ end // else: !if(ProcessColor[2] == 1'b0)
+ end // if (ProcessCount == 0)
+ end // case: Phase9
+ Phase10: begin
+ Process <= Phase11;
+ //OutData <= DqtData * OutCode;
+ end
+ Phase11: begin
+ OutEnable <= 1'b0;
+ if(NextProcessCount <64) begin
+ Process <= Phase1;
+ ProcessCount <= NextProcessCount;
+ end else begin
+ ProcessCount <= 7'd0;
+ DataOutEnable <= 1'b1;
+ DataOutColor <= ProcessColor;
+ if(ProcessColor == 5) begin
+ ProcessColor <= 3'b000;
+ if(DataInRun == 1'b0) Process <= ProcIdle;
+ else Process <= Phase1;
+ end else begin
+ Process <= Phase1;
+ ProcessColor <= ProcessColor +1;
+ end
+ end // else: !if(NextProcessCount <64)
+ end // case: Phase11
+ endcase // case(Process)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign DhtColor[1] = ProcessColor[2];
+ assign DhtColor[0] = ProcessCount != 0;
+ //assign DhtNumber = OutDhtNumber[7:0];
+ assign DhtNumber = DataNumber - TableCode + NumberCode;
+
+ assign DqtColor = ProcessColor[2];
+ assign DqtNumber = ProcessCount[5:0];
+
+ //assign DecodeUseBit = Process == Phase8;
+ assign DecodeUseBit = Process == Phase9;
+ assign DecodeUseWidth = UseWidth;
+
+ assign DecodeEnable = OutEnable == 1'b1 & Process == Phase11;
+ assign DecodeColor = ProcessColor;
+ assign DecodeCount = ProcessCount[5:0];
+ assign DecodeZero = OutZero;
+ //assign DecodeCode = OutData[15:0];
+ assign DecodeCode = DqtData * OutCode;
+
+endmodule // jpeg_hm_decode
Index: djpeg/trunk/src/jpeg_regdata.v
===================================================================
--- djpeg/trunk/src/jpeg_regdata.v (nonexistent)
+++ djpeg/trunk/src/jpeg_regdata.v (revision 6)
@@ -0,0 +1,209 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_regdata.v
+// Module Name : jpeg_regdata
+// Description : get Data
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2007/04/11
+// Rev. : 1.03
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+// 1.02 2006/10/04 Remove a RegEnd register.
+// When reset, clear on OutEnable,PreEnable,DataOut registers.
+// Remove some comments.
+// 1.03 2007/04/11 Don't OutEnable, ImageEnable == 1 and DataOut == 0xFFD9XXXX
+// Stop ReadEnable with DataEnd(after 0xFFD9 of ImageData)
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_regdata(
+ rst,
+ clk,
+
+ // Read Data
+ DataIn, //
+ DataInEnable, // Data Enable
+ DataInRead, // Data Read
+
+ // DataOut
+ DataOut, // Data Out
+ DataOutEnable, // Data Out Enable
+
+ //
+ ImageEnable,
+ ProcessIdle,
+
+ // UseData
+ UseBit, // Used data bit
+ UseWidth, // Used data bit width
+ UseByte, // Used data byte
+ UseWord // Used data word
+ );
+
+ input rst;
+ input clk;
+
+ input [31:0] DataIn;
+ input DataInEnable;
+ output DataInRead;
+
+ output [31:0] DataOut;
+ output DataOutEnable;
+
+ input ImageEnable;
+ input ProcessIdle;
+
+ input UseBit;
+ input [6:0] UseWidth;
+ input UseByte;
+ input UseWord;
+
+ wire RegValid;
+ reg [95:0] RegData;
+ reg [7:0] RegWidth;
+
+ reg DataEnd;
+
+ assign RegValid = RegWidth > 64;
+ assign DataInRead = RegValid == 1'b0 & DataInEnable == 1'b1;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ RegData <= 96'd0;
+ RegWidth <= 8'h00;
+ end else begin
+ if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin
+ if(ImageEnable == 1'b1) begin
+ if(RegData[39: 8] == 32'hFF00FF00) begin
+ RegWidth <= RegWidth + 16;
+ RegData[95:64] <= {8'h00,RegData[71:48]};
+ RegData[63:32] <= {RegData[47:40],16'hFFFF,RegData[7:0]};
+ end else if(RegData[39:24] == 16'hFF00 &
+ RegData[15: 0] == 16'hFF00) begin
+ RegWidth <= RegWidth + 16;
+ RegData[95:64] <= {8'h00,RegData[71:48]};
+ RegData[63:32] <= {RegData[47:40],8'hFF,RegData[23:16],8'hFF};
+ end else if(RegData[31: 0] == 32'hFF00FF00) begin
+ RegWidth <= RegWidth + 16;
+ RegData[95:64] <= {16'h0000,RegData[71:56]};
+ RegData[63:32] <= {RegData[55:40],16'hFFFF};
+ end else if(RegData[39:24] == 16'hFF00) begin
+ RegWidth <= RegWidth + 24;
+ RegData[95:64] <= {RegData[71:40]};
+ RegData[63:32] <= {8'hFF,RegData[23:0]};
+ end else if(RegData[31:16] == 16'hFF00) begin
+ RegWidth <= RegWidth + 24;
+ RegData[95:64] <= {RegData[71:40]};
+ RegData[63:32] <= {RegData[39:32],8'hFF,RegData[15:0]};
+ end else if(RegData[23: 8] == 16'hFF00) begin
+ RegWidth <= RegWidth + 24;
+ RegData[95:64] <= {RegData[71:40]};
+ RegData[63:32] <= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]};
+ end else if(RegData[15: 0] == 16'hFF00) begin
+ RegWidth <= RegWidth + 24;
+ RegData[95:64] <= {RegData[71:40]};
+ RegData[63:32] <= {RegData[39:32],RegData[31:16],8'hFF};
+ end else begin
+ RegWidth <= RegWidth + 32;
+ RegData[95:64] <= RegData[63:32];
+ RegData[63:32] <= RegData[31:0];
+ end
+ end else begin
+ RegWidth <= RegWidth + 32;
+ RegData[95:64] <= RegData[63:32];
+ RegData[63:32] <= RegData[31:0];
+ end
+ RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]};
+ end else if(UseBit == 1'b1) begin
+ RegWidth <= RegWidth - UseWidth;
+ end else if(UseByte == 1'b1) begin
+ RegWidth <= RegWidth - 8;
+ end else if(UseWord == 1'b1) begin
+ RegWidth <= RegWidth - 16;
+ end
+ end
+ end
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ DataEnd <= 1'b0;
+ end else begin
+ if(ProcessIdle) begin
+ DataEnd <= 1'b0;
+ end else if(ImageEnable == 1'b1 & (RegData[39:24] == 16'hFFD9 | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin
+ DataEnd <= 1'b1;
+ end
+ end
+ end
+
+ function [31:0] SliceData;
+ input [95:0] RegData;
+ input [7:0] RegWidth;
+
+ case(RegWidth)
+ 8'd65: SliceData = RegData[64:33];
+ 8'd66: SliceData = RegData[65:34];
+ 8'd67: SliceData = RegData[66:35];
+ 8'd68: SliceData = RegData[67:36];
+ 8'd69: SliceData = RegData[68:37];
+ 8'd70: SliceData = RegData[69:38];
+ 8'd71: SliceData = RegData[70:39];
+ 8'd72: SliceData = RegData[71:40];
+ 8'd73: SliceData = RegData[72:41];
+ 8'd74: SliceData = RegData[73:42];
+ 8'd75: SliceData = RegData[74:43];
+ 8'd76: SliceData = RegData[75:44];
+ 8'd77: SliceData = RegData[76:45];
+ 8'd78: SliceData = RegData[77:46];
+ 8'd79: SliceData = RegData[78:47];
+ 8'd80: SliceData = RegData[79:48];
+ 8'd81: SliceData = RegData[80:49];
+ 8'd82: SliceData = RegData[81:50];
+ 8'd83: SliceData = RegData[82:51];
+ 8'd84: SliceData = RegData[83:52];
+ 8'd85: SliceData = RegData[84:53];
+ 8'd86: SliceData = RegData[85:54];
+ 8'd87: SliceData = RegData[86:55];
+ 8'd88: SliceData = RegData[87:56];
+ 8'd89: SliceData = RegData[88:57];
+ 8'd90: SliceData = RegData[89:58];
+ 8'd91: SliceData = RegData[90:59];
+ 8'd92: SliceData = RegData[91:60];
+ 8'd93: SliceData = RegData[92:61];
+ 8'd94: SliceData = RegData[93:62];
+ 8'd95: SliceData = RegData[94:63];
+ 8'd96: SliceData = RegData[95:64];
+ default: SliceData = 32'h00000000;
+ endcase
+ endfunction
+
+ reg OutEnable;
+ reg PreEnable;
+
+ reg [31:0] DataOut;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ OutEnable <= 1'b0;
+ PreEnable <= 1'b0;
+ DataOut <= 32'h00000000;
+ end else begin
+ OutEnable <= RegWidth >64;
+ PreEnable <= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1);
+ DataOut <= SliceData(RegData,RegWidth);
+ end
+ end
+
+ assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0;
+
+endmodule
+
+
+
\ No newline at end of file
Index: djpeg/trunk/src/jpeg_idctx.v
===================================================================
--- djpeg/trunk/src/jpeg_idctx.v (nonexistent)
+++ djpeg/trunk/src/jpeg_idctx.v (revision 6)
@@ -0,0 +1,1241 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_idctx.v
+// Module Name : jpeg_idctx
+// Description : iDCT-X
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/09/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_idctx
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInSel,
+ Data00In,
+ Data01In,
+ Data02In,
+ Data03In,
+ Data04In,
+ Data05In,
+ Data06In,
+ Data07In,
+ Data08In,
+ Data09In,
+ Data10In,
+ Data11In,
+ Data12In,
+ Data13In,
+ Data14In,
+ Data15In,
+ Data16In,
+ Data17In,
+ Data18In,
+ Data19In,
+ Data20In,
+ Data21In,
+ Data22In,
+ Data23In,
+ Data24In,
+ Data25In,
+ Data26In,
+ Data27In,
+ Data28In,
+ Data29In,
+ Data30In,
+ Data31In,
+ Data32In,
+ Data33In,
+ Data34In,
+ Data35In,
+ Data36In,
+ Data37In,
+ Data38In,
+ Data39In,
+ Data40In,
+ Data41In,
+ Data42In,
+ Data43In,
+ Data44In,
+ Data45In,
+ Data46In,
+ Data47In,
+ Data48In,
+ Data49In,
+ Data50In,
+ Data51In,
+ Data52In,
+ Data53In,
+ Data54In,
+ Data55In,
+ Data56In,
+ Data57In,
+ Data58In,
+ Data59In,
+ Data60In,
+ Data61In,
+ Data62In,
+ Data63In,
+ DataInIdle,
+ DataInRelease,
+
+ DataOutIdle,
+ DataOutEnable,
+ DataOutPage,
+ DataOutCount,
+ Data0Out,
+ Data1Out
+ );
+
+ input clk;
+ input rst;
+
+ input DataInEnable;
+ output DataInSel;
+ input [15:0] Data00In;
+ input [15:0] Data01In;
+ input [15:0] Data02In;
+ input [15:0] Data03In;
+ input [15:0] Data04In;
+ input [15:0] Data05In;
+ input [15:0] Data06In;
+ input [15:0] Data07In;
+ input [15:0] Data08In;
+ input [15:0] Data09In;
+ input [15:0] Data10In;
+ input [15:0] Data11In;
+ input [15:0] Data12In;
+ input [15:0] Data13In;
+ input [15:0] Data14In;
+ input [15:0] Data15In;
+ input [15:0] Data16In;
+ input [15:0] Data17In;
+ input [15:0] Data18In;
+ input [15:0] Data19In;
+ input [15:0] Data20In;
+ input [15:0] Data21In;
+ input [15:0] Data22In;
+ input [15:0] Data23In;
+ input [15:0] Data24In;
+ input [15:0] Data25In;
+ input [15:0] Data26In;
+ input [15:0] Data27In;
+ input [15:0] Data28In;
+ input [15:0] Data29In;
+ input [15:0] Data30In;
+ input [15:0] Data31In;
+ input [15:0] Data32In;
+ input [15:0] Data33In;
+ input [15:0] Data34In;
+ input [15:0] Data35In;
+ input [15:0] Data36In;
+ input [15:0] Data37In;
+ input [15:0] Data38In;
+ input [15:0] Data39In;
+ input [15:0] Data40In;
+ input [15:0] Data41In;
+ input [15:0] Data42In;
+ input [15:0] Data43In;
+ input [15:0] Data44In;
+ input [15:0] Data45In;
+ input [15:0] Data46In;
+ input [15:0] Data47In;
+ input [15:0] Data48In;
+ input [15:0] Data49In;
+ input [15:0] Data50In;
+ input [15:0] Data51In;
+ input [15:0] Data52In;
+ input [15:0] Data53In;
+ input [15:0] Data54In;
+ input [15:0] Data55In;
+ input [15:0] Data56In;
+ input [15:0] Data57In;
+ input [15:0] Data58In;
+ input [15:0] Data59In;
+ input [15:0] Data60In;
+ input [15:0] Data61In;
+ input [15:0] Data62In;
+ input [15:0] Data63In;
+ output DataInIdle;
+ output DataInRelease;
+
+ input DataOutIdle;
+ output DataOutEnable;
+ output [2:0] DataOutPage;
+ output [1:0] DataOutCount;
+ output [15:0] Data0Out;
+ output [15:0] Data1Out;
+
+ //-------------------------------------------------------------------------
+ // Phase1
+ //-------------------------------------------------------------------------
+ reg Phase1Enable;
+ reg [2:0] Phase1Page;
+ reg [2:0] Phase1Count;
+ //reg Phase1EnableD;
+ //reg [2:0] Phase1PageD;
+ //reg [2:0] Phase1CountD;
+ reg DataInBank;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase1Enable <= 1'b0;
+ Phase1Page <= 3'd0;
+ Phase1Count <= 3'd0;
+ //Phase1EnableD <= 1'b0;
+ //Phase1PageD <= 3'd0;
+ //Phase1CountD <= 3'd0;
+ DataInBank <= 1'b0;
+ end else begin
+ if(Phase1Enable == 1'b0) begin
+ if(DataInEnable == 1'b1) begin
+ Phase1Enable <= 1'b1;
+ Phase1Page <= 3'd0;
+ Phase1Count <= 3'd0;
+ end
+ end else begin
+ if(Phase1Count == 3'd6) begin
+ if(Phase1Page == 3'd7) begin
+ Phase1Enable <= 1'b0;
+ Phase1Page <= 3'd0;
+ DataInBank <= ~DataInBank;
+ end else begin
+ Phase1Page <= Phase1Page + 3'd1;
+ end
+ Phase1Count <= 3'd0;
+ end else begin
+ Phase1Count <= Phase1Count + 3'd1;
+ end // else: !if(Phase1Count == 3'd6)
+ end // else: !if(Phase1Enable == 1'b0)
+ //Phase1EnableD <= Phase1Enable;
+ //Phase1PageD <= Phase1Page;
+ //Phase1CountD <= Phase1Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign DataInSel = DataInBank;
+ assign DataInIdle = Phase1Enable == 1'b0 & DataOutIdle == 1'b1;
+ assign DataInRelease = Phase1Enable == 1'b1 & Phase1Count == 3'd6 & Phase1Page == 3'd7;
+
+ wire signed [15:0] Phase1R0w;
+ wire signed [15:0] Phase1R1w;
+ wire signed [15:0] Phase1C0w;
+ wire signed [15:0] Phase1C1w;
+ wire signed [15:0] Phase1C2w;
+ wire signed [15:0] Phase1C3w;
+
+/*
+ always @(*) begin
+ case(Phase1Page)
+ 3'd0:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data00In;
+ Phase1R1w <= Data04In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data02In;
+ Phase1R1w <= Data06In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data01In;
+ Phase1R1w <= Data07In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data05In;
+ Phase1R1w <= Data03In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd0
+ 3'd1:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data08In;
+ Phase1R1w <= Data12In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data10In;
+ Phase1R1w <= Data14In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data09In;
+ Phase1R1w <= Data15In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data13In;
+ Phase1R1w <= Data11In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd1
+ 3'd2:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data16In;
+ Phase1R1w <= Data20In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data18In;
+ Phase1R1w <= Data22In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data17In;
+ Phase1R1w <= Data23In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data21In;
+ Phase1R1w <= Data19In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd2
+ 3'd3:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data24In;
+ Phase1R1w <= Data28In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data26In;
+ Phase1R1w <= Data30In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data25In;
+ Phase1R1w <= Data31In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data29In;
+ Phase1R1w <= Data27In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd3
+ 3'd4:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data32In;
+ Phase1R1w <= Data36In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data34In;
+ Phase1R1w <= Data38In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data33In;
+ Phase1R1w <= Data39In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data37In;
+ Phase1R1w <= Data35In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd4
+ 3'd5:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data40In;
+ Phase1R1w <= Data44In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data42In;
+ Phase1R1w <= Data46In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data41In;
+ Phase1R1w <= Data47In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data45In;
+ Phase1R1w <= Data43In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd5
+ 3'd6:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data48In;
+ Phase1R1w <= Data52In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data50In;
+ Phase1R1w <= Data54In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data49In;
+ Phase1R1w <= Data55In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data53In;
+ Phase1R1w <= Data51In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd6
+ 3'd7:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data56In;
+ Phase1R1w <= Data60In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data58In;
+ Phase1R1w <= Data62In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data57In;
+ Phase1R1w <= Data63In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data61In;
+ Phase1R1w <= Data59In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd7
+ endcase // case(Phase1Page)
+ end // always @ (*)
+*/
+ function [15:0] Phase1R0wSel;
+ input [2:0] Phase1Page;
+ input [2:0] Phase1Count;
+ input [15:0] Data00In;
+ input [15:0] Data01In;
+ input [15:0] Data02In;
+ input [15:0] Data03In;
+ input [15:0] Data04In;
+ input [15:0] Data05In;
+ input [15:0] Data06In;
+ input [15:0] Data07In;
+ input [15:0] Data08In;
+ input [15:0] Data09In;
+ input [15:0] Data10In;
+ input [15:0] Data11In;
+ input [15:0] Data12In;
+ input [15:0] Data13In;
+ input [15:0] Data14In;
+ input [15:0] Data15In;
+ input [15:0] Data16In;
+ input [15:0] Data17In;
+ input [15:0] Data18In;
+ input [15:0] Data19In;
+ input [15:0] Data20In;
+ input [15:0] Data21In;
+ input [15:0] Data22In;
+ input [15:0] Data23In;
+ input [15:0] Data24In;
+ input [15:0] Data25In;
+ input [15:0] Data26In;
+ input [15:0] Data27In;
+ input [15:0] Data28In;
+ input [15:0] Data29In;
+ input [15:0] Data30In;
+ input [15:0] Data31In;
+ input [15:0] Data32In;
+ input [15:0] Data33In;
+ input [15:0] Data34In;
+ input [15:0] Data35In;
+ input [15:0] Data36In;
+ input [15:0] Data37In;
+ input [15:0] Data38In;
+ input [15:0] Data39In;
+ input [15:0] Data40In;
+ input [15:0] Data41In;
+ input [15:0] Data42In;
+ input [15:0] Data43In;
+ input [15:0] Data44In;
+ input [15:0] Data45In;
+ input [15:0] Data46In;
+ input [15:0] Data47In;
+ input [15:0] Data48In;
+ input [15:0] Data49In;
+ input [15:0] Data50In;
+ input [15:0] Data51In;
+ input [15:0] Data52In;
+ input [15:0] Data53In;
+ input [15:0] Data54In;
+ input [15:0] Data55In;
+ input [15:0] Data56In;
+ input [15:0] Data57In;
+ input [15:0] Data58In;
+ input [15:0] Data59In;
+ input [15:0] Data60In;
+ input [15:0] Data61In;
+ input [15:0] Data62In;
+ input [15:0] Data63In;
+ begin
+ case(Phase1Page)
+ 3'd0:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data00In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data02In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data01In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data05In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd0
+ 3'd1:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data08In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data10In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data09In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data13In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd1
+ 3'd2:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data16In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data18In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data17In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data21In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd2
+ 3'd3:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data24In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data26In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data25In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data29In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd3
+ 3'd4:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data32In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data34In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data33In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data37In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd4
+ 3'd5:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data40In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data42In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data41In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data45In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd5
+ 3'd6:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data48In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data50In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data49In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data53In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd6
+ 3'd7:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data56In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data58In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data57In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data61In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd7
+ endcase // case(Phase1Page)
+ end
+ endfunction
+ function [15:0] Phase1R1wSel;
+ input [2:0] Phase1Page;
+ input [2:0] Phase1Count;
+ input [15:0] Data00In;
+ input [15:0] Data01In;
+ input [15:0] Data02In;
+ input [15:0] Data03In;
+ input [15:0] Data04In;
+ input [15:0] Data05In;
+ input [15:0] Data06In;
+ input [15:0] Data07In;
+ input [15:0] Data08In;
+ input [15:0] Data09In;
+ input [15:0] Data10In;
+ input [15:0] Data11In;
+ input [15:0] Data12In;
+ input [15:0] Data13In;
+ input [15:0] Data14In;
+ input [15:0] Data15In;
+ input [15:0] Data16In;
+ input [15:0] Data17In;
+ input [15:0] Data18In;
+ input [15:0] Data19In;
+ input [15:0] Data20In;
+ input [15:0] Data21In;
+ input [15:0] Data22In;
+ input [15:0] Data23In;
+ input [15:0] Data24In;
+ input [15:0] Data25In;
+ input [15:0] Data26In;
+ input [15:0] Data27In;
+ input [15:0] Data28In;
+ input [15:0] Data29In;
+ input [15:0] Data30In;
+ input [15:0] Data31In;
+ input [15:0] Data32In;
+ input [15:0] Data33In;
+ input [15:0] Data34In;
+ input [15:0] Data35In;
+ input [15:0] Data36In;
+ input [15:0] Data37In;
+ input [15:0] Data38In;
+ input [15:0] Data39In;
+ input [15:0] Data40In;
+ input [15:0] Data41In;
+ input [15:0] Data42In;
+ input [15:0] Data43In;
+ input [15:0] Data44In;
+ input [15:0] Data45In;
+ input [15:0] Data46In;
+ input [15:0] Data47In;
+ input [15:0] Data48In;
+ input [15:0] Data49In;
+ input [15:0] Data50In;
+ input [15:0] Data51In;
+ input [15:0] Data52In;
+ input [15:0] Data53In;
+ input [15:0] Data54In;
+ input [15:0] Data55In;
+ input [15:0] Data56In;
+ input [15:0] Data57In;
+ input [15:0] Data58In;
+ input [15:0] Data59In;
+ input [15:0] Data60In;
+ input [15:0] Data61In;
+ input [15:0] Data62In;
+ input [15:0] Data63In;
+ begin
+ case(Phase1Page)
+ 3'd0:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data04In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data06In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data07In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data03In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd0
+ 3'd1:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data12In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data14In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data15In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data11In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd1
+ 3'd2:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data20In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data22In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data23In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data19In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd2
+ 3'd3:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data28In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data30In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data31In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data27In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd3
+ 3'd4:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data36In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data38In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data39In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data35In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd4
+ 3'd5:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data44In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data46In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data47In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data43In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd5
+ 3'd6:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data52In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data54In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data55In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data51In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd6
+ 3'd7:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data60In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data62In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data63In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data59In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd7
+ endcase // case(Phase1Page)
+ end
+ endfunction
+
+ assign Phase1R0w = Phase1R0wSel(Phase1Page, Phase1Count,
+ Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In,
+ Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In,
+ Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In,
+ Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In,
+ Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In,
+ Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In,
+ Data60In, Data61In, Data62In, Data63In
+ );
+ assign Phase1R1w = Phase1R1wSel(Phase1Page, Phase1Count,
+ Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In,
+ Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In,
+ Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In,
+ Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In,
+ Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In,
+ Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In,
+ Data60In, Data61In, Data62In, Data63In
+ );
+/*
+ always @(*) begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C0w <= 16'd2896; // C4_16
+ Phase1C1w <= 16'd2896; // C4_16
+ Phase1C2w <= 16'd2896; // C4_16
+ Phase1C3w <= 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C0w <= 16'd3784; // C2_16
+ Phase1C1w <= 16'd1567; // C6_16
+ Phase1C2w <= 16'd1567; // C6_16
+ Phase1C3w <= 16'd3784; // C2_16
+ end
+ 3'd2: begin
+ Phase1C0w <= 16'd4017; // C1_16
+ Phase1C1w <= 16'd799; // C7_16
+ Phase1C2w <= 16'd799; // C7_16
+ Phase1C3w <= 16'd4017; // C1_16
+ end
+ 3'd3: begin
+ Phase1C0w <= 16'd2276; // C5_16
+ Phase1C1w <= 16'd3406; // C3_16
+ Phase1C2w <= 16'd3406; // C3_16
+ Phase1C3w <= 16'd2276; // C5_16
+ end
+ endcase // case(Phase1Count)
+ end // always @ (*)
+*/
+ function [15:0] Phase1C0wSel;
+ input [2:0] Phase1Count;
+ begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C0wSel = 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C0wSel = 16'd3784; // C2_16
+ end
+ 3'd2: begin
+ Phase1C0wSel = 16'd4017; // C1_16
+ end
+ 3'd3: begin
+ Phase1C0wSel = 16'd2276; // C5_16
+ end
+ endcase // case(Phase1Count)
+ end
+ endfunction
+
+ function [15:0] Phase1C1wSel;
+ input [2:0] Phase1Count;
+ begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C1wSel = 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C1wSel = 16'd1567; // C6_16
+ end
+ 3'd2: begin
+ Phase1C1wSel = 16'd799; // C7_16
+ end
+ 3'd3: begin
+ Phase1C1wSel = 16'd3406; // C3_16
+ end
+ endcase // case(Phase1Count)
+ end
+ endfunction
+
+ function [15:0] Phase1C2wSel;
+ input [2:0] Phase1Count;
+ begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C2wSel = 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C2wSel = 16'd1567; // C6_16
+ end
+ 3'd2: begin
+ Phase1C2wSel = 16'd799; // C7_16
+ end
+ 3'd3: begin
+ Phase1C2wSel = 16'd3406; // C3_16
+ end
+ endcase // case(Phase1Count)
+ end
+ endfunction
+
+ function [15:0] Phase1C3wSel;
+ input [2:0] Phase1Count;
+ begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C3wSel = 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C3wSel = 16'd3784; // C2_16
+ end
+ 3'd2: begin
+ Phase1C3wSel = 16'd4017; // C1_16
+ end
+ 3'd3: begin
+ Phase1C3wSel = 16'd2276; // C5_16
+ end
+ endcase // case(Phase1Count)
+ end
+ endfunction
+
+ assign Phase1C0w = Phase1C0wSel(Phase1Count);
+ assign Phase1C1w = Phase1C1wSel(Phase1Count);
+ assign Phase1C2w = Phase1C2wSel(Phase1Count);
+ assign Phase1C3w = Phase1C3wSel(Phase1Count);
+
+ reg signed [31:0] Phase1R0r;
+ reg signed [31:0] Phase1R1r;
+ reg signed [31:0] Phase1R2r;
+ reg signed [31:0] Phase1R3r;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase1R0r <= 0;
+ Phase1R1r <= 0;
+ Phase1R2r <= 0;
+ Phase1R3r <= 0;
+ end else begin
+ Phase1R0r <= Phase1R0w * Phase1C0w;
+ Phase1R1r <= Phase1R1w * Phase1C1w;
+ Phase1R2r <= Phase1R0w * Phase1C2w;
+ Phase1R3r <= Phase1R1w * Phase1C3w;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //-------------------------------------------------------------------------
+ // Phase2
+ // R0: s0,s3,s7,s6
+ // R1: s1,s2,s4,s5
+ //-------------------------------------------------------------------------
+ reg Phase2Enable;
+ reg signed [2:0] Phase2Page;
+ reg signed [2:0] Phase2Count;
+ reg Phase2EnableD;
+ reg signed [2:0] Phase2PageD;
+ reg signed [2:0] Phase2CountD;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase2Enable <= 1'b0;
+ Phase2Page <= 3'd0;
+ Phase2Count <= 3'd0;
+ Phase2EnableD <= 1'b0;
+ Phase2PageD <= 3'd0;
+ Phase2CountD <= 3'd0;
+ end else begin
+ Phase2Enable <= Phase1Enable;
+ Phase2Page <= Phase1Page;
+ Phase2Count <= Phase1Count;
+ Phase2EnableD <= Phase2Enable;
+ Phase2PageD <= Phase2Page;
+ Phase2CountD <= Phase2Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ wire signed [31:0] Phase2A0w;
+ wire signed [31:0] Phase2A1w;
+/*
+ always @(*) begin
+ Phase2A0w <= Phase1R0r + Phase1R1r;
+ Phase2A1w <= Phase1R2r - Phase1R3r;
+ end
+*/
+ assign Phase2A0w = Phase1R0r + Phase1R1r;
+ assign Phase2A1w = Phase1R2r - Phase1R3r;
+
+ reg signed [31:0] Phase2Reg [0:7];
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase2Reg[0] <= 0;
+ Phase2Reg[1] <= 0;
+ Phase2Reg[2] <= 0;
+ Phase2Reg[3] <= 0;
+ Phase2Reg[4] <= 0;
+ Phase2Reg[5] <= 0;
+ Phase2Reg[6] <= 0;
+ Phase2Reg[7] <= 0;
+ end else begin
+ case(Phase2Count)
+ 3'd0: begin
+ Phase2Reg[0] <= Phase2A0w;
+ Phase2Reg[1] <= Phase2A1w;
+ end
+ 3'd1: begin
+ Phase2Reg[3] <= Phase2A0w;
+ Phase2Reg[2] <= Phase2A1w;
+ end
+ 3'd2: begin
+ Phase2Reg[7] <= Phase2A0w;
+ Phase2Reg[4] <= Phase2A1w;
+ end
+ 3'd3: begin
+ Phase2Reg[6] <= Phase2A0w;
+ Phase2Reg[5] <= Phase2A1w;
+ end
+ endcase // case(Phase2Count)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //-------------------------------------------------------------------------
+ // Phase3
+ // R0: t0,t1,t4,t7
+ // R1: t3,t2,t5,t6
+ //-------------------------------------------------------------------------
+ reg Phase3Enable;
+ reg [2:0] Phase3Page;
+ reg [2:0] Phase3Count;
+ reg Phase3EnableD;
+ reg [2:0] Phase3PageD;
+ reg [2:0] Phase3CountD;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase3Enable <= 1'b0;
+ Phase3Page <= 3'd0;
+ Phase3Count <= 3'd0;
+ Phase3EnableD <= 1'b0;
+ Phase3PageD <= 3'd0;
+ Phase3CountD <= 3'd0;
+ end else begin
+ Phase3Enable <= Phase2EnableD;
+ Phase3Page <= Phase2PageD;
+ Phase3Count <= Phase2CountD;
+ Phase3EnableD <= Phase3Enable;
+ Phase3PageD <= Phase3Page;
+ Phase3CountD <= Phase3Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //reg signed [31:0] Phase3R0w;
+ //reg signed [31:0] Phase3R1w;
+ wire signed [31:0] Phase3R0w;
+ wire signed [31:0] Phase3R1w;
+
+ assign Phase3R0w = (Phase3Count == 3'd0)?Phase2Reg[0]:
+ (Phase3Count == 3'd1)?Phase2Reg[1]:
+ (Phase3Count == 3'd2)?Phase2Reg[4]:
+ (Phase3Count == 3'd3)?Phase2Reg[7]:
+ 32'd0;
+ assign Phase3R1w = (Phase3Count == 3'd0)?Phase2Reg[3]:
+ (Phase3Count == 3'd1)?Phase2Reg[2]:
+ (Phase3Count == 3'd2)?Phase2Reg[5]:
+ (Phase3Count == 3'd3)?Phase2Reg[6]:
+ 32'd0;
+
+
+
+ wire signed [31:0] Phase3A0w;
+ wire signed [31:0] Phase3A1w;
+/*
+ always @(*) begin
+ Phase3A0w <= Phase3R0w + Phase3R1w;
+ Phase3A1w <= Phase3R0w - Phase3R1w;
+ end
+*/
+ assign Phase3A0w = Phase3R0w + Phase3R1w;
+ assign Phase3A1w = Phase3R0w - Phase3R1w;
+
+ reg signed [31:0] Phase3Reg [0:7];
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase3Reg[0] <= 0;
+ Phase3Reg[1] <= 0;
+ Phase3Reg[2] <= 0;
+ Phase3Reg[3] <= 0;
+ Phase3Reg[4] <= 0;
+ Phase3Reg[5] <= 0;
+ Phase3Reg[6] <= 0;
+ Phase3Reg[7] <= 0;
+ end else begin
+ case(Phase3Count)
+ 3'd0: begin
+ Phase3Reg[0] <= Phase3A0w;
+ Phase3Reg[3] <= Phase3A1w;
+ end
+ 3'd1: begin
+ Phase3Reg[1] <= Phase3A0w;
+ Phase3Reg[2] <= Phase3A1w;
+ end
+ 3'd2: begin
+ Phase3Reg[4] <= Phase3A0w;
+ Phase3Reg[5] <= Phase3A1w;
+ end
+ 3'd3: begin
+ Phase3Reg[7] <= Phase3A0w;
+ Phase3Reg[6] <= Phase3A1w;
+ end
+ endcase // case(Phase3Count)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //-------------------------------------------------------------------------
+ // Phase4
+ // R0: s6
+ // R1: s5
+ //-------------------------------------------------------------------------
+ reg Phase4Enable;
+ reg [2:0] Phase4Page;
+ reg [2:0] Phase4Count;
+ reg Phase4EnableD;
+ reg [2:0] Phase4PageD;
+ reg [2:0] Phase4CountD;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase4Enable <= 1'b0;
+ Phase4Page <= 3'd0;
+ Phase4Count <= 3'd0;
+ Phase4EnableD <= 1'b0;
+ Phase4PageD <= 3'd0;
+ Phase4CountD <= 3'd0;
+ end else begin
+ Phase4Enable <= Phase3EnableD;
+ Phase4Page <= Phase3PageD;
+ Phase4Count <= Phase3CountD;
+ Phase4EnableD <= Phase4Enable;
+ Phase4PageD <= Phase4Page;
+ Phase4CountD <= Phase4Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ reg signed [42:0] Phase4R0r;
+ reg signed [42:0] Phase4R1r;
+
+ wire signed [8:0] C_181;
+ assign C_181 = 9'h0B5;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase4R0r <= 0;
+ Phase4R1r <= 0;
+ end else begin
+ case(Phase4Count)
+ 3'd2: begin
+ Phase4R0r <= (Phase3Reg[6] + Phase3Reg[5]) * C_181;
+ Phase4R1r <= (Phase3Reg[6] - Phase3Reg[5]) * C_181;
+ end
+ endcase // case(Phase4Count)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //-------------------------------------------------------------------------
+ // Phase5
+ // R0: B0,B1,B2,B3
+ // R1: B7,B6,B5,B4
+ //-------------------------------------------------------------------------
+ reg Phase5Enable;
+ reg [2:0] Phase5Page;
+ reg [2:0] Phase5Count;
+ reg Phase5EnableD;
+ reg [2:0] Phase5PageD;
+ reg [2:0] Phase5CountD;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase5Enable <= 1'b0;
+ Phase5Page <= 3'd0;
+ Phase5Count <= 3'd0;
+ Phase5EnableD <= 1'b0;
+ Phase5PageD <= 3'd0;
+ Phase5CountD <= 3'd0;
+ end else begin
+ Phase5Enable <= Phase4EnableD;
+ Phase5Page <= Phase4PageD;
+ Phase5Count <= Phase4CountD;
+ Phase5EnableD <= Phase5Enable;
+ Phase5PageD <= Phase5Page;
+ Phase5CountD <= Phase5Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ wire signed [31:0] Phase5R0w;
+ wire signed [31:0] Phase5R1w;
+ assign Phase5R0w = (Phase5Count == 3'd0)?Phase3Reg[0]:
+ (Phase5Count == 3'd1)?Phase3Reg[1]:
+ (Phase5Count == 3'd2)?Phase3Reg[2]:
+ (Phase5Count == 3'd3)?Phase3Reg[3]:
+ 32'd0;
+ assign Phase5R1w = (Phase5Count == 3'd0)?Phase3Reg[7]:
+ (Phase5Count == 3'd1)?Phase4R0r >> 8:
+ (Phase5Count == 3'd2)?Phase4R1r >> 8:
+ (Phase5Count == 3'd3)?Phase3Reg[4]:
+ 32'd0;
+
+
+ reg signed [31:0] Phase5R0r;
+ reg signed [31:0] Phase5R1r;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase5R0r <= 0;
+ Phase5R1r <= 0;
+ end else begin
+ Phase5R0r <= Phase5R0w + Phase5R1w;
+ Phase5R1r <= Phase5R0w - Phase5R1w;
+ end
+ end
+
+ assign DataOutEnable = Phase5EnableD == 1'b1 & Phase5CountD[2] == 1'b0;
+ assign DataOutPage = Phase5PageD;
+ assign DataOutCount = Phase5CountD[1:0];
+
+ assign Data0Out = Phase5R0r[26:11];
+ assign Data1Out = Phase5R1r[26:11];
+
+endmodule // jpeg_idctx
Index: djpeg/trunk/src/jpeg_idcty.v
===================================================================
--- djpeg/trunk/src/jpeg_idcty.v (nonexistent)
+++ djpeg/trunk/src/jpeg_idcty.v (revision 6)
@@ -0,0 +1,1240 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_idcty.v
+// Module Name : jpeg_idcty
+// Description : iDCT-Y
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_idcty
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInBank,
+ DataInSel,
+ Data00In,
+ Data01In,
+ Data02In,
+ Data03In,
+ Data04In,
+ Data05In,
+ Data06In,
+ Data07In,
+ Data08In,
+ Data09In,
+ Data10In,
+ Data11In,
+ Data12In,
+ Data13In,
+ Data14In,
+ Data15In,
+ Data16In,
+ Data17In,
+ Data18In,
+ Data19In,
+ Data20In,
+ Data21In,
+ Data22In,
+ Data23In,
+ Data24In,
+ Data25In,
+ Data26In,
+ Data27In,
+ Data28In,
+ Data29In,
+ Data30In,
+ Data31In,
+ Data32In,
+ Data33In,
+ Data34In,
+ Data35In,
+ Data36In,
+ Data37In,
+ Data38In,
+ Data39In,
+ Data40In,
+ Data41In,
+ Data42In,
+ Data43In,
+ Data44In,
+ Data45In,
+ Data46In,
+ Data47In,
+ Data48In,
+ Data49In,
+ Data50In,
+ Data51In,
+ Data52In,
+ Data53In,
+ Data54In,
+ Data55In,
+ Data56In,
+ Data57In,
+ Data58In,
+ Data59In,
+ Data60In,
+ Data61In,
+ Data62In,
+ Data63In,
+ DataInIdle,
+ DataInRelease,
+
+ DataOutEnable,
+ DataOutPage,
+ DataOutCount,
+ Data0Out,
+ Data1Out
+ );
+
+ input clk;
+ input rst;
+
+ input DataInEnable;
+ output DataInBank;
+ output DataInSel;
+ input [15:0] Data00In;
+ input [15:0] Data01In;
+ input [15:0] Data02In;
+ input [15:0] Data03In;
+ input [15:0] Data04In;
+ input [15:0] Data05In;
+ input [15:0] Data06In;
+ input [15:0] Data07In;
+ input [15:0] Data08In;
+ input [15:0] Data09In;
+ input [15:0] Data10In;
+ input [15:0] Data11In;
+ input [15:0] Data12In;
+ input [15:0] Data13In;
+ input [15:0] Data14In;
+ input [15:0] Data15In;
+ input [15:0] Data16In;
+ input [15:0] Data17In;
+ input [15:0] Data18In;
+ input [15:0] Data19In;
+ input [15:0] Data20In;
+ input [15:0] Data21In;
+ input [15:0] Data22In;
+ input [15:0] Data23In;
+ input [15:0] Data24In;
+ input [15:0] Data25In;
+ input [15:0] Data26In;
+ input [15:0] Data27In;
+ input [15:0] Data28In;
+ input [15:0] Data29In;
+ input [15:0] Data30In;
+ input [15:0] Data31In;
+ input [15:0] Data32In;
+ input [15:0] Data33In;
+ input [15:0] Data34In;
+ input [15:0] Data35In;
+ input [15:0] Data36In;
+ input [15:0] Data37In;
+ input [15:0] Data38In;
+ input [15:0] Data39In;
+ input [15:0] Data40In;
+ input [15:0] Data41In;
+ input [15:0] Data42In;
+ input [15:0] Data43In;
+ input [15:0] Data44In;
+ input [15:0] Data45In;
+ input [15:0] Data46In;
+ input [15:0] Data47In;
+ input [15:0] Data48In;
+ input [15:0] Data49In;
+ input [15:0] Data50In;
+ input [15:0] Data51In;
+ input [15:0] Data52In;
+ input [15:0] Data53In;
+ input [15:0] Data54In;
+ input [15:0] Data55In;
+ input [15:0] Data56In;
+ input [15:0] Data57In;
+ input [15:0] Data58In;
+ input [15:0] Data59In;
+ input [15:0] Data60In;
+ input [15:0] Data61In;
+ input [15:0] Data62In;
+ input [15:0] Data63In;
+ output DataInIdle;
+ output DataInRelease;
+
+ output DataOutEnable;
+ output [2:0] DataOutPage;
+ output [1:0] DataOutCount;
+ output [8:0] Data0Out;
+ output [8:0] Data1Out;
+
+ //-------------------------------------------------------------------------
+ // Phase1
+ //-------------------------------------------------------------------------
+ reg Phase1Enable;
+ reg [2:0] Phase1Page;
+ reg [2:0] Phase1Count;
+ //reg Phase1EnableD;
+ //reg [2:0] Phase1PageD;
+ //reg [2:0] Phase1CountD;
+ reg DataInBank;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase1Enable <= 1'b0;
+ Phase1Page <= 3'd0;
+ Phase1Count <= 3'd0;
+ //Phase1EnableD <= 1'b0;
+ //Phase1PageD <= 3'd0;
+ //Phase1CountD <= 3'd0;
+ DataInBank <= 1'b0;
+ end else begin
+ if(Phase1Enable == 1'b0) begin
+ if(DataInEnable == 1'b1) begin
+ Phase1Enable <= 1'b1;
+ Phase1Page <= 3'd0;
+ Phase1Count <= 3'd0;
+ end
+ end else begin
+ if(Phase1Count == 3'd6) begin
+ if(Phase1Page == 3'd7) begin
+ Phase1Enable <= 1'b0;
+ Phase1Page <= 3'd0;
+ DataInBank <= ~DataInBank;
+ end else begin
+ Phase1Page <= Phase1Page + 3'd1;
+ end
+ Phase1Count <= 3'd0;
+ end else begin
+ Phase1Count <= Phase1Count + 3'd1;
+ end // else: !if(Phase1Count == 3'd6)
+ end // else: !if(Phase1Enable == 1'b0)
+ //Phase1EnableD <= Phase1Enable;
+ //Phase1PageD <= Phase1Page;
+ //Phase1CountD <= Phase1Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign DataInSel = DataInBank;
+ assign DataInIdle = Phase1Enable == 1'b0;
+ assign DataInRelease = Phase1Enable == 1'b1 & Phase1Count == 3'd6 & Phase1Page == 3'd7;
+
+ wire signed [15:0] Phase1R0w;
+ wire signed [15:0] Phase1R1w;
+ wire signed [15:0] Phase1C0w;
+ wire signed [15:0] Phase1C1w;
+ wire signed [15:0] Phase1C2w;
+ wire signed [15:0] Phase1C3w;
+/*
+ always @(*) begin
+ case(Phase1Page)
+ 3'd0:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data00In;
+ Phase1R1w <= Data04In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data02In;
+ Phase1R1w <= Data06In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data01In;
+ Phase1R1w <= Data07In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data05In;
+ Phase1R1w <= Data03In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd0
+ 3'd1:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data08In;
+ Phase1R1w <= Data12In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data10In;
+ Phase1R1w <= Data14In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data09In;
+ Phase1R1w <= Data15In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data13In;
+ Phase1R1w <= Data11In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd1
+ 3'd2:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data16In;
+ Phase1R1w <= Data20In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data18In;
+ Phase1R1w <= Data22In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data17In;
+ Phase1R1w <= Data23In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data21In;
+ Phase1R1w <= Data19In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd2
+ 3'd3:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data24In;
+ Phase1R1w <= Data28In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data26In;
+ Phase1R1w <= Data30In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data25In;
+ Phase1R1w <= Data31In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data29In;
+ Phase1R1w <= Data27In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd3
+ 3'd4:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data32In;
+ Phase1R1w <= Data36In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data34In;
+ Phase1R1w <= Data38In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data33In;
+ Phase1R1w <= Data39In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data37In;
+ Phase1R1w <= Data35In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd4
+ 3'd5:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data40In;
+ Phase1R1w <= Data44In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data42In;
+ Phase1R1w <= Data46In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data41In;
+ Phase1R1w <= Data47In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data45In;
+ Phase1R1w <= Data43In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd5
+ 3'd6:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data48In;
+ Phase1R1w <= Data52In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data50In;
+ Phase1R1w <= Data54In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data49In;
+ Phase1R1w <= Data55In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data53In;
+ Phase1R1w <= Data51In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd6
+ 3'd7:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0w <= Data56In;
+ Phase1R1w <= Data60In;
+ end
+ 3'd1: begin
+ Phase1R0w <= Data58In;
+ Phase1R1w <= Data62In;
+ end
+ 3'd2: begin
+ Phase1R0w <= Data57In;
+ Phase1R1w <= Data63In;
+ end
+ 3'd3: begin
+ Phase1R0w <= Data61In;
+ Phase1R1w <= Data59In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd7
+ endcase // case(Phase1Page)
+ end // always @ (*)
+*/
+ function [15:0] Phase1R0wSel;
+ input [2:0] Phase1Page;
+ input [2:0] Phase1Count;
+ input [15:0] Data00In;
+ input [15:0] Data01In;
+ input [15:0] Data02In;
+ input [15:0] Data03In;
+ input [15:0] Data04In;
+ input [15:0] Data05In;
+ input [15:0] Data06In;
+ input [15:0] Data07In;
+ input [15:0] Data08In;
+ input [15:0] Data09In;
+ input [15:0] Data10In;
+ input [15:0] Data11In;
+ input [15:0] Data12In;
+ input [15:0] Data13In;
+ input [15:0] Data14In;
+ input [15:0] Data15In;
+ input [15:0] Data16In;
+ input [15:0] Data17In;
+ input [15:0] Data18In;
+ input [15:0] Data19In;
+ input [15:0] Data20In;
+ input [15:0] Data21In;
+ input [15:0] Data22In;
+ input [15:0] Data23In;
+ input [15:0] Data24In;
+ input [15:0] Data25In;
+ input [15:0] Data26In;
+ input [15:0] Data27In;
+ input [15:0] Data28In;
+ input [15:0] Data29In;
+ input [15:0] Data30In;
+ input [15:0] Data31In;
+ input [15:0] Data32In;
+ input [15:0] Data33In;
+ input [15:0] Data34In;
+ input [15:0] Data35In;
+ input [15:0] Data36In;
+ input [15:0] Data37In;
+ input [15:0] Data38In;
+ input [15:0] Data39In;
+ input [15:0] Data40In;
+ input [15:0] Data41In;
+ input [15:0] Data42In;
+ input [15:0] Data43In;
+ input [15:0] Data44In;
+ input [15:0] Data45In;
+ input [15:0] Data46In;
+ input [15:0] Data47In;
+ input [15:0] Data48In;
+ input [15:0] Data49In;
+ input [15:0] Data50In;
+ input [15:0] Data51In;
+ input [15:0] Data52In;
+ input [15:0] Data53In;
+ input [15:0] Data54In;
+ input [15:0] Data55In;
+ input [15:0] Data56In;
+ input [15:0] Data57In;
+ input [15:0] Data58In;
+ input [15:0] Data59In;
+ input [15:0] Data60In;
+ input [15:0] Data61In;
+ input [15:0] Data62In;
+ input [15:0] Data63In;
+ begin
+ case(Phase1Page)
+ 3'd0:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data00In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data02In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data01In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data05In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd0
+ 3'd1:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data08In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data10In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data09In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data13In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd1
+ 3'd2:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data16In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data18In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data17In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data21In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd2
+ 3'd3:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data24In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data26In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data25In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data29In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd3
+ 3'd4:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data32In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data34In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data33In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data37In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd4
+ 3'd5:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data40In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data42In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data41In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data45In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd5
+ 3'd6:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data48In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data50In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data49In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data53In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd6
+ 3'd7:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R0wSel = Data56In;
+ end
+ 3'd1: begin
+ Phase1R0wSel = Data58In;
+ end
+ 3'd2: begin
+ Phase1R0wSel = Data57In;
+ end
+ 3'd3: begin
+ Phase1R0wSel = Data61In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd7
+ endcase // case(Phase1Page)
+ end
+ endfunction
+ function [15:0] Phase1R1wSel;
+ input [2:0] Phase1Page;
+ input [2:0] Phase1Count;
+ input [15:0] Data00In;
+ input [15:0] Data01In;
+ input [15:0] Data02In;
+ input [15:0] Data03In;
+ input [15:0] Data04In;
+ input [15:0] Data05In;
+ input [15:0] Data06In;
+ input [15:0] Data07In;
+ input [15:0] Data08In;
+ input [15:0] Data09In;
+ input [15:0] Data10In;
+ input [15:0] Data11In;
+ input [15:0] Data12In;
+ input [15:0] Data13In;
+ input [15:0] Data14In;
+ input [15:0] Data15In;
+ input [15:0] Data16In;
+ input [15:0] Data17In;
+ input [15:0] Data18In;
+ input [15:0] Data19In;
+ input [15:0] Data20In;
+ input [15:0] Data21In;
+ input [15:0] Data22In;
+ input [15:0] Data23In;
+ input [15:0] Data24In;
+ input [15:0] Data25In;
+ input [15:0] Data26In;
+ input [15:0] Data27In;
+ input [15:0] Data28In;
+ input [15:0] Data29In;
+ input [15:0] Data30In;
+ input [15:0] Data31In;
+ input [15:0] Data32In;
+ input [15:0] Data33In;
+ input [15:0] Data34In;
+ input [15:0] Data35In;
+ input [15:0] Data36In;
+ input [15:0] Data37In;
+ input [15:0] Data38In;
+ input [15:0] Data39In;
+ input [15:0] Data40In;
+ input [15:0] Data41In;
+ input [15:0] Data42In;
+ input [15:0] Data43In;
+ input [15:0] Data44In;
+ input [15:0] Data45In;
+ input [15:0] Data46In;
+ input [15:0] Data47In;
+ input [15:0] Data48In;
+ input [15:0] Data49In;
+ input [15:0] Data50In;
+ input [15:0] Data51In;
+ input [15:0] Data52In;
+ input [15:0] Data53In;
+ input [15:0] Data54In;
+ input [15:0] Data55In;
+ input [15:0] Data56In;
+ input [15:0] Data57In;
+ input [15:0] Data58In;
+ input [15:0] Data59In;
+ input [15:0] Data60In;
+ input [15:0] Data61In;
+ input [15:0] Data62In;
+ input [15:0] Data63In;
+ begin
+ case(Phase1Page)
+ 3'd0:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data04In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data06In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data07In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data03In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd0
+ 3'd1:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data12In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data14In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data15In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data11In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd1
+ 3'd2:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data20In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data22In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data23In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data19In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd2
+ 3'd3:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data28In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data30In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data31In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data27In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd3
+ 3'd4:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data36In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data38In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data39In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data35In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd4
+ 3'd5:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data44In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data46In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data47In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data43In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd5
+ 3'd6:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data52In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data54In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data55In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data51In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd6
+ 3'd7:begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1R1wSel = Data60In;
+ end
+ 3'd1: begin
+ Phase1R1wSel = Data62In;
+ end
+ 3'd2: begin
+ Phase1R1wSel = Data63In;
+ end
+ 3'd3: begin
+ Phase1R1wSel = Data59In;
+ end
+ endcase // case(Phase1Count)
+ end // case: 3'd7
+ endcase // case(Phase1Page)
+ end
+ endfunction
+
+ assign Phase1R0w = Phase1R0wSel(Phase1Page, Phase1Count,
+ Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In,
+ Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In,
+ Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In,
+ Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In,
+ Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In,
+ Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In,
+ Data60In, Data61In, Data62In, Data63In
+ );
+ assign Phase1R1w = Phase1R1wSel(Phase1Page, Phase1Count,
+ Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In,
+ Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In,
+ Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In,
+ Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In,
+ Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In,
+ Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In,
+ Data60In, Data61In, Data62In, Data63In
+ );
+/*
+ always @(*) begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C0w <= 16'd2896; // C4_16
+ Phase1C1w <= 16'd2896; // C4_16
+ Phase1C2w <= 16'd2896; // C4_16
+ Phase1C3w <= 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C0w <= 16'd3784; // C2_16
+ Phase1C1w <= 16'd1567; // C6_16
+ Phase1C2w <= 16'd1567; // C6_16
+ Phase1C3w <= 16'd3784; // C2_16
+ end
+ 3'd2: begin
+ Phase1C0w <= 16'd4017; // C1_16
+ Phase1C1w <= 16'd799; // C7_16
+ Phase1C2w <= 16'd799; // C7_16
+ Phase1C3w <= 16'd4017; // C1_16
+ end
+ 3'd3: begin
+ Phase1C0w <= 16'd2276; // C5_16
+ Phase1C1w <= 16'd3406; // C3_16
+ Phase1C2w <= 16'd3406; // C3_16
+ Phase1C3w <= 16'd2276; // C5_16
+ end
+
+ endcase // case(Phase1Count)
+
+ end // always @ (*)
+*/
+
+ function [15:0] Phase1C0wSel;
+ input [2:0] Phase1Count;
+ begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C0wSel = 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C0wSel = 16'd3784; // C2_16
+ end
+ 3'd2: begin
+ Phase1C0wSel = 16'd4017; // C1_16
+ end
+ 3'd3: begin
+ Phase1C0wSel = 16'd2276; // C5_16
+ end
+ endcase // case(Phase1Count)
+ end
+ endfunction
+
+ function [15:0] Phase1C1wSel;
+ input [2:0] Phase1Count;
+ begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C1wSel = 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C1wSel = 16'd1567; // C6_16
+ end
+ 3'd2: begin
+ Phase1C1wSel = 16'd799; // C7_16
+ end
+ 3'd3: begin
+ Phase1C1wSel = 16'd3406; // C3_16
+ end
+ endcase // case(Phase1Count)
+ end
+ endfunction
+
+ function [15:0] Phase1C2wSel;
+ input [2:0] Phase1Count;
+ begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C2wSel = 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C2wSel = 16'd1567; // C6_16
+ end
+ 3'd2: begin
+ Phase1C2wSel = 16'd799; // C7_16
+ end
+ 3'd3: begin
+ Phase1C2wSel = 16'd3406; // C3_16
+ end
+ endcase // case(Phase1Count)
+ end
+ endfunction
+
+ function [15:0] Phase1C3wSel;
+ input [2:0] Phase1Count;
+ begin
+ case(Phase1Count)
+ 3'd0: begin
+ Phase1C3wSel = 16'd2896; // C4_16
+ end
+ 3'd1: begin
+ Phase1C3wSel = 16'd3784; // C2_16
+ end
+ 3'd2: begin
+ Phase1C3wSel = 16'd4017; // C1_16
+ end
+ 3'd3: begin
+ Phase1C3wSel = 16'd2276; // C5_16
+ end
+ endcase // case(Phase1Count)
+ end
+ endfunction
+
+ assign Phase1C0w = Phase1C0wSel(Phase1Count);
+ assign Phase1C1w = Phase1C1wSel(Phase1Count);
+ assign Phase1C2w = Phase1C2wSel(Phase1Count);
+ assign Phase1C3w = Phase1C3wSel(Phase1Count);
+
+ reg signed [31:0] Phase1R0r;
+ reg signed [31:0] Phase1R1r;
+ reg signed [31:0] Phase1R2r;
+ reg signed [31:0] Phase1R3r;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase1R0r <= 0;
+ Phase1R1r <= 0;
+ Phase1R2r <= 0;
+ Phase1R3r <= 0;
+ end else begin
+ Phase1R0r <= Phase1R0w * Phase1C0w;
+ Phase1R1r <= Phase1R1w * Phase1C1w;
+ Phase1R2r <= Phase1R0w * Phase1C2w;
+ Phase1R3r <= Phase1R1w * Phase1C3w;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //-------------------------------------------------------------------------
+ // Phase2
+ // R0: s0,s3,s7,s6
+ // R1: s1,s2,s4,s5
+ //-------------------------------------------------------------------------
+ reg Phase2Enable;
+ reg [2:0] Phase2Page;
+ reg [2:0] Phase2Count;
+ reg Phase2EnableD;
+ reg [2:0] Phase2PageD;
+ reg [2:0] Phase2CountD;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase2Enable <= 1'b0;
+ Phase2Page <= 3'd0;
+ Phase2Count <= 3'd0;
+ Phase2EnableD <= 1'b0;
+ Phase2PageD <= 3'd0;
+ Phase2CountD <= 3'd0;
+ end else begin
+ Phase2Enable <= Phase1Enable;
+ Phase2Page <= Phase1Page;
+ Phase2Count <= Phase1Count;
+ Phase2EnableD <= Phase2Enable;
+ Phase2PageD <= Phase2Page;
+ Phase2CountD <= Phase2Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ wire signed [31:0] Phase2A0w;
+ wire signed [31:0] Phase2A1w;
+/*
+ always @(*) begin
+ Phase2A0w <= Phase1R0r + Phase1R1r;
+ Phase2A1w <= Phase1R2r - Phase1R3r;
+ end
+*/
+
+ assign Phase2A0w = Phase1R0r + Phase1R1r;
+ assign Phase2A1w = Phase1R2r - Phase1R3r;
+
+ reg signed [31:0] Phase2Reg [0:7];
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase2Reg[0] <= 0;
+ Phase2Reg[1] <= 0;
+ Phase2Reg[2] <= 0;
+ Phase2Reg[3] <= 0;
+ Phase2Reg[4] <= 0;
+ Phase2Reg[5] <= 0;
+ Phase2Reg[6] <= 0;
+ Phase2Reg[7] <= 0;
+ end else begin
+ case(Phase2Count)
+ 3'd0: begin
+ Phase2Reg[0] <= Phase2A0w;
+ Phase2Reg[1] <= Phase2A1w;
+ end
+ 3'd1: begin
+ Phase2Reg[3] <= Phase2A0w;
+ Phase2Reg[2] <= Phase2A1w;
+ end
+ 3'd2: begin
+ Phase2Reg[7] <= Phase2A0w;
+ Phase2Reg[4] <= Phase2A1w;
+ end
+ 3'd3: begin
+ Phase2Reg[6] <= Phase2A0w;
+ Phase2Reg[5] <= Phase2A1w;
+ end
+ endcase // case(Phase2Count)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //-------------------------------------------------------------------------
+ // Phase3
+ // R0: t0,t1,t4,t7
+ // R1: t3,t2,t5,t6
+ //-------------------------------------------------------------------------
+ reg Phase3Enable;
+ reg [2:0] Phase3Page;
+ reg [2:0] Phase3Count;
+ reg Phase3EnableD;
+ reg [2:0] Phase3PageD;
+ reg [2:0] Phase3CountD;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase3Enable <= 1'b0;
+ Phase3Page <= 3'd0;
+ Phase3Count <= 3'd0;
+ Phase3EnableD <= 1'b0;
+ Phase3PageD <= 3'd0;
+ Phase3CountD <= 3'd0;
+ end else begin
+ Phase3Enable <= Phase2EnableD;
+ Phase3Page <= Phase2PageD;
+ Phase3Count <= Phase2CountD;
+ Phase3EnableD <= Phase3Enable;
+ Phase3PageD <= Phase3Page;
+ Phase3CountD <= Phase3Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ wire signed [31:0] Phase3R0w;
+ wire signed [31:0] Phase3R1w;
+
+ assign Phase3R0w = (Phase3Count == 3'd0)?Phase2Reg[0]:
+ (Phase3Count == 3'd1)?Phase2Reg[1]:
+ (Phase3Count == 3'd2)?Phase2Reg[4]:
+ (Phase3Count == 3'd3)?Phase2Reg[7]:
+ 32'd0;
+ assign Phase3R1w = (Phase3Count == 3'd0)?Phase2Reg[3]:
+ (Phase3Count == 3'd1)?Phase2Reg[2]:
+ (Phase3Count == 3'd2)?Phase2Reg[5]:
+ (Phase3Count == 3'd3)?Phase2Reg[6]:
+ 32'd0;
+
+ wire signed [31:0] Phase3A0w;
+ wire signed [31:0] Phase3A1w;
+/*
+ always @(*) begin
+ Phase3A0w <= Phase3R0w + Phase3R1w;
+ Phase3A1w <= Phase3R0w - Phase3R1w;
+ end
+*/
+
+ assign Phase3A0w = Phase3R0w + Phase3R1w;
+ assign Phase3A1w = Phase3R0w - Phase3R1w;
+
+ reg signed [31:0] Phase3Reg [0:7];
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase3Reg[0] <= 0;
+ Phase3Reg[1] <= 0;
+ Phase3Reg[2] <= 0;
+ Phase3Reg[3] <= 0;
+ Phase3Reg[4] <= 0;
+ Phase3Reg[5] <= 0;
+ Phase3Reg[6] <= 0;
+ Phase3Reg[7] <= 0;
+ end else begin
+ case(Phase3Count)
+ 3'd0: begin
+ Phase3Reg[0] <= Phase3A0w;
+ Phase3Reg[3] <= Phase3A1w;
+ end
+ 3'd1: begin
+ Phase3Reg[1] <= Phase3A0w;
+ Phase3Reg[2] <= Phase3A1w;
+ end
+ 3'd2: begin
+ Phase3Reg[4] <= Phase3A0w;
+ Phase3Reg[5] <= Phase3A1w;
+ end
+ 3'd3: begin
+ Phase3Reg[7] <= Phase3A0w;
+ Phase3Reg[6] <= Phase3A1w;
+ end
+ endcase // case(Phase3Count)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //-------------------------------------------------------------------------
+ // Phase4
+ // R0: s5
+ // R1: s6
+ //-------------------------------------------------------------------------
+ reg Phase4Enable;
+ reg [2:0] Phase4Page;
+ reg [2:0] Phase4Count;
+ reg Phase4EnableD;
+ reg [2:0] Phase4PageD;
+ reg [2:0] Phase4CountD;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase4Enable <= 1'b0;
+ Phase4Page <= 3'd0;
+ Phase4Count <= 3'd0;
+ Phase4EnableD <= 1'b0;
+ Phase4PageD <= 3'd0;
+ Phase4CountD <= 3'd0;
+ end else begin
+ Phase4Enable <= Phase3EnableD;
+ Phase4Page <= Phase3PageD;
+ Phase4Count <= Phase3CountD;
+ Phase4EnableD <= Phase4Enable;
+ Phase4PageD <= Phase4Page;
+ Phase4CountD <= Phase4Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ reg signed [42:0] Phase4R0r;
+ reg signed [42:0] Phase4R1r;
+
+ wire signed [8:0] C_181;
+ assign C_181 = 9'h0B5;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase4R0r <= 0;
+ Phase4R1r <= 0;
+ end else begin
+ case(Phase4Count)
+ 3'd2: begin
+ Phase4R0r <= (Phase3Reg[6] + Phase3Reg[5]) * C_181;
+ Phase4R1r <= (Phase3Reg[6] - Phase3Reg[5]) * C_181;
+ end
+ endcase // case(Phase4Count)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ //-------------------------------------------------------------------------
+ // Phase5
+ // R0: B0,B1,B2,B3
+ // R1: B7,B6,B5,B4
+ //-------------------------------------------------------------------------
+ reg Phase5Enable;
+ reg [2:0] Phase5Page;
+ reg [2:0] Phase5Count;
+ reg Phase5EnableD;
+ reg [2:0] Phase5PageD;
+ reg [2:0] Phase5CountD;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase5Enable <= 1'b0;
+ Phase5Page <= 3'd0;
+ Phase5Count <= 3'd0;
+ Phase5EnableD <= 1'b0;
+ Phase5PageD <= 3'd0;
+ Phase5CountD <= 3'd0;
+ end else begin
+ Phase5Enable <= Phase4EnableD;
+ Phase5Page <= Phase4PageD;
+ Phase5Count <= Phase4CountD;
+ Phase5EnableD <= Phase5Enable;
+ Phase5PageD <= Phase5Page;
+ Phase5CountD <= Phase5Count;
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ wire signed [31:0] Phase5R0w;
+ wire signed [31:0] Phase5R1w;
+ assign Phase5R0w = (Phase5Count == 3'd0)?Phase3Reg[0]:
+ (Phase5Count == 3'd1)?Phase3Reg[1]:
+ (Phase5Count == 3'd2)?Phase3Reg[2]:
+ (Phase5Count == 3'd3)?Phase3Reg[3]:
+ 32'd0;
+ assign Phase5R1w = (Phase5Count == 3'd0)?Phase3Reg[7]:
+ (Phase5Count == 3'd1)?Phase4R0r >> 8:
+ (Phase5Count == 3'd2)?Phase4R1r >> 8:
+ (Phase5Count == 3'd3)?Phase3Reg[4]:
+ 32'd0;
+
+ reg signed [31:0] Phase5R0r;
+ reg signed [31:0] Phase5R1r;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ Phase5R0r <= 0;
+ Phase5R1r <= 0;
+ end else begin
+ Phase5R0r <= Phase5R0w + Phase5R1w;
+ Phase5R1r <= Phase5R0w - Phase5R1w;
+ end
+ end
+
+ assign DataOutEnable = Phase5EnableD == 1'b1 & Phase5CountD[2] == 1'b0;
+ assign DataOutPage = Phase5PageD;
+ assign DataOutCount = Phase5CountD[1:0];
+
+ assign Data0Out = Phase5R0r[30:15];
+ assign Data1Out = Phase5R1r[30:15];
+
+endmodule // jpeg_idcty
Index: djpeg/trunk/src/jpeg_dht.v
===================================================================
--- djpeg/trunk/src/jpeg_dht.v (nonexistent)
+++ djpeg/trunk/src/jpeg_dht.v (revision 6)
@@ -0,0 +1,118 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_dht.v
+// Module Name : jpeg_dht
+// Description : DHT space
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_dht
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInColor,
+ DataInCount,
+ DataIn,
+
+ ColorNumber,
+ TableNumber,
+ ZeroTable,
+ WidhtTable
+ );
+
+ input rst;
+ input clk;
+
+ input DataInEnable;
+ input [1:0] DataInColor;
+ input [7:0] DataInCount;
+ input [7:0] DataIn;
+
+ input [1:0] ColorNumber;
+ input [7:0] TableNumber;
+ output [3:0] ZeroTable;
+ output [3:0] WidhtTable;
+
+ // RAM
+ reg [7:0] DHT_Ydc [0:15];
+ reg [7:0] DHT_Yac [0:255];
+ reg [7:0] DHT_Cdc [0:15];
+ reg [7:0] DHT_Cac [0:255];
+
+ reg [7:0] ReadDataYdc;
+ reg [7:0] ReadDataYac;
+ reg [7:0] ReadDataCdc;
+ reg [7:0] ReadDataCac;
+
+ wire [7:0] ReadData;
+
+ // RAM
+ always @(posedge clk) begin
+ if(DataInEnable ==1'b1 & DataInColor ==2'b00) begin
+ DHT_Ydc[DataInCount[3:0]] <= DataIn;
+ end
+ if(DataInEnable ==1'b1 & DataInColor ==2'b01) begin
+ DHT_Yac[DataInCount] <= DataIn;
+ end
+ if(DataInEnable ==1'b1 & DataInColor ==2'b10) begin
+ DHT_Cdc[DataInCount[3:0]] <= DataIn;
+ end
+ if(DataInEnable ==1'b1 & DataInColor ==2'b11) begin
+ DHT_Cac[DataInCount] <= DataIn;
+ end
+ end // always @ (posedge clk)
+
+ always @(posedge clk) begin
+ ReadDataYdc <= DHT_Ydc[TableNumber[3:0]];
+ ReadDataYac <= DHT_Yac[TableNumber];
+ ReadDataCdc <= DHT_Cdc[TableNumber[3:0]];
+ ReadDataCac <= DHT_Cac[TableNumber];
+ end // always @ (posedge clk or negedge rst)
+
+ // Selector
+/*
+ always @(*) begin
+ case (ColorNumber)
+ 2'b00: ReadData <= ReadDataYdc;
+ 2'b01: ReadData <= ReadDataYac;
+ 2'b10: ReadData <= ReadDataCdc;
+ 2'b11: ReadData <= ReadDataCac;
+ endcase // case(ColorNumber)
+ end
+*/
+ function [7:0] ReadDataSel;
+ input [1:0] ColorNumber;
+ input [7:0] ReadDataYdc;
+ input [7:0] ReadDataYac;
+ input [7:0] ReadDataCdc;
+ input [7:0] ReadDataCac;
+ begin
+ case (ColorNumber)
+ 2'b00: ReadDataSel = ReadDataYdc;
+ 2'b01: ReadDataSel = ReadDataYac;
+ 2'b10: ReadDataSel = ReadDataCdc;
+ 2'b11: ReadDataSel = ReadDataCac;
+ endcase
+ end
+ endfunction
+
+ assign ReadData = ReadDataSel(ColorNumber, ReadDataYdc, ReadDataYac, ReadDataCdc, ReadDataCac);
+
+ assign ZeroTable = ReadData[7:4];
+ assign WidhtTable = ReadData[3:0];
+
+endmodule // jpeg_dht
Index: djpeg/trunk/src/jpeg_decode.v
===================================================================
--- djpeg/trunk/src/jpeg_decode.v (nonexistent)
+++ djpeg/trunk/src/jpeg_decode.v (revision 6)
@@ -0,0 +1,474 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_decode.v
+// Module Name : jpeg_decode
+// Description : JPEG Deocder top module
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2007/04/11
+// Rev. : 2.0
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+// 1.02 2006/10/04 add ProcessIdle register
+// 2.00 2007/04/11
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_decode
+ (
+ rst,
+ clk,
+
+ // From FIFO
+ DataIn,
+ DataInEnable,
+ DataInRead,
+
+ JpegDecodeIdle, // Deocdeer Process Idle(1:Idle, 0:Run)
+
+ OutEnable,
+ OutWidth,
+ OutHeight,
+ OutPixelX,
+ OutPixelY,
+ OutR,
+ OutG,
+ OutB
+
+ );
+
+ input rst;
+ input clk;
+
+ input [31:0] DataIn;
+ input DataInEnable;
+ output DataInRead;
+
+ output JpegDecodeIdle;
+
+ output OutEnable;
+ output [15:0] OutWidth;
+ output [15:0] OutHeight;
+ output [15:0] OutPixelX;
+ output [15:0] OutPixelY;
+ output [7:0] OutR;
+ output [7:0] OutG;
+ output [7:0] OutB;
+
+ wire [31:0] JpegData;
+ wire JpegDataEnable;
+ wire JpegDecodeIdle;
+
+ wire UseBit;
+ wire [6:0] UseWidth;
+ wire UseByte;
+ wire UseWord;
+
+ wire ImageEnable;
+ wire EnableFF00;
+ wire DecodeFinish;
+
+// reg ProcessIdle;
+
+ //--------------------------------------------------------------------------
+ // Read JPEG Data from FIFO
+ //--------------------------------------------------------------------------
+ jpeg_regdata u_jpeg_regdata(
+ .rst(rst),
+ .clk(clk),
+
+ // Read Data
+ .DataIn ( DataIn ),
+ .DataInEnable ( DataInEnable ),
+ .DataInRead ( DataInRead ),
+
+ // DataOut
+ .DataOut ( JpegData ),
+ .DataOutEnable ( JpegDataEnable ),
+
+ //
+ .ImageEnable ( EnableFF00 ),
+ .ProcessIdle ( JpegDecodeIdle ),
+
+ // UseData
+ .UseBit ( UseBit ),
+ .UseWidth ( UseWidth ),
+ .UseByte ( UseByte ),
+ .UseWord ( UseWord )
+ );
+
+ //--------------------------------------------------------------------------
+ // Read Maker from Jpeg Data
+ //--------------------------------------------------------------------------
+ wire DqtEnable;
+ wire DqtTable;
+ wire [5:0] DqtCount;
+ wire [7:0] DqtData;
+
+ wire DhtEnable;
+ wire [1:0] DhtTable;
+ wire [7:0] DhtCount;
+ wire [7:0] DhtData;
+
+ //
+ wire HaffumanEnable;
+ wire [1:0] HaffumanTable;
+ wire [3:0] HaffumanCount;
+ wire [15:0] HaffumanData;
+ wire [7:0] HaffumanStart;
+
+ wire [11:0] JpegBlockWidth;
+
+ jpeg_decode_fsm u_jpeg_decode_fsm(
+ .rst(rst),
+ .clk(clk),
+
+ // From FIFO
+ .DataInEnable ( JpegDataEnable ),
+ .DataIn ( JpegData ),
+
+ .JpegDecodeIdle ( JpegDecodeIdle ),
+
+ .OutWidth ( OutWidth ),
+ .OutHeight ( OutHeight ),
+ .OutBlockWidth ( JpegBlockWidth ),
+ .OutEnable ( OutEnable ),
+ .OutPixelX ( OutPixelX ),
+ .OutPixelY ( OutPixelY ),
+
+ //
+ .DqtEnable ( DqtEnable ),
+ .DqtTable ( DqtTable ),
+ .DqtCount ( DqtCount ),
+ .DqtData ( DqtData ),
+
+ //
+ .DhtEnable ( DhtEnable ),
+ .DhtTable ( DhtTable ),
+ .DhtCount ( DhtCount ),
+ .DhtData ( DhtData ),
+
+ //
+ .HaffumanEnable ( HaffumanEnable ),
+ .HaffumanTable ( HaffumanTable ),
+ .HaffumanCount ( HaffumanCount ),
+ .HaffumanData ( HaffumanData ),
+ .HaffumanStart ( HaffumanStart ),
+
+ //
+ .ImageEnable ( ImageEnable ),
+ .ImageEnd ( DecodeFinish ),
+ .EnableFF00 ( EnableFF00 ),
+
+ //
+ .UseByte ( UseByte ),
+ .UseWord ( UseWord )
+ );
+
+
+ wire HmDecEnable;
+ wire [2:0] HmDecColor;
+
+ wire HmDecSel;
+ wire HmDecRelease;
+
+ wire [15:0] Hm00Data;
+ wire [15:0] Hm01Data;
+ wire [15:0] Hm02Data;
+ wire [15:0] Hm03Data;
+ wire [15:0] Hm04Data;
+ wire [15:0] Hm05Data;
+ wire [15:0] Hm06Data;
+ wire [15:0] Hm07Data;
+ wire [15:0] Hm08Data;
+ wire [15:0] Hm09Data;
+ wire [15:0] Hm10Data;
+ wire [15:0] Hm11Data;
+ wire [15:0] Hm12Data;
+ wire [15:0] Hm13Data;
+ wire [15:0] Hm14Data;
+ wire [15:0] Hm15Data;
+ wire [15:0] Hm16Data;
+ wire [15:0] Hm17Data;
+ wire [15:0] Hm18Data;
+ wire [15:0] Hm19Data;
+ wire [15:0] Hm20Data;
+ wire [15:0] Hm21Data;
+ wire [15:0] Hm22Data;
+ wire [15:0] Hm23Data;
+ wire [15:0] Hm24Data;
+ wire [15:0] Hm25Data;
+ wire [15:0] Hm26Data;
+ wire [15:0] Hm27Data;
+ wire [15:0] Hm28Data;
+ wire [15:0] Hm29Data;
+ wire [15:0] Hm30Data;
+ wire [15:0] Hm31Data;
+ wire [15:0] Hm32Data;
+ wire [15:0] Hm33Data;
+ wire [15:0] Hm34Data;
+ wire [15:0] Hm35Data;
+ wire [15:0] Hm36Data;
+ wire [15:0] Hm37Data;
+ wire [15:0] Hm38Data;
+ wire [15:0] Hm39Data;
+ wire [15:0] Hm40Data;
+ wire [15:0] Hm41Data;
+ wire [15:0] Hm42Data;
+ wire [15:0] Hm43Data;
+ wire [15:0] Hm44Data;
+ wire [15:0] Hm45Data;
+ wire [15:0] Hm46Data;
+ wire [15:0] Hm47Data;
+ wire [15:0] Hm48Data;
+ wire [15:0] Hm49Data;
+ wire [15:0] Hm50Data;
+ wire [15:0] Hm51Data;
+ wire [15:0] Hm52Data;
+ wire [15:0] Hm53Data;
+ wire [15:0] Hm54Data;
+ wire [15:0] Hm55Data;
+ wire [15:0] Hm56Data;
+ wire [15:0] Hm57Data;
+ wire [15:0] Hm58Data;
+ wire [15:0] Hm59Data;
+ wire [15:0] Hm60Data;
+ wire [15:0] Hm61Data;
+ wire [15:0] Hm62Data;
+ wire [15:0] Hm63Data;
+
+ wire DctIdle;
+
+ jpeg_haffuman u_jpeg_haffuman(
+ .rst(rst),
+ .clk(clk),
+
+ // DQT Table
+ .DqtInEnable ( DqtEnable ),
+ .DqtInColor ( DqtTable ),
+ .DqtInCount ( DqtCount[5:0] ),
+ .DqtInData ( DqtData ),
+
+ // DHT Table
+ .DhtInEnable ( DhtEnable ),
+ .DhtInColor ( DhtTable ),
+ .DhtInCount ( DhtCount ),
+ .DhtInData ( DhtData ),
+
+ // Haffuman Table
+ .HaffumanTableEnable ( HaffumanEnable ),
+ .HaffumanTableColor ( HaffumanTable ),
+ .HaffumanTableCount ( HaffumanCount ),
+ .HaffumanTableCode ( HaffumanData ),
+ .HaffumanTableStart ( HaffumanStart ),
+
+ // Haffuman Decode
+ .DataInRun ( ImageEnable ),
+ .DataInEnable ( JpegDataEnable ),
+ .DataIn ( JpegData ),
+
+ // Output decode data
+ .DecodeUseBit ( UseBit ),
+ .DecodeUseWidth ( UseWidth ),
+
+ // Data Out
+ .DataOutIdle ( DctIdle ),
+ .DataOutEnable ( HmDecEnable ),
+ .DataOutColor ( HmDecColor ),
+ .DataOutSel ( HmDecSel ),
+ .Data00Reg ( Hm00Data ),
+ .Data01Reg ( Hm01Data ),
+ .Data02Reg ( Hm02Data ),
+ .Data03Reg ( Hm03Data ),
+ .Data04Reg ( Hm04Data ),
+ .Data05Reg ( Hm05Data ),
+ .Data06Reg ( Hm06Data ),
+ .Data07Reg ( Hm07Data ),
+ .Data08Reg ( Hm08Data ),
+ .Data09Reg ( Hm09Data ),
+ .Data10Reg ( Hm10Data ),
+ .Data11Reg ( Hm11Data ),
+ .Data12Reg ( Hm12Data ),
+ .Data13Reg ( Hm13Data ),
+ .Data14Reg ( Hm14Data ),
+ .Data15Reg ( Hm15Data ),
+ .Data16Reg ( Hm16Data ),
+ .Data17Reg ( Hm17Data ),
+ .Data18Reg ( Hm18Data ),
+ .Data19Reg ( Hm19Data ),
+ .Data20Reg ( Hm20Data ),
+ .Data21Reg ( Hm21Data ),
+ .Data22Reg ( Hm22Data ),
+ .Data23Reg ( Hm23Data ),
+ .Data24Reg ( Hm24Data ),
+ .Data25Reg ( Hm25Data ),
+ .Data26Reg ( Hm26Data ),
+ .Data27Reg ( Hm27Data ),
+ .Data28Reg ( Hm28Data ),
+ .Data29Reg ( Hm29Data ),
+ .Data30Reg ( Hm30Data ),
+ .Data31Reg ( Hm31Data ),
+ .Data32Reg ( Hm32Data ),
+ .Data33Reg ( Hm33Data ),
+ .Data34Reg ( Hm34Data ),
+ .Data35Reg ( Hm35Data ),
+ .Data36Reg ( Hm36Data ),
+ .Data37Reg ( Hm37Data ),
+ .Data38Reg ( Hm38Data ),
+ .Data39Reg ( Hm39Data ),
+ .Data40Reg ( Hm40Data ),
+ .Data41Reg ( Hm41Data ),
+ .Data42Reg ( Hm42Data ),
+ .Data43Reg ( Hm43Data ),
+ .Data44Reg ( Hm44Data ),
+ .Data45Reg ( Hm45Data ),
+ .Data46Reg ( Hm46Data ),
+ .Data47Reg ( Hm47Data ),
+ .Data48Reg ( Hm48Data ),
+ .Data49Reg ( Hm49Data ),
+ .Data50Reg ( Hm50Data ),
+ .Data51Reg ( Hm51Data ),
+ .Data52Reg ( Hm52Data ),
+ .Data53Reg ( Hm53Data ),
+ .Data54Reg ( Hm54Data ),
+ .Data55Reg ( Hm55Data ),
+ .Data56Reg ( Hm56Data ),
+ .Data57Reg ( Hm57Data ),
+ .Data58Reg ( Hm58Data ),
+ .Data59Reg ( Hm59Data ),
+ .Data60Reg ( Hm60Data ),
+ .Data61Reg ( Hm61Data ),
+ .Data62Reg ( Hm62Data ),
+ .Data63Reg ( Hm63Data ),
+ .DataOutRelease (HmDecRelase)
+ );
+
+ wire DctEnable;
+ wire [2:0] DctColor;
+ wire [2:0] DctPage;
+ wire [1:0] DctCount;
+ wire [8:0] Dct0Data;
+ wire [8:0] Dct1Data;
+
+ wire [15:0] DctWidth;
+ wire [15:0] DctHeight;
+ wire [11:0] DctBlockX;
+ wire [11:0] DctBlockY;
+
+ wire YCbCrIdle;
+
+ jpeg_idct u_jpeg_idct(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable( HmDecEnable ),
+ .DataInSel( HmDecSel ),
+ .Data00In( Hm00Data ),
+ .Data01In( Hm01Data ),
+ .Data02In( Hm02Data ),
+ .Data03In( Hm03Data ),
+ .Data04In( Hm04Data ),
+ .Data05In( Hm05Data ),
+ .Data06In( Hm06Data ),
+ .Data07In( Hm07Data ),
+ .Data08In( Hm08Data ),
+ .Data09In( Hm09Data ),
+ .Data10In( Hm10Data ),
+ .Data11In( Hm11Data ),
+ .Data12In( Hm12Data ),
+ .Data13In( Hm13Data ),
+ .Data14In( Hm14Data ),
+ .Data15In( Hm15Data ),
+ .Data16In( Hm16Data ),
+ .Data17In( Hm17Data ),
+ .Data18In( Hm18Data ),
+ .Data19In( Hm19Data ),
+ .Data20In( Hm20Data ),
+ .Data21In( Hm21Data ),
+ .Data22In( Hm22Data ),
+ .Data23In( Hm23Data ),
+ .Data24In( Hm24Data ),
+ .Data25In( Hm25Data ),
+ .Data26In( Hm26Data ),
+ .Data27In( Hm27Data ),
+ .Data28In( Hm28Data ),
+ .Data29In( Hm29Data ),
+ .Data30In( Hm30Data ),
+ .Data31In( Hm31Data ),
+ .Data32In( Hm32Data ),
+ .Data33In( Hm33Data ),
+ .Data34In( Hm34Data ),
+ .Data35In( Hm35Data ),
+ .Data36In( Hm36Data ),
+ .Data37In( Hm37Data ),
+ .Data38In( Hm38Data ),
+ .Data39In( Hm39Data ),
+ .Data40In( Hm40Data ),
+ .Data41In( Hm41Data ),
+ .Data42In( Hm42Data ),
+ .Data43In( Hm43Data ),
+ .Data44In( Hm44Data ),
+ .Data45In( Hm45Data ),
+ .Data46In( Hm46Data ),
+ .Data47In( Hm47Data ),
+ .Data48In( Hm48Data ),
+ .Data49In( Hm49Data ),
+ .Data50In( Hm50Data ),
+ .Data51In( Hm51Data ),
+ .Data52In( Hm52Data ),
+ .Data53In( Hm53Data ),
+ .Data54In( Hm54Data ),
+ .Data55In( Hm55Data ),
+ .Data56In( Hm56Data ),
+ .Data57In( Hm57Data ),
+ .Data58In( Hm58Data ),
+ .Data59In( Hm59Data ),
+ .Data60In( Hm60Data ),
+ .Data61In( Hm61Data ),
+ .Data62In( Hm62Data ),
+ .Data63In( Hm63Data ),
+ .DataInIdle( DctIdle ),
+ .DataInRelease( HmDecRelase ),
+
+ .DataOutEnable ( DctEnable ),
+ .DataOutPage ( DctPage ),
+ .DataOutCount ( DctCount ),
+ .Data0Out ( Dct0Data ),
+ .Data1Out ( Dct1Data )
+ );
+
+ wire ColorEnable;
+ wire [15:0] ColorPixelX, ColorPixelY;
+ wire [7:0] ColorR, ColorG, ColorB;
+ jpeg_ycbcr u_jpeg_ycbcr(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable ( DctEnable ),
+ .DataInPage ( DctPage ),
+ .DataInCount ( DctCount ),
+ .DataInIdle ( YCbCrIdle ),
+ .Data0In ( Dct0Data ),
+ .Data1In ( Dct1Data ),
+ .DataInBlockWidth ( JpegBlockWidth ),
+
+ .OutEnable ( ColorEnable ),
+ .OutPixelX ( ColorPixelX ),
+ .OutPixelY ( ColorPixelY ),
+ .OutR ( ColorR ),
+ .OutG ( ColorG ),
+ .OutB ( ColorB )
+ );
+ // OutData
+ assign OutEnable = (ImageEnable)?ColorEnable:1'b0;
+ assign OutPixelX = (ImageEnable)?ColorPixelX:16'd0;
+ assign OutPixelY = (ImageEnable)?ColorPixelY:16'd0;
+ assign OutR = (ImageEnable)?ColorR:8'd0;
+ assign OutG = (ImageEnable)?ColorG:8'd0;
+ assign OutB = (ImageEnable)?ColorB:8'd0;
+
+endmodule // jpeg_decode
Index: djpeg/trunk/src/jpeg_decode_fsm.v
===================================================================
--- djpeg/trunk/src/jpeg_decode_fsm.v (nonexistent)
+++ djpeg/trunk/src/jpeg_decode_fsm.v (revision 6)
@@ -0,0 +1,640 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_decode_fsm.v
+// Module Name : jpeg_decode_fsm
+// Description : Decode Maker
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2007/04/11
+// Rev. : 1.03
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+// 1.02 2006/10/04 Remove a HmOldData register.
+// When reset, clear a ReadDqtTable register.
+// 1.03 2007/04/11 Remove JpegDecodeStart
+// Exchange StateMachine(Add ImageData)
+// Remove JpegDecodeStart
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_decode_fsm
+ (
+ rst,
+ clk,
+
+ // From FIFO
+ DataInEnable,
+ DataIn,
+
+ JpegDecodeIdle, // Deocdeer Process Idle(1:Idle, 0:Run)
+
+ OutWidth,
+ OutHeight,
+ OutBlockWidth,
+ OutEnable,
+ OutPixelX,
+ OutPixelY,
+
+ //
+ DqtEnable,
+ DqtTable,
+ DqtCount,
+ DqtData,
+
+ //
+ DhtEnable,
+ DhtTable,
+ DhtCount,
+ DhtData,
+
+ //
+ HaffumanEnable,
+ HaffumanTable,
+ HaffumanCount,
+ HaffumanData,
+ HaffumanStart,
+
+ //
+ ImageEnable,
+ ImageEnd,
+ EnableFF00,
+
+ //
+ UseByte,
+ UseWord
+ );
+
+ input rst;
+ input clk;
+
+ input DataInEnable;
+ input [31:0] DataIn;
+
+ output JpegDecodeIdle;
+
+ output [15:0] OutWidth;
+ output [15:0] OutHeight;
+ output [11:0] OutBlockWidth;
+ input OutEnable;
+ input [15:0] OutPixelX;
+ input [15:0] OutPixelY;
+
+ output DqtEnable;
+ output DqtTable;
+ output [5:0] DqtCount;
+ output [7:0] DqtData;
+
+ output DhtEnable;
+ output [1:0] DhtTable;
+ output [7:0] DhtCount;
+ output [7:0] DhtData;
+
+ //
+ output HaffumanEnable;
+ output [1:0] HaffumanTable;
+ output [3:0] HaffumanCount;
+ output [15:0] HaffumanData;
+ output [7:0] HaffumanStart;
+
+ //
+ output ImageEnable;
+ input ImageEnd;
+ output EnableFF00;
+
+ //
+ output UseByte;
+ output UseWord;
+
+
+ //--------------------------------------------------------------------------
+ // Read Maker from Jpeg Data
+ //--------------------------------------------------------------------------
+ reg [1:0] State;
+ reg [3:0] Process;
+ wire StateReadByte;
+ wire StateReadWord;
+ wire ImageEnable;
+
+ wire ReadSegmentEnd;
+
+ parameter Idle = 2'b00;
+ parameter GetMarker = 2'b01;
+ parameter ReadSegment = 2'b10;
+ parameter ImageData = 2'b11;
+
+ parameter NoProcess = 4'h0;
+ parameter SegSOI = 4'h1;
+ parameter SegAPP = 4'h2;
+ parameter SegDQT = 4'h3;
+ parameter SegDHT = 4'h4;
+ parameter SegSOF0 = 4'h5;
+ parameter SegSOS = 4'h6;
+ parameter SegDRI = 4'h7;
+ parameter SegRST = 4'h8;
+ parameter SegEOI = 4'h9;
+
+ reg [15:0] JpegWidth;
+ reg [15:0] JpegHeight;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ State <= Idle;
+ Process <= NoProcess;
+ end else begin
+ case(State)
+ Idle: begin
+ if(DataInEnable == 1'b1) begin
+ State <= GetMarker;
+ end
+ Process <= NoProcess;
+ end
+ GetMarker: begin
+ if(DataInEnable == 1'b1) begin
+ State <= ReadSegment;
+ case(DataIn[31:16])
+ 16'hFFD8: begin // SOI Segment
+ Process <= SegSOI;
+ end
+ 16'hFFE0: begin // APP0 Segment
+ Process <= SegAPP;
+ end
+ 16'hFFDB: begin // DQT Segment
+ Process <= SegDQT;
+ end
+ 16'hFFC4: begin // DHT Segment
+ Process <= SegDHT;
+ end
+ 16'hFFC0: begin // SOF0 Segment
+ Process <= SegSOF0;
+ end
+ 16'hFFDA: begin // SOS Segment
+ Process <= SegSOS;
+ end
+ //16'hFFDD: begin // DRI Segment
+ // Process <= SegDRI;
+ //end
+ //16'hFFDx: begin // RSTn Segment
+ // Process <= SegRST;
+ //end
+ //16'hFFD9: begin // EOI Segment
+ // Process <= SegEOI;
+ //end
+ default: begin
+ Process <= SegAPP;
+ end
+ endcase
+ end
+ end
+ ReadSegment: begin
+ if(ReadSegmentEnd == 1'b1) begin
+ Process <= NoProcess;
+ if(Process == SegSOS) begin
+ State <= ImageData;
+ end else begin
+ State <= GetMarker;
+ end
+ end
+ end
+ ImageData: begin
+ if(OutEnable & (JpegWidth == OutPixelX +1) & (JpegHeight == OutPixelY +1)) begin
+ State <= Idle;
+ end
+ end
+ endcase
+ end
+ end
+
+ assign JpegDecodeIdle = (State == Idle);
+ assign StateReadByte = 1'b0;
+ assign StateReadWord = ((State == GetMarker) & (DataInEnable == 1'b1));
+ assign ImageEnable = (State == ImageData);
+
+ wire ReadNopEnd;
+
+ assign ReadNopEnd = ((Process == SegSOI) | (Process == SegRST));
+
+ //--------------------------------------------------------------------------
+ // APP Segment
+ // Skip read data!
+ //--------------------------------------------------------------------------
+
+ reg [1:0] StateAPP;
+ reg [15:0] ReadAppCount;
+ wire ReadAppByte;
+ wire ReadAppWord;
+ wire ReadAppEnd;
+
+ parameter AppIdle = 2'd0;
+ parameter AppLength = 2'd1;
+ parameter AppRead = 2'd2;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ StateAPP <= AppIdle;
+ ReadAppCount <= 16'd0;
+ end else begin
+ case(StateAPP)
+ AppIdle: begin
+ if(Process == SegAPP) StateAPP <= AppLength;
+ ReadAppCount <= 16'd0;
+ end
+ AppLength: begin
+ if(DataInEnable == 1'b1) begin
+ ReadAppCount <= DataIn[31:16] -2;
+ StateAPP <= AppRead;
+ end
+ end
+ AppRead: begin
+ if(DataInEnable == 1'b1) begin
+ if(ReadAppCount == 1) begin
+ StateAPP <= AppIdle;
+ end else begin
+ ReadAppCount <= ReadAppCount -1;
+ end
+ end
+ end
+ endcase
+ end
+ end
+ assign ReadAppByte = (StateAPP == AppRead);
+ assign ReadAppWord = (StateAPP == AppLength);
+ assign ReadAppEnd = ((StateAPP == AppRead) & (DataInEnable == 1'b1) & (ReadAppCount == 1));
+
+ //--------------------------------------------------------------------------
+ // DQT Segment
+ //--------------------------------------------------------------------------
+
+ reg [1:0] StateDQT;
+ reg [15:0] ReadDqtCount;
+ wire ReadDqtByte;
+ wire ReadDqtWord;
+ wire ReadDqtEnd;
+ wire ReadDqtEnable;
+ wire [7:0] ReadDqtData;
+ reg ReadDqtTable;
+
+ parameter DQTIdle = 2'b00;
+ parameter DQTLength = 2'b01;
+ parameter DQTTable = 2'b10;
+ parameter DQTRead = 2'b11;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ StateDQT <= DQTIdle;
+ ReadDqtCount <= 16'h0000;
+ ReadDqtTable <= 1'b0;
+ end else begin
+ case(StateDQT)
+ DQTIdle: begin
+ if(Process == SegDQT) begin
+ StateDQT <= DQTLength;
+ end
+ ReadDqtCount <= 16'h0000;
+ end
+ DQTLength: begin
+ if(DataInEnable == 1'b1) begin
+ StateDQT <= DQTTable;
+ ReadDqtCount <= DataIn[31:16] -2;
+ end
+ end
+ DQTTable: begin
+ if(DataInEnable == 1'b1) begin
+ StateDQT <= DQTRead;
+ ReadDqtTable <= DataIn[24];
+ ReadDqtCount <= 16'd0;
+ end
+ end
+ DQTRead: begin
+ if(DataInEnable == 1'b1) begin
+ if(ReadDqtCount ==63) begin
+ StateDQT <= DQTIdle;
+ end
+ ReadDqtCount <= ReadDqtCount +1;
+ end
+ end
+ endcase
+ end
+ end
+
+ assign ReadDqtEnable = StateDQT == DQTRead;
+ assign ReadDqtData = DataIn[31:24];
+
+ assign ReadDqtByte = StateDQT == DQTRead | StateDQT == DQTTable;
+ assign ReadDqtWord = StateDQT == DQTLength;
+ assign ReadDqtEnd = StateDQT == DQTRead & DataInEnable == 1'b1 & ReadDqtCount ==63;
+
+ //--------------------------------------------------------------------------
+ // DHT Segment
+ //--------------------------------------------------------------------------
+ reg [2:0] StateDHT;
+ reg [15:0] ReadDhtCount;
+ wire ReadDhtByte;
+ wire ReadDhtWord;
+ wire ReadDhtEnd;
+ wire ReadDhtEnable;
+ wire [7:0] ReadDhtData;
+ reg [1:0] ReadDhtTable;
+
+ reg [15:0] HmShift;
+ reg [15:0] HmData;
+ reg [7:0] HmMax;
+ reg [7:0] HmCount;
+ reg HmEnable;
+
+ parameter DHTIdle = 3'h0;
+ parameter DHTLength = 3'h1;
+ parameter DHTTable = 3'h2;
+ parameter DHTMakeHm0 = 3'h3;
+ parameter DHTMakeHm1 = 3'h4;
+ parameter DHTMakeHm2 = 3'h5;
+ parameter DHTReadTable = 3'h6;
+
+ always @(posedge clk or negedge rst)
+ begin
+ if(!rst) begin
+ StateDHT <= DHTIdle;
+ ReadDhtCount <= 16'h0000;
+ ReadDhtTable <= 2'b00;
+ HmEnable <= 1'b0;
+ HmShift <= 16'h8000;
+ HmData <= 16'h0000;
+ HmMax <= 8'h00;
+ HmCount <= 8'h00;
+ end else begin // if (!rst)
+ case(StateDHT)
+ DHTIdle: begin
+ if(Process == SegDHT) begin
+ StateDHT <= DHTLength;
+ end
+ HmEnable <= 1'b0;
+ end
+ DHTLength: begin
+ if(DataInEnable == 1'b1) begin
+ StateDHT <= DHTTable;
+ ReadDhtCount <= DataIn[31:16];
+ end
+ end
+ DHTTable: begin
+ if(DataInEnable == 1'b1) begin
+ StateDHT <= DHTMakeHm0;
+ case(DataIn[31:24])
+ 8'h00: ReadDhtTable <= 2'b00;
+ 8'h10: ReadDhtTable <= 2'b01;
+ 8'h01: ReadDhtTable <= 2'b10;
+ 8'h11: ReadDhtTable <= 2'b11;
+ endcase
+ end
+ HmShift <= 16'h8000;
+ HmData <= 16'h0000;
+ HmMax <= 8'h00;
+ ReadDhtCount <= 0;
+ end // case: DHTTable
+ DHTMakeHm0: begin
+ if(DataInEnable == 1'b1) begin
+ StateDHT <= DHTMakeHm1;
+ HmCount <= DataIn[31:24];
+ end
+ HmEnable <= 1'b0;
+ end
+ DHTMakeHm1: begin
+ StateDHT <= DHTMakeHm2;
+ HmMax <= HmMax + HmCount;
+ end
+ DHTMakeHm2: begin
+ if(HmCount != 0) begin
+ HmData <= HmData + HmShift;
+ HmCount <= HmCount -1;
+ end else begin
+ if(ReadDhtCount == 15) begin
+ StateDHT <= DHTReadTable;
+ HmCount <= 8'h00;
+ //HmMax <= HmMax -1;
+ end else begin
+ HmEnable <= 1'b1;
+ StateDHT <= DHTMakeHm0;
+ ReadDhtCount <= ReadDhtCount +1;
+ end
+ HmShift <= HmShift >> 1;
+ end
+ end
+ DHTReadTable: begin
+ HmEnable <= 1'b0;
+ if(DataInEnable == 1'b1) begin
+ if(HmMax == HmCount +1) begin
+ StateDHT <= DHTIdle;
+ end
+ HmCount <= HmCount +1;
+ end
+ end
+ endcase
+ end
+ end
+
+ assign ReadDhtEnable = StateDHT == DHTReadTable;
+ assign ReadDhtData = DataIn[31:24];
+
+ assign ReadDhtByte = StateDHT == DHTTable | StateDHT == DHTMakeHm0 |
+ StateDHT == DHTReadTable;
+ assign ReadDhtWord = StateDHT == DHTLength;
+ assign ReadDhtEnd = StateDHT == DHTReadTable & DataInEnable == 1'b1 & HmMax == HmCount +1;
+
+ //--------------------------------------------------------------------------
+ // SOS Segment
+ //--------------------------------------------------------------------------
+ reg [3:0] StateSOS;
+ reg [15:0] ReadSosCount;
+ wire ReadSosByte;
+ wire ReadSosWord;
+ wire ReadSosEnd;
+
+ parameter SOSIdle = 4'h0;
+ parameter SOSLength = 4'h1;
+ parameter SOSRead0 = 4'h2;
+ parameter SOSRead1 = 4'h3;
+ parameter SOSRead2 = 4'h4;
+ parameter SOSRead3 = 4'h5;
+ parameter SOSRead4 = 4'h6;
+
+ reg EnableFF00;
+
+ always @(posedge clk or negedge rst)
+ begin
+ if(!rst) begin
+ StateSOS <= SOSIdle;
+ ReadSosCount <= 16'h0000;
+ EnableFF00 <= 1'b0;
+ end else begin
+ case(StateSOS)
+ SOSIdle: begin
+ if(Process == SegSOS) begin
+ StateSOS <= SOSLength;
+ EnableFF00 <= 1'b1;
+ end
+ end
+ SOSLength: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOS <= SOSRead0;
+ ReadSosCount <= DataIn[31:16];
+ end
+ end
+ SOSRead0: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOS <= SOSRead1;
+ ReadSosCount <= {8'h00,DataIn[31:24]};
+ end
+ end
+ SOSRead1: begin
+ if(DataInEnable == 1'b1) begin
+ if(ReadSosCount == 1) begin
+ StateSOS <= SOSRead2;
+ end else begin
+ ReadSosCount <= ReadSosCount -1;
+ end
+ end
+ end
+ SOSRead2: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOS <= SOSRead3;
+ end
+ end
+ SOSRead3: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOS <= SOSRead4;
+ end
+ end
+ SOSRead4: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOS <= SOSIdle;
+ end
+ end
+ endcase
+ end
+ end
+ assign ReadSosByte = StateSOS == SOSRead0 | StateSOS == SOSRead2 | StateSOS == SOSRead3 | StateSOS == SOSRead4;
+ assign ReadSosWord = StateSOS == SOSLength | StateSOS == SOSRead1;
+ assign ReadSosEnd = DataInEnable == 1'b1 & StateSOS == SOSRead4;
+
+ //--------------------------------------------------------------------------
+ // SOF0 Segment
+ //--------------------------------------------------------------------------
+ reg [3:0] StateSOF;
+ reg [15:0] ReadSofCount;
+ wire ReadSofByte;
+ wire ReadSofWord;
+ wire ReadSofEnd;
+
+ reg [15:0] JpegBlockWidth;
+ reg [15:0] JpegBlockHeight;
+
+ parameter SOFIdle = 4'h0;
+ parameter SOFLength = 4'h1;
+ parameter SOFRead0 = 4'h2;
+ parameter SOFReadY = 4'h3;
+ parameter SOFReadX = 4'h4;
+ parameter SOFReadComp = 4'h5;
+ parameter SOFMakeBlock0 = 4'H6;
+ parameter SOFMakeBlock1 = 4'h7;
+
+ always @(posedge clk or negedge rst)
+ begin
+ if(!rst) begin
+ StateSOF <= SOFIdle;
+ ReadSofCount <= 16'h0000;
+ JpegWidth <= 16'h0000;
+ JpegHeight <= 16'h0000;
+ JpegBlockWidth <= 16'h0000;
+ JpegBlockHeight <= 16'h0000;
+ end else begin
+ case(StateSOF)
+ SOFIdle: begin
+ if(Process == SegSOF0) begin
+ StateSOF <= SOFLength;
+ end
+ end
+ SOFLength: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOF <= SOFRead0;
+ ReadSofCount <= DataIn[31:16];
+ end
+ end
+ SOFRead0: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOF <= SOFReadY;
+ end
+ end
+ SOFReadY: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOF <= SOFReadX;
+ JpegHeight <= DataIn[31:16];
+ JpegBlockHeight <= DataIn[31:16];
+ end
+ end
+ SOFReadX: begin
+ if(DataInEnable == 1'b1) begin
+ StateSOF <= SOFReadComp;
+ JpegWidth <= DataIn[31:16];
+ JpegBlockWidth <= DataIn[31:16];
+ ReadSofCount <= 16'h0000;
+ end
+ end
+ SOFReadComp: begin
+ if(DataInEnable == 1'b1) begin
+ if(ReadSofCount == 9) begin
+ StateSOF <= SOFMakeBlock0;
+ end else begin
+ ReadSofCount <= ReadSofCount +1;
+ end
+ end
+ end
+ SOFMakeBlock0:begin
+ StateSOF <= SOFMakeBlock1;
+ JpegBlockWidth <= JpegBlockWidth +15;
+ JpegBlockHeight <= JpegBlockHeight +15;
+ end
+ SOFMakeBlock1:begin
+ StateSOF <= SOFIdle;
+ JpegBlockWidth <= JpegBlockWidth >> 4;
+ JpegBlockHeight <= JpegBlockHeight >> 4;
+ end
+ endcase
+ end
+ end
+ assign ReadSofByte = StateSOF == SOFRead0 | StateSOF == SOFReadComp;
+ assign ReadSofWord = StateSOF == SOFLength | StateSOF == SOFReadX | StateSOF == SOFReadY ;
+ assign ReadSofEnd = StateSOF == SOFMakeBlock1;
+
+ assign OutWidth = JpegWidth;
+ assign OutHeight = JpegHeight;
+ assign OutBlockWidth = JpegBlockWidth[11:0];
+
+ //
+ assign UseByte = DataInEnable == 1'b1 & (StateReadByte | ReadAppByte | ReadDqtByte | ReadDhtByte | ReadSosByte | ReadSofByte) ;
+ assign UseWord = DataInEnable == 1'b1 & (StateReadWord | ReadAppWord | ReadDqtWord | ReadDhtWord | ReadSosWord | ReadSofWord) ;
+ assign ReadSegmentEnd = ReadNopEnd | ReadAppEnd | ReadDqtEnd | ReadDhtEnd | ReadSosEnd | ReadSofEnd ;
+
+ //
+ assign DqtEnable = ReadDqtEnable;
+ assign DqtTable = ReadDqtTable;
+ assign DqtCount = ReadDqtCount[5:0];
+ assign DqtData = ReadDqtData;
+
+ //
+ assign DhtEnable = ReadDhtEnable;
+ assign DhtTable = ReadDhtTable;
+ assign DhtCount = HmCount;
+ assign DhtData = ReadDhtData;
+
+ //
+ assign HaffumanEnable = HmEnable;
+ assign HaffumanTable = ReadDhtTable;
+ assign HaffumanCount = ReadDhtCount[3:0];
+ assign HaffumanData = HmData;
+ assign HaffumanStart = HmMax;
+
+endmodule
Index: djpeg/trunk/src/jpeg_ycbcr_mem.v
===================================================================
--- djpeg/trunk/src/jpeg_ycbcr_mem.v (nonexistent)
+++ djpeg/trunk/src/jpeg_ycbcr_mem.v (revision 6)
@@ -0,0 +1,175 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_ycbcr_mem.v
+// Module Name : jpeg_ycbcr_mem
+// Description : Memory for YCbCr2RGB
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+// 1.02 2006/10/04 remove a WriteData,WriteDataA,WriteDataB wires.
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_ycbcr_mem
+ (
+ clk,
+
+ DataInEnable,
+ DataInColor,
+ DataInPage,
+ DataInCount,
+ Data0In,
+ Data1In,
+
+ DataOutAddress,
+ DataOutY,
+ DataOutCb,
+ DataOutCr
+ );
+
+ input clk;
+
+ input DataInEnable;
+ input [2:0] DataInColor;
+ input [2:0] DataInPage;
+ input [1:0] DataInCount;
+ input [8:0] Data0In;
+ input [8:0] Data1In;
+
+ input [7:0] DataOutAddress;
+ output [8:0] DataOutY;
+ output [8:0] DataOutCb;
+ output [8:0] DataOutCr;
+
+ reg [8:0] MemYA [0:127];
+ reg [8:0] MemYB [0:127];
+ reg [8:0] MemCbA [0:31];
+ reg [8:0] MemCbB [0:31];
+ reg [8:0] MemCrA [0:31];
+ reg [8:0] MemCrB [0:31];
+
+ reg [6:0] WriteAddressA;
+ reg [6:0] WriteAddressB;
+
+ always @(DataInColor or DataInPage or DataInCount) begin
+ WriteAddressA[6] <= DataInColor[1];
+ WriteAddressB[6] <= DataInColor[1];
+ if(DataInColor[2] == 1'b0) begin
+ if(DataInColor[0] == 1'b0) begin
+ case(DataInCount)
+ 2'h0: begin
+ WriteAddressA[5:0] <= DataInPage + 0;
+ WriteAddressB[5:0] <= DataInPage +112 -64;
+ end
+ 2'h1: begin
+ WriteAddressA[5:0] <= DataInPage + 16;
+ WriteAddressB[5:0] <= DataInPage + 96 -64;
+ end
+ 2'h2: begin
+ WriteAddressA[5:0] <= DataInPage + 32;
+ WriteAddressB[5:0] <= DataInPage + 80 -64;
+ end
+ 2'h3: begin
+ WriteAddressA[5:0] <= DataInPage + 48;
+ WriteAddressB[5:0] <= DataInPage + 64 -64;
+ end
+ endcase // case(DataInCount)
+ end else begin // if (DataInColor[0] == 1'b0)
+ case(DataInCount)
+ 2'h0: begin
+ WriteAddressA[5:0] <= DataInPage + 0 +8;
+ WriteAddressB[5:0] <= DataInPage +112 +8 -64;
+ end
+ 2'h1: begin
+ WriteAddressA[5:0] <= DataInPage + 16 +8;
+ WriteAddressB[5:0] <= DataInPage + 96 +8 -64;
+ end
+ 2'h2: begin
+ WriteAddressA[5:0] <= DataInPage + 32 +8;
+ WriteAddressB[5:0] <= DataInPage + 80 +8 -64;
+ end
+ 2'h3: begin
+ WriteAddressA[5:0] <= DataInPage + 48 +8;
+ WriteAddressB[5:0] <= DataInPage + 64 +8 -64;
+ end
+ endcase // case(DataInCount)
+ end // else: !if(DataInColor[0] == 1'b0)
+ end else begin // if (DataInColor[2] == 1'b0)
+ case(DataInCount)
+ 2'h0: begin
+ WriteAddressA[5:0] <= DataInPage + 0;
+ WriteAddressB[5:0] <= DataInPage + 56 -32;
+ end
+ 2'h1: begin
+ WriteAddressA[5:0] <= DataInPage + 8;
+ WriteAddressB[5:0] <= DataInPage + 48 -32;
+ end
+ 2'h2: begin
+ WriteAddressA[5:0] <= DataInPage + 16;
+ WriteAddressB[5:0] <= DataInPage + 40 -32;
+ end
+ 2'h3: begin
+ WriteAddressA[5:0] <= DataInPage + 24;
+ WriteAddressB[5:0] <= DataInPage + 32 -32;
+ end
+ endcase // case(DataInCount)
+ end // else: !if(DataInColor[2] == 1'b0)
+ end // always @ (DataInColor or DataInPage or DataInCount)
+
+ always @(posedge clk) begin
+ if(DataInColor[2] == 1'b0 & DataInEnable == 1'b1) begin
+ MemYA[WriteAddressA] <= Data0In;
+ MemYB[WriteAddressB] <= Data1In;
+ end
+ end
+
+ always @(posedge clk) begin
+ if(DataInColor == 3'b100 & DataInEnable == 1'b1) begin
+ MemCbA[WriteAddressA[4:0]] <= Data0In;
+ MemCbB[WriteAddressB[4:0]] <= Data1In;
+ end
+ end
+
+ always @(posedge clk) begin
+ if(DataInColor == 3'b101 & DataInEnable == 1'b1) begin
+ MemCrA[WriteAddressA[4:0]] <= Data0In;
+ MemCrB[WriteAddressB[4:0]] <= Data1In;
+ end
+ end
+
+ reg [8:0] ReadYA;
+ reg [8:0] ReadYB;
+ reg [8:0] ReadCbA;
+ reg [8:0] ReadCbB;
+ reg [8:0] ReadCrA;
+ reg [8:0] ReadCrB;
+
+ reg [7:0] RegAdrs;
+
+ always @(posedge clk) begin
+ RegAdrs <= DataOutAddress;
+
+ ReadYA <= MemYA[{DataOutAddress[7],DataOutAddress[5:0]}];
+ ReadYB <= MemYB[{DataOutAddress[7],DataOutAddress[5:0]}];
+
+ ReadCbA <= MemCbA[{DataOutAddress[6:5],DataOutAddress[3:1]}];
+ ReadCrA <= MemCrA[{DataOutAddress[6:5],DataOutAddress[3:1]}];
+
+ ReadCbB <= MemCbB[{DataOutAddress[6:5],DataOutAddress[3:1]}];
+ ReadCrB <= MemCrB[{DataOutAddress[6:5],DataOutAddress[3:1]}];
+ end // always @ (posedge clk)
+
+ assign DataOutY = (RegAdrs[6] ==1'b0)?ReadYA:ReadYB;
+ assign DataOutCb = (RegAdrs[7] ==1'b0)?ReadCbA:ReadCbB;
+ assign DataOutCr = (RegAdrs[7] ==1'b0)?ReadCrA:ReadCrB;
+
+endmodule // jpeg_ycbcr_mem
Index: djpeg/trunk/src/jpeg_ziguzagu_reg.v
===================================================================
--- djpeg/trunk/src/jpeg_ziguzagu_reg.v (nonexistent)
+++ djpeg/trunk/src/jpeg_ziguzagu_reg.v (revision 6)
@@ -0,0 +1,519 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_ziguzagu_reg.v
+// Module Name : jpeg_ziguzagu_reg
+// Description : Register for ziguzagu
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_ziguzagu_reg
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInAddress,
+ DataIn,
+
+ Data00Reg,
+ Data01Reg,
+ Data02Reg,
+ Data03Reg,
+ Data04Reg,
+ Data05Reg,
+ Data06Reg,
+ Data07Reg,
+ Data08Reg,
+ Data09Reg,
+ Data10Reg,
+ Data11Reg,
+ Data12Reg,
+ Data13Reg,
+ Data14Reg,
+ Data15Reg,
+ Data16Reg,
+ Data17Reg,
+ Data18Reg,
+ Data19Reg,
+ Data20Reg,
+ Data21Reg,
+ Data22Reg,
+ Data23Reg,
+ Data24Reg,
+ Data25Reg,
+ Data26Reg,
+ Data27Reg,
+ Data28Reg,
+ Data29Reg,
+ Data30Reg,
+ Data31Reg,
+ Data32Reg,
+ Data33Reg,
+ Data34Reg,
+ Data35Reg,
+ Data36Reg,
+ Data37Reg,
+ Data38Reg,
+ Data39Reg,
+ Data40Reg,
+ Data41Reg,
+ Data42Reg,
+ Data43Reg,
+ Data44Reg,
+ Data45Reg,
+ Data46Reg,
+ Data47Reg,
+ Data48Reg,
+ Data49Reg,
+ Data50Reg,
+ Data51Reg,
+ Data52Reg,
+ Data53Reg,
+ Data54Reg,
+ Data55Reg,
+ Data56Reg,
+ Data57Reg,
+ Data58Reg,
+ Data59Reg,
+ Data60Reg,
+ Data61Reg,
+ Data62Reg,
+ Data63Reg
+ );
+
+ input clk;
+ input rst;
+
+ input DataInEnable;
+ input [5:0] DataInAddress;
+ input [15:0] DataIn;
+
+ output [15:0] Data00Reg;
+ output [15:0] Data01Reg;
+ output [15:0] Data02Reg;
+ output [15:0] Data03Reg;
+ output [15:0] Data04Reg;
+ output [15:0] Data05Reg;
+ output [15:0] Data06Reg;
+ output [15:0] Data07Reg;
+ output [15:0] Data08Reg;
+ output [15:0] Data09Reg;
+ output [15:0] Data10Reg;
+ output [15:0] Data11Reg;
+ output [15:0] Data12Reg;
+ output [15:0] Data13Reg;
+ output [15:0] Data14Reg;
+ output [15:0] Data15Reg;
+ output [15:0] Data16Reg;
+ output [15:0] Data17Reg;
+ output [15:0] Data18Reg;
+ output [15:0] Data19Reg;
+ output [15:0] Data20Reg;
+ output [15:0] Data21Reg;
+ output [15:0] Data22Reg;
+ output [15:0] Data23Reg;
+ output [15:0] Data24Reg;
+ output [15:0] Data25Reg;
+ output [15:0] Data26Reg;
+ output [15:0] Data27Reg;
+ output [15:0] Data28Reg;
+ output [15:0] Data29Reg;
+ output [15:0] Data30Reg;
+ output [15:0] Data31Reg;
+ output [15:0] Data32Reg;
+ output [15:0] Data33Reg;
+ output [15:0] Data34Reg;
+ output [15:0] Data35Reg;
+ output [15:0] Data36Reg;
+ output [15:0] Data37Reg;
+ output [15:0] Data38Reg;
+ output [15:0] Data39Reg;
+ output [15:0] Data40Reg;
+ output [15:0] Data41Reg;
+ output [15:0] Data42Reg;
+ output [15:0] Data43Reg;
+ output [15:0] Data44Reg;
+ output [15:0] Data45Reg;
+ output [15:0] Data46Reg;
+ output [15:0] Data47Reg;
+ output [15:0] Data48Reg;
+ output [15:0] Data49Reg;
+ output [15:0] Data50Reg;
+ output [15:0] Data51Reg;
+ output [15:0] Data52Reg;
+ output [15:0] Data53Reg;
+ output [15:0] Data54Reg;
+ output [15:0] Data55Reg;
+ output [15:0] Data56Reg;
+ output [15:0] Data57Reg;
+ output [15:0] Data58Reg;
+ output [15:0] Data59Reg;
+ output [15:0] Data60Reg;
+ output [15:0] Data61Reg;
+ output [15:0] Data62Reg;
+ output [15:0] Data63Reg;
+
+ reg [15:0] RegData [0:63]; // Register Memory
+
+ integer i;
+
+/*
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ RegData[0] <= 16'h0000;
+ RegData[1] <= 16'h0000;
+ RegData[2] <= 16'h0000;
+ RegData[3] <= 16'h0000;
+ RegData[4] <= 16'h0000;
+ RegData[5] <= 16'h0000;
+ RegData[6] <= 16'h0000;
+ RegData[7] <= 16'h0000;
+ RegData[8] <= 16'h0000;
+ RegData[9] <= 16'h0000;
+ RegData[10] <= 16'h0000;
+ RegData[11] <= 16'h0000;
+ RegData[12] <= 16'h0000;
+ RegData[13] <= 16'h0000;
+ RegData[14] <= 16'h0000;
+ RegData[15] <= 16'h0000;
+ RegData[16] <= 16'h0000;
+ RegData[17] <= 16'h0000;
+ RegData[18] <= 16'h0000;
+ RegData[19] <= 16'h0000;
+ RegData[20] <= 16'h0000;
+ RegData[21] <= 16'h0000;
+ RegData[22] <= 16'h0000;
+ RegData[23] <= 16'h0000;
+ RegData[24] <= 16'h0000;
+ RegData[25] <= 16'h0000;
+ RegData[26] <= 16'h0000;
+ RegData[27] <= 16'h0000;
+ RegData[28] <= 16'h0000;
+ RegData[29] <= 16'h0000;
+ RegData[30] <= 16'h0000;
+ RegData[31] <= 16'h0000;
+ RegData[32] <= 16'h0000;
+ RegData[33] <= 16'h0000;
+ RegData[34] <= 16'h0000;
+ RegData[35] <= 16'h0000;
+ RegData[36] <= 16'h0000;
+ RegData[37] <= 16'h0000;
+ RegData[38] <= 16'h0000;
+ RegData[39] <= 16'h0000;
+ RegData[40] <= 16'h0000;
+ RegData[41] <= 16'h0000;
+ RegData[42] <= 16'h0000;
+ RegData[43] <= 16'h0000;
+ RegData[44] <= 16'h0000;
+ RegData[45] <= 16'h0000;
+ RegData[46] <= 16'h0000;
+ RegData[47] <= 16'h0000;
+ RegData[48] <= 16'h0000;
+ RegData[49] <= 16'h0000;
+ RegData[50] <= 16'h0000;
+ RegData[51] <= 16'h0000;
+ RegData[52] <= 16'h0000;
+ RegData[53] <= 16'h0000;
+ RegData[54] <= 16'h0000;
+ RegData[55] <= 16'h0000;
+ RegData[56] <= 16'h0000;
+ RegData[57] <= 16'h0000;
+ RegData[58] <= 16'h0000;
+ RegData[59] <= 16'h0000;
+ RegData[60] <= 16'h0000;
+ RegData[61] <= 16'h0000;
+ RegData[62] <= 16'h0000;
+ RegData[63] <= 16'h0000;
+ end else begin // if (!rst)
+ if(DataInEnable == 1'b1) begin
+ RegData[DataInAddress] <= DataIn;
+ if(DataInAddress == 6'h00) begin
+ for(i=1;i<64;i=i+1) begin
+ RegData[i] <= 16'h0000;
+ end
+ end
+ end
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+*/
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ RegData[0] <= 16'h0000;
+ RegData[1] <= 16'h0000;
+ RegData[2] <= 16'h0000;
+ RegData[3] <= 16'h0000;
+ RegData[4] <= 16'h0000;
+ RegData[5] <= 16'h0000;
+ RegData[6] <= 16'h0000;
+ RegData[7] <= 16'h0000;
+ RegData[8] <= 16'h0000;
+ RegData[9] <= 16'h0000;
+ RegData[10] <= 16'h0000;
+ RegData[11] <= 16'h0000;
+ RegData[12] <= 16'h0000;
+ RegData[13] <= 16'h0000;
+ RegData[14] <= 16'h0000;
+ RegData[15] <= 16'h0000;
+ RegData[16] <= 16'h0000;
+ RegData[17] <= 16'h0000;
+ RegData[18] <= 16'h0000;
+ RegData[19] <= 16'h0000;
+ RegData[20] <= 16'h0000;
+ RegData[21] <= 16'h0000;
+ RegData[22] <= 16'h0000;
+ RegData[23] <= 16'h0000;
+ RegData[24] <= 16'h0000;
+ RegData[25] <= 16'h0000;
+ RegData[26] <= 16'h0000;
+ RegData[27] <= 16'h0000;
+ RegData[28] <= 16'h0000;
+ RegData[29] <= 16'h0000;
+ RegData[30] <= 16'h0000;
+ RegData[31] <= 16'h0000;
+ RegData[32] <= 16'h0000;
+ RegData[33] <= 16'h0000;
+ RegData[34] <= 16'h0000;
+ RegData[35] <= 16'h0000;
+ RegData[36] <= 16'h0000;
+ RegData[37] <= 16'h0000;
+ RegData[38] <= 16'h0000;
+ RegData[39] <= 16'h0000;
+ RegData[40] <= 16'h0000;
+ RegData[41] <= 16'h0000;
+ RegData[42] <= 16'h0000;
+ RegData[43] <= 16'h0000;
+ RegData[44] <= 16'h0000;
+ RegData[45] <= 16'h0000;
+ RegData[46] <= 16'h0000;
+ RegData[47] <= 16'h0000;
+ RegData[48] <= 16'h0000;
+ RegData[49] <= 16'h0000;
+ RegData[50] <= 16'h0000;
+ RegData[51] <= 16'h0000;
+ RegData[52] <= 16'h0000;
+ RegData[53] <= 16'h0000;
+ RegData[54] <= 16'h0000;
+ RegData[55] <= 16'h0000;
+ RegData[56] <= 16'h0000;
+ RegData[57] <= 16'h0000;
+ RegData[58] <= 16'h0000;
+ RegData[59] <= 16'h0000;
+ RegData[60] <= 16'h0000;
+ RegData[61] <= 16'h0000;
+ RegData[62] <= 16'h0000;
+ RegData[63] <= 16'h0000;
+ end else begin
+ if(DataInEnable == 1'b1) begin
+ case(DataInAddress)
+ 6'd0: begin
+ RegData[0] <= DataIn;
+ RegData[1] <= 16'h0000;
+ RegData[2] <= 16'h0000;
+ RegData[3] <= 16'h0000;
+ RegData[4] <= 16'h0000;
+ RegData[5] <= 16'h0000;
+ RegData[6] <= 16'h0000;
+ RegData[7] <= 16'h0000;
+ RegData[8] <= 16'h0000;
+ RegData[9] <= 16'h0000;
+ RegData[10] <= 16'h0000;
+ RegData[11] <= 16'h0000;
+ RegData[12] <= 16'h0000;
+ RegData[13] <= 16'h0000;
+ RegData[14] <= 16'h0000;
+ RegData[15] <= 16'h0000;
+ RegData[16] <= 16'h0000;
+ RegData[17] <= 16'h0000;
+ RegData[18] <= 16'h0000;
+ RegData[19] <= 16'h0000;
+ RegData[20] <= 16'h0000;
+ RegData[21] <= 16'h0000;
+ RegData[22] <= 16'h0000;
+ RegData[23] <= 16'h0000;
+ RegData[24] <= 16'h0000;
+ RegData[25] <= 16'h0000;
+ RegData[26] <= 16'h0000;
+ RegData[27] <= 16'h0000;
+ RegData[28] <= 16'h0000;
+ RegData[29] <= 16'h0000;
+ RegData[30] <= 16'h0000;
+ RegData[31] <= 16'h0000;
+ RegData[32] <= 16'h0000;
+ RegData[33] <= 16'h0000;
+ RegData[34] <= 16'h0000;
+ RegData[35] <= 16'h0000;
+ RegData[36] <= 16'h0000;
+ RegData[37] <= 16'h0000;
+ RegData[38] <= 16'h0000;
+ RegData[39] <= 16'h0000;
+ RegData[40] <= 16'h0000;
+ RegData[41] <= 16'h0000;
+ RegData[42] <= 16'h0000;
+ RegData[43] <= 16'h0000;
+ RegData[44] <= 16'h0000;
+ RegData[45] <= 16'h0000;
+ RegData[46] <= 16'h0000;
+ RegData[47] <= 16'h0000;
+ RegData[48] <= 16'h0000;
+ RegData[49] <= 16'h0000;
+ RegData[50] <= 16'h0000;
+ RegData[51] <= 16'h0000;
+ RegData[52] <= 16'h0000;
+ RegData[53] <= 16'h0000;
+ RegData[54] <= 16'h0000;
+ RegData[55] <= 16'h0000;
+ RegData[56] <= 16'h0000;
+ RegData[57] <= 16'h0000;
+ RegData[58] <= 16'h0000;
+ RegData[59] <= 16'h0000;
+ RegData[60] <= 16'h0000;
+ RegData[61] <= 16'h0000;
+ RegData[62] <= 16'h0000;
+ RegData[63] <= 16'h0000;
+ end
+ 6'd1: RegData[1] <= DataIn;
+ 6'd2: RegData[2] <= DataIn;
+ 6'd3: RegData[3] <= DataIn;
+ 6'd4: RegData[4] <= DataIn;
+ 6'd5: RegData[5] <= DataIn;
+ 6'd6: RegData[6] <= DataIn;
+ 6'd7: RegData[7] <= DataIn;
+ 6'd8: RegData[8] <= DataIn;
+ 6'd9: RegData[9] <= DataIn;
+ 6'd10: RegData[10] <= DataIn;
+ 6'd11: RegData[11] <= DataIn;
+ 6'd12: RegData[12] <= DataIn;
+ 6'd13: RegData[13] <= DataIn;
+ 6'd14: RegData[14] <= DataIn;
+ 6'd15: RegData[15] <= DataIn;
+ 6'd16: RegData[16] <= DataIn;
+ 6'd17: RegData[17] <= DataIn;
+ 6'd18: RegData[18] <= DataIn;
+ 6'd19: RegData[19] <= DataIn;
+ 6'd20: RegData[20] <= DataIn;
+ 6'd21: RegData[21] <= DataIn;
+ 6'd22: RegData[22] <= DataIn;
+ 6'd23: RegData[23] <= DataIn;
+ 6'd24: RegData[24] <= DataIn;
+ 6'd25: RegData[25] <= DataIn;
+ 6'd26: RegData[26] <= DataIn;
+ 6'd27: RegData[27] <= DataIn;
+ 6'd28: RegData[28] <= DataIn;
+ 6'd29: RegData[29] <= DataIn;
+ 6'd30: RegData[30] <= DataIn;
+ 6'd31: RegData[31] <= DataIn;
+ 6'd32: RegData[32] <= DataIn;
+ 6'd33: RegData[33] <= DataIn;
+ 6'd34: RegData[34] <= DataIn;
+ 6'd35: RegData[35] <= DataIn;
+ 6'd36: RegData[36] <= DataIn;
+ 6'd37: RegData[37] <= DataIn;
+ 6'd38: RegData[38] <= DataIn;
+ 6'd39: RegData[39] <= DataIn;
+ 6'd40: RegData[40] <= DataIn;
+ 6'd41: RegData[41] <= DataIn;
+ 6'd42: RegData[42] <= DataIn;
+ 6'd43: RegData[43] <= DataIn;
+ 6'd44: RegData[44] <= DataIn;
+ 6'd45: RegData[45] <= DataIn;
+ 6'd46: RegData[46] <= DataIn;
+ 6'd47: RegData[47] <= DataIn;
+ 6'd48: RegData[48] <= DataIn;
+ 6'd49: RegData[49] <= DataIn;
+ 6'd50: RegData[50] <= DataIn;
+ 6'd51: RegData[51] <= DataIn;
+ 6'd52: RegData[52] <= DataIn;
+ 6'd53: RegData[53] <= DataIn;
+ 6'd54: RegData[54] <= DataIn;
+ 6'd55: RegData[55] <= DataIn;
+ 6'd56: RegData[56] <= DataIn;
+ 6'd57: RegData[57] <= DataIn;
+ 6'd58: RegData[58] <= DataIn;
+ 6'd59: RegData[59] <= DataIn;
+ 6'd60: RegData[60] <= DataIn;
+ 6'd61: RegData[61] <= DataIn;
+ 6'd62: RegData[62] <= DataIn;
+ 6'd63: RegData[63] <= DataIn;
+ endcase
+ end
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign Data00Reg = RegData[00];
+ assign Data01Reg = RegData[01];
+ assign Data08Reg = RegData[02];
+ assign Data16Reg = RegData[03];
+ assign Data09Reg = RegData[04];
+ assign Data02Reg = RegData[05];
+ assign Data03Reg = RegData[06];
+ assign Data10Reg = RegData[07];
+ assign Data17Reg = RegData[08];
+ assign Data24Reg = RegData[09];
+ assign Data32Reg = RegData[10];
+ assign Data25Reg = RegData[11];
+ assign Data18Reg = RegData[12];
+ assign Data11Reg = RegData[13];
+ assign Data04Reg = RegData[14];
+ assign Data05Reg = RegData[15];
+ assign Data12Reg = RegData[16];
+ assign Data19Reg = RegData[17];
+ assign Data26Reg = RegData[18];
+ assign Data33Reg = RegData[19];
+ assign Data40Reg = RegData[20];
+ assign Data48Reg = RegData[21];
+ assign Data41Reg = RegData[22];
+ assign Data34Reg = RegData[23];
+ assign Data27Reg = RegData[24];
+ assign Data20Reg = RegData[25];
+ assign Data13Reg = RegData[26];
+ assign Data06Reg = RegData[27];
+ assign Data07Reg = RegData[28];
+ assign Data14Reg = RegData[29];
+ assign Data21Reg = RegData[30];
+ assign Data28Reg = RegData[31];
+ assign Data35Reg = RegData[32];
+ assign Data42Reg = RegData[33];
+ assign Data49Reg = RegData[34];
+ assign Data56Reg = RegData[35];
+ assign Data57Reg = RegData[36];
+ assign Data50Reg = RegData[37];
+ assign Data43Reg = RegData[38];
+ assign Data36Reg = RegData[39];
+ assign Data29Reg = RegData[40];
+ assign Data22Reg = RegData[41];
+ assign Data15Reg = RegData[42];
+ assign Data23Reg = RegData[43];
+ assign Data30Reg = RegData[44];
+ assign Data37Reg = RegData[45];
+ assign Data44Reg = RegData[46];
+ assign Data51Reg = RegData[47];
+ assign Data58Reg = RegData[48];
+ assign Data59Reg = RegData[49];
+ assign Data52Reg = RegData[50];
+ assign Data45Reg = RegData[51];
+ assign Data38Reg = RegData[52];
+ assign Data31Reg = RegData[53];
+ assign Data39Reg = RegData[54];
+ assign Data46Reg = RegData[55];
+ assign Data53Reg = RegData[56];
+ assign Data60Reg = RegData[57];
+ assign Data61Reg = RegData[58];
+ assign Data54Reg = RegData[59];
+ assign Data47Reg = RegData[60];
+ assign Data55Reg = RegData[61];
+ assign Data62Reg = RegData[62];
+ assign Data63Reg = RegData[63];
+
+endmodule // jpeg_ziguzagu_reg
Index: djpeg/trunk/src/jpeg_ycbcr2rgb.v
===================================================================
--- djpeg/trunk/src/jpeg_ycbcr2rgb.v (nonexistent)
+++ djpeg/trunk/src/jpeg_ycbcr2rgb.v (revision 6)
@@ -0,0 +1,245 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_ycbcr2rgb.v
+// Module Name : jpeg_ycbcr2rgb
+// Description : YCbCr2RGB
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+//----------------------------------------------------------------------------
+// JPEG YCbCr -> RGB Conveter
+//----------------------------------------------------------------------------
+module jpeg_ycbcbr2rgb
+ (
+ rst,
+ clk,
+
+ InEnable,
+ InBlockX,
+ InBlockY,
+ InIdle,
+ InBank,
+ InAddress,
+ InY,
+ InCb,
+ InCr,
+
+ OutEnable,
+ OutPixelX,
+ OutPixelY,
+ OutR,
+ OutG,
+ OutB
+ );
+
+ input clk;
+ input rst;
+
+ input InEnable;
+ input [11:0] InBlockX;
+ input [11:0] InBlockY;
+ output InIdle;
+ output InBank;
+ output [7:0] InAddress;
+ input [8:0] InY;
+ input [8:0] InCb;
+ input [8:0] InCr;
+
+ output OutEnable;
+ output [15:0] OutPixelX;
+ output [15:0] OutPixelY;
+ output [7:0] OutR;
+ output [7:0] OutG;
+ output [7:0] OutB;
+
+ reg RunActive;
+ reg [7:0] RunCount;
+ reg [11:0] RunBlockX;
+ reg [11:0] RunBlockY;
+ reg RunBank;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ RunActive <= 1'b0;
+ RunBank <= 1'b0;
+ RunCount <= 8'h00;
+ RunBlockX <= 12'h000;
+ RunBlockY <= 12'h000;
+ end else begin
+ if(RunActive == 1'b0) begin
+ if(InEnable == 1'b1) begin
+ RunActive <= 1'b1;
+ RunBlockX <= InBlockX;
+ RunBlockY <= InBlockY;
+ end
+ RunCount <= 8'h00;
+ end else begin
+ if(RunCount == 8'hFF) begin
+ RunActive <= 1'b0;
+ RunBank <= ~RunBank;
+ RunCount <= 8'h00;
+ end else begin
+ RunCount <= RunCount +1;
+ end
+ end // else: !if(RunActive == 1'b0)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign InIdle = RunActive == 1'b0 | (RunActive == 1'b1 & RunCount == 8'hFF);
+ assign InAddress = RunCount;
+ assign InBank = RunBank;
+
+ reg PreEnable;
+ reg [15:0] PreCountX;
+ reg [15:0] PreCountY;
+ reg Phase0Enable;
+ reg [15:0] Phase0CountX;
+ reg [15:0] Phase0CountY;
+ reg Phase1Enable;
+ reg [15:0] Phase1CountX;
+ reg [15:0] Phase1CountY;
+ reg Phase2Enable;
+ reg [15:0] Phase2CountX;
+ reg [15:0] Phase2CountY;
+ reg Phase3Enable;
+ reg [15:0] Phase3CountX;
+ reg [15:0] Phase3CountY;
+
+ reg signed [31:0] rgb00r;
+ reg signed [31:0] r00r;
+ reg signed [31:0] g00r;
+ reg signed [31:0] g01r;
+ reg signed [31:0] b00r;
+ reg signed [31:0] r10r;
+ reg signed [31:0] g10r;
+ reg signed [31:0] g11r;
+ reg signed [31:0] b10r;
+ reg signed [31:0] r20r;
+ reg signed [31:0] g20r;
+ reg signed [31:0] b20r;
+
+ wire signed [8:0] DataY;
+ wire signed [8:0] DataCb;
+ wire signed [8:0] DataCr;
+
+ reg signed [8:0] Phase0Y;
+ reg signed [8:0] Phase0Cb;
+ reg signed [8:0] Phase0Cr;
+
+ wire signed [19:0] C_RR = 20'h59BA5; // R_Cr: 1.402 * 0x4000
+ wire signed [19:0] C_GB = 20'h16066; // G_Cb: 0.34414 * 0x4000
+ wire signed [19:0] C_GR = 20'h2DB47; // G_Cr: 0.71414 * 0x4000
+ wire signed [19:0] C_BB = 20'h71687; // B_Cb: 1.772 * 0x4000
+
+ assign DataY = InY;
+ assign DataCb = InCb;
+ assign DataCr = InCr;
+
+ reg signed [8:0] Phase1Y,Phase1Cb,Phase1Cr;
+ reg signed [8:0] Phase2Y,Phase2Cb,Phase2Cr;
+ reg signed [8:0] Phase3Y,Phase3Cb,Phase3Cr;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ rgb00r <= 0;
+ r00r <= 0;
+ g00r <= 0;
+ g01r <= 0;
+ b00r <= 0;
+
+ r10r <= 0;
+ g10r <= 0;
+ g11r <= 0;
+ b10r <= 0;
+
+ r20r <= 0;
+ g20r <= 0;
+ b20r <= 0;
+
+ Phase0Enable <= 1'b0;
+ Phase0CountX <= 16'h0000;
+ Phase0CountY <= 16'h0000;
+ Phase1Enable <= 1'b0;
+ Phase1CountX <= 16'h0000;
+ Phase1CountY <= 16'h0000;
+ Phase2Enable <= 1'b0;
+ Phase2CountX <= 16'h0000;
+ Phase2CountY <= 16'h0000;
+ Phase3Enable <= 1'b0;
+ Phase3CountX <= 16'h0000;
+ Phase3CountY <= 16'h0000;
+ end else begin // if (!rst)
+ // Pre
+ PreEnable <= RunActive;
+ PreCountX <= {RunBlockX,RunCount[3:0]};
+ PreCountY <= {RunBlockY,RunCount[7:4]};
+ // Phase0
+ Phase0Enable <= PreEnable;
+ Phase0CountX <= PreCountX;
+ Phase0CountY <= PreCountY;
+ Phase0Y <= DataY;
+ Phase0Cb <= DataCb;
+ Phase0Cr <= DataCr;
+ // Phase1
+ Phase1Enable <= Phase0Enable;
+ Phase1CountX <= Phase0CountX;
+ Phase1CountY <= Phase0CountY;
+ rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};
+ r00r <= Phase0Cr * C_RR;
+ g00r <= Phase0Cb * C_GB;
+ g01r <= Phase0Cr * C_GR;
+ b00r <= Phase0Cb * C_BB;
+
+ Phase1Y <= Phase0Y;
+ Phase1Cb <= Phase0Cb;
+ Phase1Cr <= Phase0Cr;
+
+
+ // Phase2
+ Phase2Enable <= Phase1Enable;
+ Phase2CountX <= Phase1CountX;
+ Phase2CountY <= Phase1CountY;
+ r10r <= rgb00r + r00r;
+ g10r <= rgb00r - g00r;
+ g11r <= g01r;
+ b10r <= rgb00r + b00r;
+
+ Phase2Y <= Phase1Y;
+ Phase2Cb <= Phase1Cb;
+ Phase2Cr <= Phase1Cr;
+
+ // Phase3
+ Phase3Enable <= Phase2Enable;
+ Phase3CountX <= Phase2CountX;
+ Phase3CountY <= Phase2CountY;
+ r20r <= r10r;
+ g20r <= g10r - g11r;
+ b20r <= b10r;
+
+ Phase3Y <= Phase2Y;
+ Phase3Cb <= Phase2Cb;
+ Phase3Cr <= Phase2Cr;
+
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign OutEnable = Phase3Enable;
+ assign OutPixelX = Phase3CountX;
+ assign OutPixelY = Phase3CountY;
+ assign OutR = (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];
+ assign OutG = (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];
+ assign OutB = (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];
+
+endmodule // jpeg_ycbcbr2rgb
Index: djpeg/trunk/src/jpeg_idct.v
===================================================================
--- djpeg/trunk/src/jpeg_idct.v (nonexistent)
+++ djpeg/trunk/src/jpeg_idct.v (revision 6)
@@ -0,0 +1,505 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_idct.v
+// Module Name : jpeg_idct
+// Description : iDCT top module
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_idct
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInSel,
+ Data00In,
+ Data01In,
+ Data02In,
+ Data03In,
+ Data04In,
+ Data05In,
+ Data06In,
+ Data07In,
+ Data08In,
+ Data09In,
+ Data10In,
+ Data11In,
+ Data12In,
+ Data13In,
+ Data14In,
+ Data15In,
+ Data16In,
+ Data17In,
+ Data18In,
+ Data19In,
+ Data20In,
+ Data21In,
+ Data22In,
+ Data23In,
+ Data24In,
+ Data25In,
+ Data26In,
+ Data27In,
+ Data28In,
+ Data29In,
+ Data30In,
+ Data31In,
+ Data32In,
+ Data33In,
+ Data34In,
+ Data35In,
+ Data36In,
+ Data37In,
+ Data38In,
+ Data39In,
+ Data40In,
+ Data41In,
+ Data42In,
+ Data43In,
+ Data44In,
+ Data45In,
+ Data46In,
+ Data47In,
+ Data48In,
+ Data49In,
+ Data50In,
+ Data51In,
+ Data52In,
+ Data53In,
+ Data54In,
+ Data55In,
+ Data56In,
+ Data57In,
+ Data58In,
+ Data59In,
+ Data60In,
+ Data61In,
+ Data62In,
+ Data63In,
+ DataInIdle,
+ DataInRelease,
+
+ DataOutEnable,
+ DataOutPage,
+ DataOutCount,
+ Data0Out,
+ Data1Out
+ );
+
+ input rst;
+ input clk;
+
+ input DataInEnable;
+ output DataInSel;
+ input [15:0] Data00In;
+ input [15:0] Data01In;
+ input [15:0] Data02In;
+ input [15:0] Data03In;
+ input [15:0] Data04In;
+ input [15:0] Data05In;
+ input [15:0] Data06In;
+ input [15:0] Data07In;
+ input [15:0] Data08In;
+ input [15:0] Data09In;
+ input [15:0] Data10In;
+ input [15:0] Data11In;
+ input [15:0] Data12In;
+ input [15:0] Data13In;
+ input [15:0] Data14In;
+ input [15:0] Data15In;
+ input [15:0] Data16In;
+ input [15:0] Data17In;
+ input [15:0] Data18In;
+ input [15:0] Data19In;
+ input [15:0] Data20In;
+ input [15:0] Data21In;
+ input [15:0] Data22In;
+ input [15:0] Data23In;
+ input [15:0] Data24In;
+ input [15:0] Data25In;
+ input [15:0] Data26In;
+ input [15:0] Data27In;
+ input [15:0] Data28In;
+ input [15:0] Data29In;
+ input [15:0] Data30In;
+ input [15:0] Data31In;
+ input [15:0] Data32In;
+ input [15:0] Data33In;
+ input [15:0] Data34In;
+ input [15:0] Data35In;
+ input [15:0] Data36In;
+ input [15:0] Data37In;
+ input [15:0] Data38In;
+ input [15:0] Data39In;
+ input [15:0] Data40In;
+ input [15:0] Data41In;
+ input [15:0] Data42In;
+ input [15:0] Data43In;
+ input [15:0] Data44In;
+ input [15:0] Data45In;
+ input [15:0] Data46In;
+ input [15:0] Data47In;
+ input [15:0] Data48In;
+ input [15:0] Data49In;
+ input [15:0] Data50In;
+ input [15:0] Data51In;
+ input [15:0] Data52In;
+ input [15:0] Data53In;
+ input [15:0] Data54In;
+ input [15:0] Data55In;
+ input [15:0] Data56In;
+ input [15:0] Data57In;
+ input [15:0] Data58In;
+ input [15:0] Data59In;
+ input [15:0] Data60In;
+ input [15:0] Data61In;
+ input [15:0] Data62In;
+ input [15:0] Data63In;
+ output DataInIdle;
+ output DataInRelease;
+
+ output DataOutEnable;
+ output [2:0] DataOutPage;
+ output [1:0] DataOutCount;
+ output [8:0] Data0Out;
+ output [8:0] Data1Out;
+
+ wire DctXEnable;
+ wire [2:0] DctXPage;
+ wire [1:0] DctXCount;
+ wire [15:0] DctXData0r;
+ wire [15:0] DctXData1r;
+
+ wire DctBBank;
+ wire DctBIdle;
+
+ jpeg_idctx u_jpeg_idctx(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable( DataInEnable ),
+ .DataInSel( DataInSel ),
+ .Data00In( Data00In ),
+ .Data01In( Data01In ),
+ .Data02In( Data02In ),
+ .Data03In( Data03In ),
+ .Data04In( Data04In ),
+ .Data05In( Data05In ),
+ .Data06In( Data06In ),
+ .Data07In( Data07In ),
+ .Data08In( Data08In ),
+ .Data09In( Data09In ),
+ .Data10In( Data10In ),
+ .Data11In( Data11In ),
+ .Data12In( Data12In ),
+ .Data13In( Data13In ),
+ .Data14In( Data14In ),
+ .Data15In( Data15In ),
+ .Data16In( Data16In ),
+ .Data17In( Data17In ),
+ .Data18In( Data18In ),
+ .Data19In( Data19In ),
+ .Data20In( Data20In ),
+ .Data21In( Data21In ),
+ .Data22In( Data22In ),
+ .Data23In( Data23In ),
+ .Data24In( Data24In ),
+ .Data25In( Data25In ),
+ .Data26In( Data26In ),
+ .Data27In( Data27In ),
+ .Data28In( Data28In ),
+ .Data29In( Data29In ),
+ .Data30In( Data30In ),
+ .Data31In( Data31In ),
+ .Data32In( Data32In ),
+ .Data33In( Data33In ),
+ .Data34In( Data34In ),
+ .Data35In( Data35In ),
+ .Data36In( Data36In ),
+ .Data37In( Data37In ),
+ .Data38In( Data38In ),
+ .Data39In( Data39In ),
+ .Data40In( Data40In ),
+ .Data41In( Data41In ),
+ .Data42In( Data42In ),
+ .Data43In( Data43In ),
+ .Data44In( Data44In ),
+ .Data45In( Data45In ),
+ .Data46In( Data46In ),
+ .Data47In( Data47In ),
+ .Data48In( Data48In ),
+ .Data49In( Data49In ),
+ .Data50In( Data50In ),
+ .Data51In( Data51In ),
+ .Data52In( Data52In ),
+ .Data53In( Data53In ),
+ .Data54In( Data54In ),
+ .Data55In( Data55In ),
+ .Data56In( Data56In ),
+ .Data57In( Data57In ),
+ .Data58In( Data58In ),
+ .Data59In( Data59In ),
+ .Data60In( Data60In ),
+ .Data61In( Data61In ),
+ .Data62In( Data62In ),
+ .Data63In( Data63In ),
+ .DataInIdle( DataInIdle),
+ .DataInRelease( DataInRelease ),
+
+ .DataOutIdle ( DctBIdle ),
+ .DataOutEnable ( DctXEnable ),
+ .DataOutPage ( DctXPage ),
+ .DataOutCount ( DctXCount ),
+ .Data0Out ( DctXData0r ),
+ .Data1Out ( DctXData1r )
+ );
+
+ wire [15:0] DctB00r;
+ wire [15:0] DctB01r;
+ wire [15:0] DctB02r;
+ wire [15:0] DctB03r;
+ wire [15:0] DctB04r;
+ wire [15:0] DctB05r;
+ wire [15:0] DctB06r;
+ wire [15:0] DctB07r;
+ wire [15:0] DctB08r;
+ wire [15:0] DctB09r;
+ wire [15:0] DctB10r;
+ wire [15:0] DctB11r;
+ wire [15:0] DctB12r;
+ wire [15:0] DctB13r;
+ wire [15:0] DctB14r;
+ wire [15:0] DctB15r;
+ wire [15:0] DctB16r;
+ wire [15:0] DctB17r;
+ wire [15:0] DctB18r;
+ wire [15:0] DctB19r;
+ wire [15:0] DctB20r;
+ wire [15:0] DctB21r;
+ wire [15:0] DctB22r;
+ wire [15:0] DctB23r;
+ wire [15:0] DctB24r;
+ wire [15:0] DctB25r;
+ wire [15:0] DctB26r;
+ wire [15:0] DctB27r;
+ wire [15:0] DctB28r;
+ wire [15:0] DctB29r;
+ wire [15:0] DctB30r;
+ wire [15:0] DctB31r;
+ wire [15:0] DctB32r;
+ wire [15:0] DctB33r;
+ wire [15:0] DctB34r;
+ wire [15:0] DctB35r;
+ wire [15:0] DctB36r;
+ wire [15:0] DctB37r;
+ wire [15:0] DctB38r;
+ wire [15:0] DctB39r;
+ wire [15:0] DctB40r;
+ wire [15:0] DctB41r;
+ wire [15:0] DctB42r;
+ wire [15:0] DctB43r;
+ wire [15:0] DctB44r;
+ wire [15:0] DctB45r;
+ wire [15:0] DctB46r;
+ wire [15:0] DctB47r;
+ wire [15:0] DctB48r;
+ wire [15:0] DctB49r;
+ wire [15:0] DctB50r;
+ wire [15:0] DctB51r;
+ wire [15:0] DctB52r;
+ wire [15:0] DctB53r;
+ wire [15:0] DctB54r;
+ wire [15:0] DctB55r;
+ wire [15:0] DctB56r;
+ wire [15:0] DctB57r;
+ wire [15:0] DctB58r;
+ wire [15:0] DctB59r;
+ wire [15:0] DctB60r;
+ wire [15:0] DctB61r;
+ wire [15:0] DctB62r;
+ wire [15:0] DctB63r;
+
+ wire DctBReleaseA;
+ wire DctBReleaseB;
+ wire DctBRelease;
+
+ jpeg_idctb u_jpeg_idctb(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable ( DctXEnable ),
+ .DataInPage ( DctXPage ),
+ .DataInCount ( DctXCount ),
+ .DataInIdle ( DctBIdle ),
+ .Data0In ( DctXData0r ),
+ .Data1In ( DctXData1r ),
+
+ .DataOutEnable ( DctBEnable ),
+ .DataOutSel( DctBSel),
+ .Data00Out( DctB00r ),
+ .Data01Out( DctB01r ),
+ .Data02Out( DctB02r ),
+ .Data03Out( DctB03r ),
+ .Data04Out( DctB04r ),
+ .Data05Out( DctB05r ),
+ .Data06Out( DctB06r ),
+ .Data07Out( DctB07r ),
+ .Data08Out( DctB08r ),
+ .Data09Out( DctB09r ),
+ .Data10Out( DctB10r ),
+ .Data11Out( DctB11r ),
+ .Data12Out( DctB12r ),
+ .Data13Out( DctB13r ),
+ .Data14Out( DctB14r ),
+ .Data15Out( DctB15r ),
+ .Data16Out( DctB16r ),
+ .Data17Out( DctB17r ),
+ .Data18Out( DctB18r ),
+ .Data19Out( DctB19r ),
+ .Data20Out( DctB20r ),
+ .Data21Out( DctB21r ),
+ .Data22Out( DctB22r ),
+ .Data23Out( DctB23r ),
+ .Data24Out( DctB24r ),
+ .Data25Out( DctB25r ),
+ .Data26Out( DctB26r ),
+ .Data27Out( DctB27r ),
+ .Data28Out( DctB28r ),
+ .Data29Out( DctB29r ),
+ .Data30Out( DctB30r ),
+ .Data31Out( DctB31r ),
+ .Data32Out( DctB32r ),
+ .Data33Out( DctB33r ),
+ .Data34Out( DctB34r ),
+ .Data35Out( DctB35r ),
+ .Data36Out( DctB36r ),
+ .Data37Out( DctB37r ),
+ .Data38Out( DctB38r ),
+ .Data39Out( DctB39r ),
+ .Data40Out( DctB40r ),
+ .Data41Out( DctB41r ),
+ .Data42Out( DctB42r ),
+ .Data43Out( DctB43r ),
+ .Data44Out( DctB44r ),
+ .Data45Out( DctB45r ),
+ .Data46Out( DctB46r ),
+ .Data47Out( DctB47r ),
+ .Data48Out( DctB48r ),
+ .Data49Out( DctB49r ),
+ .Data50Out( DctB50r ),
+ .Data51Out( DctB51r ),
+ .Data52Out( DctB52r ),
+ .Data53Out( DctB53r ),
+ .Data54Out( DctB54r ),
+ .Data55Out( DctB55r ),
+ .Data56Out( DctB56r ),
+ .Data57Out( DctB57r ),
+ .Data58Out( DctB58r ),
+ .Data59Out( DctB59r ),
+ .Data60Out( DctB60r ),
+ .Data61Out( DctB61r ),
+ .Data62Out( DctB62r ),
+ .Data63Out( DctB63r ),
+
+ .BankARelease( DctBReleaseA ),
+ .BankBRelease( DctBReleaseB )
+ );
+
+ assign DctBReleaseA = DctBSel == 1'b0 & DctBRelease;
+ assign DctBReleaseB = DctBSel == 1'b1 & DctBRelease;
+
+ jpeg_idcty u_jpeg_idcty(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable(DctBEnable),
+ .DataInBank(DctBBank),
+ .DataInSel(DctBSel),
+ .Data00In( DctB00r ),
+ .Data01In( DctB01r ),
+ .Data02In( DctB02r ),
+ .Data03In( DctB03r ),
+ .Data04In( DctB04r ),
+ .Data05In( DctB05r ),
+ .Data06In( DctB06r ),
+ .Data07In( DctB07r ),
+ .Data08In( DctB08r ),
+ .Data09In( DctB09r ),
+ .Data10In( DctB10r ),
+ .Data11In( DctB11r ),
+ .Data12In( DctB12r ),
+ .Data13In( DctB13r ),
+ .Data14In( DctB14r ),
+ .Data15In( DctB15r ),
+ .Data16In( DctB16r ),
+ .Data17In( DctB17r ),
+ .Data18In( DctB18r ),
+ .Data19In( DctB19r ),
+ .Data20In( DctB20r ),
+ .Data21In( DctB21r ),
+ .Data22In( DctB22r ),
+ .Data23In( DctB23r ),
+ .Data24In( DctB24r ),
+ .Data25In( DctB25r ),
+ .Data26In( DctB26r ),
+ .Data27In( DctB27r ),
+ .Data28In( DctB28r ),
+ .Data29In( DctB29r ),
+ .Data30In( DctB30r ),
+ .Data31In( DctB31r ),
+ .Data32In( DctB32r ),
+ .Data33In( DctB33r ),
+ .Data34In( DctB34r ),
+ .Data35In( DctB35r ),
+ .Data36In( DctB36r ),
+ .Data37In( DctB37r ),
+ .Data38In( DctB38r ),
+ .Data39In( DctB39r ),
+ .Data40In( DctB40r ),
+ .Data41In( DctB41r ),
+ .Data42In( DctB42r ),
+ .Data43In( DctB43r ),
+ .Data44In( DctB44r ),
+ .Data45In( DctB45r ),
+ .Data46In( DctB46r ),
+ .Data47In( DctB47r ),
+ .Data48In( DctB48r ),
+ .Data49In( DctB49r ),
+ .Data50In( DctB50r ),
+ .Data51In( DctB51r ),
+ .Data52In( DctB52r ),
+ .Data53In( DctB53r ),
+ .Data54In( DctB54r ),
+ .Data55In( DctB55r ),
+ .Data56In( DctB56r ),
+ .Data57In( DctB57r ),
+ .Data58In( DctB58r ),
+ .Data59In( DctB59r ),
+ .Data60In( DctB60r ),
+ .Data61In( DctB61r ),
+ .Data62In( DctB62r ),
+ .Data63In( DctB63r ),
+ .DataInIdle( DctYIdle ),
+ .DataInRelease( DctBRelease),
+
+ .DataOutEnable ( DataOutEnable ),
+ .DataOutPage ( DataOutPage ),
+ .DataOutCount ( DataOutCount ),
+ .Data0Out ( Data0Out ),
+ .Data1Out ( Data1Out )
+ );
+
+endmodule // jpeg_idct
Index: djpeg/trunk/src/jpeg_haffuman.v
===================================================================
--- djpeg/trunk/src/jpeg_haffuman.v (nonexistent)
+++ djpeg/trunk/src/jpeg_haffuman.v (revision 6)
@@ -0,0 +1,404 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_haffuman.v
+// Module Name : jpeg_haffuman
+// Description : Haffuam top module
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_haffuman
+ (
+ rst,
+ clk,
+
+ // DQT Table
+ DqtInEnable,
+ DqtInColor,
+ DqtInCount,
+ DqtInData,
+
+ // DHT Table
+ DhtInEnable,
+ DhtInColor,
+ DhtInCount,
+ DhtInData,
+
+ // Haffuman Table
+ HaffumanTableEnable, // Table Data In Enable
+ HaffumanTableColor, // Haffuman Table Color Number
+ HaffumanTableCount, // Table Number
+ HaffumanTableCode, // Haffuman Table Code
+ HaffumanTableStart, // Haffuman Table Start Number
+
+ // Haffuman Decode
+ DataInRun, // Data In Start
+ DataInEnable, // Data In Enable
+ DataIn, // Data In
+
+ DecodeUseBit, // Used Data Bit
+ DecodeUseWidth, // Used Data Width
+
+ // Data Out
+ DataOutIdle,
+ DataOutEnable,
+ DataOutColor,
+ DataOutSel,
+ Data00Reg,
+ Data01Reg,
+ Data02Reg,
+ Data03Reg,
+ Data04Reg,
+ Data05Reg,
+ Data06Reg,
+ Data07Reg,
+ Data08Reg,
+ Data09Reg,
+ Data10Reg,
+ Data11Reg,
+ Data12Reg,
+ Data13Reg,
+ Data14Reg,
+ Data15Reg,
+ Data16Reg,
+ Data17Reg,
+ Data18Reg,
+ Data19Reg,
+ Data20Reg,
+ Data21Reg,
+ Data22Reg,
+ Data23Reg,
+ Data24Reg,
+ Data25Reg,
+ Data26Reg,
+ Data27Reg,
+ Data28Reg,
+ Data29Reg,
+ Data30Reg,
+ Data31Reg,
+ Data32Reg,
+ Data33Reg,
+ Data34Reg,
+ Data35Reg,
+ Data36Reg,
+ Data37Reg,
+ Data38Reg,
+ Data39Reg,
+ Data40Reg,
+ Data41Reg,
+ Data42Reg,
+ Data43Reg,
+ Data44Reg,
+ Data45Reg,
+ Data46Reg,
+ Data47Reg,
+ Data48Reg,
+ Data49Reg,
+ Data50Reg,
+ Data51Reg,
+ Data52Reg,
+ Data53Reg,
+ Data54Reg,
+ Data55Reg,
+ Data56Reg,
+ Data57Reg,
+ Data58Reg,
+ Data59Reg,
+ Data60Reg,
+ Data61Reg,
+ Data62Reg,
+ Data63Reg,
+ DataOutRelease
+
+ );
+
+ input rst;
+ input clk;
+
+ // DQT Table
+ input DqtInEnable;
+ input DqtInColor;
+ input [5:0] DqtInCount;
+ input [7:0] DqtInData;
+
+ // DHT Table
+ input DhtInEnable;
+ input [1:0] DhtInColor;
+ input [7:0] DhtInCount;
+ input [7:0] DhtInData;
+
+ input HaffumanTableEnable; // Table Data In Enable
+ input [1:0] HaffumanTableColor;
+ input [3:0] HaffumanTableCount; // Table Number
+ input [15:0] HaffumanTableCode; // Haffuman Table Data
+ input [7:0] HaffumanTableStart; // Haffuman Table Start Number
+
+ input DataInRun;
+ input DataInEnable; // Data In Enable
+ input [31:0] DataIn; // Data In
+
+ output DecodeUseBit;
+ output [6:0] DecodeUseWidth;
+
+ // Data Out
+ input DataOutIdle;
+ output DataOutEnable;
+ output [2:0] DataOutColor;
+ input DataOutSel;
+ output [15:0] Data00Reg;
+ output [15:0] Data01Reg;
+ output [15:0] Data02Reg;
+ output [15:0] Data03Reg;
+ output [15:0] Data04Reg;
+ output [15:0] Data05Reg;
+ output [15:0] Data06Reg;
+ output [15:0] Data07Reg;
+ output [15:0] Data08Reg;
+ output [15:0] Data09Reg;
+ output [15:0] Data10Reg;
+ output [15:0] Data11Reg;
+ output [15:0] Data12Reg;
+ output [15:0] Data13Reg;
+ output [15:0] Data14Reg;
+ output [15:0] Data15Reg;
+ output [15:0] Data16Reg;
+ output [15:0] Data17Reg;
+ output [15:0] Data18Reg;
+ output [15:0] Data19Reg;
+ output [15:0] Data20Reg;
+ output [15:0] Data21Reg;
+ output [15:0] Data22Reg;
+ output [15:0] Data23Reg;
+ output [15:0] Data24Reg;
+ output [15:0] Data25Reg;
+ output [15:0] Data26Reg;
+ output [15:0] Data27Reg;
+ output [15:0] Data28Reg;
+ output [15:0] Data29Reg;
+ output [15:0] Data30Reg;
+ output [15:0] Data31Reg;
+ output [15:0] Data32Reg;
+ output [15:0] Data33Reg;
+ output [15:0] Data34Reg;
+ output [15:0] Data35Reg;
+ output [15:0] Data36Reg;
+ output [15:0] Data37Reg;
+ output [15:0] Data38Reg;
+ output [15:0] Data39Reg;
+ output [15:0] Data40Reg;
+ output [15:0] Data41Reg;
+ output [15:0] Data42Reg;
+ output [15:0] Data43Reg;
+ output [15:0] Data44Reg;
+ output [15:0] Data45Reg;
+ output [15:0] Data46Reg;
+ output [15:0] Data47Reg;
+ output [15:0] Data48Reg;
+ output [15:0] Data49Reg;
+ output [15:0] Data50Reg;
+ output [15:0] Data51Reg;
+ output [15:0] Data52Reg;
+ output [15:0] Data53Reg;
+ output [15:0] Data54Reg;
+ output [15:0] Data55Reg;
+ output [15:0] Data56Reg;
+ output [15:0] Data57Reg;
+ output [15:0] Data58Reg;
+ output [15:0] Data59Reg;
+ output [15:0] Data60Reg;
+ output [15:0] Data61Reg;
+ output [15:0] Data62Reg;
+ output [15:0] Data63Reg;
+ input DataOutRelease;
+
+ wire HmDqtColor;
+ wire [5:0] HmDqtNumber;
+ wire [7:0] HmDqtData;
+
+ // DQT Table
+ jpeg_dqt u_jpeg_dqt(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable ( DqtInEnable ),
+ .DataInColor ( DqtInColor ),
+ .DataInCount ( DqtInCount[5:0] ),
+ .DataIn ( DqtInData ),
+
+ .TableColor ( HmDqtColor ),
+ .TableNumber ( HmDqtNumber ),
+ .TableData ( HmDqtData )
+ );
+
+ wire [1:0] HmDhtColor;
+ wire [7:0] HmDhtNumber;
+ wire [3:0] HmDhtZero;
+ wire [3:0] HmDhtWidth;
+
+ jpeg_dht u_jpeg_dht(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable ( DhtInEnable ),
+ .DataInColor ( DhtInColor ),
+ .DataInCount ( DhtInCount ),
+ .DataIn ( DhtInData ),
+
+ .ColorNumber ( HmDhtColor ),
+ .TableNumber ( HmDhtNumber ),
+ .ZeroTable ( HmDhtZero ),
+ .WidhtTable ( HmDhtWidth )
+ );
+
+ //wire [2:0] HmDecColor;
+ wire [5:0] HmDecCount;
+ wire [15:0] HmDecData;
+
+ wire HmOutEnable;
+ wire [2:0] HmOutColor;
+
+ jpeg_hm_decode u_jpeg_hm_decode(
+ .rst(rst),
+ .clk(clk),
+
+ // Haffuman Table
+ .HaffumanTableEnable ( HaffumanTableEnable ),
+ .HaffumanTableColor ( HaffumanTableColor ),
+ .HaffumanTableCount ( HaffumanTableCount ),
+ .HaffumanTableCode ( HaffumanTableCode ),
+ .HaffumanTableStart ( HaffumanTableStart ),
+
+ // Haffuman Decode
+ .DataInRun ( DataInRun ),
+ .DataInEnable ( DataInEnable ),
+ .DataIn ( DataIn ),
+
+ // Haffuman Table List
+ .DhtColor ( HmDhtColor ),
+ .DhtNumber ( HmDhtNumber ),
+ .DhtZero ( HmDhtZero ),
+ .DhtWidth ( HmDhtWidth ),
+
+ // DQT Table
+ .DqtColor ( HmDqtColor ),
+ .DqtNumber ( HmDqtNumber ),
+ .DqtData ( HmDqtData ),
+
+ .DataOutIdle ( HmOutIdle ),
+ .DataOutEnable ( HmOutEnable ),
+ .DataOutColor ( HmOutColor ),
+
+ // Output decode data
+ .DecodeUseBit ( DecodeUseBit ),
+ .DecodeUseWidth ( DecodeUseWidth ),
+
+ .DecodeEnable ( HmDecEnable ),
+ .DecodeColor ( ),
+ .DecodeCount ( HmDecCount ),
+ .DecodeZero ( ),
+ .DecodeCode ( HmDecData )
+ );
+
+ wire BankARelease;
+ wire BankBRelease;
+
+ assign BankARelease = DataOutSel == 1'b0 & DataOutRelease;
+ assign BankBRelease = DataOutSel == 1'b1 & DataOutRelease;
+
+
+ jpeg_ziguzagu u_jpeg_ziguzagu(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable ( HmDecEnable ),
+ .DataInAddress ( HmDecCount ),
+ .DataInColor ( HmOutColor ),
+ .DataInIdle ( HmOutIdle ),
+ .DataIn ( HmDecData ),
+
+ .HaffumanEndEnable(HmOutEnable),
+
+ .DataOutEnable( DataOutEnable),
+ .DataOutColor ( DataOutColor),
+ .DataOutSel(DataOutSel),
+ .Data00Reg( Data00Reg ),
+ .Data01Reg( Data01Reg ),
+ .Data02Reg( Data02Reg ),
+ .Data03Reg( Data03Reg ),
+ .Data04Reg( Data04Reg ),
+ .Data05Reg( Data05Reg ),
+ .Data06Reg( Data06Reg ),
+ .Data07Reg( Data07Reg ),
+ .Data08Reg( Data08Reg ),
+ .Data09Reg( Data09Reg ),
+ .Data10Reg( Data10Reg ),
+ .Data11Reg( Data11Reg ),
+ .Data12Reg( Data12Reg ),
+ .Data13Reg( Data13Reg ),
+ .Data14Reg( Data14Reg ),
+ .Data15Reg( Data15Reg ),
+ .Data16Reg( Data16Reg ),
+ .Data17Reg( Data17Reg ),
+ .Data18Reg( Data18Reg ),
+ .Data19Reg( Data19Reg ),
+ .Data20Reg( Data20Reg ),
+ .Data21Reg( Data21Reg ),
+ .Data22Reg( Data22Reg ),
+ .Data23Reg( Data23Reg ),
+ .Data24Reg( Data24Reg ),
+ .Data25Reg( Data25Reg ),
+ .Data26Reg( Data26Reg ),
+ .Data27Reg( Data27Reg ),
+ .Data28Reg( Data28Reg ),
+ .Data29Reg( Data29Reg ),
+ .Data30Reg( Data30Reg ),
+ .Data31Reg( Data31Reg ),
+ .Data32Reg( Data32Reg ),
+ .Data33Reg( Data33Reg ),
+ .Data34Reg( Data34Reg ),
+ .Data35Reg( Data35Reg ),
+ .Data36Reg( Data36Reg ),
+ .Data37Reg( Data37Reg ),
+ .Data38Reg( Data38Reg ),
+ .Data39Reg( Data39Reg ),
+ .Data40Reg( Data40Reg ),
+ .Data41Reg( Data41Reg ),
+ .Data42Reg( Data42Reg ),
+ .Data43Reg( Data43Reg ),
+ .Data44Reg( Data44Reg ),
+ .Data45Reg( Data45Reg ),
+ .Data46Reg( Data46Reg ),
+ .Data47Reg( Data47Reg ),
+ .Data48Reg( Data48Reg ),
+ .Data49Reg( Data49Reg ),
+ .Data50Reg( Data50Reg ),
+ .Data51Reg( Data51Reg ),
+ .Data52Reg( Data52Reg ),
+ .Data53Reg( Data53Reg ),
+ .Data54Reg( Data54Reg ),
+ .Data55Reg( Data55Reg ),
+ .Data56Reg( Data56Reg ),
+ .Data57Reg( Data57Reg ),
+ .Data58Reg( Data58Reg ),
+ .Data59Reg( Data59Reg ),
+ .Data60Reg( Data60Reg ),
+ .Data61Reg( Data61Reg ),
+ .Data62Reg( Data62Reg ),
+ .Data63Reg( Data63Reg ),
+
+ .BankARelease(BankARelease),
+ .BankBRelease(BankBRelease)
+ );
+
+endmodule // jpeg_haffuman
Index: djpeg/trunk/src/jpeg_idctb.v
===================================================================
--- djpeg/trunk/src/jpeg_idctb.v (nonexistent)
+++ djpeg/trunk/src/jpeg_idctb.v (revision 6)
@@ -0,0 +1,763 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_idctb.v
+// Module Name : jpeg_idctb
+// Description : data register for iDCT
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_idctb
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInPage,
+ DataInCount,
+ DataInIdle,
+ Data0In,
+ Data1In,
+
+ DataOutEnable,
+ DataOutSel,
+ Data00Out,
+ Data01Out,
+ Data02Out,
+ Data03Out,
+ Data04Out,
+ Data05Out,
+ Data06Out,
+ Data07Out,
+ Data08Out,
+ Data09Out,
+ Data10Out,
+ Data11Out,
+ Data12Out,
+ Data13Out,
+ Data14Out,
+ Data15Out,
+ Data16Out,
+ Data17Out,
+ Data18Out,
+ Data19Out,
+ Data20Out,
+ Data21Out,
+ Data22Out,
+ Data23Out,
+ Data24Out,
+ Data25Out,
+ Data26Out,
+ Data27Out,
+ Data28Out,
+ Data29Out,
+ Data30Out,
+ Data31Out,
+ Data32Out,
+ Data33Out,
+ Data34Out,
+ Data35Out,
+ Data36Out,
+ Data37Out,
+ Data38Out,
+ Data39Out,
+ Data40Out,
+ Data41Out,
+ Data42Out,
+ Data43Out,
+ Data44Out,
+ Data45Out,
+ Data46Out,
+ Data47Out,
+ Data48Out,
+ Data49Out,
+ Data50Out,
+ Data51Out,
+ Data52Out,
+ Data53Out,
+ Data54Out,
+ Data55Out,
+ Data56Out,
+ Data57Out,
+ Data58Out,
+ Data59Out,
+ Data60Out,
+ Data61Out,
+ Data62Out,
+ Data63Out,
+
+ BankARelease,
+ BankBRelease
+ );
+
+ input clk;
+ input rst;
+
+ input DataInEnable;
+ input [2:0] DataInPage;
+ input [1:0] DataInCount;
+ output DataInIdle;
+ input [15:0] Data0In;
+ input [15:0] Data1In;
+
+ output DataOutEnable;
+ input DataOutSel;
+ output [15:0] Data00Out;
+ output [15:0] Data01Out;
+ output [15:0] Data02Out;
+ output [15:0] Data03Out;
+ output [15:0] Data04Out;
+ output [15:0] Data05Out;
+ output [15:0] Data06Out;
+ output [15:0] Data07Out;
+ output [15:0] Data08Out;
+ output [15:0] Data09Out;
+ output [15:0] Data10Out;
+ output [15:0] Data11Out;
+ output [15:0] Data12Out;
+ output [15:0] Data13Out;
+ output [15:0] Data14Out;
+ output [15:0] Data15Out;
+ output [15:0] Data16Out;
+ output [15:0] Data17Out;
+ output [15:0] Data18Out;
+ output [15:0] Data19Out;
+ output [15:0] Data20Out;
+ output [15:0] Data21Out;
+ output [15:0] Data22Out;
+ output [15:0] Data23Out;
+ output [15:0] Data24Out;
+ output [15:0] Data25Out;
+ output [15:0] Data26Out;
+ output [15:0] Data27Out;
+ output [15:0] Data28Out;
+ output [15:0] Data29Out;
+ output [15:0] Data30Out;
+ output [15:0] Data31Out;
+ output [15:0] Data32Out;
+ output [15:0] Data33Out;
+ output [15:0] Data34Out;
+ output [15:0] Data35Out;
+ output [15:0] Data36Out;
+ output [15:0] Data37Out;
+ output [15:0] Data38Out;
+ output [15:0] Data39Out;
+ output [15:0] Data40Out;
+ output [15:0] Data41Out;
+ output [15:0] Data42Out;
+ output [15:0] Data43Out;
+ output [15:0] Data44Out;
+ output [15:0] Data45Out;
+ output [15:0] Data46Out;
+ output [15:0] Data47Out;
+ output [15:0] Data48Out;
+ output [15:0] Data49Out;
+ output [15:0] Data50Out;
+ output [15:0] Data51Out;
+ output [15:0] Data52Out;
+ output [15:0] Data53Out;
+ output [15:0] Data54Out;
+ output [15:0] Data55Out;
+ output [15:0] Data56Out;
+ output [15:0] Data57Out;
+ output [15:0] Data58Out;
+ output [15:0] Data59Out;
+ output [15:0] Data60Out;
+ output [15:0] Data61Out;
+ output [15:0] Data62Out;
+ output [15:0] Data63Out;
+
+ input BankARelease;
+ input BankBRelease;
+
+ reg BankAEnable;
+ reg BankBEnable;
+ reg DataInBank;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ BankAEnable <= 1'b0;
+ BankBEnable <= 1'b0;
+ DataInBank <= 1'b0;
+ end else begin
+ if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
+ if(DataInEnable == 1'b1 &
+ DataInPage == 3'd7 & DataInCount == 2'd3) begin
+ BankAEnable <= 1'b1;
+ end
+ end else begin
+ if(BankARelease == 1'b1) begin
+ BankAEnable <= 1'b0;
+ end
+ end
+ if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
+ if(DataInEnable == 1'b1 &
+ DataInPage == 3'd7 & DataInCount == 2'd3) begin
+ BankBEnable <= 1'b1;
+ end
+ end else begin
+ if(BankBRelease == 1'b1) begin
+ BankBEnable <= 1'b0;
+ end
+ end
+ if(DataInEnable == 1'b1 &
+ DataInPage == 3'd7 & DataInCount == 2'd3) begin
+ DataInBank <= ~DataInBank;
+ end
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;
+
+ assign DataOutEnable = DataInEnable == 1'b1 & DataInPage == 3'b111 &
+ DataInCount == 2'b11;
+
+ reg [15:0] BankAReg [0:63];
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ BankAReg[0] <= 12'h000;
+ BankAReg[1] <= 12'h000;
+ BankAReg[2] <= 12'h000;
+ BankAReg[3] <= 12'h000;
+ BankAReg[4] <= 12'h000;
+ BankAReg[5] <= 12'h000;
+ BankAReg[6] <= 12'h000;
+ BankAReg[7] <= 12'h000;
+ BankAReg[8] <= 12'h000;
+ BankAReg[9] <= 12'h000;
+ BankAReg[10] <= 12'h000;
+ BankAReg[11] <= 12'h000;
+ BankAReg[12] <= 12'h000;
+ BankAReg[13] <= 12'h000;
+ BankAReg[14] <= 12'h000;
+ BankAReg[15] <= 12'h000;
+ BankAReg[16] <= 12'h000;
+ BankAReg[17] <= 12'h000;
+ BankAReg[18] <= 12'h000;
+ BankAReg[19] <= 12'h000;
+ BankAReg[20] <= 12'h000;
+ BankAReg[21] <= 12'h000;
+ BankAReg[22] <= 12'h000;
+ BankAReg[23] <= 12'h000;
+ BankAReg[24] <= 12'h000;
+ BankAReg[25] <= 12'h000;
+ BankAReg[26] <= 12'h000;
+ BankAReg[27] <= 12'h000;
+ BankAReg[28] <= 12'h000;
+ BankAReg[29] <= 12'h000;
+ BankAReg[30] <= 12'h000;
+ BankAReg[31] <= 12'h000;
+ BankAReg[32] <= 12'h000;
+ BankAReg[33] <= 12'h000;
+ BankAReg[34] <= 12'h000;
+ BankAReg[35] <= 12'h000;
+ BankAReg[36] <= 12'h000;
+ BankAReg[37] <= 12'h000;
+ BankAReg[38] <= 12'h000;
+ BankAReg[39] <= 12'h000;
+ BankAReg[40] <= 12'h000;
+ BankAReg[41] <= 12'h000;
+ BankAReg[42] <= 12'h000;
+ BankAReg[43] <= 12'h000;
+ BankAReg[44] <= 12'h000;
+ BankAReg[45] <= 12'h000;
+ BankAReg[46] <= 12'h000;
+ BankAReg[47] <= 12'h000;
+ BankAReg[48] <= 12'h000;
+ BankAReg[49] <= 12'h000;
+ BankAReg[50] <= 12'h000;
+ BankAReg[51] <= 12'h000;
+ BankAReg[52] <= 12'h000;
+ BankAReg[53] <= 12'h000;
+ BankAReg[54] <= 12'h000;
+ BankAReg[55] <= 12'h000;
+ BankAReg[56] <= 12'h000;
+ BankAReg[57] <= 12'h000;
+ BankAReg[58] <= 12'h000;
+ BankAReg[59] <= 12'h000;
+ BankAReg[60] <= 12'h000;
+ BankAReg[61] <= 12'h000;
+ BankAReg[62] <= 12'h000;
+ BankAReg[63] <= 12'h000;
+ end else begin // if (!rst)
+ if(DataInEnable == 1'b1 & DataInBank == 1'b0) begin
+ case(DataInPage)
+ 3'd0: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankAReg[0] <= Data0In;
+ BankAReg[7] <= Data1In;
+ end
+ 2'd1: begin
+ BankAReg[1] <= Data0In;
+ BankAReg[6] <= Data1In;
+ end
+ 2'd2: begin
+ BankAReg[2] <= Data0In;
+ BankAReg[5] <= Data1In;
+ end
+ 2'd3: begin
+ BankAReg[3] <= Data0In;
+ BankAReg[4] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd0
+ 3'd1: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankAReg[8] <= Data0In;
+ BankAReg[15] <= Data1In;
+ end
+ 2'd1: begin
+ BankAReg[9] <= Data0In;
+ BankAReg[14] <= Data1In;
+ end
+ 2'd2: begin
+ BankAReg[10] <= Data0In;
+ BankAReg[13] <= Data1In;
+ end
+ 2'd3: begin
+ BankAReg[11] <= Data0In;
+ BankAReg[12] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd1
+ 3'd2: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankAReg[16] <= Data0In;
+ BankAReg[23] <= Data1In;
+ end
+ 2'd1: begin
+ BankAReg[17] <= Data0In;
+ BankAReg[22] <= Data1In;
+ end
+ 2'd2: begin
+ BankAReg[18] <= Data0In;
+ BankAReg[21] <= Data1In;
+ end
+ 2'd3: begin
+ BankAReg[19] <= Data0In;
+ BankAReg[20] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd2
+ 3'd3: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankAReg[24] <= Data0In;
+ BankAReg[31] <= Data1In;
+ end
+ 2'd1: begin
+ BankAReg[25] <= Data0In;
+ BankAReg[30] <= Data1In;
+ end
+ 2'd2: begin
+ BankAReg[26] <= Data0In;
+ BankAReg[29] <= Data1In;
+ end
+ 2'd3: begin
+ BankAReg[27] <= Data0In;
+ BankAReg[28] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd3
+ 3'd4: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankAReg[32] <= Data0In;
+ BankAReg[39] <= Data1In;
+ end
+ 2'd1: begin
+ BankAReg[33] <= Data0In;
+ BankAReg[38] <= Data1In;
+ end
+ 2'd2: begin
+ BankAReg[34] <= Data0In;
+ BankAReg[37] <= Data1In;
+ end
+ 2'd3: begin
+ BankAReg[35] <= Data0In;
+ BankAReg[36] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd4
+ 3'd5: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankAReg[40] <= Data0In;
+ BankAReg[47] <= Data1In;
+ end
+ 2'd1: begin
+ BankAReg[41] <= Data0In;
+ BankAReg[46] <= Data1In;
+ end
+ 2'd2: begin
+ BankAReg[42] <= Data0In;
+ BankAReg[45] <= Data1In;
+ end
+ 2'd3: begin
+ BankAReg[43] <= Data0In;
+ BankAReg[44] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd5
+ 3'd6: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankAReg[48] <= Data0In;
+ BankAReg[55] <= Data1In;
+ end
+ 2'd1: begin
+ BankAReg[49] <= Data0In;
+ BankAReg[54] <= Data1In;
+ end
+ 2'd2: begin
+ BankAReg[50] <= Data0In;
+ BankAReg[53] <= Data1In;
+ end
+ 2'd3: begin
+ BankAReg[51] <= Data0In;
+ BankAReg[52] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd6
+ 3'd7: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankAReg[56] <= Data0In;
+ BankAReg[63] <= Data1In;
+ end
+ 2'd1: begin
+ BankAReg[57] <= Data0In;
+ BankAReg[62] <= Data1In;
+ end
+ 2'd2: begin
+ BankAReg[58] <= Data0In;
+ BankAReg[61] <= Data1In;
+ end
+ 2'd3: begin
+ BankAReg[59] <= Data0In;
+ BankAReg[60] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd7
+ endcase // case(DataInPage)
+ end // if (DataInEnable == 1'b1 & DataInBank == 1'b0)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ reg [15:0] BankBReg [0:63];
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ BankBReg[0] <= 12'h000;
+ BankBReg[1] <= 12'h000;
+ BankBReg[2] <= 12'h000;
+ BankBReg[3] <= 12'h000;
+ BankBReg[4] <= 12'h000;
+ BankBReg[5] <= 12'h000;
+ BankBReg[6] <= 12'h000;
+ BankBReg[7] <= 12'h000;
+ BankBReg[8] <= 12'h000;
+ BankBReg[9] <= 12'h000;
+ BankBReg[10] <= 12'h000;
+ BankBReg[11] <= 12'h000;
+ BankBReg[12] <= 12'h000;
+ BankBReg[13] <= 12'h000;
+ BankBReg[14] <= 12'h000;
+ BankBReg[15] <= 12'h000;
+ BankBReg[16] <= 12'h000;
+ BankBReg[17] <= 12'h000;
+ BankBReg[18] <= 12'h000;
+ BankBReg[19] <= 12'h000;
+ BankBReg[20] <= 12'h000;
+ BankBReg[21] <= 12'h000;
+ BankBReg[22] <= 12'h000;
+ BankBReg[23] <= 12'h000;
+ BankBReg[24] <= 12'h000;
+ BankBReg[25] <= 12'h000;
+ BankBReg[26] <= 12'h000;
+ BankBReg[27] <= 12'h000;
+ BankBReg[28] <= 12'h000;
+ BankBReg[29] <= 12'h000;
+ BankBReg[30] <= 12'h000;
+ BankBReg[31] <= 12'h000;
+ BankBReg[32] <= 12'h000;
+ BankBReg[33] <= 12'h000;
+ BankBReg[34] <= 12'h000;
+ BankBReg[35] <= 12'h000;
+ BankBReg[36] <= 12'h000;
+ BankBReg[37] <= 12'h000;
+ BankBReg[38] <= 12'h000;
+ BankBReg[39] <= 12'h000;
+ BankBReg[40] <= 12'h000;
+ BankBReg[41] <= 12'h000;
+ BankBReg[42] <= 12'h000;
+ BankBReg[43] <= 12'h000;
+ BankBReg[44] <= 12'h000;
+ BankBReg[45] <= 12'h000;
+ BankBReg[46] <= 12'h000;
+ BankBReg[47] <= 12'h000;
+ BankBReg[48] <= 12'h000;
+ BankBReg[49] <= 12'h000;
+ BankBReg[50] <= 12'h000;
+ BankBReg[51] <= 12'h000;
+ BankBReg[52] <= 12'h000;
+ BankBReg[53] <= 12'h000;
+ BankBReg[54] <= 12'h000;
+ BankBReg[55] <= 12'h000;
+ BankBReg[56] <= 12'h000;
+ BankBReg[57] <= 12'h000;
+ BankBReg[58] <= 12'h000;
+ BankBReg[59] <= 12'h000;
+ BankBReg[60] <= 12'h000;
+ BankBReg[61] <= 12'h000;
+ BankBReg[62] <= 12'h000;
+ BankBReg[63] <= 12'h000;
+ end else begin // if (!rst)
+ if(DataInEnable == 1'b1 & DataInBank == 1'b1) begin
+ case(DataInPage)
+ 3'd0: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankBReg[0] <= Data0In;
+ BankBReg[7] <= Data1In;
+ end
+ 2'd1: begin
+ BankBReg[1] <= Data0In;
+ BankBReg[6] <= Data1In;
+ end
+ 2'd2: begin
+ BankBReg[2] <= Data0In;
+ BankBReg[5] <= Data1In;
+ end
+ 2'd3: begin
+ BankBReg[3] <= Data0In;
+ BankBReg[4] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd0
+ 3'd1: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankBReg[8] <= Data0In;
+ BankBReg[15] <= Data1In;
+ end
+ 2'd1: begin
+ BankBReg[9] <= Data0In;
+ BankBReg[14] <= Data1In;
+ end
+ 2'd2: begin
+ BankBReg[10] <= Data0In;
+ BankBReg[13] <= Data1In;
+ end
+ 2'd3: begin
+ BankBReg[11] <= Data0In;
+ BankBReg[12] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd1
+ 3'd2: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankBReg[16] <= Data0In;
+ BankBReg[23] <= Data1In;
+ end
+ 2'd1: begin
+ BankBReg[17] <= Data0In;
+ BankBReg[22] <= Data1In;
+ end
+ 2'd2: begin
+ BankBReg[18] <= Data0In;
+ BankBReg[21] <= Data1In;
+ end
+ 2'd3: begin
+ BankBReg[19] <= Data0In;
+ BankBReg[20] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd2
+ 3'd3: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankBReg[24] <= Data0In;
+ BankBReg[31] <= Data1In;
+ end
+ 2'd1: begin
+ BankBReg[25] <= Data0In;
+ BankBReg[30] <= Data1In;
+ end
+ 2'd2: begin
+ BankBReg[26] <= Data0In;
+ BankBReg[29] <= Data1In;
+ end
+ 2'd3: begin
+ BankBReg[27] <= Data0In;
+ BankBReg[28] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd3
+ 3'd4: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankBReg[32] <= Data0In;
+ BankBReg[39] <= Data1In;
+ end
+ 2'd1: begin
+ BankBReg[33] <= Data0In;
+ BankBReg[38] <= Data1In;
+ end
+ 2'd2: begin
+ BankBReg[34] <= Data0In;
+ BankBReg[37] <= Data1In;
+ end
+ 2'd3: begin
+ BankBReg[35] <= Data0In;
+ BankBReg[36] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd4
+ 3'd5: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankBReg[40] <= Data0In;
+ BankBReg[47] <= Data1In;
+ end
+ 2'd1: begin
+ BankBReg[41] <= Data0In;
+ BankBReg[46] <= Data1In;
+ end
+ 2'd2: begin
+ BankBReg[42] <= Data0In;
+ BankBReg[45] <= Data1In;
+ end
+ 2'd3: begin
+ BankBReg[43] <= Data0In;
+ BankBReg[44] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd5
+ 3'd6: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankBReg[48] <= Data0In;
+ BankBReg[55] <= Data1In;
+ end
+ 2'd1: begin
+ BankBReg[49] <= Data0In;
+ BankBReg[54] <= Data1In;
+ end
+ 2'd2: begin
+ BankBReg[50] <= Data0In;
+ BankBReg[53] <= Data1In;
+ end
+ 2'd3: begin
+ BankBReg[51] <= Data0In;
+ BankBReg[52] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd6
+ 3'd7: begin
+ case(DataInCount)
+ 2'd0: begin
+ BankBReg[56] <= Data0In;
+ BankBReg[63] <= Data1In;
+ end
+ 2'd1: begin
+ BankBReg[57] <= Data0In;
+ BankBReg[62] <= Data1In;
+ end
+ 2'd2: begin
+ BankBReg[58] <= Data0In;
+ BankBReg[61] <= Data1In;
+ end
+ 2'd3: begin
+ BankBReg[59] <= Data0In;
+ BankBReg[60] <= Data1In;
+ end
+ endcase // case(DataInCount)
+ end // case: 3'd7
+ endcase // case(DataInPage)
+ end // if (DataInEnable == 1'b1 & DataInBank == 1'b1)
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign Data00Out = (DataOutSel)?BankBReg[00]:BankAReg[00];
+ assign Data01Out = (DataOutSel)?BankBReg[08]:BankAReg[08];
+ assign Data02Out = (DataOutSel)?BankBReg[16]:BankAReg[16];
+ assign Data03Out = (DataOutSel)?BankBReg[24]:BankAReg[24];
+ assign Data04Out = (DataOutSel)?BankBReg[32]:BankAReg[32];
+ assign Data05Out = (DataOutSel)?BankBReg[40]:BankAReg[40];
+ assign Data06Out = (DataOutSel)?BankBReg[48]:BankAReg[48];
+ assign Data07Out = (DataOutSel)?BankBReg[56]:BankAReg[56];
+ assign Data08Out = (DataOutSel)?BankBReg[01]:BankAReg[01];
+ assign Data09Out = (DataOutSel)?BankBReg[09]:BankAReg[09];
+ assign Data10Out = (DataOutSel)?BankBReg[17]:BankAReg[17];
+ assign Data11Out = (DataOutSel)?BankBReg[25]:BankAReg[25];
+ assign Data12Out = (DataOutSel)?BankBReg[33]:BankAReg[33];
+ assign Data13Out = (DataOutSel)?BankBReg[41]:BankAReg[41];
+ assign Data14Out = (DataOutSel)?BankBReg[49]:BankAReg[49];
+ assign Data15Out = (DataOutSel)?BankBReg[57]:BankAReg[57];
+ assign Data16Out = (DataOutSel)?BankBReg[02]:BankAReg[02];
+ assign Data17Out = (DataOutSel)?BankBReg[10]:BankAReg[10];
+ assign Data18Out = (DataOutSel)?BankBReg[18]:BankAReg[18];
+ assign Data19Out = (DataOutSel)?BankBReg[26]:BankAReg[26];
+ assign Data20Out = (DataOutSel)?BankBReg[34]:BankAReg[34];
+ assign Data21Out = (DataOutSel)?BankBReg[42]:BankAReg[42];
+ assign Data22Out = (DataOutSel)?BankBReg[50]:BankAReg[50];
+ assign Data23Out = (DataOutSel)?BankBReg[58]:BankAReg[58];
+ assign Data24Out = (DataOutSel)?BankBReg[03]:BankAReg[03];
+ assign Data25Out = (DataOutSel)?BankBReg[11]:BankAReg[11];
+ assign Data26Out = (DataOutSel)?BankBReg[19]:BankAReg[19];
+ assign Data27Out = (DataOutSel)?BankBReg[27]:BankAReg[27];
+ assign Data28Out = (DataOutSel)?BankBReg[35]:BankAReg[35];
+ assign Data29Out = (DataOutSel)?BankBReg[43]:BankAReg[43];
+ assign Data30Out = (DataOutSel)?BankBReg[51]:BankAReg[51];
+ assign Data31Out = (DataOutSel)?BankBReg[59]:BankAReg[59];
+ assign Data32Out = (DataOutSel)?BankBReg[04]:BankAReg[04];
+ assign Data33Out = (DataOutSel)?BankBReg[12]:BankAReg[12];
+ assign Data34Out = (DataOutSel)?BankBReg[20]:BankAReg[20];
+ assign Data35Out = (DataOutSel)?BankBReg[28]:BankAReg[28];
+ assign Data36Out = (DataOutSel)?BankBReg[36]:BankAReg[36];
+ assign Data37Out = (DataOutSel)?BankBReg[44]:BankAReg[44];
+ assign Data38Out = (DataOutSel)?BankBReg[52]:BankAReg[52];
+ assign Data39Out = (DataOutSel)?BankBReg[60]:BankAReg[60];
+ assign Data40Out = (DataOutSel)?BankBReg[05]:BankAReg[05];
+ assign Data41Out = (DataOutSel)?BankBReg[13]:BankAReg[13];
+ assign Data42Out = (DataOutSel)?BankBReg[21]:BankAReg[21];
+ assign Data43Out = (DataOutSel)?BankBReg[29]:BankAReg[29];
+ assign Data44Out = (DataOutSel)?BankBReg[37]:BankAReg[37];
+ assign Data45Out = (DataOutSel)?BankBReg[45]:BankAReg[45];
+ assign Data46Out = (DataOutSel)?BankBReg[53]:BankAReg[53];
+ assign Data47Out = (DataOutSel)?BankBReg[61]:BankAReg[61];
+ assign Data48Out = (DataOutSel)?BankBReg[06]:BankAReg[06];
+ assign Data49Out = (DataOutSel)?BankBReg[14]:BankAReg[14];
+ assign Data50Out = (DataOutSel)?BankBReg[22]:BankAReg[22];
+ assign Data51Out = (DataOutSel)?BankBReg[30]:BankAReg[30];
+ assign Data52Out = (DataOutSel)?BankBReg[38]:BankAReg[38];
+ assign Data53Out = (DataOutSel)?BankBReg[46]:BankAReg[46];
+ assign Data54Out = (DataOutSel)?BankBReg[54]:BankAReg[54];
+ assign Data55Out = (DataOutSel)?BankBReg[62]:BankAReg[62];
+ assign Data56Out = (DataOutSel)?BankBReg[07]:BankAReg[07];
+ assign Data57Out = (DataOutSel)?BankBReg[15]:BankAReg[15];
+ assign Data58Out = (DataOutSel)?BankBReg[23]:BankAReg[23];
+ assign Data59Out = (DataOutSel)?BankBReg[31]:BankAReg[31];
+ assign Data60Out = (DataOutSel)?BankBReg[39]:BankAReg[39];
+ assign Data61Out = (DataOutSel)?BankBReg[47]:BankAReg[47];
+ assign Data62Out = (DataOutSel)?BankBReg[55]:BankAReg[55];
+ assign Data63Out = (DataOutSel)?BankBReg[63]:BankAReg[63];
+
+endmodule // jpeg_idctb
Index: djpeg/trunk/src/jpeg_dqt.v
===================================================================
--- djpeg/trunk/src/jpeg_dqt.v (nonexistent)
+++ djpeg/trunk/src/jpeg_dqt.v (revision 6)
@@ -0,0 +1,76 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_dqt.v
+// Module Name : jpeg_dqt
+// Description : DQT spcae
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_dqt
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInColor,
+ DataInCount,
+ DataIn,
+
+ TableColor,
+ TableNumber,
+ TableData
+ );
+
+ input rst;
+ input clk;
+
+ input DataInEnable;
+ input DataInColor;
+ input [5:0] DataInCount;
+ input [7:0] DataIn;
+
+ input TableColor;
+ input [5:0] TableNumber;
+ output [7:0] TableData;
+
+ // RAM
+ reg [7:0] DQT_Y [0:63];
+ reg [7:0] DQT_C [0:63];
+
+ // RAM
+ always @(posedge clk)
+ begin
+ if(DataInEnable ==1'b1 && DataInColor ==1'b0) begin
+ DQT_Y[DataInCount] <= DataIn;
+ end
+ if(DataInEnable ==1'b1 && DataInColor ==1'b1) begin
+ DQT_C[DataInCount] <= DataIn;
+ end
+ end
+
+ reg [7:0] TableDataY;
+ reg [7:0] TableDataC;
+
+ // RAM out
+ always @(posedge clk) begin
+ TableDataY <= DQT_Y[TableNumber];
+ TableDataC <= DQT_C[TableNumber];
+ end
+
+ // Selector
+ assign TableData = (TableColor)?TableDataC:TableDataY;
+
+endmodule // jpeg_dqt
+
Index: djpeg/trunk/src/jpeg_ycbcr.v
===================================================================
--- djpeg/trunk/src/jpeg_ycbcr.v (nonexistent)
+++ djpeg/trunk/src/jpeg_ycbcr.v (revision 6)
@@ -0,0 +1,228 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_ycbcr.v
+// Module Name : jpeg_ycbcr
+// Description : Convert to RGB from YCbCr
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_ycbcr
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInPage,
+ DataInCount,
+ DataInIdle,
+ Data0In,
+ Data1In,
+ DataInBlockWidth,
+
+ OutEnable,
+ OutPixelX,
+ OutPixelY,
+ OutR,
+ OutG,
+ OutB
+ );
+
+ input rst;
+ input clk;
+
+ input DataInEnable;
+ input [2:0] DataInPage;
+ input [1:0] DataInCount;
+ output DataInIdle;
+ input [8:0] Data0In;
+ input [8:0] Data1In;
+ input [11:0] DataInBlockWidth;
+
+ output OutEnable;
+ output [15:0] OutPixelX;
+ output [15:0] OutPixelY;
+ output [7:0] OutR;
+ output [7:0] OutG;
+ output [7:0] OutB;
+
+ reg DataInBank;
+ reg [2:0] DataInColor;
+ reg [11:0] DataInBlockX;
+ reg [11:0] DataInBlockY;
+ reg BankAActive;
+ reg BankBActive;
+ wire BankAEnable;
+ wire BankBEnable;
+
+ wire [8:0] BankAY;
+ wire [8:0] BankACb;
+ wire [8:0] BankACr;
+ wire [8:0] BankBY;
+ wire [8:0] BankBCb;
+ wire [8:0] BankBCr;
+
+ reg [11:0] BankABlockX;
+ reg [11:0] BankABlockY;
+ reg [11:0] BankBBlockX;
+ reg [11:0] BankBBlockY;
+
+ wire ConvertEnable;
+ wire ConvertBank;
+ wire [7:0] ConvertAddress;
+ wire [8:0] DataY;
+ wire [8:0] DataCb;
+ wire [8:0] DataCr;
+ wire [11:0] ConvertBlockX;
+ wire [11:0] ConvertBlockY;
+
+ wire BankAIdle;
+ wire BankBIdle;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ DataInBank <= 1'b0;
+ DataInColor <= 3'b000;
+ DataInBlockX <= 12'h000;
+ DataInBlockY <= 12'h000;
+ BankAActive <= 1'b0;
+ BankBActive <= 1'b0;
+ BankABlockX <= 12'h000;
+ BankABlockY <= 12'h000;
+ BankBBlockX <= 12'h000;
+ BankBBlockY <= 12'h000;
+ end else begin // if (!rst)
+ if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
+ DataInPage == 3'b111 & DataInCount == 2'b11) begin
+ end
+ if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
+ DataInPage == 3'b111 & DataInCount == 2'b11 &
+ DataInBank == 1'b0 & BankAActive == 1'b0) begin
+ BankAActive <= 1'b1;
+ BankABlockX <= DataInBlockX;
+ BankABlockY <= DataInBlockY;
+ end else if(ConvertBank == 1'b0 & ConvertAddress == 7'b111) begin
+ BankAActive <= 1'b0;
+ end
+ if(DataInEnable == 1'b1 & DataInColor == 3'b101 &
+ DataInPage == 3'b111 & DataInCount == 2'b11 &
+ DataInBank == 1'b1 & BankBActive == 1'b0) begin
+ BankBActive <= 1'b1;
+ BankBBlockX <= DataInBlockX;
+ BankBBlockY <= DataInBlockY;
+ end else if(ConvertBank == 1'b1 & ConvertAddress == 7'b111) begin
+ BankBActive <= 1'b0;
+ end
+ if(DataInEnable == 1'b1 &
+ DataInPage == 3'b111 & DataInCount == 2'b11) begin
+ if(DataInColor == 3'b101) begin
+ DataInColor <= 3'b000;
+ DataInBank <= ~DataInBank;
+ if(DataInBlockWidth == DataInBlockX +1) begin
+ DataInBlockX <= 12'h000;
+ DataInBlockY <= DataInBlockY + 12'h001;
+ end else begin
+ DataInBlockX <= DataInBlockX + 12'h001;
+ end
+ end else begin
+ DataInColor <= DataInColor + 3'b001;
+ end // else: !if(DataInColor == 3'b101)
+ end // if (DataInEnable == 1'b1 &...
+
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign BankAEnable = DataInEnable == 1'b1 & DataInBank == 1'b0;
+ assign BankBEnable = DataInEnable == 1'b1 & DataInBank == 1'b1;
+
+ /*
+ assign ConvertBlockX = (ConvertBank)?BankBBlockX:BankABlockX;
+ assign ConvertBlockY = (ConvertBank)?BankBBlockY:BankABlockY;
+ */
+
+ assign ConvertEnable = DataInEnable == 1'b1 & DataInColor == 3'b101 &
+ DataInPage == 3'b111 & DataInCount == 2'b11;
+
+ assign DataInIdle = BankAActive == 1'b0 | BankBActive == 1'b0;
+
+ //------------------------------------------------------------------------
+ // YCbCr Memory
+ //------------------------------------------------------------------------
+ jpeg_ycbcr_mem u_jpeg_ycbcr_mem0(
+ .clk(clk),
+
+ .DataInEnable (BankAEnable),
+ .DataInColor (DataInColor),
+ .DataInPage (DataInPage),
+ .DataInCount (DataInCount),
+ .Data0In (Data0In),
+ .Data1In (Data1In),
+
+ .DataOutAddress (ConvertAddress),
+ .DataOutY (BankAY),
+ .DataOutCb (BankACb),
+ .DataOutCr (BankACr)
+ );
+ jpeg_ycbcr_mem u_jpeg_ycbcr_mem1(
+ .clk(clk),
+
+ .DataInEnable (BankBEnable),
+ .DataInColor (DataInColor),
+ .DataInPage (DataInPage),
+ .DataInCount (DataInCount),
+ .Data0In (Data0In),
+ .Data1In (Data1In),
+
+ .DataOutAddress (ConvertAddress),
+ .DataOutY (BankBY),
+ .DataOutCb (BankBCb),
+ .DataOutCr (BankBCr)
+ );
+
+ reg ConvertBankD;
+ always @(posedge clk or negedge rst) begin
+ if(!rst) ConvertBankD <= 1'b0;
+ else ConvertBankD <= ConvertBank;
+ end
+
+
+ assign DataY = (ConvertBankD)?BankBY :BankAY;
+ assign DataCb = (ConvertBankD)?BankBCb:BankACb;
+ assign DataCr = (ConvertBankD)?BankBCr:BankACr;
+
+ //------------------------------------------------------------------------
+ // YCbCr to RGB
+ //------------------------------------------------------------------------
+ jpeg_ycbcbr2rgb u_jpeg_ycbcr2rgb(
+ .rst(rst),
+ .clk(clk),
+
+ .InEnable ( ConvertEnable ),
+ .InBlockX ( DataInBlockX ),
+ .InBlockY ( DataInBlockY ),
+ .InIdle ( ConvertIdle ),
+ .InBank ( ConvertBank ),
+ .InAddress ( ConvertAddress ),
+ .InY ( DataY ),
+ .InCb ( DataCb ),
+ .InCr ( DataCr ),
+
+ .OutEnable ( OutEnable ),
+ .OutPixelX ( OutPixelX ),
+ .OutPixelY ( OutPixelY ),
+ .OutR ( OutR ),
+ .OutG ( OutG ),
+ .OutB ( OutB )
+ );
+endmodule // jpeg_ycbcr
Index: djpeg/trunk/src/jpeg_ziguzagu.v
===================================================================
--- djpeg/trunk/src/jpeg_ziguzagu.v (nonexistent)
+++ djpeg/trunk/src/jpeg_ziguzagu.v (revision 6)
@@ -0,0 +1,581 @@
+//---------------------------------------------------------------------------
+// File Name : jpeg_ziguzagu.v
+// Module Name : jpeg_ziguzagu
+// Description : Ziguzagu
+// Project : JPEG Decoder
+// Belong to :
+// Author : H.Ishihara
+// E-Mail : hidemi@sweetcafe.jp
+// HomePage : http://www.sweetcafe.jp/
+// Date : 2006/10/01
+// Rev. : 1.1
+//---------------------------------------------------------------------------
+// Rev. Date Description
+//---------------------------------------------------------------------------
+// 1.01 2006/10/01 1st Release
+//---------------------------------------------------------------------------
+// $Id:
+//---------------------------------------------------------------------------
+`timescale 1ps / 1ps
+
+module jpeg_ziguzagu
+ (
+ rst,
+ clk,
+
+ DataInEnable,
+ DataInAddress,
+ DataInColor,
+ DataInIdle,
+ DataIn,
+
+ HaffumanEndEnable,
+
+ DataOutEnable,
+ DataOutColor,
+ DataOutSel,
+ Data00Reg,
+ Data01Reg,
+ Data02Reg,
+ Data03Reg,
+ Data04Reg,
+ Data05Reg,
+ Data06Reg,
+ Data07Reg,
+ Data08Reg,
+ Data09Reg,
+ Data10Reg,
+ Data11Reg,
+ Data12Reg,
+ Data13Reg,
+ Data14Reg,
+ Data15Reg,
+ Data16Reg,
+ Data17Reg,
+ Data18Reg,
+ Data19Reg,
+ Data20Reg,
+ Data21Reg,
+ Data22Reg,
+ Data23Reg,
+ Data24Reg,
+ Data25Reg,
+ Data26Reg,
+ Data27Reg,
+ Data28Reg,
+ Data29Reg,
+ Data30Reg,
+ Data31Reg,
+ Data32Reg,
+ Data33Reg,
+ Data34Reg,
+ Data35Reg,
+ Data36Reg,
+ Data37Reg,
+ Data38Reg,
+ Data39Reg,
+ Data40Reg,
+ Data41Reg,
+ Data42Reg,
+ Data43Reg,
+ Data44Reg,
+ Data45Reg,
+ Data46Reg,
+ Data47Reg,
+ Data48Reg,
+ Data49Reg,
+ Data50Reg,
+ Data51Reg,
+ Data52Reg,
+ Data53Reg,
+ Data54Reg,
+ Data55Reg,
+ Data56Reg,
+ Data57Reg,
+ Data58Reg,
+ Data59Reg,
+ Data60Reg,
+ Data61Reg,
+ Data62Reg,
+ Data63Reg,
+
+ BankARelease,
+ BankBRelease
+ );
+
+ input clk;
+ input rst;
+
+ input DataInEnable;
+ input [5:0] DataInAddress;
+ input [2:0] DataInColor;
+ output DataInIdle;
+ input [15:0] DataIn;
+
+ input HaffumanEndEnable;
+
+ output DataOutEnable;
+ output [2:0] DataOutColor;
+ input DataOutSel;
+ output [15:0] Data00Reg;
+ output [15:0] Data01Reg;
+ output [15:0] Data02Reg;
+ output [15:0] Data03Reg;
+ output [15:0] Data04Reg;
+ output [15:0] Data05Reg;
+ output [15:0] Data06Reg;
+ output [15:0] Data07Reg;
+ output [15:0] Data08Reg;
+ output [15:0] Data09Reg;
+ output [15:0] Data10Reg;
+ output [15:0] Data11Reg;
+ output [15:0] Data12Reg;
+ output [15:0] Data13Reg;
+ output [15:0] Data14Reg;
+ output [15:0] Data15Reg;
+ output [15:0] Data16Reg;
+ output [15:0] Data17Reg;
+ output [15:0] Data18Reg;
+ output [15:0] Data19Reg;
+ output [15:0] Data20Reg;
+ output [15:0] Data21Reg;
+ output [15:0] Data22Reg;
+ output [15:0] Data23Reg;
+ output [15:0] Data24Reg;
+ output [15:0] Data25Reg;
+ output [15:0] Data26Reg;
+ output [15:0] Data27Reg;
+ output [15:0] Data28Reg;
+ output [15:0] Data29Reg;
+ output [15:0] Data30Reg;
+ output [15:0] Data31Reg;
+ output [15:0] Data32Reg;
+ output [15:0] Data33Reg;
+ output [15:0] Data34Reg;
+ output [15:0] Data35Reg;
+ output [15:0] Data36Reg;
+ output [15:0] Data37Reg;
+ output [15:0] Data38Reg;
+ output [15:0] Data39Reg;
+ output [15:0] Data40Reg;
+ output [15:0] Data41Reg;
+ output [15:0] Data42Reg;
+ output [15:0] Data43Reg;
+ output [15:0] Data44Reg;
+ output [15:0] Data45Reg;
+ output [15:0] Data46Reg;
+ output [15:0] Data47Reg;
+ output [15:0] Data48Reg;
+ output [15:0] Data49Reg;
+ output [15:0] Data50Reg;
+ output [15:0] Data51Reg;
+ output [15:0] Data52Reg;
+ output [15:0] Data53Reg;
+ output [15:0] Data54Reg;
+ output [15:0] Data55Reg;
+ output [15:0] Data56Reg;
+ output [15:0] Data57Reg;
+ output [15:0] Data58Reg;
+ output [15:0] Data59Reg;
+ output [15:0] Data60Reg;
+ output [15:0] Data61Reg;
+ output [15:0] Data62Reg;
+ output [15:0] Data63Reg;
+ input BankARelease;
+ input BankBRelease;
+
+ reg BankAEnable;
+ reg BankBEnable;
+ reg DataInBank;
+
+ reg [2:0] BankAColor;
+ reg [2:0] BankBColor;
+
+ always @(posedge clk or negedge rst) begin
+ if(!rst) begin
+ BankAEnable <= 1'b0;
+ BankBEnable <= 1'b0;
+ BankAColor <= 3'b000;
+ BankBColor <= 3'b000;
+ DataInBank <= 1'b0;
+ end else begin
+ if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
+ if(HaffumanEndEnable == 1'b1 & DataInIdle == 1'b1) begin
+ BankAEnable <= 1'b1;
+ BankAColor <= DataInColor;
+ end
+ end else begin
+ if(BankARelease == 1'b1) begin
+ BankAEnable <= 1'b0;
+ end
+ end
+ if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
+ if(HaffumanEndEnable == 1'b1 & DataInIdle == 1'b1) begin
+ BankBEnable <= 1'b1;
+ BankBColor <= DataInColor;
+ end
+ end else begin
+ if(BankBRelease == 1'b1) begin
+ BankBEnable <= 1'b0;
+ end
+ end
+ if(HaffumanEndEnable == 1'b1) begin
+ DataInBank <= ~DataInBank;
+ end
+ end // else: !if(!rst)
+ end // always @ (posedge clk or negedge rst)
+
+ assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;
+ assign DataOutEnable = BankAEnable == 1'b1 | BankBEnable == 1'b1;
+ assign DataOutColor = (DataInBank)?BankBColor:BankAColor;
+
+ wire ZigAEnable;
+ wire ZigBEnable;
+
+ wire [15:0] BankA00Reg;
+ wire [15:0] BankA01Reg;
+ wire [15:0] BankA02Reg;
+ wire [15:0] BankA03Reg;
+ wire [15:0] BankA04Reg;
+ wire [15:0] BankA05Reg;
+ wire [15:0] BankA06Reg;
+ wire [15:0] BankA07Reg;
+ wire [15:0] BankA08Reg;
+ wire [15:0] BankA09Reg;
+ wire [15:0] BankA10Reg;
+ wire [15:0] BankA11Reg;
+ wire [15:0] BankA12Reg;
+ wire [15:0] BankA13Reg;
+ wire [15:0] BankA14Reg;
+ wire [15:0] BankA15Reg;
+ wire [15:0] BankA16Reg;
+ wire [15:0] BankA17Reg;
+ wire [15:0] BankA18Reg;
+ wire [15:0] BankA19Reg;
+ wire [15:0] BankA20Reg;
+ wire [15:0] BankA21Reg;
+ wire [15:0] BankA22Reg;
+ wire [15:0] BankA23Reg;
+ wire [15:0] BankA24Reg;
+ wire [15:0] BankA25Reg;
+ wire [15:0] BankA26Reg;
+ wire [15:0] BankA27Reg;
+ wire [15:0] BankA28Reg;
+ wire [15:0] BankA29Reg;
+ wire [15:0] BankA30Reg;
+ wire [15:0] BankA31Reg;
+ wire [15:0] BankA32Reg;
+ wire [15:0] BankA33Reg;
+ wire [15:0] BankA34Reg;
+ wire [15:0] BankA35Reg;
+ wire [15:0] BankA36Reg;
+ wire [15:0] BankA37Reg;
+ wire [15:0] BankA38Reg;
+ wire [15:0] BankA39Reg;
+ wire [15:0] BankA40Reg;
+ wire [15:0] BankA41Reg;
+ wire [15:0] BankA42Reg;
+ wire [15:0] BankA43Reg;
+ wire [15:0] BankA44Reg;
+ wire [15:0] BankA45Reg;
+ wire [15:0] BankA46Reg;
+ wire [15:0] BankA47Reg;
+ wire [15:0] BankA48Reg;
+ wire [15:0] BankA49Reg;
+ wire [15:0] BankA50Reg;
+ wire [15:0] BankA51Reg;
+ wire [15:0] BankA52Reg;
+ wire [15:0] BankA53Reg;
+ wire [15:0] BankA54Reg;
+ wire [15:0] BankA55Reg;
+ wire [15:0] BankA56Reg;
+ wire [15:0] BankA57Reg;
+ wire [15:0] BankA58Reg;
+ wire [15:0] BankA59Reg;
+ wire [15:0] BankA60Reg;
+ wire [15:0] BankA61Reg;
+ wire [15:0] BankA62Reg;
+ wire [15:0] BankA63Reg;
+
+ wire [15:0] BankB00Reg;
+ wire [15:0] BankB01Reg;
+ wire [15:0] BankB02Reg;
+ wire [15:0] BankB03Reg;
+ wire [15:0] BankB04Reg;
+ wire [15:0] BankB05Reg;
+ wire [15:0] BankB06Reg;
+ wire [15:0] BankB07Reg;
+ wire [15:0] BankB08Reg;
+ wire [15:0] BankB09Reg;
+ wire [15:0] BankB10Reg;
+ wire [15:0] BankB11Reg;
+ wire [15:0] BankB12Reg;
+ wire [15:0] BankB13Reg;
+ wire [15:0] BankB14Reg;
+ wire [15:0] BankB15Reg;
+ wire [15:0] BankB16Reg;
+ wire [15:0] BankB17Reg;
+ wire [15:0] BankB18Reg;
+ wire [15:0] BankB19Reg;
+ wire [15:0] BankB20Reg;
+ wire [15:0] BankB21Reg;
+ wire [15:0] BankB22Reg;
+ wire [15:0] BankB23Reg;
+ wire [15:0] BankB24Reg;
+ wire [15:0] BankB25Reg;
+ wire [15:0] BankB26Reg;
+ wire [15:0] BankB27Reg;
+ wire [15:0] BankB28Reg;
+ wire [15:0] BankB29Reg;
+ wire [15:0] BankB30Reg;
+ wire [15:0] BankB31Reg;
+ wire [15:0] BankB32Reg;
+ wire [15:0] BankB33Reg;
+ wire [15:0] BankB34Reg;
+ wire [15:0] BankB35Reg;
+ wire [15:0] BankB36Reg;
+ wire [15:0] BankB37Reg;
+ wire [15:0] BankB38Reg;
+ wire [15:0] BankB39Reg;
+ wire [15:0] BankB40Reg;
+ wire [15:0] BankB41Reg;
+ wire [15:0] BankB42Reg;
+ wire [15:0] BankB43Reg;
+ wire [15:0] BankB44Reg;
+ wire [15:0] BankB45Reg;
+ wire [15:0] BankB46Reg;
+ wire [15:0] BankB47Reg;
+ wire [15:0] BankB48Reg;
+ wire [15:0] BankB49Reg;
+ wire [15:0] BankB50Reg;
+ wire [15:0] BankB51Reg;
+ wire [15:0] BankB52Reg;
+ wire [15:0] BankB53Reg;
+ wire [15:0] BankB54Reg;
+ wire [15:0] BankB55Reg;
+ wire [15:0] BankB56Reg;
+ wire [15:0] BankB57Reg;
+ wire [15:0] BankB58Reg;
+ wire [15:0] BankB59Reg;
+ wire [15:0] BankB60Reg;
+ wire [15:0] BankB61Reg;
+ wire [15:0] BankB62Reg;
+ wire [15:0] BankB63Reg;
+
+ assign ZigAEnable = DataInEnable == 1'b1 & DataInBank == 1'b0;
+ assign ZigBEnable = DataInEnable == 1'b1 & DataInBank == 1'b1;
+
+ jpeg_ziguzagu_reg u_jpeg_ziguzagu_reg0(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable ( ZigAEnable ),
+ .DataInAddress ( DataInAddress ),
+ .DataIn ( DataIn ),
+
+ .Data00Reg( BankA00Reg ),
+ .Data01Reg( BankA01Reg ),
+ .Data02Reg( BankA02Reg ),
+ .Data03Reg( BankA03Reg ),
+ .Data04Reg( BankA04Reg ),
+ .Data05Reg( BankA05Reg ),
+ .Data06Reg( BankA06Reg ),
+ .Data07Reg( BankA07Reg ),
+ .Data08Reg( BankA08Reg ),
+ .Data09Reg( BankA09Reg ),
+ .Data10Reg( BankA10Reg ),
+ .Data11Reg( BankA11Reg ),
+ .Data12Reg( BankA12Reg ),
+ .Data13Reg( BankA13Reg ),
+ .Data14Reg( BankA14Reg ),
+ .Data15Reg( BankA15Reg ),
+ .Data16Reg( BankA16Reg ),
+ .Data17Reg( BankA17Reg ),
+ .Data18Reg( BankA18Reg ),
+ .Data19Reg( BankA19Reg ),
+ .Data20Reg( BankA20Reg ),
+ .Data21Reg( BankA21Reg ),
+ .Data22Reg( BankA22Reg ),
+ .Data23Reg( BankA23Reg ),
+ .Data24Reg( BankA24Reg ),
+ .Data25Reg( BankA25Reg ),
+ .Data26Reg( BankA26Reg ),
+ .Data27Reg( BankA27Reg ),
+ .Data28Reg( BankA28Reg ),
+ .Data29Reg( BankA29Reg ),
+ .Data30Reg( BankA30Reg ),
+ .Data31Reg( BankA31Reg ),
+ .Data32Reg( BankA32Reg ),
+ .Data33Reg( BankA33Reg ),
+ .Data34Reg( BankA34Reg ),
+ .Data35Reg( BankA35Reg ),
+ .Data36Reg( BankA36Reg ),
+ .Data37Reg( BankA37Reg ),
+ .Data38Reg( BankA38Reg ),
+ .Data39Reg( BankA39Reg ),
+ .Data40Reg( BankA40Reg ),
+ .Data41Reg( BankA41Reg ),
+ .Data42Reg( BankA42Reg ),
+ .Data43Reg( BankA43Reg ),
+ .Data44Reg( BankA44Reg ),
+ .Data45Reg( BankA45Reg ),
+ .Data46Reg( BankA46Reg ),
+ .Data47Reg( BankA47Reg ),
+ .Data48Reg( BankA48Reg ),
+ .Data49Reg( BankA49Reg ),
+ .Data50Reg( BankA50Reg ),
+ .Data51Reg( BankA51Reg ),
+ .Data52Reg( BankA52Reg ),
+ .Data53Reg( BankA53Reg ),
+ .Data54Reg( BankA54Reg ),
+ .Data55Reg( BankA55Reg ),
+ .Data56Reg( BankA56Reg ),
+ .Data57Reg( BankA57Reg ),
+ .Data58Reg( BankA58Reg ),
+ .Data59Reg( BankA59Reg ),
+ .Data60Reg( BankA60Reg ),
+ .Data61Reg( BankA61Reg ),
+ .Data62Reg( BankA62Reg ),
+ .Data63Reg( BankA63Reg )
+ );
+
+ jpeg_ziguzagu_reg u_jpeg_ziguzagu_reg1(
+ .rst(rst),
+ .clk(clk),
+
+ .DataInEnable ( ZigBEnable ),
+ .DataInAddress ( DataInAddress ),
+ .DataIn ( DataIn ),
+
+ .Data00Reg( BankB00Reg ),
+ .Data01Reg( BankB01Reg ),
+ .Data02Reg( BankB02Reg ),
+ .Data03Reg( BankB03Reg ),
+ .Data04Reg( BankB04Reg ),
+ .Data05Reg( BankB05Reg ),
+ .Data06Reg( BankB06Reg ),
+ .Data07Reg( BankB07Reg ),
+ .Data08Reg( BankB08Reg ),
+ .Data09Reg( BankB09Reg ),
+ .Data10Reg( BankB10Reg ),
+ .Data11Reg( BankB11Reg ),
+ .Data12Reg( BankB12Reg ),
+ .Data13Reg( BankB13Reg ),
+ .Data14Reg( BankB14Reg ),
+ .Data15Reg( BankB15Reg ),
+ .Data16Reg( BankB16Reg ),
+ .Data17Reg( BankB17Reg ),
+ .Data18Reg( BankB18Reg ),
+ .Data19Reg( BankB19Reg ),
+ .Data20Reg( BankB20Reg ),
+ .Data21Reg( BankB21Reg ),
+ .Data22Reg( BankB22Reg ),
+ .Data23Reg( BankB23Reg ),
+ .Data24Reg( BankB24Reg ),
+ .Data25Reg( BankB25Reg ),
+ .Data26Reg( BankB26Reg ),
+ .Data27Reg( BankB27Reg ),
+ .Data28Reg( BankB28Reg ),
+ .Data29Reg( BankB29Reg ),
+ .Data30Reg( BankB30Reg ),
+ .Data31Reg( BankB31Reg ),
+ .Data32Reg( BankB32Reg ),
+ .Data33Reg( BankB33Reg ),
+ .Data34Reg( BankB34Reg ),
+ .Data35Reg( BankB35Reg ),
+ .Data36Reg( BankB36Reg ),
+ .Data37Reg( BankB37Reg ),
+ .Data38Reg( BankB38Reg ),
+ .Data39Reg( BankB39Reg ),
+ .Data40Reg( BankB40Reg ),
+ .Data41Reg( BankB41Reg ),
+ .Data42Reg( BankB42Reg ),
+ .Data43Reg( BankB43Reg ),
+ .Data44Reg( BankB44Reg ),
+ .Data45Reg( BankB45Reg ),
+ .Data46Reg( BankB46Reg ),
+ .Data47Reg( BankB47Reg ),
+ .Data48Reg( BankB48Reg ),
+ .Data49Reg( BankB49Reg ),
+ .Data50Reg( BankB50Reg ),
+ .Data51Reg( BankB51Reg ),
+ .Data52Reg( BankB52Reg ),
+ .Data53Reg( BankB53Reg ),
+ .Data54Reg( BankB54Reg ),
+ .Data55Reg( BankB55Reg ),
+ .Data56Reg( BankB56Reg ),
+ .Data57Reg( BankB57Reg ),
+ .Data58Reg( BankB58Reg ),
+ .Data59Reg( BankB59Reg ),
+ .Data60Reg( BankB60Reg ),
+ .Data61Reg( BankB61Reg ),
+ .Data62Reg( BankB62Reg ),
+ .Data63Reg( BankB63Reg )
+ );
+
+ assign Data00Reg = (DataOutSel)?BankB00Reg:BankA00Reg;
+ assign Data01Reg = (DataOutSel)?BankB01Reg:BankA01Reg;
+ assign Data02Reg = (DataOutSel)?BankB02Reg:BankA02Reg;
+ assign Data03Reg = (DataOutSel)?BankB03Reg:BankA03Reg;
+ assign Data04Reg = (DataOutSel)?BankB04Reg:BankA04Reg;
+ assign Data05Reg = (DataOutSel)?BankB05Reg:BankA05Reg;
+ assign Data06Reg = (DataOutSel)?BankB06Reg:BankA06Reg;
+ assign Data07Reg = (DataOutSel)?BankB07Reg:BankA07Reg;
+ assign Data08Reg = (DataOutSel)?BankB08Reg:BankA08Reg;
+ assign Data09Reg = (DataOutSel)?BankB09Reg:BankA09Reg;
+ assign Data10Reg = (DataOutSel)?BankB10Reg:BankA10Reg;
+ assign Data11Reg = (DataOutSel)?BankB11Reg:BankA11Reg;
+ assign Data12Reg = (DataOutSel)?BankB12Reg:BankA12Reg;
+ assign Data13Reg = (DataOutSel)?BankB13Reg:BankA13Reg;
+ assign Data14Reg = (DataOutSel)?BankB14Reg:BankA14Reg;
+ assign Data15Reg = (DataOutSel)?BankB15Reg:BankA15Reg;
+ assign Data16Reg = (DataOutSel)?BankB16Reg:BankA16Reg;
+ assign Data17Reg = (DataOutSel)?BankB17Reg:BankA17Reg;
+ assign Data18Reg = (DataOutSel)?BankB18Reg:BankA18Reg;
+ assign Data19Reg = (DataOutSel)?BankB19Reg:BankA19Reg;
+ assign Data20Reg = (DataOutSel)?BankB20Reg:BankA20Reg;
+ assign Data21Reg = (DataOutSel)?BankB21Reg:BankA21Reg;
+ assign Data22Reg = (DataOutSel)?BankB22Reg:BankA22Reg;
+ assign Data23Reg = (DataOutSel)?BankB23Reg:BankA23Reg;
+ assign Data24Reg = (DataOutSel)?BankB24Reg:BankA24Reg;
+ assign Data25Reg = (DataOutSel)?BankB25Reg:BankA25Reg;
+ assign Data26Reg = (DataOutSel)?BankB26Reg:BankA26Reg;
+ assign Data27Reg = (DataOutSel)?BankB27Reg:BankA27Reg;
+ assign Data28Reg = (DataOutSel)?BankB28Reg:BankA28Reg;
+ assign Data29Reg = (DataOutSel)?BankB29Reg:BankA29Reg;
+ assign Data30Reg = (DataOutSel)?BankB30Reg:BankA30Reg;
+ assign Data31Reg = (DataOutSel)?BankB31Reg:BankA31Reg;
+ assign Data32Reg = (DataOutSel)?BankB32Reg:BankA32Reg;
+ assign Data33Reg = (DataOutSel)?BankB33Reg:BankA33Reg;
+ assign Data34Reg = (DataOutSel)?BankB34Reg:BankA34Reg;
+ assign Data35Reg = (DataOutSel)?BankB35Reg:BankA35Reg;
+ assign Data36Reg = (DataOutSel)?BankB36Reg:BankA36Reg;
+ assign Data37Reg = (DataOutSel)?BankB37Reg:BankA37Reg;
+ assign Data38Reg = (DataOutSel)?BankB38Reg:BankA38Reg;
+ assign Data39Reg = (DataOutSel)?BankB39Reg:BankA39Reg;
+ assign Data40Reg = (DataOutSel)?BankB40Reg:BankA40Reg;
+ assign Data41Reg = (DataOutSel)?BankB41Reg:BankA41Reg;
+ assign Data42Reg = (DataOutSel)?BankB42Reg:BankA42Reg;
+ assign Data43Reg = (DataOutSel)?BankB43Reg:BankA43Reg;
+ assign Data44Reg = (DataOutSel)?BankB44Reg:BankA44Reg;
+ assign Data45Reg = (DataOutSel)?BankB45Reg:BankA45Reg;
+ assign Data46Reg = (DataOutSel)?BankB46Reg:BankA46Reg;
+ assign Data47Reg = (DataOutSel)?BankB47Reg:BankA47Reg;
+ assign Data48Reg = (DataOutSel)?BankB48Reg:BankA48Reg;
+ assign Data49Reg = (DataOutSel)?BankB49Reg:BankA49Reg;
+ assign Data50Reg = (DataOutSel)?BankB50Reg:BankA50Reg;
+ assign Data51Reg = (DataOutSel)?BankB51Reg:BankA51Reg;
+ assign Data52Reg = (DataOutSel)?BankB52Reg:BankA52Reg;
+ assign Data53Reg = (DataOutSel)?BankB53Reg:BankA53Reg;
+ assign Data54Reg = (DataOutSel)?BankB54Reg:BankA54Reg;
+ assign Data55Reg = (DataOutSel)?BankB55Reg:BankA55Reg;
+ assign Data56Reg = (DataOutSel)?BankB56Reg:BankA56Reg;
+ assign Data57Reg = (DataOutSel)?BankB57Reg:BankA57Reg;
+ assign Data58Reg = (DataOutSel)?BankB58Reg:BankA58Reg;
+ assign Data59Reg = (DataOutSel)?BankB59Reg:BankA59Reg;
+ assign Data60Reg = (DataOutSel)?BankB60Reg:BankA60Reg;
+ assign Data61Reg = (DataOutSel)?BankB61Reg:BankA61Reg;
+ assign Data62Reg = (DataOutSel)?BankB62Reg:BankA62Reg;
+ assign Data63Reg = (DataOutSel)?BankB63Reg:BankA63Reg;
+
+endmodule // jpeg_ziguzagu
Index: djpeg/trunk/readme.txt
===================================================================
--- djpeg/trunk/readme.txt (nonexistent)
+++ djpeg/trunk/readme.txt (revision 6)
@@ -0,0 +1,14 @@
+JPEG Decoder
+
+[Product Name] JPEG Decoder
+[Update Date ] 2007/04/18
+[Version ] Ver 1.03
+[License ] LGPL
+[Langage ] Verilog
+[Author ] Hidemi Ishihara(E-Mail:hidemi@sweetcafe.jp)
+
+Specification for Japanese
+http://claude.sweetcafe.jp//index.php?option=com_content&task=view&id=38&Itemid=88888896
+
+Specification for English
+http://translate.google.com/translate?u=http%3A%2F%2Fclaude.sweetcafe.jp%2F%2Findex.php%3Foption%3Dcom_content%26task%3Dview%26id%3D38%26Itemid%3D88888896&langpair=ja%7Cen&hl=ja&ie=UTF-8&oe=UTF-8&prev=%2Flanguage_tools
Index: djpeg/trunk/c_model/djpeg.c
===================================================================
--- djpeg/trunk/c_model/djpeg.c (nonexistent)
+++ djpeg/trunk/c_model/djpeg.c (revision 6)
@@ -0,0 +1,787 @@
+//////////////////////////////////////////////////////////////////////////////
+// JPEGデコード
+// 2005年10月26日 V1.0
+// All Rights Reserved, Copyright (c) Hidemi Ishihara
+//////////////////////////////////////////////////////////////////////////////
+//
+// JPEGを入力するとBitmapを出力します。
+//
+// % gcc -o djpeg fjpeg.c
+// % djpeg 入力ファイル名 出力ファイル名
+//////////////////////////////////////////////////////////////////////////////
+#include
+#include
+
+unsigned int BuffIndex; // JPEGデータの位置
+unsigned int BuffSize; // JPEGデータの大きさ
+unsigned int BuffX; // 画像の横サイズ
+unsigned int BuffY; // 画像の縦サイズ
+unsigned int BuffBlockX; // MCUの横個数
+unsigned int BuffBlockY; // MCUの縦個数
+unsigned char *Buff; // 伸長したデータを入れるバッファ
+
+unsigned char TableDQT[4][64]; // 量子化テーブル
+unsigned short TableDHT[4][162]; // ハフマンテーブル
+
+unsigned short TableHT[4][16]; // ハフマンスタートテーブル
+unsigned char TableHN[4][16]; // ハフマンスタート番号
+
+unsigned char BitCount = 0; // 圧縮データの読み込み位置
+unsigned int LineData; // 伸長に使うデータ
+unsigned int NextData; // 伸長に使うデータ
+
+unsigned int PreData[3]; // DC成分用の貯めバッファ
+
+// ジグザグテーブル
+int zigzag_table[]={
+ 0, 1, 8, 16,9, 2, 3,10,
+ 17,24,32,25,18,11, 4, 5,
+ 12,19,26,33,40,48,41,34,
+ 27,20,13, 6, 7,14,21,28,
+ 35,42,49,56,57,50,43,36,
+ 29,22,15,23,30,37,44,51,
+ 58,59,52,45,38,31,39,46,
+ 53,60,61,54,47,55,62,63,
+ 0
+};
+
+typedef unsigned short WORD;
+typedef unsigned long DWORD;
+typedef long LONG;
+
+typedef struct tagBITMAPFILEHEADER {
+ WORD bfType;
+ DWORD bfSize;
+ WORD bfReserved1;
+ WORD bfReserved2;
+ DWORD bfOffBits;
+} BITMAPFILEHEADER, *PBITMAPFILEHEADER;
+
+typedef struct tagBITMAPINFOHEADER{
+ DWORD biSize;
+ LONG biWidth;
+ LONG biHeight;
+ WORD biPlanes;
+ WORD biBitCount;
+ DWORD biCompression;
+ DWORD biSizeImage;
+ LONG biXPelsPerMeter;
+ LONG biYPelsPerMeter;
+ DWORD biClrUsed;
+ DWORD biClrImportant;
+} BITMAPINFOHEADER, *PBITMAPINFOHEADER;
+
+//////////////////////////////////////////////////////////////////////////////
+// Bitmapを出力する
+// file: ファイル名
+// x,y: 画像のサイズ
+// b: バイトカウント(1ドット辺りのバイト数)
+//////////////////////////////////////////////////////////////////////////////
+void BmpSave(unsigned char *file,unsigned char *buff,
+ unsigned int x,unsigned int y,unsigned int b){
+ BITMAPFILEHEADER lpBf;
+ BITMAPINFOHEADER lpBi;
+ unsigned char tbuff[4];
+ FILE *fp;
+ unsigned char str;
+ int i,k;
+
+ if((fp = fopen(file,"wb")) == NULL){
+ perror(0);
+ exit(0);
+ }
+
+ // ファイルヘッダの設定
+ tbuff[0] = 'B';
+ tbuff[1] = 'M';
+ fwrite(tbuff,2,1,fp);
+ tbuff[3] = ((14 +40 +x *y *b) >> 24) & 0xff;
+ tbuff[2] = ((14 +40 +x *y *b) >> 16) & 0xff;
+ tbuff[1] = ((14 +40 +x *y *b) >> 8) & 0xff;
+ tbuff[0] = ((14 +40 +x *y *b) >> 0) & 0xff;
+ fwrite(tbuff,4,1,fp);
+ tbuff[1] = 0;
+ tbuff[0] = 0;
+ fwrite(tbuff,2,1,fp);
+ fwrite(tbuff,2,1,fp);
+ tbuff[3] = 0;
+ tbuff[2] = 0;
+ tbuff[1] = 0;
+ tbuff[0] = 54;
+ fwrite(tbuff,4,1,fp);
+
+ // インフォメーションの設定
+ lpBi.biSize = 40;
+ lpBi.biWidth = x;
+ lpBi.biHeight = y;
+ lpBi.biPlanes = 1;
+ lpBi.biBitCount = b*8;
+ lpBi.biCompression = 0;
+ lpBi.biSizeImage = x*y*b;
+ lpBi.biXPelsPerMeter = 300;
+ lpBi.biYPelsPerMeter = 300;
+ lpBi.biClrUsed = 0;
+ lpBi.biClrImportant = 0;
+ fwrite(&lpBi,1,40,fp);
+
+ // 上下反転
+ for(k=0;k= BuffSize) return 0;
+ return buff[BuffIndex++];
+}
+//////////////////////////////////////////////////////////////////////////////
+// 2Byte取得
+unsigned short get_word(unsigned char *buff){
+ unsigned char h,l;
+ h = get_byte(buff);
+ l = get_byte(buff);
+ return (h<<8)|l;
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// 32bitデータ取得(伸長時のみ使用する)
+unsigned int get_data(unsigned char *buff){
+ unsigned char str = 0;
+ unsigned int data = 0;
+ str = get_byte(buff);
+ if(str ==0xff) if(get_byte(buff)== 0x00) str = 0xFF; else str = 0x00;
+ data = str;
+ str = get_byte(buff);
+ if(str ==0xff) if(get_byte(buff)== 0x00) str = 0xFF; else str = 0x00;
+ data = (data << 8) | str;
+ str = get_byte(buff);
+ if(str ==0xff) if(get_byte(buff)== 0x00) str = 0xFF; else str = 0x00;
+ data = (data << 8) | str;
+ str = get_byte(buff);
+ if(str ==0xff) if(get_byte(buff)== 0x00) str = 0xFF; else str = 0x00;
+ data = (data << 8) | str;
+ //printf(" Get Data: %08x\n",data);
+ return data;
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// APP0処理
+void GetAPP0(unsigned char *buff){
+ unsigned short data;
+ unsigned char str;
+ unsigned int i;
+
+ data = get_word(buff); // Lp(レングス)
+ // APP0は読まなくてもいいので取り合えずレングス分スキップする
+ for(i=0;i> 1; // 右に1bitシフトする
+ }
+
+ //printf("*** DHT Table %d\n",tablenum);
+ for(i=0;i0) BuffBlockX++;
+ BuffBlockY = (int)(BuffY /16);
+ if(BuffY % 16 >0) BuffBlockY++;
+ Buff = (unsigned char*)malloc(BuffBlockY*16*BuffBlockX*16*3);
+
+ //printf(" size : %d x %d,(%d x %d)\n",BuffX,BuffY,BuffBlockX,BuffBlockY);
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// SOS処理
+void GetSOS(unsigned char *buff){
+ unsigned short data;
+ unsigned char str;
+ unsigned int i;
+ unsigned char count;
+
+ data = get_word(buff);
+ count = get_byte(buff);
+ for(i=0;i=32){
+ LineData = NextData;
+ NextData = get_data(buff);
+ BitCount -= 32;
+ }
+ // Huffmanデコードで使用するデータに置き換える
+ if(BitCount >0){
+ BitData = (LineData << BitCount) | (NextData >> (32 - BitCount));
+ }else{
+ BitData = LineData;
+ }
+ //printf(" Haffuman BitData(%2d,%2d): %8x\n",table,count,BitData);
+
+ // 使用するテーブルのセレクト
+ if(count ==0) tablen = tabledc; else tablen = tableac;
+ code = (unsigned short)(BitData >> 16); // コードは16ビット使用する
+ // ハフマンコードがどのビット数にいるか割り出す
+ for(i=0;i<16;i++) {
+ //printf(" Haff hit(%2d:%2d): %8x,%8x\n",table,i,TableHT[tablen][i],code);
+ if(TableHT[tablen][i]>code) break;
+ }
+ i--;
+
+ code = (unsigned short)(code >> (15 - i)); // コードの下位を揃える
+ huffman = (unsigned short)(TableHT[tablen][i] >> (15 - i));
+
+ //printf(" PreUse Dht Number(%2d): %8x,%8x,%8x\n",i,code,huffman,TableHN[tablen][i]);
+
+ // ハフマンテーブルの場所を算出する
+ code = code - huffman + TableHN[tablen][i];
+
+ //printf(" Use Dht Number: %8x\n",code);
+
+ ZeroCount = (TableDHT[tablen][code] >> 4) & 0x0F; // ゼロレングスの個数
+ DataCount = (TableDHT[tablen][code]) & 0x0F; // 続くデータのビット長
+ //printf(" Dht Table: %8x,%8x\n",ZeroCount,DataCount);
+ // ハフマンコードを抜き、続くデータを取得する
+ DataCode = (BitData << (i + 1)) >> (16 + (16 - DataCount));
+ // 先頭ビットが"0"であれば負のデータ、上位ビットに１を立てて、１を足す
+ //if(!(DataCode & (1<<(DataCount-1)))) DataCode=DataCode-(1<> 11;
+ *BlockIn++ = (t1 + s6) >> 11;
+ *BlockIn++ = (t2 + s5) >> 11;
+ *BlockIn++ = (t3 + t4) >> 11;
+ *BlockIn++ = (t3 - t4) >> 11;
+ *BlockIn++ = (t2 - s5) >> 11;
+ *BlockIn++ = (t1 - s6) >> 11;
+ *BlockIn++ = (t0 - t7) >> 11;
+ }
+
+ BlockIn -= 64;
+
+ /*
+ printf("-----------------------------\n");
+ printf(" iDCT(Middle)\n");
+ printf("-----------------------------\n");
+ for(i=0;i<64;i++){
+ printf("%2d: %8x\n",i,BlockIn[i]);
+ }
+ */
+
+ for(i=0;i<8;i++){
+ s0 = (BlockIn[ 0] + BlockIn[32]) * C4_16;
+ s1 = (BlockIn[ 0] - BlockIn[32]) * C4_16;
+ s3 = BlockIn[16] * C2_16 + BlockIn[48] * C6_16;
+ s2 = BlockIn[16] * C6_16 - BlockIn[48] * C2_16;
+ s7 = BlockIn[ 8] * C1_16 + BlockIn[56] * C7_16;
+ s4 = BlockIn[ 8] * C7_16 - BlockIn[56] * C1_16;
+ s6 = BlockIn[40] * C5_16 + BlockIn[24] * C3_16;
+ s5 = BlockIn[40] * C3_16 - BlockIn[24] * C5_16;
+
+ /*
+ printf("s0:%8x\n",s0);
+ printf("s1:%8x\n",s1);
+ printf("s2:%8x\n",s2);
+ printf("s3:%8x\n",s3);
+ printf("s4:%8x\n",s4);
+ printf("s5:%8x\n",s5);
+ printf("s6:%8x\n",s6);
+ printf("s7:%8x\n",s7);
+ */
+
+ t0 = s0 + s3;
+ t1 = s1 + s2;
+ t2 = s1 - s2;
+ t3 = s0 - s3;
+ t4 = s4 + s5;
+ t5 = s4 - s5;
+ t6 = s7 - s6;
+ t7 = s6 + s7;
+
+ /*
+ printf("t0:%8x\n",t0);
+ printf("t1:%8x\n",t1);
+ printf("t2:%8x\n",t2);
+ printf("t3:%8x\n",t3);
+ printf("t4:%8x\n",t4);
+ printf("t5:%8x\n",t5);
+ printf("t6:%8x\n",t6);
+ printf("t7:%8x\n",t7);
+ */
+
+ s5 = (t6 - t5) * 181 / 256; // 1/sqrt(2)
+ s6 = (t5 + t6) * 181 / 256; // 1/sqrt(2)
+
+ /*
+ printf("s5:%8x\n",s5);
+ printf("s6:%8x\n",s6);
+ */
+
+ BlockOut[ 0] = ((t0 + t7) >> 15);
+ BlockOut[56] = ((t0 - t7) >> 15);
+ BlockOut[ 8] = ((t1 + s6) >> 15);
+ BlockOut[48] = ((t1 - s6) >> 15);
+ BlockOut[16] = ((t2 + s5) >> 15);
+ BlockOut[40] = ((t2 - s5) >> 15);
+ BlockOut[24] = ((t3 + t4) >> 15);
+ BlockOut[32] = ((t3 - t4) >> 15);
+
+ BlockIn++;
+ BlockOut++;
+ }
+ BlockOut-=8;
+ /*
+ printf("-----------------------------\n");
+ printf(" iDCT(Out)\n");
+ printf("-----------------------------\n");
+ for(i=0;i<8;i++){
+ printf(" %2d: %04x;\n",i+ 0,BlockOut[i+ 0]&0xFFFF);
+ printf(" %2d: %04x;\n",i+56,BlockOut[i+56]&0xFFFF);
+ printf(" %2d: %04x;\n",i+ 8,BlockOut[i+ 8]&0xFFFF);
+ printf(" %2d: %04x;\n",i+48,BlockOut[i+48]&0xFFFF);
+ printf(" %2d: %04x;\n",i+16,BlockOut[i+16]&0xFFFF);
+ printf(" %2d: %04x;\n",i+40,BlockOut[i+40]&0xFFFF);
+ printf(" %2d: %04x;\n",i+24,BlockOut[i+24]&0xFFFF);
+ printf(" %2d: %04x;\n",i+32,BlockOut[i+32]&0xFFFF);
+ }
+ */
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// 4:1:1のデコード処理
+void Decode411(unsigned char *buff, int *BlockY, int *BlockCb, int *BlockCr){
+ int BlockHuffman[64];
+ int BlockYLT[64];
+ int BlockYRT[64];
+ int BlockYLB[64];
+ int BlockYRB[64];
+ unsigned int i;
+
+ // 輝度(左上)
+ //printf("Block:00\n");
+ HuffmanDecode(buff,0x00,BlockHuffman);
+ DctDecode(BlockHuffman,BlockYLT);
+ // 輝度(右上)
+ //printf("Block:02\n");
+ HuffmanDecode(buff,0x00,BlockHuffman);
+ DctDecode(BlockHuffman,BlockYRT);
+ // 輝度(左下)
+ //printf("Block:03\n");
+ HuffmanDecode(buff,0x00,BlockHuffman);
+ DctDecode(BlockHuffman,BlockYLB);
+ // 輝度(右下)
+ //printf("Block:04\n");
+ HuffmanDecode(buff,0x00,BlockHuffman);
+ DctDecode(BlockHuffman,BlockYRB);
+ // 青色差
+ //printf("Block:10\n");
+ HuffmanDecode(buff,0x01,BlockHuffman);
+ DctDecode(BlockHuffman,BlockCb);
+ // 赤色差
+ //printf("Block:11\n");
+ HuffmanDecode(buff,0x02,BlockHuffman);
+ DctDecode(BlockHuffman,BlockCr);
+
+ // ブロックサイズを16x16にする
+ for(i=0;i<64;i++){
+ BlockY[(int)(i/8) *16 +(i % 8)] = BlockYLT[i];
+ BlockY[(int)(i/8) *16 +(i % 8)+8] = BlockYRT[i];
+ BlockY[(int)(i/8) *16 +(i % 8)+128] = BlockYLB[i];
+ BlockY[(int)(i/8) *16 +(i % 8)+128+8] = BlockYRB[i];
+ }
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// YUV→RGBに変換
+void DecodeYUV(int *y, int *cb, int *cr, unsigned char *rgb){
+ int r,g,b;
+ int p,i;
+
+ //printf("----RGB----\n");
+ for(i=0;i<256;i++){
+ p = ((int)(i/32) * 8) + ((int)((i % 16)/2));
+ r = 128 + y[i] + cr[p]*1.402;
+ r = (r & 0xffffff00) ? (r >> 24) ^ 0xff : r;
+ g = 128 + y[i] - cb[p]*0.34414 - cr[p]*0.71414;
+ g = (g & 0xffffff00) ? (g >> 24) ^ 0xff : g;
+ b = 128 + y[i] + cb[p]*1.772;
+ b = (b & 0xffffff00) ? (b >> 24) ^ 0xff : b;
+ rgb[i*3+0] = b;
+ rgb[i*3+1] = g;
+ rgb[i*3+2] = r;
+ /*
+ printf("[RGB]%3d: %3x,%3x,%3x = %2x,%2x,%2x\n",i,
+ y[i]&0x1FF,cr[p]&0x1FF,cb[p]&0x1FF,
+ rgb[i*3+2],rgb[i*3+1],rgb[i*3+0]);
+ */
+ }
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// イメージのデコード
+void Decode(unsigned char *buff,unsigned char *rgb){
+ int BlockY[256];
+ int BlockCb[256];
+ int BlockCr[256];
+ int x,y,i,p;
+
+ for(y=0;y= BuffSize)){
+ if(Image ==0){
+ data = get_word(buff);
+ switch(data){
+ case 0xFFD8: // SOI
+ break;
+ case 0xFFE0: // APP0
+ GetAPP0(buff);
+ break;
+ case 0xFFDB: // DQT
+ GetDQT(buff);
+ break;
+ case 0xFFC4: // DHT
+ GetDHT(buff);
+ break;
+ case 0xFFC0: // SOF
+ GetSOF(buff);
+ break;
+ case 0xFFDA: // SOS
+ GetSOS(buff);
+ Image = 1;
+ // データの準備
+ PreData[0] = 0x00;
+ PreData[1] = 0x00;
+ PreData[2] = 0x00;
+ LineData = get_data(buff);
+ NextData = get_data(buff);
+ BitCount =0;
+ break;
+ case 0xFFD9: // EOI
+ break;
+ default:
+ // 判別できないヘッダーは読み飛ばす
+ if((data & 0xFF00) == 0xFF00 && !(data == 0xFF00)){
+ data = get_word(buff);
+ for(i=0;i
djpeg/trunk/image/test.jpg
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: djpeg/trunk
===================================================================
--- djpeg/trunk (nonexistent)
+++ djpeg/trunk (revision 6)
djpeg/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: djpeg/web_uploads
===================================================================
--- djpeg/web_uploads (nonexistent)
+++ djpeg/web_uploads (revision 6)
djpeg/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: djpeg/branches
===================================================================
--- djpeg/branches (nonexistent)
+++ djpeg/branches (revision 6)
djpeg/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: djpeg/tags
===================================================================
--- djpeg/tags (nonexistent)
+++ djpeg/tags (revision 6)
djpeg/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##