URL
https://opencores.org/ocsvn/ffr16/ffr16/trunk
Subversion Repositories ffr16
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/sources/fpu/050803KN/FAT16RD.PSM
93,9 → 93,9
;-- |
;-- REGISTERS INITIALIZATION |
;-- |
inicialization: |
initialization: |
; |
; WISHBONE INTERFACES INIZIALIZATION |
; WISHBONE INTERFACES INITIALIZATION |
; |
LOAD sF,00 |
OUTPUT sF,DATA_WB_OUT_7_0_MASTER |
/trunk/sources/fpu/050803KN/compile/FAT16RD.PSM
1,5 → 1,5
; FAT16 READER V.050303 - Armando Astarloa - 16 BIT VER. |
; APERT - UPV/EHU 2003 - DISTRIBUTED UNDER GPL LICENCE |
; APERT - UPV/EHU 2003 - DISTRIBUTED UNDER GPL LICENSE |
; |
; s0 -> TMP0 s1 -> TMP1 s2 -> TMP2 s3 -> TMP3 s4 -> TMP4 / SECTORS_PER_CLUSTER_READED s5 -> TMP5/SECTOR_WORDS_READED (256 TO 0) |
; s6 -> TMP s7 -> SECTORS_PER_CLUSTER s8 -> CLUSTER_BEGIN_LBA0 (FAT) s9 -> CLUSTER_BEGIN_LBA1 sA -> CLUSTER_BEGIN_LBA2 |
93,9 → 93,9
;-- |
;-- REGISTERS INITIALIZATION |
;-- |
inicialization: |
initialization: |
; |
; WISHBONE INTERFACES INIZIALIZATION |
; WISHBONE INTERFACES INITIALIZATION |
; |
LOAD sF,00 |
OUTPUT sF,DATA_WB_OUT_7_0_MASTER |
/trunk/sources/hau/240603KN/compile/cfreader.psm
204,7 → 204,7
;-- |
;-- REGISTERS INITIALIZATION |
;-- |
inicialization: |
initialization: |
; |
; BUS CONTROL : WRITE NOT ENABLE |
; |
211,7 → 211,7
LOAD sF,00 |
OUTPUT sF,CONTROL_OUT |
; |
; WISHBONE BUS INIZIALIZATION |
; WISHBONE BUS INITIALIZATION |
; |
LOAD sF,00 |
OUTPUT sF,DATA_WB_OUT_7_0 |
218,7 → 218,7
OUTPUT sF,DATA_WB_OUT_15_8 |
OUTPUT sF,CONTROL_WB_OUT |
; |
; IDE BUS INICIALIZATION |
; IDE BUS INITIALIZATION |
; |
LOAD sF,00 |
OUTPUT sF,DATA_IDE_OUT_7_0 |
688,7 → 688,7
CALL soft_reset |
LOAD s5,ERROR_MY_STATUS |
RETURN |
;JUMP inicialization (STACK OVERFLOW???) |
;JUMP initialization (STACK OVERFLOW???) |
|
soft_reset: |
LOAD sD,SOFT_RESET |
/trunk/sources/hau/240603KN/cfreader.psm
204,7 → 204,7
;-- |
;-- REGISTERS INITIALIZATION |
;-- |
inicialization: |
initialization: |
; |
; BUS CONTROL : WRITE NOT ENABLE |
; |
211,7 → 211,7
LOAD sF,00 |
OUTPUT sF,CONTROL_OUT |
; |
; WISHBONE BUS INIZIALIZATION |
; WISHBONE BUS INITIALIZATION |
; |
LOAD sF,00 |
OUTPUT sF,DATA_WB_OUT_7_0 |
218,7 → 218,7
OUTPUT sF,DATA_WB_OUT_15_8 |
OUTPUT sF,CONTROL_WB_OUT |
; |
; IDE BUS INICIALIZATION |
; IDE BUS INITIALIZATION |
; |
LOAD sF,00 |
OUTPUT sF,DATA_IDE_OUT_7_0 |
688,7 → 688,7
CALL soft_reset |
LOAD s5,ERROR_MY_STATUS |
RETURN |
;JUMP inicialization (STACK OVERFLOW???) |
;JUMP initialization (STACK OVERFLOW???) |
|
soft_reset: |
LOAD sD,SOFT_RESET |