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URL https://opencores.org/ocsvn/fpu/fpu/trunk

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Rev 5 → Rev 6

/trunk/FPU.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/test_vectors/mkall.bat
184,3 → 184,171
pg -q -m 15 -R -n 499995 -ll -o combo/fpu_combo1.hex
 
pg -q -m 15 -R -n 499995 -s 17 -o combo/fpu_combo2.hex
 
pg -q -m 63 -R -n 499995 -ll -s 7 -o combo/fpu_combo3.hex
 
pg -q -m 63 -R -n 499995 -s 255 -o combo/fpu_combo4.hex
 
 
 
rem -------------------- i2f round to nearest even
 
pg -q -r 0 -m 16 -p 0 -o rtne/i2f_pat0.hex
 
pg -q -r 0 -m 16 -p 1 -o rtne/i2f_pat1.hex
 
pg -q -r 0 -m 16 -p 2 -o rtne/i2f_pat2.hex
 
pg -q -r 0 -m 16 -n 199990 -ll -o rtne/i2f_lg.hex
 
pg -q -r 0 -m 16 -n 199990 -o rtne/i2f_sm.hex
 
 
rem -------------------- i2f round to zero
 
pg -q -r 3 -m 16 -p 0 -o rtzero/i2f_pat0.hex
 
pg -q -r 3 -m 16 -p 1 -o rtzero/i2f_pat1.hex
 
pg -q -r 3 -m 16 -p 2 -o rtzero/i2f_pat2.hex
 
pg -q -r 3 -m 16 -n 199990 -ll -o rtzero/i2f_lg.hex
 
pg -q -r 3 -m 16 -n 199990 -o rtzero/i2f_sm.hex
 
 
 
rem -------------------- i2f round to inf + (up)
 
pg -q -r 2 -m 16 -p 0 -o rup/i2f_pat0.hex
 
pg -q -r 2 -m 16 -p 1 -o rup/i2f_pat1.hex
 
pg -q -r 2 -m 16 -p 2 -o rup/i2f_pat2.hex
 
pg -q -r 2 -m 16 -n 199990 -ll -o rup/i2f_lg.hex
 
pg -q -r 2 -m 16 -n 199990 -o rup/i2f_sm.hex
 
 
 
rem -------------------- i2f round to inf - (down)
 
pg -q -r 1 -m 16 -p 0 -o rdown/i2f_pat0.hex
 
pg -q -r 1 -m 16 -p 1 -o rdown/i2f_pat1.hex
 
pg -q -r 1 -m 16 -p 2 -o rdown/i2f_pat2.hex
 
pg -q -r 1 -m 16 -n 199990 -ll -o rdown/i2f_lg.hex
 
pg -q -r 1 -m 16 -n 199990 -o rdown/i2f_sm.hex
 
 
 
rem -------------------- f2i round to nearest even
 
pg -q -r 0 -m 32 -p 0 -o rtne/f2i_pat0.hex
 
pg -q -r 0 -m 32 -p 1 -o rtne/f2i_pat1.hex
 
pg -q -r 0 -m 32 -p 2 -o rtne/f2i_pat2.hex
 
pg -q -r 0 -m 32 -n 199990 -ll -o rtne/f2i_lg.hex
 
pg -q -r 0 -m 32 -n 199990 -o rtne/f2i_sm.hex
 
 
rem -------------------- f2i round to zero
 
pg -q -r 3 -m 32 -p 0 -o rtzero/f2i_pat0.hex
 
pg -q -r 3 -m 32 -p 1 -o rtzero/f2i_pat1.hex
 
pg -q -r 3 -m 32 -p 2 -o rtzero/f2i_pat2.hex
 
pg -q -r 3 -m 32 -n 199990 -ll -o rtzero/f2i_lg.hex
 
pg -q -r 3 -m 32 -n 199990 -o rtzero/f2i_sm.hex
 
 
 
rem -------------------- f2i round to inf + (up)
 
pg -q -r 2 -m 32 -p 0 -o rup/f2i_pat0.hex
 
pg -q -r 2 -m 32 -p 1 -o rup/f2i_pat1.hex
 
pg -q -r 2 -m 32 -p 2 -o rup/f2i_pat2.hex
 
pg -q -r 2 -m 32 -n 199990 -ll -o rup/f2i_lg.hex
 
pg -q -r 2 -m 32 -n 199990 -o rup/f2i_sm.hex
 
 
 
rem -------------------- f2i round to inf - (down)
 
pg -q -r 1 -m 32 -p 0 -o rdown/f2i_pat0.hex
 
pg -q -r 1 -m 32 -p 1 -o rdown/f2i_pat1.hex
 
pg -q -r 1 -m 32 -p 2 -o rdown/f2i_pat2.hex
 
pg -q -r 1 -m 32 -n 199990 -ll -o rdown/f2i_lg.hex
 
pg -q -r 1 -m 32 -n 199990 -o rdown/f2i_sm.hex
 
 
rem -------------------- frem round to nearest even
 
pg -q -r 0 -m 64 -p 0 -o rtne/frem_pat0.hex
 
pg -q -r 0 -m 64 -p 1 -o rtne/frem_pat1.hex
 
pg -q -r 0 -m 64 -p 2 -o rtne/frem_pat2.hex
 
pg -q -r 0 -m 64 -n 199990 -ll -o rtne/frem_lg.hex
 
pg -q -r 0 -m 64 -n 199990 -o rtne/frem_sm.hex
 
 
rem -------------------- frem round to zero
 
pg -q -r 3 -m 64 -p 0 -o rtzero/frem_pat0.hex
 
pg -q -r 3 -m 64 -p 1 -o rtzero/frem_pat1.hex
 
pg -q -r 3 -m 64 -p 2 -o rtzero/frem_pat2.hex
 
pg -q -r 3 -m 64 -n 199990 -ll -o rtzero/frem_lg.hex
 
pg -q -r 3 -m 64 -n 199990 -o rtzero/frem_sm.hex
 
 
 
rem -------------------- frem round to inf + (up)
 
pg -q -r 2 -m 64 -p 0 -o rup/frem_pat0.hex
 
pg -q -r 2 -m 64 -p 1 -o rup/frem_pat1.hex
 
pg -q -r 2 -m 64 -p 2 -o rup/frem_pat2.hex
 
pg -q -r 2 -m 64 -n 199990 -ll -o rup/frem_lg.hex
 
pg -q -r 2 -m 64 -n 199990 -o rup/frem_sm.hex
 
 
 
rem -------------------- frem round to inf - (down)
 
pg -q -r 1 -m 64 -p 0 -o rdown/frem_pat0.hex
 
pg -q -r 1 -m 64 -p 1 -o rdown/frem_pat1.hex
 
pg -q -r 1 -m 64 -p 2 -o rdown/frem_pat2.hex
 
pg -q -r 1 -m 64 -n 199990 -ll -o rdown/frem_lg.hex
 
pg -q -r 1 -m 64 -n 199990 -o rdown/frem_sm.hex
/trunk/test_vectors/pg.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/test_vectors/pg-src/fptpg.c
49,8 → 49,6
{
int i;
int count=25;
int do_i2f=0;
int do_f2i=0;
int ar = 0;
int seed = 12345678;
 
74,14 → 72,15
printf(" 1 = float_round_down\n");
printf(" 2 = float_round_up\n");
printf(" 3 = float_round_to_zero\n");
printf(" -i2f Generate Integer to Floating Point Conv. Vectors.\n");
printf(" -f2i Generate Floating Point to Integer Conv. Vectors.\n");
printf(" -m N Generate Test patters for operation N.\n");
printf(" Where N is a combination of:\n");
printf(" 1 = Add operations\n");
printf(" 2 = Subtract Operations\n");
printf(" 4 = Multiply Operations\n");
printf(" 8 = Divide operations\n");
printf(" 1 = Add operations\n");
printf(" 2 = Subtract Operations\n");
printf(" 4 = Multiply Operations\n");
printf(" 8 = Divide operations\n");
printf(" 16 = Integer to Floating Point Conversion\n");
printf(" 32 = Floating Point to Integer Conversion\n");
printf(" 64 = Remainder Function\n");
printf(" -s N Use N as seed for rand() functions.\n");
printf(" -R Randomize rounding mode.\n");
return(0);
91,10 → 90,6
 
while((argc-1)>=i) {
 
if(strcmp(argv[i],"-i2f")==0) do_i2f=1;
else
if(strcmp(argv[i],"-f2i")==0) do_f2i=1;
else
if(strcmp(argv[i],"-v")==0) verb=1;
else
if(strcmp(argv[i],"-q")==0) quiet=1;
152,7 → 147,7
srand( seed );
 
if(!quiet) {
printf("\n Floating Point Test Vector Generation V1.5\n");
printf("\n Floating Point Test Vector Generation V1.6\n");
printf("\t by Rudolf Usselmann rudi@asics.ws\n\n");
 
switch(float_rounding_mode) {
166,16 → 161,27
}
 
if(count==25) {
if(pat==1) count = 92416;
else
if(pat==2) count = 92416;
else
if(pat==3) count = 15376;
 
if( (ar & 0x10) | (ar & 0x20) ) {
 
if(pat==1) count = 304;
else
if(pat==2) count = 304;
else
if(pat==3) count = 124;
 
} else {
 
if(pat==1) count = 92416;
else
if(pat==2) count = 92416;
else
if(pat==3) count = 15376;
 
}
 
}
 
if(do_i2f) i2f(count);
if(do_f2i) f2i(count);
if(ar) arop(count,ar);
 
return(0);
191,9 → 197,13
int sub=0;
int mul=0;
int div=0;
int i2f=0;
int f2i=0;
int rem=0;
int oper;
int err;
int err_count=0;
int tmp;
 
if(!quiet) printf("\nGenerating %0d Arithmetic test vectors ...\n",count);
 
208,16 → 218,22
}
 
if(!quiet) {
if(op & 0x1) printf("Add OP\n");
if(op & 0x2) printf("Sub OP\n");
if(op & 0x4) printf("Mul OP\n");
if(op & 0x8) printf("Div OP\n");
if(op & 0x01) printf("Add OP\n");
if(op & 0x02) printf("Sub OP\n");
if(op & 0x04) printf("Mul OP\n");
if(op & 0x08) printf("Div OP\n");
if(op & 0x10) printf("int2float\n");
if(op & 0x20) printf("float2int\n");
if(op & 0x40) printf("Remainder\n");
}
 
if(op & 0x1) add=1;
if(op & 0x2) sub=1;
if(op & 0x4) mul=1;
if(op & 0x8) div=1;
if(op & 0x01) add=1;
if(op & 0x02) sub=1;
if(op & 0x04) mul=1;
if(op & 0x08) div=1;
if(op & 0x10) i2f=1;
if(op & 0x20) f2i=1;
if(op & 0x40) rem=1;
 
f1 = get_pat(0); // Initialize pattern generator ...
 
239,10 → 255,39
 
oper = -1;
while(oper == -1) {
float_exception_flags = 0; // Reset Exceptions
float_exception_flags = 0; // Reset Exceptions
 
if( (rand() % 4)==3 & div) {
oper = 8;
if( (rand() % 8)==6 & rem) {
oper = 0x40;
f3 = float32_rem( f1, f2 );
float_exception_flags = 0; // Reset Exceptions
f3 = float32_rem( f1, f2 );
}
 
if( (rand() % 8)==5 & f2i) {
oper = 0x20;
f3 = float32_to_int32( f1 );
float_exception_flags = 0; // Reset Exceptions
f3 = float32_to_int32( f1 );
f2 = 0;
}
 
if( (rand() % 8)==4 & i2f) {
oper = 0x10;
 
 
tmp = (int) f1;
 
 
f3 = int32_to_float32( tmp );
float_exception_flags = 0; // Reset Exceptions
f3 = int32_to_float32( tmp );
f2 =0;
}
 
 
if( (rand() % 8)==3 & div) {
oper = 0x08;
f3 = float32_div( f1, f2);
float_exception_flags = 0; // Reset Exceptions
f3 = float32_div( f1, f2);
254,8 → 299,8
// }
}
 
if( (rand() % 4)==2 & mul) {
oper = 4;
if( (rand() % 8)==2 & mul) {
oper = 0x04;
f3 = float32_mul( f1, f2);
float_exception_flags = 0; // Reset Exceptions
f3 = float32_mul( f1, f2);
267,8 → 312,8
// }
}
 
if( (rand() % 4)==1 & sub) {
oper = 2;
if( (rand() % 8)==1 & sub) {
oper = 0x02;
f3 = float32_sub( f1, f2);
float_exception_flags = 0; // Reset Exceptions
f3 = float32_sub( f1, f2);
280,8 → 325,8
// }
}
 
if( (rand() % 4)==0 & add) {
oper = 1;
if( (rand() % 8)==0 & add) {
oper = 0x01;
f3 = float32_add( f1, f2);
float_exception_flags = 0; // Reset Exceptions
f3 = float32_add( f1, f2);
303,8 → 348,8
// printf("Exceptions: %x\n",float_exception_flags);
if(verb) printf("rmode: %01x, except: %02x, oper: %01x opa: %08x, opb: %08x res: %08x\n", float_rounding_mode, float_exception_flags, oper, f1, f2, f3);
fprintf(fp,"%01x%02x%01x%08x%08x%08x\n", float_rounding_mode, float_exception_flags, oper, f1, f2, f3);
if(verb) printf("rmode: %01x, except: %02x, oper: %02x opa: %08x, opb: %08x res: %08x\n", float_rounding_mode, float_exception_flags, oper, f1, f2, f3);
fprintf(fp,"%01x%02x%02x%08x%08x%08x\n", float_rounding_mode, float_exception_flags, oper, f1, f2, f3);
}
else {
printf("\t Vecor mismatch between library and system calculations. This Vector\n");
/trunk/test_vectors/pg-src/README
8,10 → 8,10
http://HTTP.CS.Berkeley.EDU/~jhauser/arithmetic/SoftFloat.html
 
Once installed, change directory to SoftFloat-2a/softfloat/bits32,
copy the included two source file to this directory and compile
copy the included source file to this directory and compile
using a command like:
 
gcc -I386-Win32-gcc -opg.exe fptpg.c conv.c softfloat.c
gcc -I386-Win32-gcc -opg.exe fptpg.c softfloat.c
 
This build has been tested on SPARC Solaris systems and WIndows NT
with cygwin and gcc.
/trunk/test_vectors/README
21,7 → 21,7
mode are randomly selected and may change every cycle. This
tests are located in the combo directory.
 
There are currently 10,602,998 test vectors !
There are currently 14,808,684 test vectors !
 
WARNING: You need about 320Mb of disk space to build all test
WARNING: You need about 470Mb of disk space to build all test
vectors !!!
/trunk/verilog/post_norm.v
35,11 → 35,12
 
`timescale 1ns / 100ps
 
module post_norm( clk, fpu_op, sign, rmode, fract_in, exp_in, exp_ovf,
module post_norm( clk, fpu_op, opas, sign, rmode, fract_in, exp_in, exp_ovf,
opa_dn, opb_dn, rem_00, div_opa_ldz, output_zero, out,
ine, overflow, underflow);
ine, overflow, underflow, f2i_out_sign);
input clk;
input [2:0] fpu_op;
input opas;
input sign;
input [1:0] rmode;
input [47:0] fract_in;
52,6 → 53,7
output [30:0] out;
output ine;
output overflow, underflow;
output f2i_out_sign;
 
////////////////////////////////////////////////////////////////////////
//
72,6 → 74,8
wire op_dn = opa_dn | opb_dn;
wire op_mul = fpu_op[2:0]==3'b010;
wire op_div = fpu_op[2:0]==3'b011;
wire op_i2f = fpu_op[2:0]==3'b100;
wire op_f2i = fpu_op[2:0]==3'b101;
reg [5:0] fi_ldz;
 
wire g, r, s;
121,6 → 125,15
wire [6:0] ldz_all;
wire [7:0] ldz_dif;
 
wire [8:0] div_scht1a;
wire [7:0] f2i_shft;
wire [55:0] exp_f2i_1;
wire f2i_zero, f2i_max;
wire [7:0] f2i_emin;
wire [7:0] conv_shft;
wire [7:0] exp_i2f, exp_f2i, conv_exp;
wire round2_f2i;
 
////////////////////////////////////////////////////////////////////////
//
// Normalize and Round Logic
189,7 → 202,6
wire rmode_00, rmode_01, rmode_10, rmode_11;
 
// Misc common signals
 
assign exp_in_ff = &exp_in;
assign exp_in_00 = !(|exp_in);
assign exp_in_80 = exp_in[7] & !(|exp_in[6:0]);
210,13 → 222,18
// Fasu Output will be denormalized ...
assign dn = !op_mul & !op_div & (exp_in_00 | (exp_next_mi[8] & !fract_in[47]) );
 
 
// ---------------------------------------------------------------------
// Fraction Normalization
wire [8:0] div_scht1a;
parameter f2i_emax = 8'h9d;
 
// Incremented fraction for rounding
assign fract_out_pl1 = fract_out + 1;
 
// Special Signals for f2i
assign f2i_emin = rmode_00 ? 8'h7e : 8'h7f;
assign f2i_zero = (!opas & (exp_in<f2i_emin)) | (opas & (exp_in>f2i_emax)) | (opas & (exp_in<f2i_emin) & (fract_in_00 | !rmode_11));
assign f2i_max = (!opas & (exp_in>f2i_emax)) | (opas & (exp_in<f2i_emin) & !fract_in_00 & rmode_11);
 
// Claculate various shifting options
 
assign {shft_co,shftr_mul} = (!exp_ovf[1] & exp_in_00) ? {1'b0, exp_out} : exp_in_mi1 ;
230,6 → 247,7
assign div_dn = op_dn & div_shft1_co;
assign div_nr = op_dn & exp_ovf[1] & !(|fract_in[46:23]) & (div_shft3>8'h16);
 
assign f2i_shft = exp_in-8'h7d;
 
// Select shifting direction
assign left_right = op_div ? lr_div : op_mul ? lr_mul : 1;
241,7 → 259,6
(!op_dn & exp_out_00 & !exp_ovf[1]) ? 1 :
exp_ovf[1] ? 0 :
1;
 
assign lr_mul = (shft_co | (!exp_ovf[1] & exp_in_00) |
(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00) )) ? 1 :
( exp_ovf[1] | exp_in_00 ) ? 0 :
250,8 → 267,11
// Select Left and Right shift value
assign fasu_shift = (dn | exp_out_00) ? (exp_in_00 ? 8'h2 : exp_in_pl1[7:0]) : {2'h0, fi_ldz};
assign shift_right = op_div ? shftr_div : shftr_mul;
assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : fasu_shift;
 
assign conv_shft = op_f2i ? f2i_shft : {2'h0, fi_ldz};
 
assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : (op_f2i | op_i2f) ? conv_shft : fasu_shift;
 
assign shftl_mul = (shft_co |
(!exp_ovf[1] & exp_in_00) |
(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00))) ? exp_in_pl1[7:0] : {2'h0, fi_ldz};
259,19 → 279,16
assign shftl_div = ( op_dn & exp_out_00 & !(!exp_ovf[1] & exp_ovf[0])) ? div_shft1[7:0] :
(!op_dn & exp_out_00 & !exp_ovf[1]) ? exp_in[7:0] :
{2'h0, fi_ldz};
 
assign shftr_div = (op_dn & exp_ovf[1]) ? div_shft3 :
(op_dn & div_shft1_co) ? div_shft4 :
div_shft2;
// Do the actual shifting
assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0];
assign fract_in_shftl = (|shift_left[7:6] ) ? 0 : fract_in<<shift_left[5:0];
assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0];
assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 0 : fract_in<<shift_left[5:0];
 
 
// Chose final fraction output
assign {fract_out,fract_trunc} = left_right ? fract_in_shftl : fract_in_shftr;
 
 
// ---------------------------------------------------------------------
// Exponent Normalization
 
284,18 → 301,30
assign exp_out1_mi1 = exp_out1 - 1;
 
assign exp_next_mi = exp_in_pl1 - fi_ldz_mi1; // 9 bits - includes carry out
 
assign exp_fix_diva = exp_in - fi_ldz_mi22;
assign exp_fix_divb = exp_in - fi_ldz_mi1;
 
assign exp_zero = (exp_ovf[1] & !exp_ovf[0] & op_mul & (!exp_rnd_adj2a | !rmode[1])) | (op_mul & exp_out1_co);
assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
assign exp_out = op_div ? exp_div : exp_zero ? 8'h0 : dn ? {6'h0, fract_in[47:46]} : exp_out1;
 
assign f2i_out_sign = !opas ? ((exp_in<f2i_emin) ? 0 : (exp_in>f2i_emax) ? 0 : opas) :
((exp_in<f2i_emin) ? 0 : (exp_in>f2i_emax) ? 1 : opas);
 
assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-fi_ldz);
assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
assign exp_f2i = f2i_zero ? 0 : f2i_max ? 8'hff : exp_f2i_1[55:48];
assign conv_exp = op_f2i ? exp_f2i : exp_i2f;
 
assign exp_out = op_div ? exp_div : (op_f2i | op_i2f) ? conv_exp : exp_zero ? 8'h0 : dn ? {6'h0, fract_in[47:46]} : exp_out1;
 
assign ldz_all = div_opa_ldz + fi_ldz;
assign ldz_dif = fi_ldz_2 - div_opa_ldz;
assign fi_ldz_2a = 6'd23 - fi_ldz;
assign fi_ldz_2 = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
 
assign div_exp1 = exp_in_mi1 + fi_ldz_2; // 9 bits - includes carry out
 
assign div_exp2 = exp_in_pl1 - ldz_all;
assign div_exp3 = exp_in + ldz_dif;
 
303,7 → 332,7
opb_dn ? div_exp1[7:0] :
(opa_dn & !( (exp_in<div_opa_ldz) | (div_exp2>9'hfe) )) ? div_exp2 :
(opa_dn | (exp_in_00 & !exp_ovf[1]) ) ? 0 :
exp_out1_mi1;
exp_out1_mi1;
 
assign div_inf = opb_dn & !opa_dn & (div_exp1[7:0] < 8'h7f);
 
321,18 → 350,16
assign round = (g & r) | (r & s) ;
assign {exp_rnd_adj0, fract_out_rnd0} = round ? fract_out_pl1 : {1'b0, fract_out};
assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out;
assign ovf0 = exp_out_final_ff & !rmode_01;
assign ovf0 = exp_out_final_ff & !rmode_01 & !op_f2i;
 
// round to zero
assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn) ? 23'h7fffff : fract_out;
assign exp_fix_div = (fi_ldz>23) ? exp_fix_diva : exp_fix_divb;
assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out;
assign exp_fix_div = (fi_ldz>22) ? exp_fix_diva : exp_fix_divb;
assign exp_out_rnd1 = (g & r & s & exp_in_ff) ? (op_div ? exp_fix_div : exp_next_mi[7:0]) :
exp_out_ff ? exp_in : exp_out;
 
(exp_out_ff & !op_f2i) ? exp_in : exp_out;
assign ovf1 = exp_out_ff & !dn;
 
// round to +inf (UP) and -inf (DOWN)
//assign r_sign = rmode_11 ? !sign : sign;
assign r_sign = sign;
 
assign round2a = !exp_out_fe | !fract_out_7fffff | (exp_out_fe & fract_out_7fffff);
351,13 → 378,14
)
);
 
assign round2 = (op_mul | op_div) ? round2_fmul : round2_fasu;
assign round2_f2i = rmode_10 & (( |fract_in[23:0] & !opas & (exp_in<8'h80 )) | (|fract_trunc));
assign round2 = (op_mul | op_div) ? round2_fmul : op_f2i ? round2_f2i : round2_fasu;
 
assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 : {1'b0, fract_out};
assign exp_out_rnd2a = exp_rnd_adj2a ? (exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1 : exp_out;
assign exp_out_rnd2a = exp_rnd_adj2a ? ((exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1) : exp_out;
 
assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn) ? 23'h7fffff : fract_out_rnd2a;
assign exp_out_rnd2 = (r_sign & exp_out_ff) ? 8'hfe : exp_out_rnd2a;
assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out_rnd2a;
assign exp_out_rnd2 = (r_sign & exp_out_ff & !op_f2i) ? 8'hfe : exp_out_rnd2a;
 
 
// Choose rounding mode
426,12 → 454,12
)
) | (op_div & rmode[1] & exp_in_ff & op_dn & !r_sign & (fi_ldz_2 < 24) & (exp_out_rnd!=8'hfe) );
 
assign fract_out_final = (inf_out | ovf0 | output_zero) ? 23'h0 :
max_num ? 23'h7fffff :
assign fract_out_final = (inf_out | ovf0 | output_zero ) ? 23'h0 :
(max_num | (f2i_max & op_f2i) ) ? 23'h7fffff :
fract_out_rnd;
 
assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero) ? 8'h00 :
((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out) ? 8'hff :
assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero ) ? 8'h00 :
((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out | (f2i_max & op_f2i) ) ? 8'hff :
max_num ? 8'hfe :
exp_out_rnd;
 
491,8 → 519,20
(exp_ovf[0] & (exp_ovf[1] | exp_out_ff) );
 
assign overflow = op_div ? overflow_fdiv : (ovf0 | ovf1);
assign ine = (r & !dn) | (s & !dn) | max_num | (op_div & !rem_00);
 
wire f2i_ine;
 
assign f2i_ine = (f2i_zero & !fract_in_00 & !opas) |
(|fract_trunc) |
(f2i_zero & (exp_in<8'h80) & opas & !fract_in_00) |
(f2i_max & rmode_11 & (exp_in<8'h80));
 
 
 
assign ine = op_f2i ? f2i_ine :
op_i2f ? (|fract_trunc) :
((r & !dn) | (s & !dn) | max_num | (op_div & !rem_00));
 
// ---------------------------------------------------------------------
// Debugging Stuff
 
507,7 → 547,7
wire [47:0] fract_in_del;
wire overflow_del;
wire [1:0] exp_ovf_del;
wire [22:0] fract_out_x_del;
wire [22:0] fract_out_x_del, fract_out_rnd2a_del;
wire [24:0] trunc_xx_del;
wire exp_rnd_adj2a_del;
wire [22:0] fract_dn_del;
520,6 → 560,8
wire [5:0] fi_ldz_del;
wire rx_del;
wire ez_del;
wire lr;
wire [7:0] shr, shl, exp_div_del;
 
delay2 #26 ud000(clk, test.u0.fracta, fracta_del);
delay2 #26 ud001(clk, test.u0.fractb, fractb_del);
543,6 → 585,13
delay1 #5 ud027(clk, fi_ldz, fi_ldz_del);
delay1 #0 ud028(clk, rem_00, rx_del);
 
delay1 #0 ud029(clk, left_right, lr);
delay1 #7 ud030(clk, shift_right, shr);
delay1 #7 ud031(clk, shift_left, shl);
delay1 #22 ud032(clk, fract_out_rnd2a, fract_out_rnd2a_del);
 
delay1 #7 ud033(clk, exp_div, exp_div_del);
 
always @(test.error_event)
begin
 
551,9 → 600,13
$display("ERROR: GRS: %b exp_ovf: %b dn: %h exp_in: %h exp_out: %h, exp_rnd_adj2a: %b",
grs_del, exp_ovf_del, dn_del, exp_in_del, exp_out_del, exp_rnd_adj2a_del);
 
$display(" div_opa: %b, div_opb: %b, rem_00: %b",
fracta_div_del, fractb_div_del, rx_del);
$display(" div_opa: %b, div_opb: %b, rem_00: %b, exp_div: %h",
fracta_div_del, fractb_div_del, rx_del, exp_div_del);
 
$display(" lr: %b, shl: %h, shr: %h",
lr, shl, shr);
 
 
$display(" overflow: %b, fract_in=%b fa:%h fb:%h",
overflow_del, fract_in_del, fracta_del, fractb_del);
 
560,8 → 613,8
$display(" div_opa_ldz: %h, div_inf: %b, inf_out: %b, max_num: %b, fi_ldz: %h, fi_ldz_2: %h",
div_opa_ldz_del, div_inf_del, inf_out_del, max_num_del, fi_ldz_del, fi_ldz_2_del);
 
$display(" fract_out_x: %b, fract_trunc: %b\n",
fract_out_x_del, trunc_xx_del);
$display(" fract_out_x: %b, fract_out_rnd2a_del: %h, fract_trunc: %b\n",
fract_out_x_del, fract_out_rnd2a_del, trunc_xx_del);
end
 
 
/trunk/verilog/fpu.v
299,18 → 299,48
// Normalize Result
//
wire ine_d;
wire [47:0] fract_denorm, fract_div;
reg [47:0] fract_denorm;
wire [47:0] fract_div;
wire sign_d;
reg sign;
reg [30:0] opa_r1;
reg [47:0] fract_i2f;
reg opas_r1, opas_r2;
wire f2i_out_sign;
 
always @(posedge clk) // Exponent must be once cycle delayed
exp_r <= #1 fpu_op_r2[1] ? exp_mul : exp_fasu;
case(fpu_op_r2)
0,1: exp_r <= #1 exp_fasu;
2,3: exp_r <= #1 exp_mul;
4: exp_r <= #1 0;
5: exp_r <= #1 opa_r1[30:23];
endcase
 
assign fract_div = (opb_dn ? quo[49:2] : {quo[26:0], 21'h0});
 
assign fract_denorm = !fpu_op_r3[1] ? {fract_out_q, 20'h0}:
fpu_op_r3[0] ? fract_div : prod;
always @(posedge clk)
opa_r1 <= #1 opa_r[30:0];
 
always @(posedge clk)
fract_i2f <= #1 (fpu_op_r2==5) ?
(sign_d ? 1-{24'h00, (|opa_r1[30:23]), opa_r1[22:0]}-1 : {24'h0, (|opa_r1[30:23]), opa_r1[22:0]}) :
(sign_d ? 1 - {opa_r1, 17'h01} : {opa_r1, 17'h0});
 
always @(fpu_op_r3 or fract_out_q or prod or fract_div or fract_i2f)
case(fpu_op_r3)
0,1: fract_denorm = {fract_out_q, 20'h0};
2: fract_denorm = prod;
3: fract_denorm = fract_div;
4,5: fract_denorm = fract_i2f;
endcase
 
 
always @(posedge clk)
opas_r1 <= #1 opa_r[31];
 
always @(posedge clk)
opas_r2 <= #1 opas_r1;
 
assign sign_d = fpu_op_r2[1] ? sign_mul : sign_fasu;
 
always @(posedge clk)
318,6 → 348,7
 
post_norm u4(.clk(clk), // System Clock
.fpu_op(fpu_op_r3), // Floating Point Operation
.opas(opas_r2), // OPA Sign
.sign(sign), // Sign of the result
.rmode(rmode_r3), // Rounding mode
.fract_in(fract_denorm), // Fraction Input
331,7 → 362,8
.out(out_d), // Normalized output (un-registered)
.ine(ine_d), // Result Inexact output (un-registered)
.overflow(overflow_d), // Overflow output (un-registered)
.underflow(underflow_d) // Underflow output (un-registered)
.underflow(underflow_d), // Underflow output (un-registered)
.f2i_out_sign(f2i_out_sign) // F2I Output Sign
);
 
////////////////////////////////////////////////////////////////////////
382,7 → 414,7
) ? QNAN : INF;
 
always @(posedge clk)
out[30:0] <= #1 (mul_inf | div_inf | (inf_d & (fpu_op_r3!=3'b011)) | snan_d | qnan_d) ? out_fixed :
out[30:0] <= #1 (mul_inf | div_inf | (inf_d & (fpu_op_r3!=3'b011) & (fpu_op_r3!=3'b101)) | snan_d | qnan_d) & fpu_op_r3!=3'b100 ? out_fixed :
out_d;
 
assign out_d_00 = !(|out_d);
391,7 → 423,8
assign sign_div_final = (sign_exe_r & (opa_inf & opb_inf)) ? !sign_mul_r : sign_mul_r | (opa_00 & opb_00);
 
always @(posedge clk)
out[31] <= #1 ((fpu_op_r3==3'b010) & !(snan_d | qnan_d)) ? sign_mul_final :
out[31] <= #1 ((fpu_op_r3==3'b101) & out_d_00) ? (f2i_out_sign & !(qnan_d | snan_d) ) :
((fpu_op_r3==3'b010) & !(snan_d | qnan_d)) ? sign_mul_final :
((fpu_op_r3==3'b011) & !(snan_d | qnan_d)) ? sign_div_final :
(snan_d | qnan_d | ind_d) ? nan_sign_d :
output_zero_fasu ? result_zero_sign_d :
407,8 → 440,9
assign ine_fasu = (ine_d | overflow_d | underflow_d) & !(snan_d | qnan_d | inf_d);
 
always @(posedge clk)
ine <= #1 !fpu_op_r3[1] ? ine_fasu :
fpu_op_r3[0] ? ine_div : ine_mul;
ine <= #1 fpu_op_r3[2] ? ine_d :
!fpu_op_r3[1] ? ine_fasu :
fpu_op_r3[0] ? ine_div : ine_mul;
 
 
assign overflow_fasu = overflow_d & !(snan_d | qnan_d | inf_d);
416,8 → 450,9
assign overflow_fdiv = (overflow_d & !(opb_00 | inf_d | snan_d | qnan_d));
 
always @(posedge clk)
overflow <= #1 !fpu_op_r3[1] ? overflow_fasu :
fpu_op_r3[0] ? overflow_fdiv : overflow_fmul;
overflow <= #1 fpu_op_r3[2] ? 0 :
!fpu_op_r3[1] ? overflow_fasu :
fpu_op_r3[0] ? overflow_fdiv : overflow_fmul;
 
always @(posedge clk)
underflow_fmul_r <= #1 underflow_fmul_d;
433,7 → 468,8
assign underflow_fdiv = underflow_fasu & !opb_00;
 
always @(posedge clk)
underflow <= #1 !fpu_op_r3[1] ? underflow_fasu :
underflow <= #1 fpu_op_r3[2] ? 0 :
!fpu_op_r3[1] ? underflow_fasu :
fpu_op_r3[0] ? underflow_fdiv : underflow_fmul;
 
always @(posedge clk)
481,9 → 517,11
 
// Status Outputs
always @(posedge clk)
qnan <= #1 snan_d | qnan_d | (ind_d & !fasu_op_r2) |
(opa_00 & opb_00 & fpu_op_r3==3'b011) |
(((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010);
qnan <= #1 fpu_op_r3[2] ? 0 : (
snan_d | qnan_d | (ind_d & !fasu_op_r2) |
(opa_00 & opb_00 & fpu_op_r3==3'b011) |
(((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010)
);
 
assign inf_fmul = (((inf_mul_r | inf_mul2) & (rmode_r3==2'h0)) | opa_inf | opb_inf) &
!((opa_inf & opb_00) | (opb_inf & opa_00 )) &
490,13 → 528,15
fpu_op_r3==3'b010;
 
always @(posedge clk)
inf <= #1 !(qnan_d | snan_d) & (
inf <= #1 fpu_op_r3[2] ? 0 :
(!(qnan_d | snan_d) & (
((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) |
(inf_d & !(ind_d & !fasu_op_r2) & !fpu_op_r3[1]) |
inf_fmul |
(!opa_00 & opb_00 & fpu_op_r3==3'b011) |
(fpu_op_r3==3'b011 & opa_inf & !opb_inf)
);
)
);
 
assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d);
assign output_zero_fdiv = (div_00 | (out_d_00 & !opb_00)) & !(opa_inf & opb_inf) &
506,7 → 546,8
!(opa_inf & opb_00) & !(opb_inf & opa_00);
 
always @(posedge clk)
zero <= #1 fpu_op_r3==3'b011 ? output_zero_fdiv :
zero <= #1 fpu_op_r3==3'b101 ? out_d_00 & !(snan_d | qnan_d):
fpu_op_r3==3'b011 ? output_zero_fdiv :
fpu_op_r3==3'b010 ? output_zero_fmul :
output_zero_fasu ;
 
/trunk/README
38,5 → 38,5
Do not change the directory structure, the testbench
depends on it !
 
Please also rea the readme file in the test_vectors
Please also read the README file in the test_vectors
directory.
/trunk/test_bench/test_top.v
52,9 → 52,9
reg [2:0] fpu_op, fpu_op1, fpu_op2, fpu_op3, fpu_op4, fpu_op5;
reg [3:0] rmode, rmode1, rmode2, rmode3, rmode4, rmode5;
reg start, s1, s2, s3, s4;
reg [111:0] tmem[0:500000];
reg [111:0] tmp;
reg [3:0] oper;
reg [115:0] tmem[0:500000];
reg [115:0] tmp;
reg [7:0] oper;
reg [7:0] exc, exc1, exc2, exc3, exc4;
integer i;
wire ine;
70,6 → 70,8
reg fp_mul;
reg fp_div;
reg fp_combo;
reg fp_i2f;
reg fp_f2i;
reg test_exc;
reg show_prog;
event error_event;
91,17 → 93,28
vcount = 0;
 
show_prog = 0;
 
fp_combo = 0;
fp_fasu = 0;
fp_mul = 0;
fp_div = 0;
fp_i2f = 1;
fp_f2i = 1;
 
test_exc = 1;
test_sel = 5'b01111;
test_rmode = 4'b1111;
 
//test_sel = 5'b00110;
//test_rmode = 4'b01110;
 
fp_combo = 1;
fp_fasu = 1;
fp_mul = 1;
fp_div = 1;
test_exc = 1;
test_sel = 5'b00110;
test_rmode = 4'b0101;
fp_i2f = 1;
fp_f2i = 1;
 
//test_sel = 5'b00110;
//test_rmode = 4'b01110;
 
test_sel = 5'b11111;
test_rmode = 4'b1111;
 
126,7 → 139,7
opa = 32'hx;
opb = 32'hx;
fpu_rmode = 2'hx;
fpu_op = 2'hx;
fpu_op = 3'hx;
 
repeat(4) @(posedge clk);
#1;
140,9 → 153,9
#1;
start = 1;
tmp = tmem[i];
rmode = tmp[111:108];
exc = tmp[107:100];
oper = tmp[99:96];
rmode = tmp[115:112];
exc = tmp[111:104];
oper = tmp[103:96];
opa = tmp[95:64];
opb = tmp[63:32];
exp = tmp[31:00];
166,12 → 179,16
// 2 sub
// 4 mul
// 8 div
// ...
 
case(oper)
1: fpu_op=3'b000; // Add
2: fpu_op=3'b001; // Sub
4: fpu_op=3'b010; // Mul
8: fpu_op=3'b011; // Div
8'b00000001: fpu_op=3'b000; // Add
8'b00000010: fpu_op=3'b001; // Sub
8'b00000100: fpu_op=3'b010; // Mul
8'b00001000: fpu_op=3'b011; // Div
8'b00010000: fpu_op=3'b100; // i2f
8'b00100000: fpu_op=3'b101; // f2i
8'b01000000: fpu_op=3'b110; // rem
default: fpu_op=3'bx;
endcase
 
260,6 → 277,7
$display("\nERROR: DIV_BY_ZERO Exception: Expected: %h, Got %h\n",exc4[2],div_by_zero);
end
 
 
if(ine !== exc4[5])
begin
exc_err=1;
292,13 → 310,14
$display("\nERROR: INF Detection Failed. INF: %h, Sum: %h\n", inf, sum);
end
if(qnan !== ( &sum[30:23] & |sum[22:0] ) )
 
if(qnan !== ( &sum[30:23] & |sum[22:0] ) & !(fpu_op4==5) )
begin
exc_err=1;
$display("\nERROR: QNAN Detection Failed. QNAN: %h, Sum: %h\n", qnan, sum);
end
 
 
if(snan !== ( ( &opa4[30:23] & !opa4[22] & |opa4[21:0]) | ( &opb4[30:23] & !opb4[22] & |opb4[21:0]) ) )
begin
exc_err=1;
309,6 → 328,7
 
 
m0 = ( (|sum) !== 1'b1) & ( (|sum) !== 1'b0); // result unknown (ERROR)
//m0 = ( (|sum) === 1'bx) & 0;
m1 = (exp4 === sum); // results are equal
 
// NAN *** Ignore Fraction Detail ***
325,6 → 345,7
#0.6;
$display("\n%t: ERROR: output mismatch. Expected %h, Got %h (%h)", $time, exp4, sum, {opa4, opb4, exp4} );
$write("opa:\t"); disp_fp(opa4);
$display("opa:\t%h",opa4[30:0]);
case(fpu_op4)
0: $display("\t+");
1: $display("\t-");
/trunk/test_bench/sel_test.vh
39,6 → 39,14
$readmemh ("test_vectors/combo/fpu_combo2.hex", tmem);
run_test;
 
$display("\nRunning Combo Test 3 ...\n");
$readmemh ("test_vectors/combo/fpu_combo3.hex", tmem);
run_test;
 
$display("\nRunning Combo Test 4 ...\n");
$readmemh ("test_vectors/combo/fpu_combo4.hex", tmem);
run_test;
 
end
 
if(fp_fasu)
679,3 → 687,340
end
end
end
 
 
 
if(fp_i2f)
begin
 
$display("\n\nTesting FP I2F Unit\n");
 
if(test_rmode[0])
begin
$display("\n+++++ ROUNDING MODE: Nearest Even\n\n");
 
if(test_sel[0])
begin
$display("\nRunning Pat 0 Test ...\n");
$readmemh ("test_vectors/rtne/i2f_pat0.hex", tmem);
run_test;
end
if(test_sel[1])
begin
$display("\nRunning Pat 1 Test ...\n");
$readmemh ("test_vectors/rtne/i2f_pat1.hex", tmem);
run_test;
end
if(test_sel[2])
begin
$display("\nRunning Pat 2 Test ...\n");
$readmemh ("test_vectors/rtne/i2f_pat2.hex", tmem);
run_test;
end
if(test_sel[3])
begin
$display("\nRunning Random Lg. Num Test ...\n");
$readmemh ("test_vectors/rtne/i2f_lg.hex", tmem);
run_test;
end
if(test_sel[4])
begin
$display("\nRunning Random Sm. Num Test ...\n");
$readmemh ("test_vectors/rtne/i2f_sm.hex", tmem);
run_test;
end
end
 
if(test_rmode[1])
begin
$display("\n\n+++++ ROUNDING MODE: Towards Zero\n\n");
 
if(test_sel[0])
begin
$display("\nRunning Pat 0 Test ...\n");
$readmemh ("test_vectors/rtzero/i2f_pat0.hex", tmem);
run_test;
end
if(test_sel[1])
begin
$display("\nRunning Pat 1 Test ...\n");
$readmemh ("test_vectors/rtzero/i2f_pat1.hex", tmem);
run_test;
end
if(test_sel[2])
begin
$display("\nRunning Pat 2 Test ...\n");
$readmemh ("test_vectors/rtzero/i2f_pat2.hex", tmem);
run_test;
end
if(test_sel[3])
begin
$display("\nRunning Random Lg. Num Test ...\n");
$readmemh ("test_vectors/rtzero/i2f_lg.hex", tmem);
run_test;
end
if(test_sel[4])
begin
$display("\nRunning Random Sm. Num Test ...\n");
$readmemh ("test_vectors/rtzero/i2f_sm.hex", tmem);
run_test;
end
end
 
if(test_rmode[2])
begin
$display("\n\n+++++ ROUNDING MODE: Towards INF+ (UP)\n\n");
 
if(test_sel[0])
begin
$display("\nRunning Pat 0 Test ...\n");
$readmemh ("test_vectors/rup/i2f_pat0.hex", tmem);
run_test;
end
if(test_sel[1])
begin
$display("\nRunning Pat 1 Test ...\n");
$readmemh ("test_vectors/rup/i2f_pat1.hex", tmem);
run_test;
end
if(test_sel[2])
begin
$display("\nRunning Pat 2 Test ...\n");
$readmemh ("test_vectors/rup/i2f_pat2.hex", tmem);
run_test;
end
if(test_sel[3])
begin
$display("\nRunning Random Lg. Num Test ...\n");
$readmemh ("test_vectors/rup/i2f_lg.hex", tmem);
run_test;
end
 
if(test_sel[4])
begin
$display("\nRunning Random Sm. Num Test ...\n");
$readmemh ("test_vectors/rup/i2f_sm.hex", tmem);
run_test;
end
 
end
 
if(test_rmode[3])
begin
$display("\n\n+++++ ROUNDING MODE: Towards INF- (DOWN)\n\n");
 
if(test_sel[0])
begin
$display("\nRunning Pat 0 Test ...\n");
$readmemh ("test_vectors/rdown/i2f_pat0.hex", tmem);
run_test;
end
if(test_sel[1])
begin
$display("\nRunning Pat 1 Test ...\n");
$readmemh ("test_vectors/rdown/i2f_pat1.hex", tmem);
run_test;
end
if(test_sel[2])
begin
$display("\nRunning Pat 2 Test ...\n");
$readmemh ("test_vectors/rdown/i2f_pat2.hex", tmem);
run_test;
end
if(test_sel[3])
begin
$display("\nRunning Random Lg. Num Test ...\n");
$readmemh ("test_vectors/rdown/i2f_lg.hex", tmem);
run_test;
end
 
if(test_sel[4])
begin
$display("\nRunning Random Sm. Num Test ...\n");
$readmemh ("test_vectors/rdown/i2f_sm.hex", tmem);
run_test;
end
end
end
 
 
if(fp_f2i)
begin
 
$display("\n\nTesting FP F2I Unit\n");
 
if(test_rmode[0])
begin
$display("\n+++++ ROUNDING MODE: Nearest Even\n\n");
 
if(test_sel[0])
begin
$display("\nRunning Pat 0 Test ...\n");
$readmemh ("test_vectors/rtne/f2i_pat0.hex", tmem);
run_test;
end
if(test_sel[1])
begin
$display("\nRunning Pat 1 Test ...\n");
$readmemh ("test_vectors/rtne/f2i_pat1.hex", tmem);
run_test;
end
if(test_sel[2])
begin
$display("\nRunning Pat 2 Test ...\n");
$readmemh ("test_vectors/rtne/f2i_pat2.hex", tmem);
run_test;
end
if(test_sel[3])
begin
$display("\nRunning Random Lg. Num Test ...\n");
$readmemh ("test_vectors/rtne/f2i_lg.hex", tmem);
run_test;
end
if(test_sel[4])
begin
$display("\nRunning Random Sm. Num Test ...\n");
$readmemh ("test_vectors/rtne/f2i_sm.hex", tmem);
run_test;
end
end
 
if(test_rmode[1])
begin
$display("\n\n+++++ ROUNDING MODE: Towards Zero\n\n");
 
if(test_sel[0])
begin
$display("\nRunning Pat 0 Test ...\n");
$readmemh ("test_vectors/rtzero/f2i_pat0.hex", tmem);
run_test;
end
if(test_sel[1])
begin
$display("\nRunning Pat 1 Test ...\n");
$readmemh ("test_vectors/rtzero/f2i_pat1.hex", tmem);
run_test;
end
if(test_sel[2])
begin
$display("\nRunning Pat 2 Test ...\n");
$readmemh ("test_vectors/rtzero/f2i_pat2.hex", tmem);
run_test;
end
if(test_sel[3])
begin
$display("\nRunning Random Lg. Num Test ...\n");
$readmemh ("test_vectors/rtzero/f2i_lg.hex", tmem);
run_test;
end
if(test_sel[4])
begin
$display("\nRunning Random Sm. Num Test ...\n");
$readmemh ("test_vectors/rtzero/f2i_sm.hex", tmem);
run_test;
end
end
 
if(test_rmode[2])
begin
$display("\n\n+++++ ROUNDING MODE: Towards INF+ (UP)\n\n");
 
if(test_sel[0])
begin
$display("\nRunning Pat 0 Test ...\n");
$readmemh ("test_vectors/rup/f2i_pat0.hex", tmem);
run_test;
end
if(test_sel[1])
begin
$display("\nRunning Pat 1 Test ...\n");
$readmemh ("test_vectors/rup/f2i_pat1.hex", tmem);
run_test;
end
if(test_sel[2])
begin
$display("\nRunning Pat 2 Test ...\n");
$readmemh ("test_vectors/rup/f2i_pat2.hex", tmem);
run_test;
end
if(test_sel[3])
begin
$display("\nRunning Random Lg. Num Test ...\n");
$readmemh ("test_vectors/rup/f2i_lg.hex", tmem);
run_test;
end
 
if(test_sel[4])
begin
$display("\nRunning Random Sm. Num Test ...\n");
$readmemh ("test_vectors/rup/f2i_sm.hex", tmem);
run_test;
end
 
end
 
if(test_rmode[3])
begin
$display("\n\n+++++ ROUNDING MODE: Towards INF- (DOWN)\n\n");
 
if(test_sel[0])
begin
$display("\nRunning Pat 0 Test ...\n");
$readmemh ("test_vectors/rdown/f2i_pat0.hex", tmem);
run_test;
end
if(test_sel[1])
begin
$display("\nRunning Pat 1 Test ...\n");
$readmemh ("test_vectors/rdown/f2i_pat1.hex", tmem);
run_test;
end
if(test_sel[2])
begin
$display("\nRunning Pat 2 Test ...\n");
$readmemh ("test_vectors/rdown/f2i_pat2.hex", tmem);
run_test;
end
if(test_sel[3])
begin
$display("\nRunning Random Lg. Num Test ...\n");
$readmemh ("test_vectors/rdown/f2i_lg.hex", tmem);
run_test;
end
 
if(test_sel[4])
begin
$display("\nRunning Random Sm. Num Test ...\n");
$readmemh ("test_vectors/rdown/f2i_sm.hex", tmem);
run_test;
end
end
end

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