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URL https://opencores.org/ocsvn/instruction_list_pipelined_processor_with_peripherals/instruction_list_pipelined_processor_with_peripherals/trunk

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Rev 5 → Rev 6

/instruction_list_pipelined_processor_with_peripherals/trunk/hdl/controlUnit.v
5,7 → 5,7
 
module controlUnit (clk, reset, instOpCode, acc0, iomemCode,
branch,
accMuxSel, accEn, op2MuxSel, aluOpcode,
accMuxSel, accEn, op2MuxSel, aluEn, aluOpcode,
bitRamEn, bitRamRw, byteRamEn, byteRamRw,
inputRead, outputRw
33,6 → 33,7
output [`accMuxSelLen-1:0] accMuxSel;
output accEn;
output [`op2MuxSelLen-1:0] op2MuxSel;
output aluEn;
output [`aluOpcodeLen-1:0] aluOpcode;
output bitRamEn, bitRamRw, byteRamEn, byteRamRw;
output inputRead, outputRw;
53,6 → 54,7
reg [`accMuxSelLen-1:0] accMuxSel;
reg accEn;
reg [`op2MuxSelLen-1:0] op2MuxSel;
reg aluEn;
reg [`aluOpcodeLen-1:0] aluOpcode;
reg bitRamEn, bitRamRw, byteRamEn, byteRamRw;
reg inputRead, outputRw;
93,7 → 95,7
begin
state = s;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluOpcode = 0; bitRamEn = 0;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0; aluEn = 0; aluOpcode = 0; bitRamEn = 0;
bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timeAndCounter_peripheral
129,6 → 131,7
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
aluEn = 0;
aluOpcode = 0;
bitRamEn = 0;
bitRamRw = 1;
158,10 → 161,14
state = sBr;
branch = 1; // branch to some address . . .
if (acc0)
branch = 1; // branch to some address . . .
else
branch = 0;
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
aluEn = 0;
aluOpcode = 0;
bitRamEn = 0;
bitRamRw = 1;
201,14 → 208,14
2'b11 : op2MuxSel = `op2MuxSelByteRam;
default: op2MuxSel = `op2MuxSelInput;
endcase
aluEn = 1;
aluOpcode = `LD_data;
bitRamEn = 0;
bitRamEn = 1;
bitRamRw = 1;
byteRamEn = 0;
byteRamEn = 1;
byteRamRw = 1;
inputRead = 0;
inputRead = 1;
outputRw = 1;
`ifdef timeAndCounter_peripheral
236,6 → 243,7
accEn = 1; // acc enabled
op2MuxSel = 0;
aluOpcode = 0;
aluEn = 0;
bitRamEn = 0;
bitRamRw = 1;
byteRamEn = 0;
266,14 → 274,13
accMuxSel = 0;
accEn = 0;
op2MuxSel = 0;
aluEn = 0;
aluOpcode = 0;
bitRamRw = 0;
byteRamRw = 0;
inputRead = 0;
 
case (iomemCode)
2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; end
2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; end
2'b01 : begin bitRamRw = 0; byteRamRw = 1; outputRw = 1; bitRamEn = 1; byteRamEn = 1; end
2'b10 : begin bitRamRw = 1; byteRamRw = 0; outputRw = 1; bitRamEn = 1; byteRamEn = 1; end
2'b11 : begin bitRamRw = 1; byteRamRw = 1; outputRw = 0; end
default: begin bitRamRw = 1; byteRamRw = 1; outputRw = 1; end
endcase
297,7 → 304,7
`ADD : begin
state = sAlu;
aluOpcode = `ADD_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
319,7 → 326,7
`SUB : begin
state = sAlu;
aluOpcode = `SUB_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
344,7 → 351,7
`AND : begin
state = sAlu;
aluOpcode = `AND_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
367,7 → 374,7
`OR : begin
state = sAlu;
aluOpcode = `OR_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
390,7 → 397,7
`XOR : begin
state = sAlu;
aluOpcode = `XOR_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
413,7 → 420,7
`GrT : begin
state = sAlu;
aluOpcode = `GT_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
438,7 → 445,7
`GE : begin
state = sAlu;
aluOpcode = `GE_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
463,7 → 470,7
`EQ : begin
state = sAlu;
aluOpcode = `EQ_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
488,7 → 495,7
`LE : begin
state = sAlu;
aluOpcode = `LE_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
513,7 → 520,7
`LT : begin
state = sAlu;
aluOpcode = `LT_alu;
aluEn = 1;
branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
539,7 → 546,7
entypeEn = 0; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 1; tcLoadEn = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
561,7 → 568,7
entypeEn = 1; tcAccRead = 0; tcResetEn = 0; tcPresetEn = 0; tcLoadEn = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
584,7 → 591,7
entypeEn = 0; tcAccRead = 0; tcResetEn = 1; tcPresetEn = 0; tcLoadEn = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
608,7 → 615,7
accMuxSel = `accMuxSelTcLoad; accEn = 1; // loading TC status data
aluOpcode = 0; branch = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
632,7 → 639,7
accMuxSel = `accMuxSelTcAcc; accEn = 1; // loading TC ACC data
aluOpcode = 0; branch = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
657,7 → 664,7
accMuxSel = `accMuxSelUart; accEn = 1; // loading UART data
aluOpcode = 0; branch = 0;op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0;op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
680,7 → 687,7
uartRead = 0; uartWrite = 1;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
aluEn = 0; aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
704,7 → 711,7
sconEn = 1; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
727,7 → 734,7
sconEn = 0; spiStatRead = 1; spiBufRead = 0; spiBufWrite = 0; spiBufShift = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
750,7 → 757,7
sconEn = 0; spiStatRead = 0; spiBufRead = 0; spiBufWrite = 1; spiBufShift = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
773,7 → 780,7
sconEn = 0; spiStatRead = 0; spiBufRead = 1; spiBufWrite = 0; spiBufShift = 0;
aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
aluEn = 0; aluOpcode = 0; branch = 0; accMuxSel = 0; accEn = 0; op2MuxSel = 0;
bitRamEn = 0; bitRamRw = 1; byteRamEn = 0; byteRamRw = 1; inputRead = 0; outputRw = 1;
`ifdef timerAndCounter_peripheral
806,7 → 813,9
sLd : begin
accEn = 0;
aluEn = 0;
accEn = 1;
accMuxSel = `accMuxSelAluOut;
state = s;
end // end case sLd
816,6 → 825,7
end
sAlu : begin
aluEn = 0;
accEn = 1;
accMuxSel = `accMuxSelAluOut;
state = s;
/instruction_list_pipelined_processor_with_peripherals/trunk/hdl/top.v
14,7 → 14,6
);
 
 
 
input clk,reset;
input [`inputNumber-1:0] IN;
output [`outputNumber-1:0] OUT;
50,6 → 49,7
wire [`accMuxSelLen-1:0] accMuxSelOutc;
wire accEnOutc;
wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
wire aluEnc;
wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
wire inputReadOutc, outputRwOutc;
67,6 → 67,7
wire [`accMuxSelLen-1:0] accMuxSelOut;
wire accEnOut;
wire [`op2MuxSelLen-1:0] op2MuxSelOut;
wire aluEn;
wire [`aluOpcodeLen-1:0] aluOpcodeOut;
wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
wire inputReadOut, outputRwOut;
140,29 → 141,25
wire [`instFieldLen-1:0] instField1;
wire [`instFieldLen-1:0] instField2;
ppReg1 PipeLine_Reg1 (clk, instOpcode, instField, instOpcode1, instField1);
ppReg1 PipeLine_Reg1 (clk, instOpCode, instField, instOpCode1, instField1);
 
 
//-------- Control Unit Module Instance
 
controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
branchc,
accMuxSelc, accEnc, op2MuxSelc, aluOpcodec,
bitRamEnc, bitRamRwc, byteRamEnc, byteRamRwc,
inputReadc, outputRwc
branchOutc,
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
`ifdef timerAndCounter_peripheral
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
`endif
`ifdef UART_peripheral
, uartReadOutc, uartWriteOutcc
`endif
`ifdef SPI_peripheral
, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
`endif
`ifdef timerAndCounter_peripheral
, entypeEnc, tcAccReadc, tcResetEnc, tcPresetEnc, tcLoadEnc
`endif
`ifdef UART_peripheral
, uartReadc, uartWritec
`endif
`ifdef SPI_peripheral
, sconEnc, spiStatReadc, spiBufReadc, spiBufWritec, spiBufShiftc
`endif
);
 
 
173,7 → 170,7
 
ppReg2 PipeLine_Reg2 (clk,
branchOutc,
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluOpcodeOutc, bitRamEnOutc,
accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
`ifdef timerAndCounter_peripheral
, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
187,7 → 184,7
, instField1
, branchOut,
accMuxSelOut, accEnOut, op2MuxSelOut, aluOpcodeOut,
accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
inputReadOut, outputRwOut
235,7 → 232,7
byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluOut, carryOut);
alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);
wire bitIn;
318,14 → 315,10
 
`ifdef SPI_peripheral
 
spiStatReg SPI_STATUS_REG ();
spiConReg SPI_CONTROL_REG ();
spiBufReg SPI_BUFFER_REG ();
spiEngine SPI_MAIN ();
 
spi_top SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);
 
 
`endif
endmodule
/instruction_list_pipelined_processor_with_peripherals/trunk/hdl/defines.v
98,7 → 98,7
// peripheral defines
`define timerAndCounter_peripheral
`define UART_peripheral
//`define SPI_peripheral
`define SPI_peripheral
 
 
//-----------------------------------------------------------------------------------------------------
/instruction_list_pipelined_processor_with_peripherals/trunk/hdl/spi_top.v
0,0 → 1,33
 
`include "timescale.v"
`include "defines.v"
 
 
module spi_top(clk, sconEN, statREAD, sconIN, statOUT, wrBUF, rdBUF, bufIN, bufOUT, MI, MO, SCK);
 
input clk, MI, sconEN, statREAD, wrBUF, rdBUF;
input [7:0] sconIN, bufIN;
output MO, SCK;
output [7:0] statOUT, bufOUT;
wire BF;
wire [7:0] sconOUT, bufOUT, bufregIN;
wire [7:0] buffer_out8;
spiStatReg STATUS_REG (statREAD, statOUT, BF);
 
 
spiConReg CONTROL_REG (sconEN, sconIN, sconOUT);
 
 
spiBufReg BUFFER_REG (rdBUF, bufregIN, bufOUT);
 
 
spiEngine ENGINE (bufIN, bufregIN, clk, MI, MO, SCK, wrBUF, sconOUT[7], sconOUT[0], BF);
 
endmodule
/instruction_list_pipelined_processor_with_peripherals/trunk/hdl/alu.v
2,7 → 2,7
`include "timescale.v"
`include "defines.v"
 
module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2,
module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn,
output [7:0] aluOut, output carryOut);
19,61 → 19,70
begin
 
case (aluOpcode)
`AND_alu : begin
aluOutput = op1 & op2;
end
`OR_alu : begin
aluOutput = op1 | op2;
end
`XOR_alu : begin
aluOutput = op1^op2;
end
`GT_alu : begin
aluOutput = op1>op2 ? 1'b1 : 1'b0;
end
`GE_alu : begin
aluOutput = op1>=op2 ? 1'b1 : 1'b0;
end
`EQ_alu : begin
aluOutput = op1==op2 ? 1'b1 : 1'b0;
end
`LE_alu : begin
aluOutput = op1<=op2 ? 1'b1 : 1'b0;
end
`LT_alu : begin
aluOutput = op1<op2 ? 1'b1 : 1'b0;
end
`ADD_alu : begin
aluOutput = addRes[7:0];
carryOutput = addRes[8];
end
`SUB_alu : begin
aluOutput = subRes[7:0];
carryOutput = subRes[8];
end
`LD_data : begin
aluOutput = op1;
end
default : begin
aluOutput = 16'b0;
$write ("Unknown operation. \nmodule : ALU");
end
endcase
if (aluEn)
begin
case (aluOpcode)
`AND_alu : begin
aluOutput = op1 & op2;
end
`OR_alu : begin
aluOutput = op1 | op2;
end
`XOR_alu : begin
aluOutput = op1^op2;
end
`GT_alu : begin
aluOutput = op1>op2 ? 1'b1 : 1'b0;
end
`GE_alu : begin
aluOutput = op1>=op2 ? 1'b1 : 1'b0;
end
`EQ_alu : begin
aluOutput = op1==op2 ? 1'b1 : 1'b0;
end
`LE_alu : begin
aluOutput = op1<=op2 ? 1'b1 : 1'b0;
end
`LT_alu : begin
aluOutput = op1<op2 ? 1'b1 : 1'b0;
end
`ADD_alu : begin
aluOutput = addRes[7:0];
carryOutput = addRes[8];
end
`SUB_alu : begin
aluOutput = subRes[7:0];
carryOutput = subRes[8];
end
`LD_data : begin
aluOutput = op1;
end
default : begin
aluOutput = 16'b0;
$write ("Unknown operation. \nmodule : ALU");
end
endcase
end
else
begin
aluOutput = aluOutput;
end
end
assign aluOut = aluOutput;
/instruction_list_pipelined_processor_with_peripherals/trunk/hdl/ppReg1.v
0,0 → 1,28
 
`include "timescale.v"
`include "defines.v"
 
 
module ppReg1 (clk, opcodeIn, fieldIn, opcodeOut, fieldOut);
 
input clk;
input [`instOpCodeLen-1:0] opcodeIn;
input [`instFieldLen-1:0] fieldIn;
output [`instOpCodeLen-1:0] opcodeOut;
output [`instFieldLen-1:0] fieldOut;
reg [`instOpCodeLen-1:0] opcodeOut;
reg [`instFieldLen-1:0] fieldOut;
always @ (posedge clk)
begin
opcodeOut = opcodeIn;
fieldOut = fieldIn;
end
 
 
 
endmodule
/instruction_list_pipelined_processor_with_peripherals/trunk/hdl/ppReg2.v
0,0 → 1,158
 
`include "timescale.v"
`include "defines.v"
 
 
module ppReg2 (clk,
branchIn,
accMuxSelIn, accEnIn, op2MuxSelIn, aluEnIn, aluOpcodeIn,
bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn,
inputReadIn, outputRwIn
`ifdef timerAndCounter_peripheral
, entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn, tcLoadEnIn
`endif
`ifdef UART_peripheral
, uartReadIn, uartWriteIn
`endif
`ifdef SPI_peripheral
, sconEnIn, spiStatReadIn, spiBufReadIn, spiBufWriteIn, spiBufShiftIn
`endif
, fieldIn
, branchOut,
accMuxSelOut, accEnOut, op2MuxSelOut, aluEnOut, aluOpcodeOut,
bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
inputReadOut, outputRwOut
`ifdef timerAndCounter_peripheral
, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
`endif
`ifdef UART_peripheral
, uartReadOut, uartWriteOut
`endif
`ifdef SPI_peripheral
, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
`endif
, fieldOut
);
 
input clk;
input branchIn;
input [`accMuxSelLen-1:0] accMuxSelIn;
input accEnIn;
input [`op2MuxSelLen-1:0] op2MuxSelIn;
input aluEnIn;
input [`aluOpcodeLen-1:0] aluOpcodeIn;
input bitRamEnIn, bitRamRwIn, byteRamEnIn, byteRamRwIn;
input inputReadIn, outputRwIn;
`ifdef timerAndCounter_peripheral
input entypeEnIn, tcAccReadIn, tcResetEnIn, tcPresetEnIn, tcLoadEnIn;
`endif
`ifdef UART_peripheral
input uartReadIn, uartWriteIn;
`endif
`ifdef SPI_peripheral
input sconEnIn, spiStatReadIn, spiBufReadIn, spiBufWriteIn, spiBufShiftIn;
`endif
input [`instFieldLen-1:0] fieldIn;
 
output branchOut;
output [`accMuxSelLen-1:0] accMuxSelOut;
output accEnOut;
output [`op2MuxSelLen-1:0] op2MuxSelOut;
output aluEnOut;
output [`aluOpcodeLen-1:0] aluOpcodeOut;
output bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
output inputReadOut, outputRwOut;
`ifdef timerAndCounter_peripheral
output entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
`endif
`ifdef UART_peripheral
output uartReadOut, uartWriteOut;
`endif
`ifdef SPI_peripheral
output sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
`endif
output [`instFieldLen-1:0] fieldOut;
reg branchOut;
reg [`accMuxSelLen-1:0] accMuxSelOut;
reg accEnOut;
reg [`op2MuxSelLen-1:0] op2MuxSelOut;
reg aluEnOut;
reg [`aluOpcodeLen-1:0] aluOpcodeOut;
reg bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
reg inputReadOut, outputRwOut;
`ifdef timerAndCounter_peripheral
reg entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
`endif
`ifdef UART_peripheral
reg uartReadOut, uartWriteOut;
`endif
`ifdef SPI_peripheral
reg sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
`endif
 
reg [`instFieldLen-1:0] fieldOut;
 
 
 
always @ (posedge clk)
begin
fieldOut = fieldIn;
branchOut = branchIn;
accMuxSelOut = accMuxSelIn;
accEnOut = accEnIn;
op2MuxSelOut = op2MuxSelIn;
aluEnOut = aluEnIn;
aluOpcodeOut = aluOpcodeIn;
bitRamEnOut = bitRamEnIn;
bitRamRwOut = bitRamRwIn;
byteRamEnOut = byteRamEnIn;
byteRamRwOut = byteRamRwIn;
inputReadOut = inputReadIn;
outputRwOut = outputRwIn;
`ifdef timerAndCounter_peripheral
 
entypeEnOut = entypeEnIn;
tcAccReadOut = tcAccReadIn;
tcResetEnOut = tcResetEnIn;
tcPresetEnOut = tcPresetEnIn;
tcLoadEnOut = tcLoadEnIn;
 
`endif
 
 
`ifdef UART_peripheral
 
uartReadOut = uartReadIn;
uartWriteOut = uartWriteIn;
 
`endif
 
 
`ifdef SPI_peripheral
sconEnOut = sconEnIn;
spiStatReadOut = spiStatReadIn;
spiBufReadOut = spiBufReadIn;
spiBufWriteOut = spiBufWriteIn;
spiBufShiftOut = spiBufShiftIn;
`endif
end
 
 
endmodule

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