URL
https://opencores.org/ocsvn/mdct/mdct/trunk
Subversion Repositories mdct
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/source/testbench/MDCTTB_PKG.vhd
144,7 → 144,7
(72,92,95,98,112,100,103,99) |
); |
|
-- CANON EOS10D high quality pictures |
-- CANON EOS10D super fine quality |
constant Q_CANON10D : I_MATRIX_TYPE := |
( |
(1, 1, 1, 1, 1, 1, 2, 2), |
/trunk/DOC/mdct_spec.doc
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/mdct.mpf
558,14 → 558,14
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144946089 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_12 = C:/elektronika/dct/mdct/source/testbench/MDCTTB_PKG.vhd |
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_13 = C:/elektronika/dct/mdct/source/DCT1D.vhd |
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_14 = C:/elektronika/dct/mdct/source/MDCT.VHD |
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_15 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd |
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_16 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD |
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_13 = C:/elektronika/dct/mdct/source/MDCT.VHD |
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_14 = C:/elektronika/dct/mdct/source/DCT1D.vhd |
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_15 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD |
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_File_16 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd |
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 93 |
Project_Sim_Count = 0 |
Project_Folder_Count = 4 |
Project_Folder_0 = TESTBENCH |
603,6 → 603,6
XML_CustomDoubleClick = |
LOGFILE_DoubleClick = Edit |
LOGFILE_CustomDoubleClick = |
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/testbench/MDCT_TB.DO 0 0} {C:/elektronika/dct/MDCT/source/MDCT.VHD 0 0} {C:/elektronika/dct/MDCT/source/MDCT_PKG.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT2D.VHD 0 1} |
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/testbench/MDCT_TB.DO 0 0} {C:/elektronika/dct/MDCT/source/MDCT.VHD 0 0} {C:/elektronika/dct/MDCT/source/MDCT_PKG.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 1} {C:/elektronika/dct/MDCT/source/DCT2D.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 0} |
Project_Major_Version = 6 |
Project_Minor_Version = 1 |
/trunk/transcript
9,11 → 9,9
#// OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS |
#// AND IS SUBJECT TO LICENSE TERMS. |
#// |
# OpenFile "C:/elektronika/dct/MDCT_EXPORT/mdct.mpf" |
# OpenFile "C:/elektronika/dct/MDCT/mdct.mpf" |
#Loading project mdct |
#** Error: (vlib-35) Failed to create directory "work". |
#File exists. (errno = EEXIST) |
#Modifying C:/elektronika/dct/MDCT_EXPORT/mdct.mpf |
#Modifying C:/elektronika/dct/MDCT/mdct.mpf |
#Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005 |
#-- Loading package standard |
#-- Loading package std_logic_1164 |
124,7 → 122,7
#-- Loading entity clkgen |
#-- Loading entity inpimage |
#** Warning: (vlib-34) Library already exists at "work". |
#Modifying C:/elektronika/dct/MDCT_EXPORT/mdct.mpf |
#Modifying C:/elektronika/dct/MDCT/mdct.mpf |
#Model Technology ModelSim SE vcom 6.1a Compiler 2005.07 Jul 19 2005 |
#-- Loading package standard |
#-- Loading package std_logic_1164 |