OpenCores
URL https://opencores.org/ocsvn/mpdma/mpdma/trunk

Subversion Repositories mpdma

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Rev 5 → Rev 6

/trunk/system.log
0,0 → 1,12
Xilinx Platform Studio (XPS)
Xilinx EDK 7.1.2 Build EDK_H.12.5.1
 
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
 
Created pcores directory
Copied file bitgen.ut from $XILINX_EDK/data/xflow directory to etc directory
Copied file bitgen_spartan3.ut from $XILINX_EDK/data directory to etc directory
Copied file fast_runtime.opt from $XILINX_EDK/data/xflow directory to etc directory
WARNING:MDT - Created an empty D:\mpdma\data\system.ucf. If your design needs any constraints, please make changes to this UCF file.
Project Opened.
No changes to be saved in XMP file
/trunk/system.mss
0,0 → 1,96
 
PARAMETER VERSION = 2.2.0
 
 
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER STDIN = RS232_Uart_1
PARAMETER STDOUT = RS232_Uart_1
END
 
 
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER XMDSTUB_PERIPHERAL = debug_module
END
 
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = opbarb
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = mb_opb
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = debug_module
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = RS232_Uart_1
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = sysace
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = SysACE_CompactFlash
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddr
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = sysclk_inv
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = clk90_inv
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ddr_clk90_inv
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_0
END
 
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_1
END
 
 
/trunk/system.xmp
0,0 → 1,50
#Please do not modify this file by hand
XmpVersion: 7.1
IntStyle: default
ModuleSearchPath: D:/XilinxXUP/lib/
MHS File: system.mhs
MSS File: system.mss
NPL File: projnav/system.ise
Architecture: virtex2p
Device: xc2vp30
Package: ff896
SpeedGrade: -7
UseProjNav: 0
AddToNPL: 0
PNImportBitFile:
PNImportBmmFile:
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
SynProj: xst
ReloadPbde: 0
MainMhsEditor: 0
InsertNoPads: 0
HdlLang: VHDL
Simulator: mti
SimModel: BEHAVIORAL
SimXLib:
SimEdkLib:
MixLangSim: 1
UcfFile: data/system.ucf
Processor: microblaze_0
BootLoop: 0
XmdStub: 0
SwProj: TestApp_Memory
Processor: microblaze_0
Executable: TestApp_Memory/executable.elf
Source: TestApp_Memory/src/TestApp_Memory.c
DefaultInit: EXECUTABLE
InitBram: 1
Active: 1
CompilerOptLevel: 2
GlobPtrOpt: 0
DebugSym: 1
AsmOpt:
LinkOpt:
ProgStart:
StackSize:
HeapSize:
LinkerScript: TestApp_Memory/src/TestApp_Memory_LinkScr
ProgCCFlags:
/trunk/TestApp_Memory/src/TestApp_Memory.c
0,0 → 1,88
/*
* * Copyright (c) 2004 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*/
 
/*
* Xilinx EDK 7.1.2 EDK_H.12.5.1
*
* This file is a sample test application
*
* This application is intended to test and/or illustrate some
* functionality of your system. The contents of this file may
* vary depending on the IP in your system and may use existing
* IP driver functions. These drivers will be generated in your
* XPS project when you run the "Generate Libraries" menu item
* in XPS.
*
* Your XPS project directory is at:
* D:\mpdma
*/
 
 
// Located in: microblaze_0/include/xparameters.h
#include "xparameters.h"
 
#include "xutil.h"
 
//====================================================
 
int main (void) {
 
 
print("-- Entering main() --\r\n");
 
/*
* MemoryTest routine will not be run for the memory at
* 0x00000000 (dlmb_cntlr)
* because it is being used to hold a part of this application program
*/
 
 
/* Testing DDR Memory (DDR_256MB_32MX64_rank1_row13_col10_cl2_5)*/
{
XStatus status;
 
print("Starting MemoryTest for DDR_256MB_32MX64_rank1_row13_col10_cl2_5:\r\n");
print(" Running 32-bit test...");
status = XUtil_MemoryTest32((Xuint32*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 1024, 0xAAAA5555, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 16-bit test...");
status = XUtil_MemoryTest16((Xuint16*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 2048, 0xAA55, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 8-bit test...");
status = XUtil_MemoryTest8((Xuint8*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 4096, 0xA5, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
}
 
print("-- Exiting main() --\r\n");
return 0;
}
 
/trunk/TestApp_Memory/src/TestApp_Memory_LinkScr
0,0 → 1,99
 
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000;
 
/* Define all the memory regions in the system */
MEMORY
{
ilmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0xffff
}
 
/*
* Specify the default entry point to the program
*/
ENTRY(_start)
 
/*
* Define the sections, and where they are mapped in memory
*/
SECTIONS
{
 
.text : {
_ftext = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
_etext = .;
} > ilmb_cntlr
 
.rodata : {
_frodata = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
_erodata = .;
} > ilmb_cntlr
 
/* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */
.sdata2 : {
. = ALIGN(8);
_sdata2_start = .;
*(.sdata2)
. = ALIGN(8);
_sdata2_end = .;
} > ilmb_cntlr
_sdata2_size = _sdata2_end - _sdata2_start;
PROVIDE (_SDA2_BASE_ = _sdata2_start + (_sdata2_size / 2 ));
 
.data : {
. = ALIGN(4);
_fdata = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
_edata = .;
} > ilmb_cntlr
 
.eh_frame : {
*(.eh_frame)
} > ilmb_cntlr
 
/* Alignments by 8 to ensure that _SDA_BASE_ on a word boundary */
/* Note that .sdata and .sbss must be contiguous */
 
.sdata : {
. = ALIGN(8);
_ssro = .;
*(.sdata)
} > ilmb_cntlr
.sbss : {
. = ALIGN(4);
PROVIDE (__sbss_start = .);
*(.sbss)
. = ALIGN(8);
_essro = .;
} > ilmb_cntlr
PROVIDE (__sbss_end = _essro);
_ssro_size = _essro - _ssro;
PROVIDE (_SDA_BASE_ = _ssro + (_ssro_size / 2 ));
 
.bss : {
. = ALIGN(4);
PROVIDE (__bss_start = .);
*(.bss)
*(COMMON)
. = ALIGN(4);
PROVIDE (__bss_end = .);
} > ilmb_cntlr
 
.bss_stack : {
. = ALIGN(8);
_heap = .;
_heap_start = _heap;
. += _STACK_SIZE;
. = ALIGN(8);
_stack = .;
__stack = _stack;
} > ilmb_cntlr
}
 
/trunk/data/system.ucf
0,0 → 1,347
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################
 
Net sys_clk_pin LOC=AJ15;
Net sys_clk_pin IOSTANDARD = LVCMOS25;
Net sys_rst_pin LOC=AH5;
Net sys_rst_pin IOSTANDARD = LVTTL;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
 
## FPGA pin constraints
Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8;
Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7;
Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW;
Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH15;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AF21;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AG21;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AC19;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AD19;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AE22;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AE21;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AH22;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AE15;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AD15;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG14;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AF14;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AE14;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AD14;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AC15;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AB15;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AH9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE10;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AE9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AD12;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AC12;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AG10;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AF10;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB16;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AD17;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AC16;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS25;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin SLEW = SLOW;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin DRIVE = 8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD16;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<12> LOC=M25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<12> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<11> LOC=N25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<11> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<10> LOC=L26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<10> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<9> LOC=M29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<9> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<8> LOC=K30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<8> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<7> LOC=G25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<6> LOC=G26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<5> LOC=D26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<4> LOC=J24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<3> LOC=K24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<2> LOC=F28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<1> LOC=F30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<0> LOC=M24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<1> LOC=M26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<0> LOC=K26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin LOC=L27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin LOC=R26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin LOC=R24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin LOC=N29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin LOC=N26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<7> LOC=U26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> LOC=V29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> LOC=W29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> LOC=T22;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> LOC=W28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> LOC=W27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> LOC=W26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> LOC=W25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> LOC=E30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> LOC=J29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> LOC=M30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> LOC=P29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> LOC=V23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> LOC=AA25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> LOC=AC25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> LOC=AH26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> LOC=C27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> LOC=D28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> LOC=D29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> LOC=D30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> LOC=H25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> LOC=H26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> LOC=E27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> LOC=E28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> LOC=J26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> LOC=G27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> LOC=G28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> LOC=G30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> LOC=L23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> LOC=L24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> LOC=H27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> LOC=H28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> LOC=J27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> LOC=J28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> LOC=K29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> LOC=L29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> LOC=N23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> LOC=N24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> LOC=K27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> LOC=K28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> LOC=R22;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> LOC=M27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> LOC=M28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> LOC=P30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> LOC=P23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> LOC=P24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> LOC=N27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> LOC=N28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> LOC=V27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> LOC=Y30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> LOC=U24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> LOC=U23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> LOC=V26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> LOC=V25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> LOC=Y29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> LOC=AA29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> LOC=Y26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> LOC=AA28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> LOC=AA27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> LOC=W24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> LOC=W23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> LOC=AB28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> LOC=AB27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> LOC=AC29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> LOC=AB25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> LOC=AE29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> LOC=AA24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> LOC=AA23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> LOC=AD28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> LOC=AD27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> LOC=AF30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> LOC=AF29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> LOC=AF25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> LOC=AG30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> LOC=AG29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> LOC=AD26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> LOC=AD25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> LOC=AG28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> LOC=AH27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> LOC=AH29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> LOC=AC27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> LOC=AD29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> LOC=AB23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> LOC=AC28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> LOC=AD30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> LOC=AB24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_CLK_FB LOC=C16;
Net fpga_0_DDR_CLK_FB IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_CLK_FB_OUT LOC=G23;
Net fpga_0_DDR_CLK_FB_OUT IOSTANDARD = SSTL2_II;
/trunk/system.bsb
0,0 → 1,347
 
/trunk/system.mhs
0,0 → 1,278
#
# ##############################################################################
#
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
#
# Thu Oct 19 14:57:41 2006
#
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -7
#
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory : 64 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 Single Rank = 256 MB
#
# ##############################################################################
 
 
PARAMETER VERSION = 2.1.0
 
 
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = OUTPUT, VEC = [6:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = INOUT, VEC = [15:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, DIR = OUTPUT, VEC = [0:2]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, DIR = OUTPUT, VEC = [0:2]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, DIR = OUTPUT, VEC = [0:12]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, DIR = OUTPUT, VEC = [0:1]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, DIR = OUTPUT, VEC = [0:7]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, DIR = INOUT, VEC = [0:7]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, DIR = INOUT, VEC = [0:63]
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
PORT sys_rst_pin = sys_rst_s, DIR = INPUT
 
 
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END
 
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
 
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
 
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
 
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
 
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
 
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END
 
BEGIN opb_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER HW_VER = 1.00.c
PARAMETER C_MEM_WIDTH = 16
PARAMETER C_BASEADDR = 0x41800000
PARAMETER C_HIGHADDR = 0x4180ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END
 
BEGIN opb_ddr
PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
PARAMETER HW_VER = 2.00.b
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CLK_PAIRS = 4
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 100000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 20000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_DDR_DWIDTH = 64
PARAMETER C_MEM0_BASEADDR = 0x30000000
PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
PORT Device_Clk90_in = clk_90_s
PORT Device_Clk90_in_n = clk_90_n_s
PORT Device_Clk = sys_clk_s
PORT Device_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
 
BEGIN util_vector_logic
PARAMETER INSTANCE = sysclk_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = sys_clk_s
PORT Res = sys_clk_n_s
END
 
BEGIN util_vector_logic
PARAMETER INSTANCE = clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = clk_90_s
PORT Res = clk_90_n_s
END
 
BEGIN util_vector_logic
PARAMETER INSTANCE = ddr_clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_clk_90_s
PORT Res = ddr_clk_90_n_s
END
 
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
 
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_PHASE_SHIFT = 60
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END
 
/trunk/etc/bitgen.ut
0,0 → 1,21
-g ConfigRate:4
-g CclkPin:PULLUP
-g TdoPin:PULLNONE
-g M1Pin:PULLDOWN
-g DonePin:PULLUP
-g DriveDone:No
-g StartUpClk:JTAGCLK
-g DONE_cycle:4
-g GTS_cycle:5
-g M0Pin:PULLUP
-g M2Pin:PULLUP
-g ProgPin:PULLUP
-g TckPin:PULLUP
-g TdiPin:PULLUP
-g TmsPin:PULLUP
-g DonePipe:No
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:NONE
-m
-g Persist:No
/trunk/etc/fast_runtime.opt
0,0 → 1,80
FLOWTYPE = FPGA;
###############################################################
## Filename: fast_runtime.opt
##
## Option File For Xilinx FPGA Implementation Flow for Fast
## Runtime.
##
## Version: 4.1.1
###############################################################
#
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-bm <design>.bmm # Block RAM memory map file
<userdesign>; # User design - pick from xflow command line
-uc <design>.ucf; # ucf constraints
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
 
#
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-pr b; # Pack internal FF/latches into IOBs
#-fp <design>.mfp; # Floorplan file
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
 
#
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>_map.twr; # Output trace report file
-xml <design>_map.twx; # Output XML version of the timing report
#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
 
#
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
<inputdir><design>_map.ncd; # Input mapped NCD file
<design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
 
#
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>.twr; # Output trace report file
-xml <design>.twx; # Output XML version of the timing report
#-tsi <design>.tsi; # Produce Timing Specification Interaction report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce
 
 
/trunk/etc/download.cmd
0,0 → 1,6
setMode -bscan
setCable -p auto
identify
assignfile -p 3 -file implementation/download.bit
program -p 3
quit
/trunk/etc/bitgen_spartan3.ut
0,0 → 1,15
-g CclkPin:PULLUP
-g TdoPin:PULLNONE
-g M1Pin:PULLDOWN
-g DonePin:PULLUP
-g StartUpClk:JTAGCLK
-g M0Pin:PULLUP
-g M2Pin:PULLUP
-g ProgPin:PULLUP
-g TckPin:PULLUP
-g TdiPin:PULLUP
-g TmsPin:PULLUP
-g LCK_cycle:NoWait
-g Security:NONE
-m
-g Persist:No

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