URL
https://opencores.org/ocsvn/mytwoqcache/mytwoqcache/trunk
Subversion Repositories mytwoqcache
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/mytwoqcache/trunk/2QCache.vhd
1,41 → 1,41
---------------------------------------------------------------------------------- |
-- Company: Gerhard Hohner |
-- Engineer: Gerhard Hohner |
-- |
-- Create Date: 07:41:47 12/14/2010 |
-- Design Name: 2Q cache |
-- Module Name: Cache - Rtl |
-- Project Name: |
-- Target Devices: designed for spartan 3A, but no dependecies |
-- Tool versions: |
-- Description: implements 2Q cache strategy, write back |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
---------------------------------------------------------------------------------- |
library IEEE, work; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_arith.all; |
use work.global.all; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity Cache is |
generic( constant blocksizeld: integer := 11; -- ld of size of one tagram |
constant ldways: integer := 1; -- ld of number of tagrams |
constant ldCachedWords: integer := 2); -- ld of number of 32-bit words |
-- in one cacheline |
port( nReset: in std_ulogic; -- System reset active low |
Clock: in std_ulogic; -- System Clock |
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 07:41:47 12/14/2010 |
-- Design Name: |
-- Module Name: Cache - Rtl |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE, work; |
use IEEE.std_logic_1164.all; |
use IEEE.std_logic_arith.all; |
use work.global.all; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity Cache is |
generic( constant blocksizeld: integer := 11; |
constant ldways: integer := 1; |
constant ldCachedWords: integer := 2); |
port( nReset: in std_ulogic; -- System reset active low |
Clock: in std_ulogic; -- System Clock |
AddressIn: in std_ulogic_vector(RAMrange'high + 1 downto 0); -- Address of memory fetch |
DataIn: in std_ulogic_vector( 31 downto 0); -- Data to write |
IOCode: in std_ulogic_vector(2 downto 0); -- operation |
DataIn: in std_ulogic_vector( 31 downto 0); -- Data to write |
IOCode: in std_ulogic_vector(2 downto 0); -- operation |
-- Bit |
-- 2 0 read |
-- 1 write |
42,50 → 42,48
-- 1 0 11 word |
-- 10 halfword |
-- 01 single byte |
-- 00 no operation |
DataOut: out std_ulogic_vector( 31 downto 0); -- Data read |
-- 00 no operation |
DataOut: out std_ulogic_vector( 31 downto 0); -- Data read |
done: out std_ulogic; |
-- memory interface |
AddressOut: out std_ulogic_vector(RAMrange'high downto 0); -- memory address |
DataBlockIn: in std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data from memory |
reads: out std_ulogic; -- read memory |
DataBlockOut: out std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data to memory |
Mask: out std_ulogic_vector( 2 ** ldCachedWords * 4 - 1 downto 0); -- enables for each byte active low |
-- memory interface |
AddressOut: out std_ulogic_vector(RAMrange'high downto 0); -- memory address |
DataBlockIn: in std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data from memory |
reads: out std_ulogic; -- read memory |
DataBlockOut: out std_ulogic_vector( 2 ** ldCachedWords * 32 - 1 downto 0); -- data to memory |
Mask: out std_ulogic_vector( 2 ** ldCachedWords * 4 - 1 downto 0); -- enables for each byte active low |
writes: out std_ulogic; -- write memory |
led: out std_ulogic_vector(0 to 1); -- control led for tests |
ack: in std_ulogic -- acknowledge from memory |
); |
end Cache; |
|
ack: in std_ulogic -- acknowledge from memory |
); |
end Cache; |
|
architecture Rtl of Cache is |
constant ways: integer := 2 ** ldways; -- number of tagrams |
constant ldqueue: integer := 1; -- ld of number of fifos ( 1 for 2Q strategy) |
-- next two constants can be modified |
constant ldram: integer := blocksizeld + ldways - 1; -- ld of size of cacheram |
constant ldqueuelength: integer := ldram; -- ld of size of one fifo |
constant ways: integer := 2 ** ldways; |
constant ldqueue: integer := 1; |
constant ldram: integer := blocksizeld + ldways - 1; |
constant ldqueuelength: integer := ldram; |
|
type IOType is ( Start, busy); |
type tType is ( inittag, startt, startt1, tagtest, tagwait, stateget, stateget1, finish); |
type IOType is ( Start, busy); |
type tType is ( inittag, startt, startt1, tagtest, tagwait, stateget, stateget1, finish, finished); |
type rType is ( raminit, ramstart, ramstart1, ramcheck, ramcheck1, ramcheck2, ramread, ramread1, ramupdate, |
ramupdate1, ramupdate2, ramupdate3, ramflush, ramflush1, ramwait, ramwait1, ramclean, ramclean1); |
type fType is ( queuestart, queuewait, queuewaitAm1, queuewaitAm2, queuewaitA11, queuewaitA12, queueelim); |
subtype myint is natural range 15 downto 0; |
type TagRAMType is record |
cacheAddr: std_ulogic_vector( ldram - 1 downto 0); |
cacheValid: std_ulogic; |
Tag: std_ulogic_vector( RAMrange'high downto 2 + ldCachedWords + blocksizeld); |
TagValid: std_ulogic; |
ramupdate1, ramupdate2, ramupdate3, ramflush, ramflush1, ramwait, ramwait1, ramclean, ramclean1); |
type fType is ( queuestart, queuewait, queuewaitAm1, queuewaitAm2, queuewaitA11, queuewaitA12, queueelim); |
subtype myint is natural range 15 downto 0; |
type TagRAMType is record |
cacheAddr: std_ulogic_vector( ldram - 1 downto 0); |
cacheValid: std_ulogic; |
Tag: std_ulogic_vector( RAMrange'high downto 2 + ldCachedWords + blocksizeld); |
TagValid: std_ulogic; |
end record; |
type WordType is record |
Word: std_ulogic_vector(31 downto 0); |
Word: std_ulogic_vector(31 downto 0); |
Modified: std_ulogic_vector( 3 downto 0); |
end record; |
type WordArray is array ( 2 ** ldCachedWords - 1 downto 0) of WordType; |
type CacheType is record |
type WordArray is array ( 2 ** ldCachedWords - 1 downto 0) of WordType; |
type CacheType is record |
Words: WordArray; |
FiFoaddr: std_ulogic_vector( ldqueuelength - 1 downto 0); |
counter: std_ulogic_vector( ldqueue - 1 downto 0); |
end record; |
Am: std_ulogic; -- redifined and renamed |
end record; |
type FiFoType is record |
Word: std_ulogic_vector( blocksizeld - 1 downto 0); |
way: std_ulogic_vector( ldways downto 0); |
100,7 → 98,7
type RAMFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( 35 downto 0); |
type RAMFiles is array ( 2 ** ldCachedWords - 1 downto 0) of RAMFile; |
type RAMBuffer is array ( 2 ** ldCachedWords - 1 downto 0) of std_ulogic_vector( 35 downto 0); |
type AFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldqueuelength + ldqueue - 1 downto 0); |
type AFile is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldqueuelength downto 0); -- redimensioned |
|
type myarrayf is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( ldram - 1 downto 0); |
type myarrayA is array ( 2 ** ldram - 1 downto 0) of std_ulogic_vector( blocksizeld + ldways + 1 downto 0); |
107,7 → 105,7
|
signal RAMs: RAMFiles; |
signal Ax: AFile; |
signal tagRAM: TagFiles; |
signal tagRAM: TagFiles; |
signal tagdummy, tagBuff, TagRAMIn, TagRAMOut: TagRAMarray; |
signal RecBuff, CacheIn, CacheOut: CacheType; |
signal blockIn, blockOut: WordArray; |
117,37 → 115,36
signal putAm, removeAm, getAm, emptyAm, fullAm: std_ulogic; |
signal A1Inaddr, A1Outaddr, AmInaddr, AmOutaddr: std_ulogic_vector( ldqueuelength - 1 downto 0); |
signal emptyf, getf, putf: std_ulogic; |
signal queueentry: std_ulogic_vector( blocksizeld - 1 downto 0); |
signal cindex, FreeOut, FreeIn: std_ulogic_vector( ldram - 1 downto 0); |
signal ramf: myarrayf; |
signal counterf: unsigned( ldram downto 0); |
signal cindex, FreeOut, FreeIn: std_ulogic_vector( ldram - 1 downto 0); |
signal ramf: myarrayf; |
signal counterf: unsigned( ldram downto 0); |
signal firstf, lastf: unsigned( ldram - 1 downto 0); |
signal newFiFoAddr: std_ulogic_vector( ldqueuelength - 1 downto 0); |
signal newcounter: std_ulogic_vector( ldqueue - 1 downto 0); |
signal newAm: std_ulogic; -- redifined and renamed |
signal initcount: unsigned( blocksizeld - 1 downto 0); |
signal initcount1: unsigned( ldram - 1 downto 0); |
signal ramA1: myarrayA; |
signal counterA1: unsigned( ldqueuelength downto 0); |
signal firstA1, lastA1: unsigned( ldqueuelength - 1 downto 0); |
signal ramAm: myarrayA; |
signal counterAm: unsigned( ldqueuelength downto 0); |
signal firstAm, lastAm: unsigned( ldqueuelength - 1 downto 0); |
signal ramA1: myarrayA; |
signal counterA1: unsigned( ldqueuelength downto 0); |
signal firstA1, lastA1: unsigned( ldqueuelength - 1 downto 0); |
signal ramAm: myarrayA; |
signal counterAm: unsigned( ldqueuelength downto 0); |
signal firstAm, lastAm: unsigned( ldqueuelength - 1 downto 0); |
|
signal AddressInh: std_ulogic_vector( AddressIn'range); |
signal IOCodeh: std_ulogic_vector( IOCode'range); |
signal AddressInt: std_ulogic_vector( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords); |
signal found, free, elim, del: myint; |
signal AddressInh: std_ulogic_vector( AddressIn'high -1 downto 0); |
signal IOCodeh: std_ulogic_vector( IOCode'range); |
signal toFlush, AddressInt: std_ulogic_vector( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords); |
signal found, free, elim, del: myint; |
signal stateIO: IOType; |
signal statetag: tType; |
signal stateram: rType; |
signal statequeue: fType; |
signal entered, enableram, enablequeue, queuedone, readsh, writesh, doneh, cleared, |
interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt: std_ulogic; |
|
begin |
signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, |
interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt: std_ulogic; |
|
begin |
|
|
|
|
|
blockIO: process( nReset, Clock, readb, writeb) is |
variable s: std_ulogic; |
begin |
201,7 → 198,7
|
tagrams: process ( nReset, Clock) is |
variable a, b, d: myint; |
variable DataInTag, DataOutTag: TagBuffer; |
variable DataInTag, DataOutTag: TagBuffer; |
begin |
if rising_edge(Clock) then |
if nReset /= '1' then |
210,6 → 207,7
enableram <= '0'; |
found <= 15; |
free <= 15; |
done <= '0'; -- NEW |
initcount <= ( others => '0'); |
AddressInt <= ( others => '0'); |
IOCodeh <= ( others => '0'); |
233,36 → 231,33
writet <= '1'; |
end if; |
when startt => |
-- valid IOCode and valid address? |
if IOCode( 1 downto 0) /= "00" and AddressIn( AddressIn'high) = '0' then |
-- request encountered |
AddressInh <= AddressIn; |
IOCodeh <= IOCode; |
AddressInh <= AddressIn(AddressInh'range); |
IOCodeh <= IOCode; |
AddressInt <= AddressIn( AddressInt'range); |
DataInh <= DataIn; |
statetag <= startt1; |
end if; |
|
writet <= '0'; |
when startt1 => |
statetag <= tagtest; |
when tagtest => |
a := 15; |
a := 15; |
b := 15; |
|
for i in 0 to TagRAMarray'high loop |
if tagRAMOut( i).tagValid = '1' then |
if AddressInh(tagRAMout( i).tag'range) = tagRAMout( i).tag then |
|
for i in 0 to TagRAMarray'high loop |
if tagRAMOut( i).tagValid = '1' then |
if AddressInh(tagRAMout( i).tag'range) = tagRAMout( i).tag then |
a := i; -- present |
end if; |
else |
b := i; -- free entry |
end if; |
end loop; |
end if; |
else |
b := i; -- free entry |
end if; |
end loop; |
|
found <= a; |
free <= b; |
|
found <= a; |
free <= b; |
|
if stateram = ramstart then |
enableram <= '1'; |
statetag <= tagwait; |
272,7 → 267,7
|
if interrupt = '1' then |
enableram <= '0'; |
AddressInt <= queueentry; |
AddressInt <= toFlush; |
statetag <= stateget; |
elsif queuedone = '1' then |
enableram <= '0'; |
302,8 → 297,13
tagRAMIn <= tagBuff; |
writet <= '1'; |
AddressInt <= AddressInh( AddressInt'range); |
statetag <= startt; |
done <= '1'; |
statetag <= finished; |
end if; |
when finished => -- NEW |
writet <= '0'; |
done <= '0'; |
statetag <= startt; |
end case; |
|
for i in tagRAM'range loop |
311,8 → 311,6
|
if writet = '1' then |
tagRAM(i)(to_integer( AddressInt)) <= DataInTag( i); |
led(0) <= '1'; |
led(1) <= '0'; |
else |
DataOutTag( i) := tagRAM(i)(to_integer( AddressInt)); |
|
320,8 → 318,6
TagRAMOut( i).cacheValid <= DataOutTag( i)( ldram); |
TagRAMOut( i).Tag <= DataOutTag( i)( DataOutTag( 0)'high - 1 downto ldram + 1); |
TagRAMOut( i).TagValid <= DataOutTag( i)( DataOutTag( 0)'high); |
led(0) <= '0'; |
led(1) <= '1'; |
end if; |
end loop; |
end if; |
330,14 → 326,14
|
dataram: process (nReset, Clock, enableram) is |
variable en, acc, hi: std_ulogic; |
variable f, g: std_ulogic_vector( ldqueuelength + ldqueue - 1 downto 0); |
variable f, g: std_ulogic_vector( CacheIn.FiFoAddr'length downto 0); |
variable a, b: RAMBuffer; |
variable index, index1: integer; |
|
variable address: std_ulogic_vector( ldram - 1 downto 0); |
variable uaddress: unsigned( ldram - 1 downto 0); |
variable address: std_ulogic_vector( ldram - 1 downto 0); |
variable uaddress: unsigned( ldram - 1 downto 0); |
variable datum: std_ulogic_vector( FreeIn'range); |
variable w: std_ulogic; |
variable w: std_ulogic; |
begin |
if rising_edge(Clock) then |
if nReset /= '1' then |
353,10 → 349,9
accqueue <= '0'; |
initcount1 <= ( others => '0'); |
FreeIn <= ( others => '0'); |
firstf <= ( others => '0'); |
lastf <= ( others => '0'); |
counterf <= ( others => '0'); |
entered <= '0'; |
firstf <= ( others => '0'); |
lastf <= ( others => '0'); |
counterf <= ( others => '0'); |
else |
hi := accinterrupt or interrupt; |
acc := accqueue or queuedone; |
382,15 → 377,11
when ramstart => |
putf <= '0'; |
|
if enableram = '1' then |
if entered = '0' then |
tagBuff <= tagRAMOut; |
elim <= 15; |
entered <= '1'; |
end if; |
|
if enableram = '1' then -- UPDATE |
tagBuff <= tagRAMOut; |
elim <= 15; |
stateram <= ramstart1; |
end if; |
end if; |
when ramstart1 => |
putf <= '0'; |
|
414,7 → 405,7
when ramcheck1 => |
stateram <= ramcheck2; |
when ramcheck2 => |
if cacheOut.counter(0) = '0' or elim = ways - 1 then |
if cacheOut.Am = '0' or elim = ways - 1 then |
RecBuff <= cacheOut; |
en := '1'; |
stateram <= ramwait; |
467,7 → 458,7
end if; |
end if; |
when ramwait1 => |
if del /= 15 and enableram = '1' then |
if del /= 15 and enableram = '1' then |
cindex <= tagdummy( del).cacheAddr; |
FreeIn <= tagdummy( del).cacheAddr; |
putf <= tagdummy( del).cacheValid; |
522,12 → 513,11
end if; |
|
cacheIn.FiFoAddr <= newFiFoAddr; |
cacheIn.counter <= newcounter; |
cacheIn.Am <= newAm; |
|
getf <= '0'; |
writec <= '1'; |
doneh <= '1'; |
entered <= '0'; |
|
stateram <= ramupdate3; |
when ramupdate3 => |
545,7 → 535,7
if del /= 15 then |
blockOut <= cacheOut.words; |
writeb <= tagdummy( del).tagValid; |
AddressOut <= tagdummy( del).tag & queueentry & ( ldCachedWords + 1 downto 0 => '0'); |
AddressOut <= tagdummy( del).tag & toFlush & ( ldCachedWords + 1 downto 0 => '0'); |
stateram <= ramflush; |
end if; |
when ramflush => |
581,13 → 571,13
enablequeue <= en; |
accqueue <= acc; |
|
f := CacheIn.counter & CacheIn.FiFoAddr; |
f := CacheIn.Am & CacheIn.FiFoAddr; |
if writec = '1' then |
Ax( to_integer( cindex)) <= f; |
else |
g := Ax( to_integer( cindex)); |
CacheOut.FiFoAddr <= g( ldqueuelength - 1 downto 0); |
CacheOut.counter <= g( ldqueuelength + ldqueue - 1 downto ldqueuelength); |
CacheOut.FiFoAddr <= g( g'high - 1 downto g'low); |
CacheOut.Am <= g( g'high); |
end if; |
|
for i in RAMBuffer'range loop |
601,28 → 591,28
end if; |
end loop; |
|
if putf = '1' then |
address := std_ulogic_vector( firstf); |
datum := FreeIn; |
firstf <= firstf + 1; |
counterf <= counterf + 1; |
if putf = '1' then |
address := std_ulogic_vector( firstf); |
datum := FreeIn; |
firstf <= firstf + 1; |
counterf <= counterf + 1; |
w := '1'; |
else |
uaddress := lastf; |
if getf = '1' and counterf /= 0 then |
uaddress := lastf; |
if getf = '1' and counterf /= 0 then |
counterf <= counterf - 1; |
uaddress := uaddress + 1; |
uaddress := uaddress + 1; |
end if; |
lastf <= uaddress; |
lastf <= uaddress; |
address := std_ulogic_vector( uaddress); |
w := '0'; |
end if; |
w := '0'; |
end if; |
|
if w = '1' then |
ramf( to_integer( address)) <= datum; |
ramf( to_integer( address)) <= datum; |
else |
FreeOut <= ramf( to_integer( address)); |
end if; |
FreeOut <= ramf( to_integer( address)); |
end if; |
|
end if; |
end if; |
629,42 → 619,40
end process dataram; |
|
emptyf <= '1' when counterf = 0 else '0'; |
|
done <= doneh and accqueue; |
|
queues: process( nReset, Clock, enablequeue) is |
variable acc, hi: std_ulogic; |
variable A1OutBuff, AmOutBuff: std_ulogic_vector( blocksizeld + ldways + 1 downto 0); |
variable addressA1: std_ulogic_vector( ldqueuelength - 1 downto 0); |
variable diff, uaddressA1: unsigned( ldqueuelength - 1 downto 0); |
variable addressA1: std_ulogic_vector( ldqueuelength - 1 downto 0); |
variable diff, uaddressA1: unsigned( ldqueuelength - 1 downto 0); |
variable datumA1: std_ulogic_vector( A1OutBuff'range); |
variable wA1: std_ulogic; |
variable addressAm: std_ulogic_vector( ldqueuelength - 1 downto 0); |
variable uaddressAm: unsigned( ldqueuelength - 1 downto 0); |
variable wA1: std_ulogic; |
variable addressAm: std_ulogic_vector( ldqueuelength - 1 downto 0); |
variable uaddressAm: unsigned( ldqueuelength - 1 downto 0); |
variable datumAm: std_ulogic_vector( AmOutBuff'range); |
variable wAm: std_ulogic; |
variable wAm: std_ulogic; |
begin |
if rising_edge(Clock) then |
if nReset /= '1' then |
del <= 15; |
statequeue <= queuestart; |
queuedone <= '0'; |
interrupt <= '0'; |
accdone <= '0'; |
cleared <= '0'; |
del <= 15; |
firstA1 <= ( others => '0'); |
A1Outaddr <= ( others => '0'); |
lastA1 <= ( others => '0'); |
preempted <= '0'; |
firstA1 <= ( others => '0'); |
A1Outaddr <= ( others => '0'); |
lastA1 <= ( others => '0'); |
counterA1 <= ( others => '0'); |
firstAm <= ( others => '0'); |
AmOutaddr <= ( others => '0'); |
lastAm <= ( others => '0'); |
counterAm <= ( others => '0'); |
firstAm <= ( others => '0'); |
AmOutaddr <= ( others => '0'); |
lastAm <= ( others => '0'); |
counterAm <= ( others => '0'); |
else |
hi := '0'; |
acc := accdone or doneh; |
|
diff := firstA1 - unsigned( RecBuff.FiFoAddr); -- relative position in A1 |
diff := firstA1 - unsigned( RecBuff.FiFoAddr); |
|
case statequeue is |
when queuestart => |
672,17 → 660,17
|
if enablequeue = '1' then |
if found /= 15 then |
if RecBuff.counter(0) = '1' or -- in Am |
( RecBuff.counter(0) = '0' and diff( diff'high) = '0') then -- in lower half of A1 |
if RecBuff.Am = '1' or -- in Am |
( RecBuff.Am = '0' and diff( diff'high) = '0') then -- in lower half of A1 |
queuedone <= '1'; |
newFiFoAddr <= RecBuff.FiFoAddr; |
newcounter <= RecBuff.counter; |
newAm <= RecBuff.Am; |
statequeue <= queuewait; |
elsif fullAm = '1' then |
-- Am full |
if AmOut.valid = '1' then |
del <= to_integer( AmOut.way); |
queueentry <= AmOut.word; |
toFlush <= AmOut.word; |
getAm <= '1'; |
hi := '1'; |
statequeue <= queuewait; |
701,7 → 689,7
-- remove last entry from A1 |
if A1Out.valid = '1' then |
del <= to_integer( A1Out.way); |
queueentry <= A1Out.word; |
toFlush <= A1Out.word; |
getA1 <= '1'; |
hi := '1'; |
statequeue <= queuewait; |
710,7 → 698,7
-- remove last entry from Am |
if AmOut.valid = '1' then |
del <= to_integer( AmOut.way); |
queueentry <= AmOut.word; |
toFlush <= AmOut.word; |
getAm <= '1'; |
hi := '1'; |
statequeue <= queuewait; |
728,7 → 716,7
if not ( to_integer( A1Out.way) = elim and |
A1Out.word = AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords)) then |
del <= to_integer( A1Out.way); |
queueentry <= A1Out.word; |
toFlush <= A1Out.word; |
statequeue <= queueelim; |
end if; |
|
735,6 → 723,7
getA1 <= '1'; |
end if; |
else |
getA1 <= '0'; -- NEW, inserted the only bug!!!!!!!!!!!!!! |
A1In.word <= AddressInh( 2 + ldCachedWords + blocksizeld - 1 downto 2 + ldCachedWords); |
A1In.way <= std_ulogic_vector(to_unsigned( elim, ldways + 1)); |
A1In.valid <= '1'; |
752,7 → 741,7
|
if acc = '1' then |
acc := '0'; |
del <= 15; |
del <= 15; |
statequeue <= queuestart; |
end if; |
when queuewaitAm1 => |
761,7 → 750,7
statequeue <= queuewaitAm2; |
when queuewaitAm2 => |
newFiFoAddr <= AmOutAddr; |
newCounter(0) <= '1'; |
newAm <= '1'; |
queuedone <= '1'; |
statequeue <= queuewait; |
when queuewaitA11 => |
769,20 → 758,20
statequeue <= queuewaitA12; |
when queuewaitA12 => |
newFiFoAddr <= A1OutAddr; |
newCounter(0) <= '0'; |
newAm <= '0'; |
removeA1 <= '0'; |
removeAm <= '0'; |
queuedone <= '1'; |
cleared <= '0'; |
preempted <= '0'; |
statequeue <= queuewait; |
when queueelim => |
putA1 <= '0'; |
getA1 <= '0'; |
|
if RecBuff.counter(0) = '1' and cleared = '0' then |
if RecBuff.Am = '1' and preempted = '0' then |
AmInAddr <= RecBuff.FiFoAddr; |
removeAm <= '1'; |
elsif cleared = '0' then |
elsif preempted = '0' then |
A1InAddr <= RecBuff.FiFoAddr; |
removeA1 <= '1'; |
end if; |
789,7 → 778,7
|
if getA1 = '1' then |
hi := '1'; |
cleared <= '1'; |
preempted <= '1'; |
statequeue <= queuewait; |
else |
statequeue <= queuewaitA12; |
799,80 → 788,80
interrupt <= hi; |
accdone <= acc; |
|
if putA1 = '1' or removeA1 = '1' then |
if removeA1 = '0' then |
addressA1 := std_ulogic_vector( firstA1); |
if putA1 = '1' or removeA1 = '1' then |
if removeA1 = '0' then |
addressA1 := std_ulogic_vector( firstA1); |
datumA1 := A1In.valid & A1In.way & A1In.Word; |
firstA1 <= firstA1 + 1; |
counterA1 <= counterA1 + 1; |
A1Outaddr <= std_ulogic_vector( firstA1); |
else |
addressA1 := A1Inaddr( addressA1'range); |
datumA1 := ( others => '0'); |
firstA1 <= firstA1 + 1; |
counterA1 <= counterA1 + 1; |
A1Outaddr <= std_ulogic_vector( firstA1); |
else |
addressA1 := A1Inaddr( addressA1'range); |
datumA1 := ( others => '0'); |
end if; |
wA1 := '1'; |
else |
uaddressA1 := lastA1; |
if (getA1 = '1' or A1Out.valid = '0') and counterA1 /= 0 then |
counterA1 <= counterA1 - 1; |
uaddressA1 := uaddressA1 + 1; |
wA1 := '1'; |
else |
uaddressA1 := lastA1; |
if (getA1 = '1' or A1Out.valid = '0') and counterA1 /= 0 then |
counterA1 <= counterA1 - 1; |
uaddressA1 := uaddressA1 + 1; |
end if; |
lastA1 <= uaddressA1; |
addressA1 := std_ulogic_vector( uaddressA1); |
wA1 := '0'; |
wA1 := '0'; |
end if; |
|
if wA1 = '1' then |
ramA1( to_integer( addressA1)) <= datumA1; |
ramA1( to_integer( addressA1)) <= datumA1; |
else |
A1OutBuff := ramA1( to_integer( addressA1)); |
A1OutBuff := ramA1( to_integer( addressA1)); |
|
A1Out.Word <= A1OutBuff( blocksizeld - 1 downto 0); |
A1Out.way <= A1OutBuff( blocksizeld + ldways downto blocksizeld); |
A1Out.valid <= A1OutBuff( blocksizeld + ldways + 1); |
end if; |
end if; |
|
if putAm = '1' or removeAm = '1' then |
if removeAm = '0' then |
addressAm := std_ulogic_vector( firstAm); |
if putAm = '1' or removeAm = '1' then |
if removeAm = '0' then |
addressAm := std_ulogic_vector( firstAm); |
datumAm := AmIn.valid & AmIn.way & AmIn.Word; |
firstAm <= firstAm + 1; |
counterAm <= counterAm + 1; |
AmOutaddr <= std_ulogic_vector( firstAm); |
else |
addressAm := AmInaddr( addressAm'range); |
datumAm := ( others => '0'); |
firstAm <= firstAm + 1; |
counterAm <= counterAm + 1; |
AmOutaddr <= std_ulogic_vector( firstAm); |
else |
addressAm := AmInaddr( addressAm'range); |
datumAm := ( others => '0'); |
end if; |
wAm := '1'; |
else |
uaddressAm := lastAm; |
if (getAm = '1' or AmOut.valid = '0') and counterAm /= 0 then |
counterAm <= counterAm - 1; |
uaddressAm := uaddressAm + 1; |
wAm := '1'; |
else |
uaddressAm := lastAm; |
if (getAm = '1' or AmOut.valid = '0') and counterAm /= 0 then |
counterAm <= counterAm - 1; |
uaddressAm := uaddressAm + 1; |
end if; |
lastAm <= uaddressAm; |
addressAm := std_ulogic_vector( uaddressAm); |
wAm := '0'; |
wAm := '0'; |
end if; |
|
|
if wAm = '1' then |
ramAm( to_integer( addressAm)) <= datumAm; |
ramAm( to_integer( addressAm)) <= datumAm; |
else |
AmOutBuff := ramAm( to_integer( addressAm)); |
|
|
AmOut.Word <= AmOutBuff( blocksizeld - 1 downto 0); |
AmOut.way <= AmOutBuff( blocksizeld + ldways downto blocksizeld); |
AmOut.valid <= AmOutBuff( blocksizeld + ldways + 1); |
end if; |
end if; |
end if; |
end if; |
end process queues; |
|
fullA1 <= counterA1( counterA1'high); |
emptyA1 <= '1' when counterA1 = 0 else '0'; |
emptyA1 <= '1' when counterA1 = 0 else '0'; |
|
fullAm <= counterAm( counterAm'high); |
emptyAm <= '1' when counterAm = 0 else '0'; |
emptyAm <= '1' when counterAm = 0 else '0'; |
|
end Rtl; |
|
end Rtl; |
|