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URL https://opencores.org/ocsvn/ps2/ps2/trunk

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    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/trunk/bench/verilog/ps2_test_bench.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/02/18 18:08:31 mihad
// One bug fixed
//
// Revision 1.1.1.1 2002/02/18 16:16:55 mihad
// Initial project import - working
//
527,7 → 530,7
flags`SUBSEQ_WAITS = 0 ;
 
read_data`READ_ADDRESS = `KBD_DATA_REG ;
read_data`READ_SEL = 4'h1 ;
read_data`READ_SEL = 4'h8 ;
 
read_status = 0 ;
 
560,7 → 563,7
flags`SUBSEQ_WAITS = 0 ;
read_data`READ_ADDRESS = `KBD_STATUS_REG ;
read_data`READ_SEL = 4'h1 ;
read_data`READ_SEL = 4'h8 ;
read_status = 0 ;
597,7 → 600,7
 
write_data`WRITE_ADDRESS = address_i ;
write_data`WRITE_DATA = data_i ;
write_data`WRITE_SEL = 4'h1 ;
write_data`WRITE_SEL = 4'h8 ;
 
read_status_reg(kbd_status, ok_o) ;
 
/trunk/rtl/verilog/ps2_wb_if.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/02/18 18:07:55 mihad
// One bug fixed
//
// Revision 1.1.1.1 2002/02/18 16:16:56 mihad
// Initial project import - working
//
133,16 → 136,16
wire [7:0] status_byte = {perr, timeout, mouse_output_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full, input_buffer_full} ;
 
reg read_input_buffer_reg ;
wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[0] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h0) ;
wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h0) ;
 
reg write_output_buffer_reg ;
wire write_output_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[0] && !wb_ack_o && !write_output_buffer_reg && wb_we_i && (wb_adr_i[2:0] == 3'h0) ;
wire write_output_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i && (wb_adr_i[2:0] == 3'h0) ;
 
reg read_status_register_reg ;
wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[0] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h4) ;
wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h4) ;
 
reg send_command_reg ;
wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[0] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[2:0] == 3'h4) ;
wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[2:0] == 3'h4) ;
 
reg translate_o,
enable1,
/trunk/sim/rtl_sim/run/run_ps2_sim.scr
45,7 → 45,10
#// CVS Revision History
#//
#// $Log: not supported by cvs2svn $
#// Revision 1.1.1.1 2002/02/18 16:16:55 mihad
#// Initial project import - working
#//
#//
 
echo "-MESSAGES" > ./ncvlog.args
echo "-NOCOPYRIGHT" >> ./ncvlog.args
55,6 → 58,7
echo "-INCDIR ../../../rtl/verilog" >> ./ncvlog.args
echo '-DEFINE "PS2_NUM_OF_NORMAL_SCANCODES 85"' >> ./ncvlog.args
echo '-DEFINE "PS2_NUM_OF_EXTENDED_SCANCODES 38"' >> ./ncvlog.args
echo '-DEFINE "SIM"' >> ./ncvlog.args
 
if ( $# > 0 ) then
if ( $# == 1 ) then

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