OpenCores
URL https://opencores.org/ocsvn/r2000/r2000/trunk

Subversion Repositories r2000

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/trunk/r2000pl/bench/verilog/tb_r2000_soc.v
5,7 → 5,7
//// This file is part of the r2000pl Pipelined ////
//// opencores effort. ////
//// Simple Pipelined Mips 32 bits processor ////
//// <http://www.opencores.org/cores/YOUR DIRECTORY/> ////
//// <http://www.opencores.org/projects.cgi/web/r2000/> ////
//// ////
//// Module Description: ////
//// Test bench of the r2000pl cpu soc ////
/trunk/r2000pl/rtl/verilog/r2000/r2000_pipe_ctrl.v
119,7 → 119,7
// ---------------------------------------------- //
// When (RAW hazard) or (mult/div interlock) or (I-cache miss) then => : stall[PC, IF/ID], flush[ID/EX]
// When (D-cache miss) then => : stall[PC, IF/ID, ID/EX, EX/MEM, MEM/WB], freeze[EX, MEM, WB]
// When (D-cache miss) then => : stall[PC, IF/ID, ID/EX, EX/MEM], flush[MEM/WB], freeze[EX, MEM]
// When (eXception) then => :
// ---------------------------------------------- //
// STALL : stop do not update the pipe
170,8 → 170,8
end else
`endif //CP0
if(Event_DCacheMiss) begin
{IF_stall, IFID_stall , IDEX_stall , EXMEM_stall , MEMWB_stall} = { `HIGH, `HIGH, `HIGH, `HIGH, `HIGH};
{ EX_freeze , MEM_freeze , WB_freeze} = { `LOW, `LOW, `LOW};
{IF_stall, IFID_stall , IDEX_stall , EXMEM_stall , MEMWB_flush} = { `HIGH, `HIGH, `HIGH, `HIGH, `HIGH};
{ EX_freeze , MEM_freeze } = { `LOW, `LOW};
end else
if(Event_ICacheMiss || Event_MultDivInterlock || Event_RawHazard) begin
/trunk/r2000pl/sim/rtl_sim/bin/r2000pl.mpf
568,60 → 568,60
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 32 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_mux2.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_shifter.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 26 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_msel.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_cpu_pipe.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_mux3.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_master_if.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 29 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_mux3.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_cpu_pipe.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_shifter.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 26 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_msel.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_decoder.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_mux4.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_decoder.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_top.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 35 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_master_if.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 29 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_aluctrl.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_mux5.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_19 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_aluctrl.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_19 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_top.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 35 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_mux7.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_alu.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_22 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000_soc.v
Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_23 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_cp0.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_24 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_bradecoder.v
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_25 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/mem/asram_core.v
Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 36 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_26 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_rf.v
Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 33 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_27 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_slave_if.v
Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 34 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_28 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_multdiv.v
Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_29 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_forward.v
Project_File_P_29 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_30 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_d-cache.v
Project_File_P_30 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_31 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_regfile.v
Project_File_P_31 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 25 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_32 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_pipe.v
Project_File_P_32 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000_soc.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_22 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_alu.v
Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_23 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_bradecoder.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_24 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_cp0.v
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_25 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_rf.v
Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 33 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_26 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/mem/asram_core.v
Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 36 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_27 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_d-cache.v
Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_28 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_forward.v
Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_29 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_multdiv.v
Project_File_P_29 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_30 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/conmax/wb_conmax_slave_if.v
Project_File_P_30 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 34 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_31 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_pipe.v
Project_File_P_31 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_32 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_regfile.v
Project_File_P_32 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 25 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_33 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_multiplier.v
Project_File_P_33 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_34 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_divisor.v
Project_File_P_34 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_34 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_comparator.v
Project_File_P_34 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_35 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_cpu.v
Project_File_P_35 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_36 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_comparator.v
Project_File_P_36 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_36 = C:/CVSROOT/r2000/r2000pl/rtl/verilog/r2000/r2000_divisor.v
Project_File_P_36 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 0 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
/trunk/r2000pl/sim/rtl_sim/bin/r2000pl.prj
9,10 → 9,11
</project>
 
<workspace version="Crimson Editor 3.60">
<localfile path="C:\CVSROOT\r2000\r2000pl\rtl\verilog\r2000\r2000_pipe_ctrl.v" linenum="1" placement="0:1:-1:-1:-4:-23:0:0:652:595" />
<localfile path="C:\CVSROOT\r2000\r2000pl\rtl\verilog\r2000\r2000_cpu_pipe.v" linenum="1" placement="0:1:-1:-1:-4:-23:22:22:678:621" />
<localfile path="C:\CVSROOT\r2000\r2000pl\bench\verilog\tb_r2000_soc.v" linenum="1" placement="0:1:-1:-1:-4:-23:110:110:965:709" />
<localfile path="C:\CVSROOT\r2000\release.txt" linenum="334" placement="0:1:-1:-1:-4:-23:132:132:987:731" />
<localfile path="C:\CVSROOT\r2000\r2000pl\rtl\verilog\r2000\r2000_cp0.v" linenum="1" placement="2:3:-1:-1:-4:-23:176:176:1031:775" />
<localfile path="C:\CVSROOT\r2000\r2000pl\rtl\verilog\r2000\r2000_pipe_ctrl.v" linenum="136" placement="2:3:-1:-1:-4:-23:0:0:652:595" />
<localfile path="C:\CVSROOT\r2000\r2000pl\rtl\verilog\r2000\r2000_cpu_pipe.v" linenum="528" placement="0:1:-1:-1:-4:-23:22:22:678:621" />
<localfile path="C:\CVSROOT\r2000\release.txt" linenum="395" placement="0:1:-1:-1:-4:-23:132:132:987:731" />
<localfile path="C:\CVSROOT\r2000\r2000pl\rtl\verilog\r2000\r2000_cp0.v" linenum="1" placement="0:1:-1:-1:-4:-23:176:176:1031:775" />
<localfile path="C:\CVSROOT\r2000\r2000pl\rtl\verilog\r2000\define.h" linenum="319" placement="0:1:-1:-1:-4:-23:264:264:1119:863" />
<localfile path="C:\CVSROOT\r2000\r2000pl\bench\verilog\tb_r2000_soc.v" linenum="1" placement="0:1:-1:-1:-4:-23:286:286:1141:885" />
</workspace>
 
/trunk/release.txt
429,3 → 429,6
- The Pipeline must stall when Mult/Div unit is busy.
- Whether there's a mflo or mfhi.
- see `define MULTIPLE_ALU
 
- When D-Cache miss, there's no need to stall MEMWB and freeze WB.
- The solution is to flush MEMWB only.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.