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Rev 5 → Rev 6

/sdhc-sc-core/trunk/src/crc-ea.vhdl File deleted \ No newline at end of file
/sdhc-sc-core/trunk/src/tb-crc-ea.vhdl File deleted \ No newline at end of file
/sdhc-sc-core/trunk/src/crc-p.vhdl File deleted \ No newline at end of file
/sdhc-sc-core/trunk/src/grpCrc/unitCrc/src/Crc-Rtl-ea.vhdl
0,0 → 1,84
-------------------------------------------------
-- author: Rainer Kastl
--
-- CRC implementation with generic polynoms.
--
-- While the data is shifted in bit by bit iDataIn
-- has to be '1'. The CRC can be shifted out by
-- setting iDataIn to '0'.
-- If the CRC should be checked it has to be shifted
-- in directly after the data. If the remainder is 0,
-- the CRC is correct.
-------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.CRCs.all;
 
entity crc is
generic (
gPolynom : std_ulogic_vector := crc7
);
port (
iClk : in std_ulogic;
inResetAsync : in std_ulogic; -- Asynchronous low active reset
iClear : in std_ulogic; -- Synchronous reset for the registers
iDataIn : in std_ulogic; -- Signal that currently data is shifted in.
-- Otherwise the current remainder is shifted out.
iData : in std_ulogic; -- Data input
oSerial : out std_ulogic; -- Serial data output
oParallel : out std_ulogic_vector(gPolynom'high - 1 downto gPolynom'low)
-- parallel data output
);
begin
-- check the used polynom
assert gPolynom(gPolynom'high) = '1' report
"Invalid polynom: no '1' at the highest position." severity failure;
assert gPolynom(gPolynom'low) = '1' report
"Invalid polynom: no '1' at the lowest position." severity failure;
end crc;
 
architecture rtl of crc is
 
signal regs : std_ulogic_vector(oParallel'range);
 
begin
 
-- shift registers
crc : process (iClk, inResetAsync) is
variable input : std_ulogic;
begin
if (inResetAsync = '0') then
regs <= (others => '0');
elsif (rising_edge(iClk)) then
if (iClear = '1') then
regs <= (others => '0');
elsif (iClear = '0') then
if (iDataIn = '1') then
-- calculate CRC
input := iData xor regs(regs'high);
 
regs(0) <= input;
 
for idx in 1 to regs'high loop
if (gPolynom(idx) = '1') then
regs(idx) <= regs(idx-1) xor input;
else
regs(idx) <= regs(idx-1);
end if;
end loop;
else
-- shift data out
regs(0) <= '0';
for idx in 1 to regs'high loop
regs(idx) <= regs(idx-1);
end loop;
end if;
end if;
end if;
end process crc;
 
oParallel <= regs;
oSerial <= regs(regs'high);
 
end architecture rtl;
/sdhc-sc-core/trunk/src/grpCrc/unitCrc/src/tbCrc-bhv-ea.vhdl
0,0 → 1,135
-------------------------------------------------
-- tb-crc-ea.vhdl
-- author: Rainer Kastl
--
-- Testbench for the generic crc implementation.
-- Uses both crc7 as well as crc16 from the package
-- pcrc.
-------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.CRCs.all;
 
entity tbCrc is
end entity tbCrc;
 
architecture bhv of tbCrc is
signal Clk, nResetAsync : std_ulogic := '0';
signal CRC_7 : std_ulogic_vector(6 downto 0);
signal CRC_16 : std_ulogic_vector(15 downto 0);
signal DataToCrc_7, DataToCrc_16 : std_ulogic;
signal CRCDataIn_7,CRCClear_7 : std_ulogic;
signal CRCDataIn_16,CRCClear_16 : std_ulogic;
signal SerialCRC_7, SerialCRC_16 : std_ulogic;
 
signal EndOfSim : boolean := false; -- stop clock generation when true
 
-- Use the negative clock edge to setup the signals in front of the positive
-- edge. Therefore no extra clock cycle is needed.
procedure Test (
Data : in std_ulogic_vector;
Valid : in std_ulogic_vector;
signal CRC : in std_ulogic_vector;
signal SerialCRC : in std_ulogic;
signal CRCDataIn : out std_ulogic;
signal DataToCrc : out std_ulogic;
signal CRCClear : out std_ulogic) is
 
variable counter : natural := 0;
 
begin
wait until Clk = '0';
-- shift data in
CRCClear <= '0';
CRCDataIn <= '1';
 
while (counter <= Data'high) loop
DataToCrc <= Data(counter);
counter := counter + 1;
wait until Clk = '0';
end loop;
 
-- compare parallel output
CRCDataIn <= '0';
 
assert (Valid = CRC) report "CRC error." severity error;
 
-- compare serial output
counter := 0;
while (counter <= CRC'high) loop
assert (Valid(counter) = SerialCRC) report "Serial CRC error"
severity error;
counter := counter + 1;
wait until clk = '0';
end loop;
 
-- clear the registers, not needed after shifting the serial data out
CRCClear <= '1';
wait until Clk = '0';
 
CRCClear <= '0';
end procedure;
 
begin
 
Clk <= not Clk after 10 ns when EndOfSim = false else '0';
nResetAsync <= '1' after 100 ns;
 
generate_and_test7 : process is
procedure Test7(
Data : in std_ulogic_vector;
Valid : in std_ulogic_vector) is
begin
Test(Data, Valid, CRC_7, SerialCRC_7, CRCDataIn_7, DataToCrc_7,
CRCClear_7);
end procedure;
 
procedure Test16(
Data : in std_ulogic_vector;
Valid : in std_ulogic_vector) is
begin
Test(Data, Valid, CRC_16, SerialCRC_16, CRCDataIn_16, DataToCrc_16,
CRCClear_16);
end procedure;
 
variable data : std_ulogic_vector(0 to (512*8)-1) := (others => '1');
begin
wait until (nResetAsync = '1');
 
Test7("0100000000000000000000000000000000000000","1001010");
Test7("01000000000000000000000000000000000000001001010","0000000");
Test7("0101000100000000000000000000000000000000","0101010");
Test7("01010001000000000000000000000000000000000101010","0000000");
Test7("0001000100000000000000000000100100000000","0110011");
Test7("00010001000000000000000000001001000000000110011","0000000");
Test16(data, X"7FA1");
Test16(X"1234567890ABCDEF", X"2FBC");
Test16(X"1234567890ABCDEF2FBC", X"0000");
Test16(X"F0F0F0F0F0F0F0F0F0F0", X"63E2");
Test16(X"F0F0F0F0F0F0F0F0F0F063E2", X"0000");
 
EndOfSim <= true;
report "Simulation finished." severity note;
end process;
 
duv7: entity work.crc
port map (iClk => Clk,
inResetAsync => nResetAsync,
iDataIn => CRCDataIn_7,
iClear => CRCClear_7,
iData => DataToCrc_7,
oParallel => CRC_7,
oSerial => SerialCRC_7);
 
duv16: entity work.crc
generic map (gPolynom => crc16)
port map (iClk => Clk,
inResetAsync => nResetAsync,
iDataIn => CRCDataIn_16,
iClear => CRCClear_16,
iData => DataToCrc_16,
oParallel => CRC_16,
oSerial => SerialCRC_16);
 
end architecture bhv;
/sdhc-sc-core/trunk/src/grpCrc/unitCrc/sim/wave.do
0,0 → 1,135
add wave *
/sdhc-sc-core/trunk/src/grpCrc/unitCrc/sim/tbcrc-unattented.tcl
0,0 → 1,3
do tbcrc.tcl
exit
 
/sdhc-sc-core/trunk/src/grpCrc/unitCrc/sim/tbcrc.tcl
0,0 → 1,22
set pkgs {Crc CRCs}
set units {Crc Crc {Rtl}}
set tb Crc
set tbarch bhv
 
vlib work
vmap work work
 
foreach {grp pkg} $pkgs {
vcom ../../../grp$grp/pkg$pkg/src/$pkg-p.vhdl
}
 
foreach {grp en arch} $units {
vcom ../../../grp$grp/unit$en/src/$en-$arch-ea.vhdl
}
 
vcom ../../unit$tb/src/tb$tb-$tbarch-ea.vhdl
 
vsim tb$tb
 
do wave.do
run -all
/sdhc-sc-core/trunk/src/grpCrc/pkgCRCs/src/CRCs-p.vhdl
0,0 → 1,10
library ieee;
use ieee.std_logic_1164.all;
 
package CRCs is
 
constant crc7 : std_ulogic_vector(7 downto 0) := B"1000_1001";
constant crc16 : std_ulogic_vector(16 downto 0) := (16 => '1', 12 => '1',
5 => '1', 0 => '1', others => '0');
 
end package CRCs;
/sdhc-sc-core/trunk/sim/modelsim.ini File deleted
/sdhc-sc-core/trunk/sim/tbcrc-unattented.tcl File deleted
/sdhc-sc-core/trunk/sim/tbcrc.tcl File deleted

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