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Rev 5 → Rev 6
/trunk/VHDL/linked_list_mem_pkg.vhd
1,26 → 1,62
-- $Author: rpaley_yid $ |
-- $Date: 2003-01-14 21:48:10 $ |
-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/linked_list_mem_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $ |
-- $Locker |
-- $Revision: 1.1.1.1 $ |
-- $State: Exp $ |
|
-- -------------------------------------------------------------------------- |
-- |
-- Purpose: This package implements functions to allocate, write, read, and |
-- deallocate a linked list based memory. |
---------------------------------------------------------------------- |
---- ---- |
---- Single port asynchronous RAM simulation model ---- |
---- ---- |
---- This file is part of the single_port project ---- |
---- ---- |
---- Description ---- |
---- This package implements functions to allocate, write, read ---- |
---- and deallocate a linked list based memory. ---- |
---- ---- |
---- Authors: ---- |
---- - Robert Paley, rpaley_yid@yahoo.com ---- |
---- - Michael Geng, vhdl@MichaelGeng.de ---- |
---- ---- |
---- References: ---- |
---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- |
---- ISBN: 1-55860-270-4 (pbk.) ---- |
---- 2. Writing Testbenches - Functional Verification of HDL ---- |
---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
-- |
-- |
-- References: |
-- 1. The Designer's Guide to VHDL by Peter Ashenden |
-- ISBN: 1-55860-270-4 (pbk.) |
-- 2. Writing Testbenches - Functional Verification of HDL models by |
-- Janick Bergeron | ISBN: 0-7923-7766-4 |
-- CVS Revision History |
-- |
-- Notes: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1.1.1 2003/01/14 21:48:10 rpaley_yid |
-- initial checkin |
-- |
-- -------------------------------------------------------------------------- |
|
-- Revision 1.1 2003/01/14 17:47:32 Default |
-- Initial revision |
-- |
-- Revision 1.1 2002/12/24 18:03:50 Default |
-- Initial revision |
-- |
LIBRARY IEEE; |
LIBRARY WORK; |
USE IEEE.STD_LOGIC_1164.ALL; |
27,31 → 63,30
USE WORK.single_port_pkg.all; |
|
PACKAGE linked_list_mem_pkg IS |
-- pointer to one data word in the memory |
-- The reason for using a pointer here is that it seems to be the only way to keep the model |
-- independent of the data width |
TYPE data_ptr IS ACCESS BIT_VECTOR; |
-- data memory array type definition |
TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_typ; |
TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_ptr; |
-- Define memory page linked list cell. This cell contains, |
-- the mem_array, starting page address, valid data array, and |
-- the pointer to the next element in the linked list. |
TYPE mem_page_typ; |
-- pointer to next item in the linked list. |
TYPE mem_page_ptr IS ACCESS mem_page_typ; |
TYPE mem_page_ptr IS ACCESS mem_page_typ; |
TYPE mem_page_typ IS RECORD |
mem_array : mem_array_typ; -- data memory |
-- This array is a flag which indicates if the corresponding |
-- address location inside mem_array contains valid data. |
data_valid_array : BIT_VECTOR( 0 TO PAGEDEPTH-1); |
mem_array : mem_array_typ; -- data memory |
page_address : addr_typ; |
next_cell : mem_page_ptr; |
next_cell : mem_page_ptr; |
END RECORD mem_page_typ; |
PROCEDURE rw_mem ( |
VARIABLE data : INOUT data_inter_typ; |
VARIABLE addr : addr_typ; |
VARIABLE write_flag : BOOLEAN; |
VARIABLE next_cell : INOUT mem_page_ptr |
); |
VARIABLE data : INOUT STD_LOGIC_VECTOR; |
VARIABLE addr : IN addr_typ; |
VARIABLE next_cell : INOUT mem_page_ptr; |
CONSTANT write_flag : IN BOOLEAN); |
PROCEDURE deallocate_mem ( |
VARIABLE next_cell : INOUT mem_page_ptr |
); |
VARIABLE next_cell : INOUT mem_page_ptr); |
|
END PACKAGE linked_list_mem_pkg; |
|
61,16 → 96,14
-- the linked list, if the particular page does not exist, create it. |
-- -------------------------------------------------- |
PROCEDURE rw_mem ( |
VARIABLE data : INOUT data_inter_typ; |
VARIABLE addr : addr_typ; |
VARIABLE write_flag : BOOLEAN; |
VARIABLE next_cell : INOUT mem_page_ptr |
) IS |
VARIABLE current_cell_v : mem_page_ptr; -- current page pointer |
VARIABLE page_address_v : addr_typ; -- calculated page address |
VARIABLE index_v : INTEGER; -- address within the memory page |
VARIABLE mem_array_v : mem_array_typ; |
VARIABLE data_valid_array_v : BIT_VECTOR(0 TO PAGEDEPTH-1); |
VARIABLE data : INOUT STD_LOGIC_VECTOR; |
VARIABLE addr : IN addr_typ; |
VARIABLE next_cell : INOUT mem_page_ptr; |
CONSTANT write_flag : IN BOOLEAN) IS |
VARIABLE current_cell_v : mem_page_ptr; -- current page pointer |
VARIABLE page_address_v : addr_typ; -- calculated page address |
VARIABLE index_v : INTEGER; -- address within the memory page |
VARIABLE mem_array_v : mem_array_typ; |
BEGIN |
-- Copy the top of the linked list pointer to a working pointer |
current_cell_v := next_cell; |
81,67 → 114,57
-- Search through the memory to determine if the calculated |
-- memory page exists. Stop searching when reach the end of |
-- the linked list. |
WHILE ( current_cell_v /= NULL |
AND current_cell_v.page_address /= page_address_v) LOOP |
WHILE ( current_cell_v /= NULL AND |
current_cell_v.page_address /= page_address_v) LOOP |
current_cell_v := current_cell_v.next_cell; |
END LOOP; |
|
IF write_flag THEN |
IF ( current_cell_v /= NULL AND -- Check if address exists in memory. |
current_cell_v.page_address = page_address_v |
) THEN |
current_cell_v.page_address = page_address_v ) THEN |
-- Found the memory page the particular address belongs to |
current_cell_v.mem_array(index_v) := TO_BITVECTOR(data); |
-- set memory location valid flag |
current_cell_v.data_valid_array(index_v) := '1'; |
IF ( current_cell_v.mem_array(index_v) /= NULL ) THEN |
current_cell_v.mem_array(index_v).ALL := TO_BITVECTOR(data); |
ELSE |
current_cell_v.mem_array(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data)); |
END IF; |
ELSE |
-- The memory page the address belongs to was not allocated in memory. |
-- Allocate page here and assign data. |
mem_array_v(index_v) := TO_BITVECTOR(data); |
data_valid_array_v(index_v) := '1'; |
next_cell := NEW mem_page_typ'( mem_array => mem_array_v, |
data_valid_array => data_valid_array_v, |
mem_array_v(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data)); |
next_cell := NEW mem_page_typ'( mem_array => mem_array_v, |
page_address => page_address_v, |
next_cell => next_cell |
); |
next_cell => next_cell); |
END IF; |
ELSE -- Read memory |
IF ( current_cell_v /= NULL AND -- Check if address exists in memory. |
current_cell_v.page_address = page_address_v AND |
current_cell_v.data_valid_array(index_v) = '1' |
) THEN |
current_cell_v.mem_array(index_v) /= NULL ) THEN |
-- Found the memory page the particular address belongs to, |
-- and the memory location has valid data. |
data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v)); |
data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v).ALL); |
ELSE |
-- Trying to read from unwritten or unallocated |
-- memory location, return 'U'; |
data := (OTHERS => 'U'); |
data := (data'RANGE => 'U'); |
END IF; |
END IF; |
END PROCEDURE rw_mem; |
|
PROCEDURE deallocate_mem ( |
VARIABLE next_cell : INOUT mem_page_ptr |
) IS |
VARIABLE next_cell : INOUT mem_page_ptr) IS |
VARIABLE delete_cell_v : mem_page_ptr; |
BEGIN |
-- Deallocate the linked link memory from work station memory. |
WHILE next_cell /= NULL LOOP -- while not reached the end of the LL |
delete_cell_v := next_cell; -- Copy pointer to record for deleting |
FOR i IN 0 TO PAGEDEPTH-1 LOOP |
IF delete_cell_v.mem_array(i) /= NULL THEN |
deallocate(delete_cell_v.mem_array(i)); |
END IF; |
END LOOP; |
next_cell := next_cell.next_cell; -- set pointer to next cell in LL |
deallocate(delete_cell_v); -- Deallocate current cell from memory. |
END LOOP; |
END PROCEDURE deallocate_mem; |
END PACKAGE BODY LINKED_LIST_MEM_PKG; |
|
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1 2003/01/14 17:47:32 Default |
-- Initial revision |
-- |
-- Revision 1.1 2002/12/24 18:03:50 Default |
-- Initial revision |
-- |
|
|
|
/trunk/VHDL/single_port.vhd
1,33 → 1,71
-- $Author: rpaley_yid $ |
-- $Date: 2003-01-14 21:48:11 $ |
-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ |
-- $Locker |
-- $Revision: 1.1.1.1 $ |
-- $State: Exp $ |
|
-- -------------------------------------------------------------------------- |
-- |
-- Purpose: This is a single port asynchronous memory. This files |
-- describes three architectures. Two architectures are traditional |
-- array based memories. One describes the memory as an array of |
-- STD_LOGIC_VECTOR, and the other describes the ARRAY as BIT_VECTOR. |
-- The third architecture describes the memory arranged as a linked |
-- list in order to conserve computer memory usage. The memory |
-- is organized as a linked list of BIT_VECTOR arrays whose size |
-- is defined PAGEDEPTH in single_port_pkg.vhd. |
---------------------------------------------------------------------- |
---- ---- |
---- Single port asynchronous RAM simulation model ---- |
---- ---- |
---- This file is part of the single_port project ---- |
---- ---- |
---- Description ---- |
---- This is a single port asynchronous memory. This files ---- |
---- describes three architectures. Two architectures are ---- |
---- traditional array based memories. One describes the memory ---- |
---- as an array of STD_LOGIC_VECTOR, and the other describes ---- |
---- the ARRAY as BIT_VECTOR. ---- |
---- The third architecture describes the memory arranged as a ---- |
---- linked list in order to conserve computer memory usage. The ---- |
---- memory is organized as a linked list of BIT_VECTOR arrays ---- |
---- whose size is defined by the constant PAGEDEPTH in ---- |
---- single_port_pkg.vhd. ---- |
---- ---- |
---- Authors: ---- |
---- - Robert Paley, rpaley_yid@yahoo.com ---- |
---- - Michael Geng, vhdl@MichaelGeng.de ---- |
---- ---- |
---- References: ---- |
---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- |
---- ISBN: 1-55860-270-4 (pbk.) ---- |
---- 2. Writing Testbenches - Functional Verification of HDL ---- |
---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
-- |
-- |
-- References: |
-- 1. The Designer's Guide to VHDL by Peter Ashenden |
-- ISBN: 1-55860-270-4 (pbk.) |
-- 2. Writing Testbenches - Functional Verification of HDL models by |
-- Janick Bergeron | ISBN: 0-7923-7766-4 |
-- CVS Revision History |
-- |
-- Notes: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid |
-- initial checkin |
-- |
-- -------------------------------------------------------------------------- |
-- Revision 1.1 2003/01/14 17:48:31 Default |
-- Initial revision |
-- |
-- Revision 1.1 2002/12/24 18:09:05 Default |
-- Initial revision |
-- |
LIBRARY IEEE; |
LIBRARY WORK; |
USE IEEE.STD_LOGIC_1164.ALL; |
USE IEEE.NUMERIC_STD.ALL; |
USE WORK.single_port_pkg.ALL; |
35,25 → 73,22
|
ENTITY single_port IS |
GENERIC ( |
rnwtQ : TIME := 1 NS |
); |
rnwtQ : TIME := 1 NS); |
PORT ( |
d : IN data_inter_typ; |
q : OUT data_inter_typ; |
a : IN addr_inter_typ; |
rnw : IN STD_LOGIC; |
dealloc_mem : IN BOOLEAN |
); |
d : IN STD_LOGIC_VECTOR; |
q : OUT STD_LOGIC_VECTOR; |
a : IN STD_LOGIC_VECTOR; |
rnw : IN STD_LOGIC; |
dealloc_mem : IN BOOLEAN := FALSE); |
END ENTITY single_port; |
|
ARCHITECTURE ArrayMemNoFlag OF single_port IS |
BEGIN |
|
mem_proc : PROCESS |
TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1) OF data_inter_typ; |
mem_proc : PROCESS(d, a, rnw) |
TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF STD_LOGIC_VECTOR(d'RANGE); |
VARIABLE mem : mem_typ; |
BEGIN |
WAIT on rnw'transaction; |
IF ( rnw = '0') THEN -- Write |
mem(TO_INTEGER(unsigned(a))) := d; |
ELSE -- Read |
66,13 → 101,12
ARCHITECTURE ArrayMem OF single_port IS |
BEGIN |
|
mem_proc : PROCESS |
TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF data_typ; |
mem_proc : PROCESS(d, a, rnw) |
TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BIT_VECTOR(d'RANGE); |
TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN; |
VARIABLE mem : mem_typ; |
VARIABLE mem : mem_typ; |
VARIABLE flag : flag_typ; |
BEGIN |
WAIT ON rnw'transaction; |
IF ( rnw = '0') THEN -- Write |
mem(TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d); |
flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag |
80,7 → 114,7
IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN |
q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ; |
ELSE -- reading invalid memory location |
q <= (OTHERS => 'U') after rnwtQ; |
q <= (q'RANGE => 'U') after rnwtQ; |
END IF; |
END IF; |
END PROCESS mem_proc; |
87,31 → 121,28
END ArrayMem; |
|
ARCHITECTURE LinkedList OF single_port IS |
BEGIN |
CONSTANT WRITE_MEM : BOOLEAN := true; |
CONSTANT READ_MEM : BOOLEAN := false; |
BEGIN |
|
mem_proc : PROCESS |
VARIABLE mem_page_v : mem_page_ptr; |
VARIABLE d_v : data_inter_typ; |
VARIABLE a_v : addr_typ; |
VARIABLE WRITE_MEM_v : BOOLEAN := true; |
VARIABLE READ_MEM_v : BOOLEAN := false; |
mem_proc : PROCESS(d, a, rnw, dealloc_mem) |
VARIABLE mem_page_v : mem_page_ptr; |
VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE); |
VARIABLE a_v : addr_typ; |
BEGIN |
WAIT ON dealloc_mem'transaction , rnw'TRANSACTION; |
IF NOT dealloc_mem THEN |
d_v := d; |
a_v := TO_INTEGER(unsigned(a)); |
IF ( rnw = '0' ) THEN -- write to linked list memory |
rw_mem( data => d_v, |
addr => a_v, |
write_flag => WRITE_MEM_v, |
next_cell => mem_page_v |
); |
rw_mem( data => d_v, |
addr => a_v, |
next_cell => mem_page_v, |
write_flag => WRITE_MEM); |
ELSE -- read from linked list memory |
rw_mem( data => d_v, |
addr => a_v, |
write_flag => READ_MEM_v, |
next_cell => mem_page_v |
); |
rw_mem( data => d_v, |
addr => a_v, |
next_cell => mem_page_v, |
write_flag => READ_MEM); |
q <= d_v after rnwtQ; |
END IF; |
ELSE -- Deallocate memory from work station memory. |
120,12 → 151,3
END PROCESS mem_proc; |
|
END LinkedList; |
|
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1 2003/01/14 17:48:31 Default |
-- Initial revision |
-- |
-- Revision 1.1 2002/12/24 18:09:05 Default |
-- Initial revision |
-- |
|
/trunk/VHDL/single_port_pkg.vhd
1,64 → 1,55
-- $Author: rpaley_yid $ |
-- $Date: 2003-01-14 21:48:11 $ |
-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ |
-- $Locker: $ |
-- $Revision: 1.1.1.1 $ |
-- $State: Exp $ |
|
-- -------------------------------------------------------------------------- |
-- |
-- Purpose: Package file for single_port memory and testbench |
-- |
-- References: |
-- 1. The Designer's Guide to VHDL by Peter Ashenden |
-- ISBN: 1-55860-270-4 (pbk.) |
-- 2. Writing Testbenches - Functional Verification of HDL models by |
-- Janick Bergeron | ISBN: 0-7923-7766-4 |
---------------------------------------------------------------------- |
---- ---- |
---- Single port asynchronous RAM simulation model ---- |
---- ---- |
---- This file is part of the single_port project ---- |
---- ---- |
---- Description ---- |
---- Package file for single_port memory and testbench ---- |
---- ---- |
---- Authors: ---- |
---- - Robert Paley, rpaley_yid@yahoo.com ---- |
---- - Michael Geng, vhdl@MichaelGeng.de ---- |
---- ---- |
---- References: ---- |
---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- |
---- ISBN: 1-55860-270-4 (pbk.) ---- |
---- 2. Writing Testbenches - Functional Verification of HDL ---- |
---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
-- |
-- Notes: |
-- CVS Revision History |
-- |
-- -------------------------------------------------------------------------- |
|
LIBRARY IEEE; |
USE IEEE.STD_LOGIC_1164.ALL; |
USE IEEE.NUMERIC_STD.ALL; |
|
PACKAGE single_port_pkg IS |
CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth |
CONSTANT PAGENUM : INTEGER := 4096; -- number of pages in memory. |
CONSTANT DATA_WIDTH : INTEGER := 32; -- memory data bus width |
CONSTANT ADDRESS_WIDTH : INTEGER := 16; -- memory address bus width |
-- Data bus type for memory interface |
SUBTYPE data_inter_typ IS STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); |
-- Data bus type for internal memory |
SUBTYPE data_typ IS BIT_VECTOR(DATA_WIDTH-1 DOWNTO 0); |
-- Address bus type for memory interface |
SUBTYPE addr_inter_typ IS STD_LOGIC_VECTOR(ADDRESS_WIDTH-1 DOWNTO 0); |
-- Address bus type for internal memory |
SUBTYPE addr_typ IS NATURAL; |
-- Operations testbench can do. |
TYPE do_typ IS ( init , read , write , dealloc , end_test ); |
|
TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench |
do : do_typ; |
addr : addr_inter_typ; |
data : data_inter_typ; |
event : BOOLEAN; |
END RECORD to_srv_typ; |
|
TYPE frm_srv_typ IS RECORD -- Record passed from test bench to test case |
data : data_inter_typ; |
event : BOOLEAN; |
END RECORD frm_srv_typ; |
|
|
END PACKAGE single_port_pkg; |
|
PACKAGE BODY single_port_pkg IS |
|
END PACKAGE BODY single_port_pkg; |
|
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid |
-- initial checkin |
-- |
-- Revision 1.1 2003/01/14 17:48:44 Default |
-- Initial revision |
-- |
65,6 → 56,25
-- Revision 1.1 2002/12/24 17:58:49 Default |
-- Initial revision |
-- |
LIBRARY IEEE; |
USE IEEE.STD_LOGIC_1164.ALL; |
USE IEEE.NUMERIC_STD.ALL; |
|
PACKAGE single_port_pkg IS |
CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth |
CONSTANT PAGENUM : INTEGER := 4096; -- number of pages in memory. |
-- Address bus type for internal memory |
SUBTYPE addr_typ IS NATURAL; |
-- Operations testbench can do. |
TYPE do_typ IS ( init , read , write , dealloc , end_test ); |
|
TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench |
do : do_typ; |
addr : INTEGER; |
data : INTEGER; |
event : BOOLEAN; |
END RECORD to_srv_typ; |
END PACKAGE single_port_pkg; |
|
PACKAGE BODY single_port_pkg IS |
END PACKAGE BODY single_port_pkg; |
/trunk/VHDL/tb_single_port.vhd
1,28 → 1,67
-- $Author: rpaley_yid $ |
-- $Date: 2003-01-14 21:48:11 $ |
-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tb_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ |
-- $Locker |
-- $Revision: 1.1.1.1 $ |
-- $State: Exp $ |
|
-- -------------------------------------------------------------------------- |
-- |
-- Purpose: This file specifies test bench harness for the single_port |
-- Memory. It also contains the configuration files for all the |
-- tests. |
---------------------------------------------------------------------- |
---- ---- |
---- Single port asynchronous RAM simulation model ---- |
---- ---- |
---- This file is part of the single_port project ---- |
---- ---- |
---- Description ---- |
---- This file specifies test bench harness for the single_port ---- |
---- Memory. It also contains the configuration files for all the ---- |
---- tests. ---- |
---- ---- |
---- Authors: ---- |
---- - Robert Paley, rpaley_yid@yahoo.com ---- |
---- - Michael Geng, vhdl@MichaelGeng.de ---- |
---- ---- |
---- References: ---- |
---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- |
---- ISBN: 1-55860-270-4 (pbk.) ---- |
---- 2. Writing Testbenches - Functional Verification of HDL ---- |
---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
-- |
-- |
-- References: |
-- 1. The Designer's Guide to VHDL by Peter Ashenden |
-- ISBN: 1-55860-270-4 (pbk.) |
-- 2. Writing Testbenches - Functional Verification of HDL models by |
-- Janick Bergeron | ISBN: 0-7923-7766-4 |
-- CVS Revision History |
-- |
-- Notes: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid |
-- initial checkin |
-- |
-- -------------------------------------------------------------------------- |
-- Revision 1.1 2003/01/14 17:49:04 Default |
-- Initial revision |
-- |
-- Revision 1.2 2002/12/31 19:19:43 Default |
-- Updated 'transaction statements for fixed simulator. |
-- |
-- Revision 1.1 2002/12/24 18:10:18 Default |
-- Initial revision |
-- |
LIBRARY IEEE; |
LIBRARY WORK; |
USE IEEE.STD_LOGIC_1164.ALL; |
USE IEEE.NUMERIC_STD.ALL; |
USE WORK.linked_list_mem_pkg.ALL; |
36,50 → 75,47
|
COMPONENT single_port IS |
GENERIC ( |
rnwtQ : TIME := 1 NS |
); |
rnwtQ : TIME := 1 NS); |
PORT ( |
d : IN data_inter_typ; |
q : OUT data_inter_typ; |
a : IN addr_inter_typ; |
rnw : IN STD_LOGIC; |
dealloc_mem : BOOLEAN |
); |
d : IN STD_LOGIC_VECTOR; |
q : OUT STD_LOGIC_VECTOR; |
a : IN STD_LOGIC_VECTOR; |
rnw : IN STD_LOGIC; |
dealloc_mem : BOOLEAN); |
END COMPONENT single_port; |
|
COMPONENT tc_single_port IS |
PORT ( |
to_srv : OUT to_srv_typ; |
frm_srv : IN frm_srv_typ |
); |
to_srv : OUT to_srv_typ; |
frm_srv : IN STD_LOGIC_VECTOR); |
END COMPONENT tc_single_port; |
CONSTANT DATA_WIDTH : INTEGER := 32; |
CONSTANT ADDR_WIDTH : INTEGER := 16; |
|
SIGNAL d : data_inter_typ; |
SIGNAL q : data_inter_typ; |
SIGNAL a : addr_inter_typ; |
SIGNAL rnw : STD_LOGIC; |
SIGNAL dealloc_mem : BOOLEAN; |
SIGNAL to_srv : to_srv_typ; |
SIGNAL frm_srv : frm_srv_typ; |
SIGNAL tie_vdd : STD_LOGIC := '1'; |
SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); |
SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); |
SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); |
SIGNAL rnw : STD_LOGIC; |
SIGNAL dealloc_mem : BOOLEAN; |
SIGNAL to_srv : to_srv_typ; |
SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE); |
SIGNAL tie_vdd : STD_LOGIC := '1'; |
BEGIN |
dut : single_port |
PORT MAP ( |
d => d, |
a => a, |
q => q, |
rnw => rnw, |
dealloc_mem => dealloc_mem |
); |
d => d, |
a => a, |
q => q, |
rnw => rnw, |
dealloc_mem => dealloc_mem); |
|
tc : tc_single_port |
PORT MAP ( |
to_srv => to_srv, |
frm_srv => frm_srv |
); |
to_srv => to_srv, |
frm_srv => frm_srv); |
|
single_port_server : PROCESS |
VARIABLE frm_srv_v : frm_srv_typ; |
VARIABLE frm_srv_v : STD_LOGIC_VECTOR(d'RANGE); |
CONSTANT ACCESS_DELAY : TIME := 5 NS; |
BEGIN |
-- Wait until the test case is finished setting up the next memory access. |
90,14 → 126,14
REPORT "initialized" |
SEVERITY NOTE; |
WHEN read => -- perform memory read |
d <= to_srv.data; |
a <= to_srv.addr; |
d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length)); |
a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length)); |
rnw <= '1'; |
-- Wait for data to appear |
WAIT FOR ACCESS_DELAY; |
WHEN write => -- perform memory write |
d <= to_srv.data; |
a <= to_srv.addr; |
d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length)); |
a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length)); |
rnw <= '0'; |
WAIT FOR ACCESS_DELAY; |
WHEN dealloc => -- deallocate the linked list for the LL architecture |
105,7 → 141,7
WHEN end_test => -- reached the end of the test case |
WAIT; |
END CASE; |
frm_srv_v.data := q; |
frm_srv_v := q; |
-- Send message to test case to continue the test. |
frm_srv <= frm_srv_v ; WAIT FOR 0 NS; |
END PROCESS single_port_server; |
176,16 → 212,3
END FOR; -- tc; |
END FOR; -- BHV |
END CONFIGURATION memnoflag_error_cfg; |
|
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1 2003/01/14 17:49:04 Default |
-- Initial revision |
-- |
-- Revision 1.2 2002/12/31 19:19:43 Default |
-- Updated 'transaction statements for fixed simulator. |
-- |
-- Revision 1.1 2002/12/24 18:10:18 Default |
-- Initial revision |
-- |
|
|
/trunk/VHDL/tc_single_port.vhd
1,27 → 1,65
-- $Author: rpaley_yid $ |
-- $Date: 2003-01-14 21:48:11 $ |
-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tc_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ |
-- $Locker |
-- $Revision: 1.1.1.1 $ |
-- $State: Exp $ |
|
-- -------------------------------------------------------------------------- |
-- |
-- Purpose: This file specifies test cases for the single_port |
-- Memory. |
---------------------------------------------------------------------- |
---- ---- |
---- Single port asynchronous RAM simulation model ---- |
---- ---- |
---- This file is part of the single_port project ---- |
---- ---- |
---- Description ---- |
---- This file specifies test cases for the single_port Memory. ---- |
---- ---- |
---- Authors: ---- |
---- - Robert Paley, rpaley_yid@yahoo.com ---- |
---- - Michael Geng, vhdl@MichaelGeng.de ---- |
---- ---- |
---- References: ---- |
---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- |
---- ISBN: 1-55860-270-4 (pbk.) ---- |
---- 2. Writing Testbenches - Functional Verification of HDL ---- |
---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
-- |
-- |
-- References: |
-- 1. The Designer's Guide to VHDL by Peter Ashenden |
-- ISBN: 1-55860-270-4 (pbk.) |
-- 2. Writing Testbenches - Functional Verification of HDL models by |
-- Janick Bergeron | ISBN: 0-7923-7766-4 |
-- CVS Revision History |
-- |
-- Notes: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid |
-- initial checkin |
-- |
-- -------------------------------------------------------------------------- |
-- Revision 1.1 2003/01/14 17:49:04 Default |
-- Initial revision |
-- |
-- Revision 1.2 2002/12/31 19:19:43 Default |
-- Updated 'transaction statements for fixed simulator. |
-- |
-- Revision 1.1 2002/12/24 18:13:50 Default |
-- Initial revision |
-- |
LIBRARY IEEE; |
LIBRARY WORK; |
USE IEEE.STD_LOGIC_1164.ALL; |
USE IEEE.NUMERIC_STD.ALL; |
USE WORK.SINGLE_PORT_PKG.ALL; |
29,9 → 67,8
|
ENTITY tc_single_port IS |
PORT ( |
to_srv : OUT to_srv_typ; |
frm_srv : IN frm_srv_typ |
); |
to_srv : OUT to_srv_typ; |
frm_srv : IN STD_LOGIC_VECTOR); |
END ENTITY tc_single_port; |
|
-- -------------------------------------------------- |
55,51 → 92,49
ARCHITECTURE TC0 OF tc_single_port IS |
BEGIN |
MAIN : PROCESS |
VARIABLE to_srv_v : to_srv_typ; |
VARIABLE frm_srv_v : frm_srv_typ; |
VARIABLE dv : data_inter_typ := |
STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length)); |
VARIABLE offset_v : INTEGER; |
VARIABLE to_srv_v : to_srv_typ; |
VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE); |
VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) := |
STD_LOGIC_VECTOR(TO_UNSIGNED(1, frm_srv'length)); |
VARIABLE offset_v : INTEGER; |
BEGIN |
offset_v := 0; |
-- Run this write/read test 10 times for benchmark |
-- purposes. |
for i in 0 to 9 loop |
for index in 0 to 2*PAGEDEPTH-1 loop |
-- Specify to testbench server to perform write operation; |
to_srv_v.do := write; |
to_srv_v.data := dv; -- specify data to write |
dv := To_StdLogicVector(TO_BitVector(dv) rol 1); -- ROL 1 for next write |
-- Specify physical address. |
to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v, |
ADDRESS_WIDTH)); |
to_srv <= to_srv_v ; WAIT FOR 0 NS; |
WAIT ON frm_srv'TRANSACTION; |
end loop; |
-- Reset data to 1. |
dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length)); |
for index in 0 to 2*PAGEDEPTH-1 loop |
-- Perform read operation. |
to_srv_v.do := read; |
-- Specify physical address. |
to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v, |
ADDRESS_WIDTH)); |
to_srv <= to_srv_v ; WAIT FOR 0 NS; |
WAIT ON frm_srv'TRANSACTION; |
-- Compare actual with expected read back data, if the |
-- the expected and actual to not compare, print the |
-- expected and actual values. |
ASSERT frm_srv.data = dv |
REPORT "Expected: " & HexImage(frm_srv.data) & |
" did not equal Actual: " & HexImage(dv) |
SEVERITY ERROR; |
-- Set expected data for next read. |
dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) rol 1); |
end loop; |
end loop; |
FOR i IN 0 to 9 LOOP |
FOR index IN 0 to 2*PAGEDEPTH-1 LOOP |
-- Specify to testbench server to perform write operation; |
to_srv_v.do := write; |
to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write |
dv := To_StdLogicVector(TO_BitVector(dv) ROL 1); -- ROL 1 for next write |
-- Specify physical address. |
to_srv_v.addr := index+offset_v; |
to_srv <= to_srv_v; |
WAIT ON frm_srv'TRANSACTION; |
END LOOP; |
-- Reset data to 1. |
dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,frm_srv'length)); |
FOR index IN 0 to 2*PAGEDEPTH-1 LOOP |
-- Perform read operation. |
to_srv_v.do := read; |
-- Specify physical address. |
to_srv_v.addr := index+offset_v; |
to_srv <= to_srv_v; |
WAIT ON frm_srv'TRANSACTION; |
-- Compare actual with expected read back data, if the |
-- the expected and actual to not compare, print the |
-- expected and actual values. |
ASSERT frm_srv = dv |
REPORT "Expected: " & HexImage(frm_srv) & |
" did not equal Actual: " & HexImage(dv) |
SEVERITY ERROR; |
-- Set expected data for next read. |
dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) ROL 1); |
END LOOP; |
END LOOP; |
to_srv_v.do := dealloc; -- Deallocate memory |
-- |
to_srv <= to_srv_v ; WAIT FOR 0 NS; |
to_srv <= to_srv_v; |
-- Tell test bench server process test completed. |
to_srv_v.do := end_test; |
to_srv <= to_srv_v; |
114,27 → 149,26
-- Test Case TC1 |
-- This test case is to check if the test bench will |
-- return 'U' for invalid memory locations for |
-- single_port architectures ArrayMEm and LinkedList |
-- single_port architectures ArrayMem and LinkedList |
-- -------------------------------------------------- |
ARCHITECTURE TC1 OF tc_single_port IS |
BEGIN |
MAIN : PROCESS |
VARIABLE to_srv_v : to_srv_typ; |
VARIABLE frm_srv_v : frm_srv_typ; |
VARIABLE dv : data_inter_typ := (OTHERS => 'U'); |
VARIABLE to_srv_v : to_srv_typ; |
VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE); |
VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) := (OTHERS => 'U'); |
BEGIN |
-- Perform read operation. |
to_srv_v.do := read; |
-- Specify physical address. |
to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, |
ADDRESS_WIDTH)); |
to_srv <= to_srv_v; WAIT FOR 0 NS; |
to_srv_v.addr := 0; |
to_srv <= to_srv_v; |
WAIT ON frm_srv'TRANSACTION; |
-- Compare actual with expected read back data, if the |
-- the expected and actual to not compare, print the |
-- expected and actual values. |
ASSERT frm_srv.data = dv |
REPORT "Expected: " & HexImage(frm_srv.data) & |
ASSERT frm_srv = dv |
REPORT "Expected: " & HexImage(frm_srv) & |
" did not equal Actual: " & HexImage(dv) |
SEVERITY ERROR; |
|
143,36 → 177,34
-- Specify to testbench server to perform write operation; |
to_srv_v.do := write; |
dv := X"a5a5a5a5"; |
to_srv_v.data := dv; -- specify data to write |
to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write |
-- Specify physical address. |
to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, |
ADDRESS_WIDTH)); |
to_srv <= to_srv_v; WAIT FOR 0 NS; |
to_srv_v.addr := 0; |
to_srv <= to_srv_v; |
-- Wait until the test bench server finished with the write. |
-- WAIT UNTIL frm_srv.event = true; |
WAIT ON frm_srv'transaction; |
WAIT ON frm_srv'TRANSACTION; |
|
to_srv_v.do := read; |
-- Specify physical address. |
to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, |
ADDRESS_WIDTH)); |
to_srv <= to_srv_v; WAIT FOR 0 NS; |
WAIT ON frm_srv'transaction; |
to_srv_v.addr := 0; |
to_srv <= to_srv_v; |
WAIT ON frm_srv'TRANSACTION; |
|
-- Compare actual with expected read back data, if the |
-- the expected and actual to not compare, print the |
-- expected and actual values. |
ASSERT frm_srv.data = dv |
REPORT "Expected: " & HexImage(frm_srv.data) & |
ASSERT frm_srv = dv |
REPORT "Expected: " & HexImage(frm_srv) & |
" did not equal Actual: " & HexImage(dv) |
SEVERITY ERROR; |
|
to_srv_v.do := dealloc; -- Deallocate memory |
-- |
to_srv <= to_srv_v; WAIT FOR 0 NS; |
to_srv <= to_srv_v; |
-- Tell test bench server process test completed. |
to_srv_v.do := end_test; |
to_srv <= to_srv_v; WAIT FOR 0 NS; |
to_srv <= to_srv_v; |
|
ASSERT FALSE |
REPORT "Completed Test TC1" |
180,15 → 212,3
WAIT; |
END PROCESS main; |
END TC1; |
|
-- $Log: not supported by cvs2svn $ |
-- Revision 1.1 2003/01/14 17:49:04 Default |
-- Initial revision |
-- |
-- Revision 1.2 2002/12/31 19:19:43 Default |
-- Updated 'transaction statements for fixed simulator. |
-- |
-- Revision 1.1 2002/12/24 18:13:50 Default |
-- Initial revision |
-- |
|