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URL https://opencores.org/ocsvn/systemc_rng/systemc_rng/trunk

Subversion Repositories systemc_rng

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Rev 5 → Rev 6

/trunk/bench/systemc/main.cpp
46,7 → 46,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2004/08/30 17:01:50 jcastillo
// Used indent command
//
// Revision 1.2 2004/08/25 15:32:23 jcastillo
// Corrected to run under MSVC60
//
// Revision 1.1.1.1 2004/08/19 14:27:14 jcastillo
// First import
//
56,39 → 61,41
#include "rng.h"
 
#ifdef __GNUC__
#include "iostream.h"
#include "iostream.h"
#endif
 
 
int sc_main(int argc, char* argv[]){
sc_clock clk("clk",1,SC_US);
rng *rng1;
stimulus *st1;
rng1=new rng("rng");
st1=new stimulus("stimulus");
sc_signal<bool> reset;
sc_signal<bool> loadseed_i;
sc_signal<sc_uint<32> > seed_i;
sc_signal<sc_uint<32> > number_o;
rng1->clk(clk);
rng1->reset(reset);
rng1->loadseed_i(loadseed_i);
rng1->seed_i(seed_i);
rng1->number_o(number_o);
st1->clk(clk);
st1->reset(reset);
st1->loadseed_o(loadseed_i);
st1->seed_o(seed_i);
st1->number_i(number_o);
int
sc_main (int argc, char *argv[])
{
 
sc_start(-1);
sc_clock clk ("clk", 1, SC_US);
 
return 0;
}
rng *rng1;
stimulus *st1;
 
rng1 = new rng ("rng");
st1 = new stimulus ("stimulus");
 
sc_signal < bool > reset;
sc_signal < bool > loadseed_i;
sc_signal < sc_uint < 32 > >seed_i;
sc_signal < sc_uint < 32 > >number_o;
 
rng1->clk (clk);
rng1->reset (reset);
rng1->loadseed_i (loadseed_i);
rng1->seed_i (seed_i);
rng1->number_o (number_o);
 
st1->clk (clk);
st1->reset (reset);
st1->loadseed_o (loadseed_i);
st1->seed_o (seed_i);
st1->number_i (number_o);
 
sc_start (-1);
 
return 0;
 
}
/trunk/bench/systemc/stimulus.cpp
46,24 → 46,33
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 17:01:50 jcastillo
// Used indent command
//
// Revision 1.1.1.1 2004/08/19 14:27:14 jcastillo
// First import
//
 
#include "systemc.h"
#include "stimulus.h"
void stimulus::tb(){
wait(clk->posedge_event());
reset.write(0);
wait(clk->posedge_event());
reset.write(1);
wait(clk->posedge_event());
loadseed_o.write(1);
seed_o.write(0x12678);
wait(clk->posedge_event());
loadseed_o.write(0);
for(;;){
wait(clk->posedge_event());
cout << (unsigned int)number_i.read() << endl;
}
}
 
void
stimulus::tb ()
{
 
wait (clk->posedge_event ());
reset.write (0);
wait (clk->posedge_event ());
reset.write (1);
wait (clk->posedge_event ());
loadseed_o.write (1);
seed_o.write (0x12678);
wait (clk->posedge_event ());
loadseed_o.write (0);
for (;;)
{
wait (clk->posedge_event ());
cout << (unsigned int) number_i.read () << endl;
}
 
}
/trunk/bench/systemc/stimulus.h
46,27 → 46,35
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/30 17:01:50 jcastillo
// Used indent command
//
// Revision 1.1.1.1 2004/08/19 14:27:14 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE(stimulus){
SC_MODULE (stimulus)
{
 
sc_in<bool> clk;
sc_out<bool> reset;
sc_out<bool> loadseed_o;
sc_out<sc_uint<32> > seed_o;
sc_in<sc_uint<32> > number_i;
void tb();
SC_CTOR(stimulus){
cout.unsetf(ios::dec);
cout.setf(ios::hex);
cout.setf(ios::showbase);
SC_THREAD(tb);
}
sc_in < bool > clk;
sc_out < bool > reset;
 
sc_out < bool > loadseed_o;
sc_out < sc_uint < 32 > >seed_o;
sc_in < sc_uint < 32 > >number_i;
 
void tb ();
 
SC_CTOR (stimulus)
{
 
cout.unsetf (ios::dec);
cout.setf (ios::hex);
cout.setf (ios::showbase);
 
SC_THREAD (tb);
 
}
};
/trunk/rtl/systemc/main.cpp
46,6 → 46,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/08/25 15:32:23 jcastillo
// Corrected to run under MSVC60
//
// Revision 1.1.1.1 2004/08/19 14:27:14 jcastillo
// First import
//
55,39 → 58,41
#include "rng.h"
 
#ifdef __GNUC__
#include "iostream.h"
#include "iostream.h"
#endif
 
 
int sc_main(int argc, char* argv[]){
sc_clock clk("clk",1,SC_US);
rng *rng1;
stimulus *st1;
rng1=new rng("rng");
st1=new stimulus("stimulus");
sc_signal<bool> reset;
sc_signal<bool> loadseed_i;
sc_signal<sc_uint<32> > seed_i;
sc_signal<sc_uint<32> > number_o;
rng1->clk(clk);
rng1->reset(reset);
rng1->loadseed_i(loadseed_i);
rng1->seed_i(seed_i);
rng1->number_o(number_o);
st1->clk(clk);
st1->reset(reset);
st1->loadseed_o(loadseed_i);
st1->seed_o(seed_i);
st1->number_i(number_o);
int
sc_main (int argc, char *argv[])
{
 
sc_start(-1);
sc_clock clk ("clk", 1, SC_US);
 
return 0;
}
rng *rng1;
stimulus *st1;
 
rng1 = new rng ("rng");
st1 = new stimulus ("stimulus");
 
sc_signal < bool > reset;
sc_signal < bool > loadseed_i;
sc_signal < sc_uint < 32 > >seed_i;
sc_signal < sc_uint < 32 > >number_o;
 
rng1->clk (clk);
rng1->reset (reset);
rng1->loadseed_i (loadseed_i);
rng1->seed_i (seed_i);
rng1->number_o (number_o);
 
st1->clk (clk);
st1->reset (reset);
st1->loadseed_o (loadseed_i);
st1->seed_o (seed_i);
st1->number_i (number_o);
 
sc_start (-1);
 
return 0;
 
}
/trunk/rtl/systemc/stimulus.cpp
46,24 → 46,30
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/08/19 14:27:14 jcastillo
// First import
//
 
#include "systemc.h"
#include "stimulus.h"
void stimulus::tb(){
wait(clk->posedge_event());
reset.write(0);
wait(clk->posedge_event());
reset.write(1);
wait(clk->posedge_event());
loadseed_o.write(1);
seed_o.write(0x12678);
wait(clk->posedge_event());
loadseed_o.write(0);
for(;;){
wait(clk->posedge_event());
cout << (unsigned int)number_i.read() << endl;
}
}
 
void
stimulus::tb ()
{
 
wait (clk->posedge_event ());
reset.write (0);
wait (clk->posedge_event ());
reset.write (1);
wait (clk->posedge_event ());
loadseed_o.write (1);
seed_o.write (0x12678);
wait (clk->posedge_event ());
loadseed_o.write (0);
for (;;)
{
wait (clk->posedge_event ());
cout << (unsigned int) number_i.read () << endl;
}
 
}
/trunk/rtl/systemc/rng.cpp
46,137 → 46,162
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/08/19 14:27:14 jcastillo
// First import
//
 
#include "rng.h"
 
void rng::combinate(){
if(!reset.read()){
number_o.write(0);
}else{
number_o.write(LFSR_reg.read().range(31,0)^CASR_reg.read().range(31,0));
}
void
rng::combinate ()
{
if (!reset.read ())
{
number_o.write (0);
}
else
{
number_o.write (LFSR_reg.read ().range (31, 0) ^ CASR_reg.read ().
range (31, 0));
}
}
 
void rng::LFSR(){
sc_uint<43> LFSR_var;
bool outbit;
if(!reset.read()){
LFSR_reg.write(1);
}else{
if(loadseed_i.read()){
LFSR_var.range(42,31)=0;
LFSR_var.range(31,0)=seed_i.read();
LFSR_reg.write(LFSR_var);
}else{
LFSR_var=LFSR_reg.read();
outbit=LFSR_var[42];
LFSR_var[42]=LFSR_var[41];
LFSR_var[41]=LFSR_var[40]^outbit;
LFSR_var[40]=LFSR_var[39];
LFSR_var[39]=LFSR_var[38];
LFSR_var[38]=LFSR_var[37];
LFSR_var[37]=LFSR_var[36];
LFSR_var[36]=LFSR_var[35];
LFSR_var[35]=LFSR_var[34];
LFSR_var[34]=LFSR_var[33];
LFSR_var[33]=LFSR_var[32];
LFSR_var[32]=LFSR_var[31];
LFSR_var[31]=LFSR_var[30];
LFSR_var[30]=LFSR_var[29];
LFSR_var[29]=LFSR_var[28];
LFSR_var[28]=LFSR_var[27];
LFSR_var[27]=LFSR_var[26];
LFSR_var[26]=LFSR_var[25];
LFSR_var[25]=LFSR_var[24];
LFSR_var[24]=LFSR_var[23];
LFSR_var[23]=LFSR_var[22];
LFSR_var[22]=LFSR_var[21];
LFSR_var[21]=LFSR_var[20];
LFSR_var[20]=LFSR_var[19]^outbit;
LFSR_var[19]=LFSR_var[18];
LFSR_var[18]=LFSR_var[17];
LFSR_var[17]=LFSR_var[16];
LFSR_var[16]=LFSR_var[15];
LFSR_var[15]=LFSR_var[14];
LFSR_var[14]=LFSR_var[13];
LFSR_var[13]=LFSR_var[12];
LFSR_var[12]=LFSR_var[11];
LFSR_var[11]=LFSR_var[10];
LFSR_var[10]=LFSR_var[9];
LFSR_var[9]=LFSR_var[8];
LFSR_var[8]=LFSR_var[7];
LFSR_var[7]=LFSR_var[6];
LFSR_var[6]=LFSR_var[5];
LFSR_var[5]=LFSR_var[4];
LFSR_var[4]=LFSR_var[3];
LFSR_var[3]=LFSR_var[2];
LFSR_var[2]=LFSR_var[1];
LFSR_var[1]=LFSR_var[0]^outbit;
LFSR_var[0]=LFSR_var[42];
LFSR_reg.write(LFSR_var);
}
}
void
rng::LFSR ()
{
 
sc_uint < 43 > LFSR_var;
bool outbit;
 
if (!reset.read ())
{
LFSR_reg.write (1);
}
else
{
if (loadseed_i.read ())
{
LFSR_var.range (42, 31) = 0;
LFSR_var.range (31, 0) = seed_i.read ();
LFSR_reg.write (LFSR_var);
 
}
else
{
LFSR_var = LFSR_reg.read ();
 
outbit = LFSR_var[42];
LFSR_var[42] = LFSR_var[41];
LFSR_var[41] = LFSR_var[40] ^ outbit;
LFSR_var[40] = LFSR_var[39];
LFSR_var[39] = LFSR_var[38];
LFSR_var[38] = LFSR_var[37];
LFSR_var[37] = LFSR_var[36];
LFSR_var[36] = LFSR_var[35];
LFSR_var[35] = LFSR_var[34];
LFSR_var[34] = LFSR_var[33];
LFSR_var[33] = LFSR_var[32];
LFSR_var[32] = LFSR_var[31];
LFSR_var[31] = LFSR_var[30];
LFSR_var[30] = LFSR_var[29];
LFSR_var[29] = LFSR_var[28];
LFSR_var[28] = LFSR_var[27];
LFSR_var[27] = LFSR_var[26];
LFSR_var[26] = LFSR_var[25];
LFSR_var[25] = LFSR_var[24];
LFSR_var[24] = LFSR_var[23];
LFSR_var[23] = LFSR_var[22];
LFSR_var[22] = LFSR_var[21];
LFSR_var[21] = LFSR_var[20];
LFSR_var[20] = LFSR_var[19] ^ outbit;
LFSR_var[19] = LFSR_var[18];
LFSR_var[18] = LFSR_var[17];
LFSR_var[17] = LFSR_var[16];
LFSR_var[16] = LFSR_var[15];
LFSR_var[15] = LFSR_var[14];
LFSR_var[14] = LFSR_var[13];
LFSR_var[13] = LFSR_var[12];
LFSR_var[12] = LFSR_var[11];
LFSR_var[11] = LFSR_var[10];
LFSR_var[10] = LFSR_var[9];
LFSR_var[9] = LFSR_var[8];
LFSR_var[8] = LFSR_var[7];
LFSR_var[7] = LFSR_var[6];
LFSR_var[6] = LFSR_var[5];
LFSR_var[5] = LFSR_var[4];
LFSR_var[4] = LFSR_var[3];
LFSR_var[3] = LFSR_var[2];
LFSR_var[2] = LFSR_var[1];
LFSR_var[1] = LFSR_var[0] ^ outbit;
LFSR_var[0] = LFSR_var[42];
 
LFSR_reg.write (LFSR_var);
}
}
}
 
void rng::CASR(){
sc_uint<43> CASR_var,CASR_out;
if(!reset.read()){
CASR_reg.write(1);
}else{
if(loadseed_i.read()){
CASR_var.range(36,31)=0;
CASR_var.range(31,0)=seed_i.read();
CASR_reg.write(CASR_var);
}else{
CASR_var=CASR_reg.read();
CASR_out[36]=CASR_var[35]^CASR_var[0] ;
CASR_out[35]=CASR_var[34]^CASR_var[36] ;
CASR_out[34]=CASR_var[33]^CASR_var[35] ;
CASR_out[33]=CASR_var[32]^CASR_var[34] ;
CASR_out[32]=CASR_var[31]^CASR_var[33] ;
CASR_out[31]=CASR_var[30]^CASR_var[32] ;
CASR_out[30]=CASR_var[29]^CASR_var[31] ;
CASR_out[29]=CASR_var[28]^CASR_var[30] ;
CASR_out[28]=CASR_var[27]^CASR_var[29] ;
CASR_out[27]=CASR_var[26]^CASR_var[28] ;
CASR_out[26]=CASR_var[25]^CASR_var[27] ;
CASR_out[25]=CASR_var[24]^CASR_var[26] ;
CASR_out[24]=CASR_var[23]^CASR_var[25] ;
CASR_out[23]=CASR_var[22]^CASR_var[24] ;
CASR_out[22]=CASR_var[21]^CASR_var[23] ;
CASR_out[21]=CASR_var[20]^CASR_var[22] ;
CASR_out[20]=CASR_var[19]^CASR_var[21] ;
CASR_out[19]=CASR_var[18]^CASR_var[20] ;
CASR_out[18]=CASR_var[17]^CASR_var[19] ;
CASR_out[17]=CASR_var[16]^CASR_var[18] ;
CASR_out[16]=CASR_var[15]^CASR_var[17] ;
CASR_out[15]=CASR_var[14]^CASR_var[16] ;
CASR_out[14]=CASR_var[13]^CASR_var[15] ;
CASR_out[13]=CASR_var[12]^CASR_var[14] ;
CASR_out[12]=CASR_var[11]^CASR_var[13] ;
CASR_out[11]=CASR_var[10]^CASR_var[12] ;
CASR_out[10]=CASR_var[9]^CASR_var[11] ;
CASR_out[9]=CASR_var[8]^CASR_var[10] ;
CASR_out[8]=CASR_var[7]^CASR_var[9] ;
CASR_out[7]=CASR_var[6]^CASR_var[8] ;
CASR_out[6]=CASR_var[5]^CASR_var[7] ;
CASR_out[5]=CASR_var[4]^CASR_var[6] ;
CASR_out[4]=CASR_var[3]^CASR_var[5] ;
CASR_out[3]=CASR_var[2]^CASR_var[4] ;
CASR_out[2]=CASR_var[1]^CASR_var[3] ;
CASR_out[1]=CASR_var[0]^CASR_var[2] ;
CASR_out[0]=CASR_var[36]^CASR_var[1] ;
CASR_reg.write(CASR_out);
}
}
void
rng::CASR ()
{
 
sc_uint < 43 > CASR_var, CASR_out;
 
if (!reset.read ())
{
CASR_reg.write (1);
}
else
{
if (loadseed_i.read ())
{
CASR_var.range (36, 31) = 0;
CASR_var.range (31, 0) = seed_i.read ();
CASR_reg.write (CASR_var);
 
}
else
{
CASR_var = CASR_reg.read ();
 
CASR_out[36] = CASR_var[35] ^ CASR_var[0];
CASR_out[35] = CASR_var[34] ^ CASR_var[36];
CASR_out[34] = CASR_var[33] ^ CASR_var[35];
CASR_out[33] = CASR_var[32] ^ CASR_var[34];
CASR_out[32] = CASR_var[31] ^ CASR_var[33];
CASR_out[31] = CASR_var[30] ^ CASR_var[32];
CASR_out[30] = CASR_var[29] ^ CASR_var[31];
CASR_out[29] = CASR_var[28] ^ CASR_var[30];
CASR_out[28] = CASR_var[27] ^ CASR_var[29];
CASR_out[27] = CASR_var[26] ^ CASR_var[28];
CASR_out[26] = CASR_var[25] ^ CASR_var[27];
CASR_out[25] = CASR_var[24] ^ CASR_var[26];
CASR_out[24] = CASR_var[23] ^ CASR_var[25];
CASR_out[23] = CASR_var[22] ^ CASR_var[24];
CASR_out[22] = CASR_var[21] ^ CASR_var[23];
CASR_out[21] = CASR_var[20] ^ CASR_var[22];
CASR_out[20] = CASR_var[19] ^ CASR_var[21];
CASR_out[19] = CASR_var[18] ^ CASR_var[20];
CASR_out[18] = CASR_var[17] ^ CASR_var[19];
CASR_out[17] = CASR_var[16] ^ CASR_var[18];
CASR_out[16] = CASR_var[15] ^ CASR_var[17];
CASR_out[15] = CASR_var[14] ^ CASR_var[16];
CASR_out[14] = CASR_var[13] ^ CASR_var[15];
CASR_out[13] = CASR_var[12] ^ CASR_var[14];
CASR_out[12] = CASR_var[11] ^ CASR_var[13];
CASR_out[11] = CASR_var[10] ^ CASR_var[12];
CASR_out[10] = CASR_var[9] ^ CASR_var[11];
CASR_out[9] = CASR_var[8] ^ CASR_var[10];
CASR_out[8] = CASR_var[7] ^ CASR_var[9];
CASR_out[7] = CASR_var[6] ^ CASR_var[8];
CASR_out[6] = CASR_var[5] ^ CASR_var[7];
CASR_out[5] = CASR_var[4] ^ CASR_var[6];
CASR_out[4] = CASR_var[3] ^ CASR_var[5];
CASR_out[3] = CASR_var[2] ^ CASR_var[4];
CASR_out[2] = CASR_var[1] ^ CASR_var[3];
CASR_out[1] = CASR_var[0] ^ CASR_var[2];
CASR_out[0] = CASR_var[36] ^ CASR_var[1];
 
CASR_reg.write (CASR_out);
}
}
}
/trunk/rtl/systemc/stimulus.h
46,27 → 46,32
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/08/19 14:27:14 jcastillo
// First import
//
 
#include "systemc.h"
 
SC_MODULE(stimulus){
SC_MODULE (stimulus)
{
 
sc_in<bool> clk;
sc_out<bool> reset;
sc_out<bool> loadseed_o;
sc_out<sc_uint<32> > seed_o;
sc_in<sc_uint<32> > number_i;
void tb();
SC_CTOR(stimulus){
cout.unsetf(ios::dec);
cout.setf(ios::hex);
cout.setf(ios::showbase);
SC_THREAD(tb);
}
sc_in < bool > clk;
sc_out < bool > reset;
 
sc_out < bool > loadseed_o;
sc_out < sc_uint < 32 > >seed_o;
sc_in < sc_uint < 32 > >number_i;
 
void tb ();
 
SC_CTOR (stimulus)
{
 
cout.unsetf (ios::dec);
cout.setf (ios::hex);
cout.setf (ios::showbase);
 
SC_THREAD (tb);
 
}
};
/trunk/rtl/systemc/rng.h
46,38 → 46,43
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2004/08/19 14:27:14 jcastillo
// First import
//
#include "systemc.h"
 
SC_MODULE(rng){
SC_MODULE (rng)
{
 
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> loadseed_i;
sc_in<sc_uint<32> > seed_i;
sc_out<sc_uint<32> > number_o;
sc_signal<sc_uint<43> > LFSR_reg;
sc_signal<sc_uint<37> > CASR_reg;
void CASR();
void LFSR();
void combinate();
SC_CTOR(rng){
SC_METHOD(CASR);
sensitive_pos << clk;
sensitive_neg << reset;
SC_METHOD(LFSR);
sensitive_pos << clk;
sensitive_neg << reset;
SC_METHOD(combinate);
sensitive_pos << clk;
sensitive_neg << reset;
}
};
sc_in < bool > clk;
sc_in < bool > reset;
 
sc_in < bool > loadseed_i;
sc_in < sc_uint < 32 > >seed_i;
 
sc_out < sc_uint < 32 > >number_o;
 
sc_signal < sc_uint < 43 > >LFSR_reg;
sc_signal < sc_uint < 37 > >CASR_reg;
 
void CASR ();
void LFSR ();
void combinate ();
 
SC_CTOR (rng)
{
 
SC_METHOD (CASR);
sensitive_pos << clk;
sensitive_neg << reset;
 
SC_METHOD (LFSR);
sensitive_pos << clk;
sensitive_neg << reset;
 
SC_METHOD (combinate);
sensitive_pos << clk;
sensitive_neg << reset;
 
}
};

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