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https://opencores.org/ocsvn/wb_prefetch_spram/wb_prefetch_spram/trunk
Subversion Repositories wb_prefetch_spram
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/trunk/rtl/verilog/wb_prefetch_spram.v
56,7 → 56,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/07/30 05:38:02 lampret |
// Adding empty directories required by HDL coding guidelines |
// |
// |
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`include "timescale.v" |
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142,12 → 145,18
assign ram_addr = (~correct_data | we_i) ? adr_i : predicted_addr; |
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// |
// RAM's current output data is the same as data request by WISHBONE master |
// Assert correct_data if RAM's current output data is the same as data |
// requested by WISHBONE master |
// |
assign correct_data = (adr_i == last_addr); |
assign ack_o = correct_data & valid_cycle; |
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// |
// Acknowledge current WISHBONE transfer if correct data was delivered |
// or if it is write transfer |
// |
assign ack_o = (correct_data | we_i) & valid_cycle; |
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// |
// Address used to address RAM at the last WISHBONE read beat |
// |
always @(posedge clk_i or posedge rst_i) |