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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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  • This comparison shows the changes necessary to convert path 
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    from Rev 50 to Rev 51
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  •

Rev 50 → Rev 51

/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
32,8 → 32,8
class SDCommandToken;
logic startbit;
logic transbit;
logic[5:0] id;
SDCommandArg arg;
rand logic[5:0] id;
rand SDCommandArg arg;
aCrc crc7;
logic endbit;
 
79,6 → 79,13
return crc;
endfunction
 
function automatic bit equals(SDCommandToken rhs);
if(id == rhs.id && arg == rhs.arg) begin
return 1;
end
return 0;
endfunction
 
endclass
 
class SDCommandResponse;
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
11,7 → 11,7
program Test(ISdCmd ICmd);
initial begin
SDCard card = new(ICmd, $root.Testbed.CmdReceived);
SDCommandToken recvCmd;
SDCommandToken recvCmd, sendCmd;
bit done = 0;
 
ICmd.Clk <= 0;
25,6 → 25,8
fork
begin // generator
@ICmd.cb;
sendCmd = new();
sendCmd.randomize();
-> $root.Testbed.ApplyCommand;
end
 
33,8 → 35,8
 
begin // driver for SdCmd
@$root.Testbed.ApplyCommand;
ICmd.CmdId <= 0;
ICmd.Arg <= 'h00000000;
ICmd.CmdId <= sendCmd.id;
ICmd.Arg <= sendCmd.arg;
ICmd.Valid <= 1;
-> $root.Testbed.CardRecv;
end
49,7 → 51,10
begin // checker
@$root.Testbed.CmdReceived;
recvCmd = card.getCmd();
recvCmd.display();
sendCmd.display();
recvCmd.checkFromHost();
assert(recvCmd.equals(sendCmd) == 1);
end
 
join;
/sdhc-sc-core/trunk/src/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
71,22 → 71,23
-- Comb. process
NextStateAndOutput : process (iFromController, ioCmd, SerialCrc, State, Counter)
 
procedure NextStateWhenAllSent (constant length : in natural; constant toState : in aSdCmdState) is
procedure NextStateWhenAllSent (constant nextlength : in natural; constant toState : in aSdCmdState) is
begin
if (Counter < length-1) then
NextCounter <= Counter + 1;
if (Counter > 0) then
NextCounter <= Counter - 1;
else
NextCounter <= to_unsigned(0, NextCounter'length);
NextCounter <= to_unsigned(nextlength, NextCounter'length);
NextState <= toState;
end if;
end procedure NextStateWhenAllSent;
 
procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector; constant toState : in aSdCmdState) is
procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector;
constant toState : in aSdCmdState; constant nextlength : in natural) is
begin
Output.Cmd <= container(to_integer(NextCounter));
Output.Crc.Data <= container(to_integer(NextCounter));
Output.Cmd <= container(to_integer(Counter));
Output.Crc.Data <= container(to_integer(Counter));
Output.Crc.DataIn <= cActivated;
NextStateWhenAllSent(container'length, toState);
NextStateWhenAllSent(nextlength, toState);
end procedure SendBitsAndCalcCrc;
 
begin
114,17 → 115,20
Output.Cmd <= cSdTransBitHost;
Output.Crc.DataIn <= cActivated;
Output.Crc.Data <= cSdTransBitHost;
NextCounter <= to_unsigned(iFromController.Content.id'high,
NextCounter'length);
NextState <= cmdid;
 
when cmdid =>
SendBitsAndCalcCrc(iFromController.Content.id, arg);
SendBitsAndCalcCrc(iFromController.Content.id, arg,
iFromController.Content.arg'high);
 
when arg =>
SendBitsAndCalcCrc(iFromController.Content.arg, crc);
SendBitsAndCalcCrc(iFromController.Content.arg, crc, crc7'high-1);
 
when crc =>
Output.Cmd <= SerialCrc;
NextStateWhenAllSent(crc7'length-1, endbit);
NextStateWhenAllSent(0, endbit);
 
when endbit =>
Output.Cmd <= cSdEndBit;

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