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Rev 505 → Rev 506

/trunk/mp3/bench/verilog/xess_top.v
44,7 → 44,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
//
// Xess board - top bench module
 
`include "timescale.v"
126,7 → 129,7
 
xfpga_top i_xess_fpga(
.clk( clk ),
// .clk2(clk2),
.clk2(clk2),
.rstn( rstn ),
.flash_rstn( flash_rstn ),
/trunk/mp3/bench/verilog/bench_define.v
44,10 → 44,24
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/11/04 18:51:06 lampret
// First import.
//
//
`define RESET_TIME 10
`define INIT_CLK_VALUE 1'b0
`define CLK_PERIOD_DIV2 50
 
`define INIT_CLK2_VALUE 1'b0
 
`ifdef OR1200_CLMODE_1TO2
`define CLK2_PERIOD_DIV2 25
`else
`ifdef OR1200_CLMODE_1TO4
Unsuppported
`else
`define CLK2_PERIOD_DIV2 50
`endif
`endif
 
//`define FLASH_GENERIC
/trunk/mp3/bench/verilog/or1200_monitor.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/11/23 08:50:35 lampret
// Typos.
//
// Revision 1.2 2001/11/10 04:22:55 lampret
// Modified monitor tu support exceptions.
//
61,80 → 64,103
//
//
 
`include "defines.v"
`include "or1200_defines.v"
 
`define RISC_TOP xess_top.i_xess_fpga.risc
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP xess_top.i_xess_fpga.risc
 
// Enable debug_mem task. Only affects simulation.
`define enable_debug_mem
//
// Enable display_arch_state task
//
`define OR1200_DISPLAY_ARCH_STATE
 
// Enable display_arch_state task. Only affects simulation.
`define enable_display_arch_state
 
module or1200_monitor;
 
integer fexe;
reg [23:0] ref;
integer fspr;
 
//
// Initialization
//
initial begin
ref = 0;
fexe = $fopen("executed.log");
$timeformat (-9, 2, " ns", 12);
fspr = $fopen("sprs.log");
end
 
//
// Write state of the OR1200 registers into a file
//
// Limitation: only a small subset of register file RAMs
// are supported
//
task display_arch_state;
reg [5:0] i;
reg [31:0] r;
integer j;
begin
`ifdef enable_display_arch_state
`ifdef OR1200_DISPLAY_ARCH_STATE
ref = ref + 1;
$fwrite(fexe, "\nEXECUTED(): %h: %h", xess_top.i_xess_fpga.risc.cpu.except.wb_pc, xess_top.i_xess_fpga.risc.cpu.id.wb_insn);
$fwrite(fexe, "\nEXECUTED(): %h: %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
for(i = 0; i < 32; i = i + 1) begin
if (i % 4 == 0)
$fdisplay(fexe);
`ifdef XILINX_RAMB4
`ifdef OR1200_XILINX_RAMB4
r = 32'h0000_0000;
for(j = 0; j < 16; j = j + 1) begin
r[j] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_0.mem[i*16+j];
r[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[i*16+j];
end
for(j = 0; j < 16; j = j + 1) begin
r[j+16] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_1.mem[i*16+j];
r[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[i*16+j];
end
$fwrite(fexe, "GPR%d: %h ", i, r);
`else
`ifdef XILINX_RAM32X1D
`ifdef OR1200_XILINX_RAM32X1D
`else
`ifdef ARTISAN_SDP
`ifdef OR1200_ARTISAN_SDP
`else
$fwrite(fexe, "GPR%d: %h ", i, xess_top.i_xess_fpga.risc.cpu.rf.rf_a.mem[i]);
$fwrite(fexe, "GPR%d: %h ", i, `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[i]);
`endif
`endif
`endif
end
$fdisplay(fexe);
r = xess_top.i_xess_fpga.risc.cpu.sprs.sr;
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
$fwrite(fexe, "SR : %h ", r);
r = xess_top.i_xess_fpga.risc.cpu.sprs.epcr;
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
$fwrite(fexe, "EPCR0: %h ", r);
r = xess_top.i_xess_fpga.risc.cpu.sprs.eear;
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
$fwrite(fexe, "EEAR0: %h ", r);
r = xess_top.i_xess_fpga.risc.cpu.sprs.esr;
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
$fdisplay(fexe, "ESR0 : %h", r);
`endif
end
endtask
 
always @(posedge xess_top.i_xess_fpga.risc.cpu.id.clk)
if (!xess_top.i_xess_fpga.risc.cpu.id.wb_freeze) begin
//
// Hooks for:
// - displaying registers
// - end of simulation
// - access to SPRs
//
always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
#2;
if ((xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1500ffff) && (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14000000)
&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1400444f)
&& !(`RISC_TOP.cpu.except.except_flushpipe && xess_top.i_xess_fpga.risc.cpu.except.ex_dslot))
if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[0])
&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
display_arch_state;
if (xess_top.i_xess_fpga.risc.cpu.id.ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)
// caught_sys203;
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)
$finish;
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR) // l.mtspr
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dataout);
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR) // l.mfspr
$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
end
 
endmodule

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