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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
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    from Rev 506 to Rev 507
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  •

Rev 506 → Rev 507

/trunk/mp3/sim/run/run_regression
0,0 → 1,171
#!/bin/csh -f
 
set iter = 1;
set failed = 0;
set all_tests = 0;
# List all test cases
set simpletests=(immu-nocache dmmu-nocache basic-nocache mul-nocache-O2 syscall-nocache cbasic-nocache-O2 ints1-nocache ints2-nocache \
immu-icdc dmmu-icdc basic-icdc mul-icdc-O2 syscall-icdc cbasic-icdc-O2 ints1-icdc ints2-icdc)
set complextests=(immu-ic dmmu-ic basic-ic mul-ic-O2 syscall-ic cbasic-ic-O2 ints1-ic ints2-ic \
immu-dc dmmu-dc basic-dc mul-dc-O2 syscall-dc cbasic-dc-O2 ints1-dc ints2-dc \
mul-nocache-O0 cbasic-nocache-O0 \
mul-icdc-O0 cbasic-icdc-O0 \
mul-ic-O0 cbasic-ic-O0 \
mul-dc-O0 cbasic-dc-O0)
set simpletimes=(10 10 40 40 40 40 40 60 \
10 10 40 40 40 40 40 40)
set complextimes=(10 10 40 40 40 40 40 40 \
10 10 40 40 40 40 40 60 \
40 40 \
40 40 \
40 40 \
40 40)
set iterations=( \
"OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC" \
"OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_REGISTERED_INPUTS" \
"OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS" \
"OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS+OR1200_CLMODE_1TO2" \
"OR1200_REGISTERED_OUTPUTS+OR1200_CLMODE_1TO2" \
"OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \
"OR1200_REGISTERED_OUTPUTS" \
"" \
"OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS+FLASH_GENERIC_REGISTERED" \
"")
 
# Process arguments
if ($1 == "simple") then
set tests=(${simpletests})
set maxtimes=(${simpletimes})
else
set tests=(${simpletests} ${complextests})
set maxtimes=(${simpletimes} ${complextimes})
endif
if ($1 == "single") then
set tests=(${simpletests} ${complextests})
set maxtimes=(${simpletimes} ${complextimes})
set tests=${tests[$2]}
set maxtimes=${maxtimes[$2]}
endif
if ($1 == "clean") then
rm -rf ../log/*
rm -rf ../out/wave/*
exit 0;
else if ($1 == "sim") then
goto sim;
endif
 
# List all selected tests
set i = 0;
foreach test ($tests)
@ i += 1;
echo -n " Test ${i}: ${test}, $maxtimes[$i] ms\t"
if ((${i} % 2) == 0) then
echo ""
endif
end
 
echo ""
 
set i = 1;
while ($iterations[$i] != "")
echo " Iteration ${i}: ${iterations[$i]}\t"
@ i += 1;
end
 
# Prepare all .args files
iteration:
echo ""
echo "<<<"
echo "<<< Iteration ${iter}: ${iterations[$iter]}"
echo "<<<"
if (${iterations[$iter]} != "") then
ncprep +define+${iterations[$iter]} -f ../bin/nc.scr > ncprep.out
else
ncprep -f ../bin/nc.scr > ncprep.out
endif
if (`tail -1 ncprep.out | grep Failed` != "") then
echo ""
cat ncprep.out
exit
endif
 
# Run NC-Verilog compiler
echo ""
echo "\t@@@"
echo "\t@@@ Compiling sources"
echo "\t@@@"
ncvlog -NOCOPYRIGHT -f ncvlog.args > ncvlog.out
if ($status != 0) then
echo "\t@@@ FAILED"
echo ""
cat ncvlog.out
exit
else
echo "\t@@@ Passed"
endif
 
# Run the NC-Verilog elaborator (build the design hierarchy)
echo ""
echo "\t@@@"
echo "\t@@@ Building design hierarchy (elaboration)"
echo "\t@@@"
ncelab -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ncelab.out
if ($status != 0) then
echo "\t@@@ FAILED"
echo ""
cat ncelab.out
exit
else
echo "\t@@@ Passed"
endif
 
# Run the NC-Verilog simulator (simulate the design)
sim:
set i = 0;
foreach test ($tests)
@ i += 1;
echo ""
echo "\t###"
echo "\t### Running test ${i}: ${test}, $maxtimes[$i] ms"
echo "\t###"
 
echo "database -open waves -into ../out/wave/i${iter}-${test} -default" > sim.tcl
echo "probe -create -shm xess_top -all -variables -depth all" >> sim.tcl
echo "stop -create -time $maxtimes[$i]ms -relative" >> sim.tcl
echo "run" >> sim.tcl
echo "quit" >> sim.tcl
 
cp ../src/${test}.mem ../src/flash.in
ncsim -NOCOPYRIGHT -f ncsim.args > ncsim.out
if ($status != 0) then
cat ncsim.out
exit
else
set magic=`tail -1 sprs.log | cut -d'-' -f2 | cut -c2-9`
set magictime=`tail -1 sprs.log | cut -d'n' -f1`
if ($magic == "deaddead") then
echo "\t### Passed (@time $magictime)"
@ all_tests += 1;
else
echo "\t### FAILED (@time $magictime, magic# 0x$magic)"
@ failed += 1;
@ all_tests += 1;
endif
mv flash.log ../log/i${iter}-${test}-flash.log
mv executed.log ../log/i${iter}-${test}-executed.log
mv sram.log ../log/i${iter}-${test}-sram.log
mv sprs.log ../log/i${iter}-${test}-sprs.log
endif
end
 
@ iter += 1;
if ($iterations[$iter] != "") then
goto iteration
else
echo ""
echo "<<<"
echo "<<< End of Regression Iterations"
echo "<<<"
echo "<<< Failed $failed out of $all_tests"
echo "<<<"
endif
trunk/mp3/sim/run/run_regression Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/mp3/sim/run/run_sim =================================================================== --- trunk/mp3/sim/run/run_sim (revision 506) +++ trunk/mp3/sim/run/run_sim (revision 507) @@ -1,8 +1,9 @@ #!/bin/csh -f -ncprep -f ../bin/nc.scr +#ncprep -f ../bin/nc.scr #debussy -f ../bin/nc.scr -#nLint -f ../bin/nc.scr +nLint -f ../bin/nc.scr +exit; #verilog -f ../bin/nc.scr # mv ncverilog.log ../log/ncverilog.log @@ -12,7 +13,7 @@ endif # Run the NC-Verilog elaborator (build the design hierarchy) -ncelab -f ncelab.args +ncelab -NOTIMINGCHECKS -f ncelab.args if ($status != 0) then exit endif
/trunk/mp3/sim/bin/nc.scr
2,7 → 2,7
+access+wr
+overwrite
+mess
+tcl+../bin/sim.tcl
+tcl+sim.tcl
+max_err_count+2
 
//
76,48 → 76,53
// RTL files (or1200)
//
+incdir+../../rtl/verilog/or1200
../../rtl/verilog/or1200/wb_biu.v
../../rtl/verilog/or1200/id.v
../../rtl/verilog/or1200/cpu.v
../../rtl/verilog/or1200/rf.v
../../rtl/verilog/or1200/alu.v
../../rtl/verilog/or1200/lsu.v
../../rtl/verilog/or1200/operandmuxes.v
../../rtl/verilog/or1200/wbmux.v
../../rtl/verilog/or1200/ifetch.v
../../rtl/verilog/or1200/frz_logic.v
../../rtl/verilog/or1200/sprs.v
../../rtl/verilog/or1200/or1200.v
../../rtl/verilog/or1200/pic.v
../../rtl/verilog/or1200/pm.v
../../rtl/verilog/or1200/tt.v
../../rtl/verilog/or1200/except.v
../../rtl/verilog/or1200/dc.v
../../rtl/verilog/or1200/dc_fsm.v
../../rtl/verilog/or1200/reg2mem.v
../../rtl/verilog/or1200/mem2reg.v
../../rtl/verilog/or1200/dc_tag.v
../../rtl/verilog/or1200/dc_ram.v
../../rtl/verilog/or1200/ic.v
../../rtl/verilog/or1200/ic_fsm.v
../../rtl/verilog/or1200/ic_tag.v
../../rtl/verilog/or1200/ic_ram.v
../../rtl/verilog/or1200/immu.v
../../rtl/verilog/or1200/itlb.v
../../rtl/verilog/or1200/dmmu.v
../../rtl/verilog/or1200/dtlb.v
../../rtl/verilog/or1200/generic_multp2_32x32.v
../../rtl/verilog/or1200/cfgr.v
../../rtl/verilog/or1200/du.v
../../rtl/verilog/or1200/mult_mac.v
../../rtl/verilog/or1200/generic_dpram_32x32.v
../../rtl/verilog/or1200/generic_spram_2048x32.v
../../rtl/verilog/or1200/generic_spram_2048x8.v
../../rtl/verilog/or1200/generic_spram_512x20.v
../../rtl/verilog/or1200/generic_spram_64x14.v
../../rtl/verilog/or1200/generic_spram_64x21.v
../../rtl/verilog/or1200/generic_spram_64x23.v
../../rtl/verilog/or1200/xcv_ram32x8d.v
../../rtl/verilog/or1200/or1200_wb_biu.v
../../rtl/verilog/or1200/or1200_ctrl.v
../../rtl/verilog/or1200/or1200_cpu.v
../../rtl/verilog/or1200/or1200_rf.v
../../rtl/verilog/or1200/or1200_alu.v
../../rtl/verilog/or1200/or1200_lsu.v
../../rtl/verilog/or1200/or1200_operandmuxes.v
../../rtl/verilog/or1200/or1200_wbmux.v
../../rtl/verilog/or1200/or1200_genpc.v
../../rtl/verilog/or1200/or1200_if.v
../../rtl/verilog/or1200/or1200_freeze.v
../../rtl/verilog/or1200/or1200_sprs.v
../../rtl/verilog/or1200/or1200_top.v
../../rtl/verilog/or1200/or1200_pic.v
../../rtl/verilog/or1200/or1200_pm.v
../../rtl/verilog/or1200/or1200_tt.v
../../rtl/verilog/or1200/or1200_except.v
../../rtl/verilog/or1200/or1200_dc_top.v
../../rtl/verilog/or1200/or1200_dc_fsm.v
../../rtl/verilog/or1200/or1200_reg2mem.v
../../rtl/verilog/or1200/or1200_mem2reg.v
../../rtl/verilog/or1200/or1200_dc_tag.v
../../rtl/verilog/or1200/or1200_dc_ram.v
../../rtl/verilog/or1200/or1200_ic_top.v
../../rtl/verilog/or1200/or1200_ic_fsm.v
../../rtl/verilog/or1200/or1200_ic_tag.v
../../rtl/verilog/or1200/or1200_ic_ram.v
../../rtl/verilog/or1200/or1200_immu_top.v
../../rtl/verilog/or1200/or1200_immu_tlb.v
../../rtl/verilog/or1200/or1200_dmmu_top.v
../../rtl/verilog/or1200/or1200_dmmu_tlb.v
../../rtl/verilog/or1200/or1200_amultp2_32x32.v
../../rtl/verilog/or1200/or1200_gmultp2_32x32.v
../../rtl/verilog/or1200/or1200_cfgr.v
../../rtl/verilog/or1200/or1200_du.v
../../rtl/verilog/or1200/or1200_mult_mac.v
../../rtl/verilog/or1200/or1200_dpram_32x32.v
../../rtl/verilog/or1200/or1200_spram_2048x32.v
../../rtl/verilog/or1200/or1200_spram_2048x8.v
../../rtl/verilog/or1200/or1200_spram_512x20.v
../../rtl/verilog/or1200/or1200_spram_256x21.v
../../rtl/verilog/or1200/or1200_spram_1024x8.v
../../rtl/verilog/or1200/or1200_spram_1024x32.v
../../rtl/verilog/or1200/or1200_spram_64x14.v
../../rtl/verilog/or1200/or1200_spram_64x22.v
../../rtl/verilog/or1200/or1200_spram_64x24.v
../../rtl/verilog/or1200/or1200_xcv_ram32x8d.v
 
//
// Library files
126,6 → 131,7
../../lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v
+incdir+../../lib/xilinx/unisims
../../lib/xilinx/unisims/RAMB4_S16.v
../../lib/xilinx/unisims/RAMB4_S8.v
../../lib/xilinx/unisims/RAMB4_S4.v
../../lib/xilinx/unisims/RAMB4_S2.v
../../lib/xilinx/unisims/RAMB4_S16_S16.v

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