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Rev 51 → Rev 52
/jart/branches/ver0branch/mod0.vhd
0,0 → 1,94
-- Author : Julian Andres Guarin Reyes. |
-- Project : JART, Just Another Ray Tracer. |
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co |
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-- This code was entirely written by Julian Andres Guarin Reyes. |
-- The following code is licensed under GNU Public License |
-- http://www.gnu.org/licenses/gpl-3.0.txt. |
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-- This file is part of JART (Just Another Ray Tracer). |
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
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-- You should have received a copy of the GNU General Public License |
-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>. |
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-- Reminder 0 detector with load. |
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
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entity mod0 is |
generic (WIDTH : integer range 1 to 32); |
port ( |
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clk : in std_logic, --Clock |
rst : in std_logic, --Reset |
icload : in std_logic_vector (WIDTH-1 downto 0), -- Input data to load in the counter register |
imload : in std_logic_vector (WIDTH-1 downto 0), -- Output data to load in the module register (a comparison register) |
cload : in std_logic, --Signal to load in the counter |
mload : in std_logic, --Signal to load in the module, |
enable : in std_logic, --Signal to start counting, |
mod0 : out std_logic_vector -- Counter Value. |
); |
end clearableCounter; |
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architecture rtl of clearableCounter is |
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signal sCounter : std_logic_vector (WIDTH-1 downto 0); -- Register where the counting takes place |
signal sModule : std_logic_vector (WIDTH-1 downto 0); -- Register where the module is stored |
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begin |
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process (clk,rst) |
begin |
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if rst='0' then |
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sCounter <= (others => '1'); |
sModule <= (others => '0'); |
mod0 <= '1'; |
elsif rising_edge (clk) then |
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-- Load a new module |
if mload <='1' then |
sModule <= imload; |
end if; |
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-- Load a new counter |
if cload <='1' then |
sCounter <= icload; |
end if; |
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-- Count Up and Detect Module. |
if enable <='1' then |
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sCounter <= sCounter + 1; |
if sCounter = sModule then |
mod0 <= '1'; |
else |
mod0 <= '0'; |
end if; |
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end if; |
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end process; |
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end rtl; |
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