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Rev 51 → Rev 52

/trunk/hdl/rtl/sparc_core/bw_r_frf.v
51,8 → 51,10
output [77:0] frf_dp_data;
 
wire [7:0] regfile_index;
wire [7:0] regfile_index_low;
wire [7:0] regfile_index_high;
//XST WA CR436004
(* keep = "yes" *) wire [7:0] regfile_index_low;
(* keep = "yes" *) wire [7:0] regfile_index_high;
//
 
 
reg [38:0] regfile_high [127:0];
/trunk/hdl/rtl/sparc_core/sparc_exu_alu.v
141,7 → 141,7
 
// Logic/pass rs2_data
dff invert_d2e(.din(ifu_exu_invert_d), .clk(clk), .q(invert_e), .se(se), .si(), .so());
sparc_exu_alulogic logic(.rs1_data(byp_alu_rs1_data_e[63:0]),
sparc_exu_alulogic logic_MAYBEARESERVEDWORD(.rs1_data(byp_alu_rs1_data_e[63:0]),
.rs2_data(byp_alu_rs2_data_e[63:0]),
.isand(ecl_alu_log_sel_and_e),
.isor(ecl_alu_log_sel_or_e),
/trunk/hdl/rtl/sparc_core/sparc_ifu_fcl.v
1623,7 → 1623,11
// 0in <fire -message "ERROR: sparc_ifu_fcl: rd and wr req to I$ at the same time"
 
 
 
$display("CACHE_CONTENTION", "ERROR: sparc_ifu_fcl: rd and wr req to I$ at the same time");
 
end
end
/trunk/hdl/rtl/sparc_core/bw_r_rf32x152b.v
38,146 → 38,61
 
 
 
module bw_r_rf32x152b (/*AUTOARG*/
// Outputs
dout, so,
// Inputs
rd_en, rd_adr, wr_en, wr_adr, din,
si, se, sehold, rclk, rst_tri_en, reset_l);
 
parameter NUMENTRIES = 32 ; // number of entries in dfq
 
input [4:0] rd_adr; // read adr.
input rd_en; // read pointer
input wr_en; // write pointer vld
input [4:0] wr_adr; // write adr.
input [151:0] din; // wr data
input rclk; // clock
input reset_l; // active low reset
input rst_tri_en; // reset and scan
input sehold; // scan hold
input si; // scan in
input se; // scan enable
module bw_r_rf32x152b(dout, so, rd_en, rd_adr, wr_en, wr_adr, din, si, se,
sehold, rclk, rst_tri_en, reset_l);
 
output [151:0] dout ; // data read out
output so ; // scan out
parameter NUMENTRIES = 32;
 
wire [151:0] dout;
wire clk;
wire wr_vld;
input [4:0] rd_adr;
input rd_en;
input wr_en;
input [4:0] wr_adr;
input [151:0] din;
input rclk;
input reset_l;
input rst_tri_en;
input sehold;
input si;
input se;
output [151:0] dout;
reg [151:0] dout;
output so;
 
reg [151:0] dfq_mem [NUMENTRIES-1:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
wire clk;
wire wr_vld;
 
reg [151:0] local_dout;
// reg so;
reg [151:0] dfq_mem[(NUMENTRIES - 1):0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
 
integer i,j;
assign clk = rclk;
assign wr_vld = ((wr_en & (~rst_tri_en)) & reset_l);
 
//
// added for atpg support
wire [4:0] sehold_rd_adr; // output of sehold mux - read adr.
wire sehold_rd_en; // output of sehold mux - read pointer
wire sehold_wr_en; // output of sehold mux - write pointer vld
wire [4:0] sehold_wr_adr; // output of sehold mux - write adr.
wire [151:0] sehold_din; // wr data
always @(posedge clk) begin
if (wr_vld) begin
dfq_mem[wr_adr] = din;
end
end
always @(posedge clk) begin
if (rd_en) begin
dout[151:0] <= dfq_mem[rd_adr[4:0]];
end
end
endmodule
 
wire [4:0] rd_adr_d1; // flopped read adr.
wire rd_en_d1; // flopped read pointer
wire wr_en_d1; // flopped write pointer vld
wire [4:0] wr_adr_d1; // flopped write adr.
wire [151:0] din_d1; // flopped wr data
 
//
// creating local clock
assign clk=rclk;
//
//=========================================================================================
// support for atpg pattern generation
//=========================================================================================
//
// read controls
dp_mux2es #(6) mux_sehold_rd_ctrl (
.in0 ({rd_adr[4:0], rd_en}),
.in1 ({rd_adr_d1[4:0], rd_en_d1}),
.sel (sehold),
.dout ({sehold_rd_adr[4:0],sehold_rd_en})
);
 
dff #(6) dff_rd_ctrl_d1(
.din ({sehold_rd_adr[4:0], sehold_rd_en}),
.q ({rd_adr_d1[4:0], rd_en_d1}),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// write controls
dp_mux2es #(6) mux_sehold_wr_ctrl (
.in0 ({wr_adr[4:0], wr_en}),
.in1 ({wr_adr_d1[4:0], wr_en_d1}),
.sel (sehold),
.dout ({sehold_wr_adr[4:0],sehold_wr_en})
);
 
dff #(6) dff_wr_ctrl_d1(
.din ({sehold_wr_adr[4:0], sehold_wr_en}),
.q ({wr_adr_d1[4:0], wr_en_d1}),
.clk (clk),
.se (se),
.si (),
.so ()
);
//
// write data
dp_mux2es #(152) mux_sehold_din (
.in0 (din[151:0]),
.in1 (din_d1[151:0]),
.sel (sehold),
.dout (sehold_din[151:0])
);
 
dff #(152) dff_din_d1(
.din (sehold_din[151:0]),
.q (din_d1[151:0]),
.clk (clk),
.se (se),
.si (),
.so ()
);
 
//
// diable write to register file during reset or scan
assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l;
 
// always @ (posedge clk)
// begin
// so <= 1'bx;
// end
 
//=========================================================================================
// generate wordlines
//=========================================================================================
 
// Word-Line Generation skipped. Implicit in read and write.
 
//=========================================================================================
// write or read to/from memory
//=========================================================================================
 
 
always @ ( posedge clk )
begin
if (wr_vld)
dfq_mem[sehold_wr_adr] = sehold_din[151:0] ;
end
 
always @ ( posedge clk )
begin
if (sehold_rd_en)
begin
 
local_dout[151:0] <= dfq_mem[sehold_rd_adr[4:0]];
 
 
 
188,8 → 103,6
 
 
 
end
end
 
 
 
201,7 → 114,6
 
 
 
assign dout[151:0] = local_dout[151:0];
 
 
 
242,4 → 154,135
 
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/trunk/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
432,11 → 432,15
// 0in <fire -message "MILSTATE, Error: SPARC/IFU/MILFSM: unknown state!"
 
 
if($time>2)
if ($time > (4* 1))
begin
 
 
 
$display ("MILSTATE",
"Error: SPARC/IFU/MILFSM: unknown state! %b\n",
milstate);
"Error: SPARC/IFU/MILFSM: unknown state! %b\n",milstate);
end
 
// synopsys translate_on
/trunk/hdl/rtl/sparc_core/bw_r_irf.v
138,6 → 138,15
new_agp_d1,
new_agp_d2;
 
 
 
 
 
 
 
 
 
 
reg [71:0] active_win_thr_rd_w_neg;
reg [71:0] active_win_thr_rd_w2_neg;
reg [6:0] thr_rd_w_neg;
145,6 → 154,7
reg active_win_thr_rd_w_neg_wr_en;
reg active_win_thr_rd_w2_neg_wr_en;
reg rst_tri_en_neg;
 
wire se;
wire clk;
219,6 → 229,16
////////////////////////////////////////////////////////////////
// This is a latch that works if both wen is high and clk is low
 
 
 
 
 
 
 
 
 
 
 
always @(negedge clk) begin
rst_tri_en_neg <= rst_tri_en;
// write conflict results in X written to destination
248,6 → 268,8
active_win_thr_rd_w2_neg_wr_en <= 1'b0;
end
end
 
 
 
 
507,7 → 529,7
//reg [71:0] active_window [127:0];// 32x4 72 bit registers
 
always @(negedge clk)
if(ifu_exu_ren1_d)
if(ifu_exu_ren1_d) //comes from a posedge clk
case(thr_rs1[4:0])
5'b00000: irf_byp_rs1_data_d <= rd_data00;
5'b00001: irf_byp_rs1_data_d <= rd_data01;
/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
130,7 → 130,7
wire visop_w3_vld;
wire add;
wire align;
wire logic;
wire logic_MAYBEARESERVEDWORD;
wire siam;
wire alignaddr;
 
256,14 → 256,14
////////////////////////////////////
assign add = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & opf[4] & ~opf[3];
assign align = ~opf[8] & ~opf[7] & opf[6] & ~opf[5] & ~opf[4] & opf[3] & ~opf[2] & ~opf[1] & ~opf[0];
assign logic = ~opf[8] & ~opf[7] & opf[6] & opf[5];
assign logic_MAYBEARESERVEDWORD = ~opf[8] & ~opf[7] & opf[6] & opf[5];
assign siam = ~opf[8] & opf[7] & ~opf[6] & ~opf[5] & ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1] & opf[0];
assign alignaddr = ~opf[8] & ~opf[7] & ~opf[6] & ~opf[5] & opf[4] & opf[3] & ~opf[2] & ~opf[0]; //alignaddress
 
assign illegal_vis_e = (visop_e & ~(add | align | logic | siam | alignaddr) |
assign illegal_vis_e = (visop_e & ~(add | align | logic_MAYBEARESERVEDWORD | siam | alignaddr) |
illegal_rs1_e | illegal_rs2_e | illegal_siam_e);
assign rs1_check_nonzero_e = visop_e & (siam | (logic & (opf_log_zero | opf_log_one | opf_log_src2 | opf_log_not2)));
assign rs2_check_nonzero_e = visop_e & logic & (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_not1);
assign rs1_check_nonzero_e = visop_e & (siam | (logic_MAYBEARESERVEDWORD & (opf_log_zero | opf_log_one | opf_log_src2 | opf_log_not2)));
assign rs2_check_nonzero_e = visop_e & logic_MAYBEARESERVEDWORD & (opf_log_zero | opf_log_one | opf_log_src1 | opf_log_not1);
assign illegal_rs1_e = (frs1_e[4:0] != 5'b00000) & rs1_check_nonzero_e;
assign illegal_rs2_e = (frs2_e[4:0] != 5'b00000) & rs2_check_nonzero_e;
assign illegal_siam_e = ((frd_e[4:0] != 5'b00000) | frs2_e[4] | frs2_e[3]) & siam & visop_e;
276,7 → 276,7
assign ctl_vis_cin = opf[2];
assign ctl_vis_add32 = opf[1];
 
// controls for logic
// controls for logic_MAYBEARESERVEDWORD
assign opf_log_zero = ~opf[4] & ~opf[3] & ~opf[2] & ~opf[1];
assign opf_log_nor = ~opf[4] & ~opf[3] & ~opf[2] & opf[1];
assign opf_log_andnot2 = ~opf[4] & ~opf[3] & opf[2] & ~opf[1];
294,7 → 294,7
assign opf_log_or = opf[4] & opf[3] & opf[2] & ~opf[1];
assign opf_log_one = opf[4] & opf[3] & opf[2] & opf[1];
 
// selects for logic mux
// selects for logic_MAYBEARESERVEDWORD mux
assign ctl_vis_log_sel_nand = opf_log_or | opf_log_nand | opf_log_ornot1 | opf_log_ornot2;
assign ctl_vis_log_sel_xor = opf_log_xor | opf_log_xnor;
assign ctl_vis_log_sel_nor = opf_log_and | opf_log_nor | opf_log_andnot1 | opf_log_andnot2;
/trunk/hdl/rtl/sparc_core/bw_r_irf_register.v
20,6 → 20,57
// ========== Copyright Header End ============================================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
module bw_r_irf_register(clk, wren, save, save_addr, restore, restore_addr, wr_data, rd_data);
input clk;
input wren;
116,6 → 167,7
 
 
 
 
 
 
 
/trunk/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
355,7 → 355,11
// 0in <fire -message "thrfsm.v: Error! Invalid State"
 
$display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
 
 
//$display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
// synopsys translate_on
if (rst_thread)
/trunk/hdl/rtl/sparc_core/bw_r_tlb.v
620,6 → 620,12
 
 
 
 
 
 
 
module bw_r_tlb ( /*AUTOARG*/
// Outputs
tlb_rd_tte_tag, tlb_rd_tte_data, tlb_pgnum, tlb_pgnum_crit,
691,7 → 697,7
wire [42:0] wr_tte_data ;
wire [29:3] phy_pgnum_m;
wire [29:0] pgnum_m;
wire [8-1:0] used ;
wire [64-1:0] used ;
wire tlb_not_writeable ;
wire [40:25] tlb_cam_key_masked ;
wire [26:0] tlb_cam_comp_key ;
698,36 → 704,35
wire cam_vld ;
wire demap_other ;
wire [3:0] cache_way_hit ;
wire [8-1:0] mismatch;
wire [64-1:0] mismatch;
 
reg tlb_not_writeable_d1 ;
reg tlb_writeable ;
wire [8-1:0] tlb_entry_locked ;
wire [8-1:0] cam_hit ;
wire [8-1:0] demap_hit ;
reg [8-1:0] ademap_hit ;
wire [64-1:0] tlb_entry_locked ;
wire [64-1:0] cam_hit ;
wire [64-1:0] demap_hit ;
reg [64-1:0] ademap_hit ;
wire [58:0] rd_tte_tag ; // CHANGE
wire [42:0] rd_tte_data ;
reg [58:0] tlb_rd_tte_tag ; // CHANGE
reg [42:0] tlb_rd_tte_data ;
reg cam_vld_tmp ;
reg [2:0] cam_pid ;
reg [53:0] cam_data ;
reg demap_auto, demap_other_tmp, demap_all ;
reg [8-1:0] tlb_entry_vld ;
wire [8-1:0] tlb_entry_used ;
reg [8-1:0] tlb_entry_replace ;
reg [8-1:0] tlb_entry_replace_d2 ;
reg [64-1:0] tlb_entry_vld ;
wire [64-1:0] tlb_entry_used ;
reg [64-1:0] tlb_entry_replace ;
reg [64-1:0] tlb_entry_replace_d2 ;
reg [29:0] pgnum_g ;
reg [3:0] cache_set_vld_g;
reg [29:0] cache_ptag_w0_g,cache_ptag_w1_g;
reg [29:0] cache_ptag_w2_g,cache_ptag_w3_g;
reg [8-1:0] rw_wdline ;
reg [64-1:0] rw_wdline ;
 
reg rd_tag;
reg rd_data;
reg wr_vld_tmp;
reg [3-1:0] rw_index;
reg [6-1:0] rw_index;
reg rw_index_vld;
wire [29:0] vrtl_pgnum_m;
wire bypass ;
847,7 → 852,7
assign rw_disable = ~arst_l | rst_tri_en ;
 
 
reg [3-1:0] cam_hit_encoded;
reg [6-1:0] cam_hit_encoded;
integer ii;
 
reg cam_hit_any;
854,8 → 859,8
 
always @(cam_hit) begin
cam_hit_any = 1'b0;
cam_hit_encoded = {3{1'b0}};
for(ii=0;ii<8;ii=ii+1) begin
cam_hit_encoded = {6{1'b0}};
for(ii=0;ii<64;ii=ii+1) begin
if(cam_hit[ii]) begin
cam_hit_encoded = ii;
cam_hit_any = 1'b1;
915,7 → 920,7
rd_tag <= rd_tag ;
rd_data <= rd_data ;
rw_index_vld <= rw_index_vld ;
rw_index[3-1:0] <= rw_index[3-1:0] ;
rw_index[6-1:0] <= rw_index[6-1:0] ;
end
else
begin
929,7 → 934,7
rd_tag <= tlb_rd_tag_vld ;
rd_data <= tlb_rd_data_vld ;
rw_index_vld <= tlb_rw_index_vld ;
rw_index[3-1:0] <= tlb_rw_index[3-1:0] ;
rw_index[6-1:0] <= tlb_rw_index[6-1:0] ;
end
 
end
949,11 → 954,11
//=========================================================================================
 
 
assign tlb_rd_tte_tag[58:0] = rd_tte_tag[58:0] ; // CHANGE
 
// Stage to next cycle.
always @ (posedge clk)
begin
tlb_rd_tte_tag[58:0] <= rd_tte_tag[58:0] ; // CHANGE
tlb_rd_tte_data[42:0] <= rd_tte_data[42:0] ;
end
 
967,7 → 972,7
always @ ( negedge clk )
begin
for (n=0;n<8;n=n+1)
for (n=0;n<64;n=n+1)
begin
if (demap_auto & demap_other)
ademap_hit[n] = (~mismatch[n] & demap_other & tlb_entry_vld[n]) ;
976,7 → 981,7
end // always
 
 
assign tlb_cam_hit = |cam_hit[8-1:0] ;
assign tlb_cam_hit = |cam_hit[64-1:0] ;
 
// Change tlb_entry_vld handling for multi-threaded tlb writes.
// A write is always preceeded by an autodemap. The intent is to make the result of autodemap
991,8 → 996,8
always @ (/*AUTOSENSE*/rd_data or rd_tag or rw_index or rw_index_vld
or wr_vld_tmp)
begin
for (i=0;i<8;i=i+1)
if ((rw_index[3-1:0] == i) & ((wr_vld_tmp & rw_index_vld) | rd_tag | rd_data))
for (i=0;i<64;i=i+1)
if ((rw_index[6-1:0] == i) & ((wr_vld_tmp & rw_index_vld) | rd_tag | rd_data))
rw_wdline[i] = 1'b1 ;
else rw_wdline[i] = 1'b0 ;
 
1001,7 → 1006,7
 
always @ (negedge clk)
begin
for (r=0;r<8;r=r+1)
for (r=0;r<64;r=r+1)
begin // for
if (((rw_index_vld & rw_wdline[r]) | (~rw_index_vld & tlb_entry_replace_d2[r])) &
wr_vld & ~rw_disable)
1115,7 → 1120,7
// Choosing replacement entry
// Replacement entry is integer k
 
assign tlb_not_writeable = &used[8-1:0] ;
assign tlb_not_writeable = &used[64-1:0] ;
/*
// Used bit can be set because of write or because of cam-hit.
always @(negedge clk)
1145,7 → 1150,7
 
// Determine whether entry should be squashed.
 
assign used[8-1:0] = tlb_entry_used[8-1:0] & tlb_entry_vld[8-1:0] ;
assign used[64-1:0] = tlb_entry_used[64-1:0] & tlb_entry_vld[64-1:0] ;
 
 
// Based on updated Used state, generate replacement entry.
1152,14 → 1157,14
// So, replacement entries can be generated on a cycle-by-cycle basis.
//always @(/*AUTOSENSE*/squash or used)
 
reg [8-1:0] tlb_entry_replace_d1;
reg [64-1:0] tlb_entry_replace_d1;
reg tlb_replace_flag;
always @(/*AUTOSENSE*/used)
begin
tlb_replace_flag=1'b0;
tlb_entry_replace_d1 = {8-1{1'b0}};
tlb_entry_replace_d1 = {64-1{1'b0}};
// Priority is given to entry0
for (u=0;u<8;u=u+1)
for (u=0;u<64;u=u+1)
begin
if(~tlb_replace_flag & ~used[u])
begin
1168,7 → 1173,7
end
end
if(~tlb_replace_flag) begin
tlb_entry_replace_d1[8-1] = 1'b1;
tlb_entry_replace_d1[64-1] = 1'b1;
end
end
always @(posedge clk)
1182,14 → 1187,14
tlb_entry_replace_d2 <= tlb_entry_replace ;
end
 
reg [3-1:0] tlb_index_a1;
reg [3-1:0] tlb_index;
reg [6-1:0] tlb_index_a1;
reg [6-1:0] tlb_index;
wire tlb_index_vld_a1 = |tlb_entry_replace;
reg tlb_index_vld;
integer jj;
always @(tlb_entry_replace) begin
tlb_index_a1 = {3{1'b0}};
for(jj=0;jj<8;jj=jj+1)
tlb_index_a1 = {6{1'b0}};
for(jj=0;jj<64;jj=jj+1)
if(tlb_entry_replace[jj]) tlb_index_a1 = jj;
end
always @(posedge clk) begin
1293,13 → 1298,13
input rw_index_vld;
input wr_vld_tmp;
input clk;
input [3-1:0] rw_index;
input [3-1:0] tlb_index;
input [6-1:0] rw_index;
input [6-1:0] tlb_index;
input tlb_index_vld;
input rw_disable;
input rst_tri_en;
input [58:0] wr_tte_tag;
input [8-1:0] tlb_entry_vld;
input [64-1:0] tlb_entry_vld;
input tlb_writeable;
input wr_vld;
input [2:0] cam_pid;
1308,59 → 1313,56
input [53:0] cam_data;
input cam_vld ;
 
output [8-1:0] cam_hit ;
output [8-1:0] demap_hit ;
output [8-1:0] tlb_entry_used;
output [8-1:0] tlb_entry_locked;
reg [8-1:0] tlb_entry_locked ;
output [64-1:0] cam_hit ;
output [64-1:0] demap_hit ;
output [64-1:0] tlb_entry_used;
output [64-1:0] tlb_entry_locked;
reg [64-1:0] tlb_entry_locked ;
 
output [58:0] rd_tte_tag;
output [8-1:0] mismatch;
reg [58:0] rd_tte_tag;
output [64-1:0] mismatch;
 
reg [8-1:0] sat;
reg [64-1:0] sat;
 
reg [8-1:0] mismatch;
reg [8-1:0] cam_hit ;
reg [8-1:0] demap_all_but_locked_hit ;
reg [64-1:0] mismatch;
reg [64-1:0] cam_hit ;
reg [64-1:0] demap_all_but_locked_hit ;
reg [58:0] tag ; // CHANGE
 
reg [58:0] rd_tte_tag;
 
reg [8-1:0] mismatch_va_b47_28;
reg [8-1:0] mismatch_va_b27_22;
reg [8-1:0] mismatch_va_b21_16;
reg [8-1:0] mismatch_va_b15_13;
reg [8-1:0] mismatch_ctxt;
reg [8-1:0] mismatch_pid;
reg [8-1:0] mismatch_type;
reg [8-1:0] tlb_entry_used ;
reg [64-1:0] mismatch_va_b47_28;
reg [64-1:0] mismatch_va_b27_22;
reg [64-1:0] mismatch_va_b21_16;
reg [64-1:0] mismatch_va_b15_13;
reg [64-1:0] mismatch_ctxt;
reg [64-1:0] mismatch_pid;
reg [64-1:0] mismatch_type;
reg [64-1:0] tlb_entry_used ;
 
integer i,j,n,m, w, p, k, s, t;
 
 
reg [58:0] tte_tag_ram [8-1:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [58:0] tte_tag_ram [64-1:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
 
reg [58:0] tmp_tag ;
 
wire wren = rw_index_vld & wr_vld_tmp & ~rw_disable;
wire tlben = tlb_index_vld & ~rw_index_vld & wr_vld_tmp & ~rw_disable;
wire [6-1:0] wr_addr = wren ? rw_index : tlb_index;
 
reg [58:0] tmp_tag ;
 
always @ (negedge clk) begin
//=========================================================================================
// Write TLB
//=========================================================================================
if(rw_index_vld & wr_vld_tmp & ~rw_disable) begin
tte_tag_ram[rw_index] <= wr_tte_tag[58:0];
tlb_entry_used[rw_index] <= wr_tte_tag[24];
tlb_entry_locked[rw_index] = wr_tte_tag[25];
rd_tte_tag[58:0] <= wr_tte_tag[58:0] ; // CHANGE
end else
if(tlb_index_vld & ~rw_index_vld & wr_vld_tmp & ~rw_disable) begin
tte_tag_ram[tlb_index] <= wr_tte_tag[58:0];
tlb_entry_used[tlb_index] <= wr_tte_tag[24];
tlb_entry_locked[tlb_index] = wr_tte_tag[25];
rd_tte_tag[58:0] <= wr_tte_tag[58:0] ; // CHANGE
 
if(wren | tlben) begin
tte_tag_ram[wr_addr] <= wr_tte_tag[58:0];
tlb_entry_used[wr_addr] <= wr_tte_tag[24];
tlb_entry_locked[wr_addr] = wr_tte_tag[25];
end else begin
tlb_entry_used <= (tlb_entry_used | cam_hit) & (tlb_entry_locked | ~{8{~tlb_writeable & ~cam_vld & ~wr_vld & ~rd_tag & ~rst_tri_en}}) ;
tlb_entry_used <= (tlb_entry_used | cam_hit) & (tlb_entry_locked | ~{64{~tlb_writeable & ~cam_vld & ~wr_vld & ~rd_tag & ~rst_tri_en}}) ;
end
 
//=========================================================================================
1368,21 → 1370,34
//=========================================================================================
 
if(rd_tag & ~rw_disable) begin
tmp_tag = tte_tag_ram[rw_index];
rd_tte_tag[58:0] <= {tmp_tag[58:27], tlb_entry_vld[rw_index],
tlb_entry_locked[rw_index], tlb_entry_used[rw_index], tmp_tag[23:0]};
tmp_tag <= tte_tag_ram[rw_index];
end
 
 
end // always
 
always @(posedge clk) begin
if(rd_tag & ~rw_disable)
rd_tte_tag[58:0] = {tmp_tag[58:27], tlb_entry_vld[rw_index], tlb_entry_locked[rw_index], tlb_entry_used[rw_index], tmp_tag[23:0]};
else if(wren | tlben)
rd_tte_tag[58:0] = wr_tte_tag[58:0];
end
 
reg [58:0] tte_tag_ram2 [64-1:0];
 
always @ (negedge clk) begin
if(wren | tlben)
tte_tag_ram2[wr_addr] <= wr_tte_tag[58:0];
end
 
 
always @ (cam_data or cam_pid or cam_vld or demap_all
or demap_other or tlb_entry_vld)
begin
for (n=0;n<8;n=n+1)
for (n=0;n<64;n=n+1)
begin
tag[58:0] = tte_tag_ram[n] ; // CHANGE
tag[58:0] = tte_tag_ram2[n] ; // CHANGE
 
mismatch_va_b47_28[n] =
(tag[53:34]
1423,11 → 1438,13
 
end // always
 
assign demap_hit = demap_all ? ~mismatch & demap_all_but_locked_hit & tlb_entry_vld & {8{demap_other}}
: ~mismatch & tlb_entry_vld & {8{demap_other}};
assign demap_hit = demap_all ? ~mismatch & demap_all_but_locked_hit & tlb_entry_vld & {64{demap_other}}
: ~mismatch & tlb_entry_vld & {64{demap_other}};
 
endmodule
 
 
 
module bw_r_tlb_data_ram(rd_data, rw_index_vld, wr_vld_tmp, clk, cam_vld,
rw_index, tlb_index, tlb_index_vld, rw_disable, rst_tri_en, wr_tte_data,
rd_tte_data, cam_index, cam_hit_any, wr_vld);
/trunk/hdl/rtl/sparc_core/bw_r_rf16x160.v
297,6 → 297,7
.wr_data(wrdata_d1[ 7: 0]),
.rd_data(dout[ 7: 0]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr1 (
308,6 → 309,7
.wr_data(wrdata_d1[ 15: 8]),
.rd_data(dout[ 15: 8]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr2 (
319,6 → 321,7
.wr_data(wrdata_d1[ 23: 16]),
.rd_data(dout[ 23: 16]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr3 (
330,6 → 333,7
.wr_data(wrdata_d1[ 31: 24]),
.rd_data(dout[ 31: 24]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr4 (
341,6 → 345,7
.wr_data(wrdata_d1[ 39: 32]),
.rd_data(dout[ 39: 32]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr5 (
352,6 → 357,7
.wr_data(wrdata_d1[ 47: 40]),
.rd_data(dout[ 47: 40]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr6 (
363,6 → 369,7
.wr_data(wrdata_d1[ 55: 48]),
.rd_data(dout[ 55: 48]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr7 (
374,6 → 381,7
.wr_data(wrdata_d1[ 63: 56]),
.rd_data(dout[ 63: 56]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr8 (
385,6 → 393,7
.wr_data(wrdata_d1[ 71: 64]),
.rd_data(dout[ 71: 64]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr9 (
396,6 → 405,7
.wr_data(wrdata_d1[ 79: 72]),
.rd_data(dout[ 79: 72]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr10(
407,6 → 417,7
.wr_data(wrdata_d1[ 87: 80]),
.rd_data(dout[ 87: 80]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr11(
418,6 → 429,7
.wr_data(wrdata_d1[ 95: 88]),
.rd_data(dout[ 95: 88]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr12(
429,6 → 441,7
.wr_data(wrdata_d1[103: 96]),
.rd_data(dout[103: 96]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr13(
440,6 → 453,7
.wr_data(wrdata_d1[111:104]),
.rd_data(dout[111:104]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr14(
451,6 → 465,7
.wr_data(wrdata_d1[119:112]),
.rd_data(dout[119:112]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr15(
462,6 → 477,7
.wr_data(wrdata_d1[127:120]),
.rd_data(dout[127:120]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr16(
473,6 → 489,7
.wr_data(wrdata_d1[135:128]),
.rd_data(dout[135:128]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr17(
484,6 → 501,7
.wr_data(wrdata_d1[143:136]),
.rd_data(dout[143:136]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr18(
495,6 → 513,7
.wr_data(wrdata_d1[151:144]),
.rd_data(dout[151:144]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
bw_r_rf16x2 arr19(
506,6 → 525,7
.wr_data(wrdata_d1[159:152]),
.rd_data(dout[159:152]),
.clk(wr_clk),
.rd_clk(rd_clk),
.reset_l(reset_l));
 
 
666,7 → 686,7
 
 
module bw_r_rf16x2(word_wen, wen, ren, wr_addr, rd_addr, wr_data,
rd_data, clk, reset_l);
rd_data, clk, rd_clk, reset_l);
input [3:0] word_wen;
input wen;
input ren;
675,14 → 695,15
input [7:0] wr_data;
output [7:0] rd_data;
input clk;
input rd_clk;
input reset_l;
 
reg [7:0] rd_data_temp;
 
reg [1:0] inq_ary0[15:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
reg [1:0] inq_ary1[15:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
reg [1:0] inq_ary2[15:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
reg [1:0] inq_ary3[15:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */;
reg [1:0] inq_ary0[15:0];
reg [1:0] inq_ary1[15:0];
reg [1:0] inq_ary2[15:0];
reg [1:0] inq_ary3[15:0];
 
always @(posedge clk) begin
if(reset_l & wen & word_wen[0])
694,44 → 715,14
if(reset_l & wen & word_wen[3])
inq_ary3[wr_addr] = {wr_data[7],wr_data[3]};
end
/*
always @(wen or word_wen or reset_l or wr_data or wr_addr) begin
if (reset_l) begin
if(wen & word_wen[0])
inq_ary0[wr_addr] = {wr_data[4],wr_data[0]};
if(wen & word_wen[1])
inq_ary1[wr_addr] = {wr_data[5],wr_data[1]};
if(wen & word_wen[2])
inq_ary2[wr_addr] = {wr_data[6],wr_data[2]};
if(wen & word_wen[3])
inq_ary3[wr_addr] = {wr_data[7],wr_data[3]};
 
always @(negedge rd_clk) begin
if (~reset_l) begin
rd_data_temp = 8'b0;
end else if(ren == 1'b1) begin
rd_data_temp = {inq_ary3[rd_addr], inq_ary2[rd_addr], inq_ary1[rd_addr], inq_ary0[rd_addr]};
end
end
*/
always @(ren or rd_addr or reset_l or
wr_addr or wen or word_wen) begin
if (reset_l && (ren == 1'b1)) begin
rd_data_temp = {inq_ary3[rd_addr], inq_ary2[rd_addr],
inq_ary1[rd_addr], inq_ary0[rd_addr]};
if (rd_addr == wr_addr) begin
if(wen & word_wen[0]) begin
rd_data_temp[1:0] = 2'b0;
end
if(wen & word_wen[1]) begin
rd_data_temp[3:2] = 2'b0;
end
if(wen & word_wen[2]) begin
rd_data_temp[5:4] = 2'b0;
end
if(wen & word_wen[3]) begin
rd_data_temp[7:6] = 2'b0;
end
end
end
else
rd_data_temp = 8'b0;
end
 
assign rd_data = {rd_data_temp[7], rd_data_temp[5], rd_data_temp[3],
rd_data_temp[1], rd_data_temp[6], rd_data_temp[4],

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