OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 510 to Rev 511
    ↔ Reverse comparison
  •

Rev 510 → Rev 511

/trunk/or1ksim/cpu/or32/execute.c
833,11 → 833,35
mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
}
void l_nop() {
unsigned long stackaddr;
int k = eval_operand32(0, &breakpoint);
cur->func_unit = it_nop;
if (nop_period > nop_maxperiod)
nop_maxperiod = nop_period;
nop_period = 0;
nops++;
switch (k) {
case NOP_NOP:
break;
case NOP_EXIT:
printf("exit(%d)\n", eval_reg (3));
if (config.debug.gdb_enabled)
set_stall_state (1);
else
cont_run = 0;
break;
case NOP_PRINTF:
stackaddr = eval_reg(4);
simprintf(stackaddr, eval_reg(3));
debug(5, "simprintf %x\n", stackaddr);
break;
case NOP_REPORT:
printf("report(0x%x);\n", eval_reg(3));
default:
if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
printf("report %i (0x%x);\n", k - NOP_REPORT_FIRST, eval_reg(3));
break;
}
}
void l_bnf() {
cur->func_unit = it_branch;
927,43 → 951,31
}
}
void l_sys() {
 
#if 0
if (eval_operand32(0, &breakpoint) > 200) {
unsigned long stackaddr, fmtaddr, args;
switch (eval_operand32(0, &breakpoint)) {
case 201:
set_reg32 (RETURNV_REGNO, cycles + loadcycles + storecycles);
break;
case 202:
stackaddr = eval_reg(4);
simprintf(stackaddr, eval_reg(3));
debug(5, "simprintf %x %x %x\n", stackaddr, fmtaddr, args);
break;
case 203:
printf("syscall exit(%d)\n", eval_reg (3));
if (config.debug.gdb_enabled)
set_stall_state (1);
else
cont_run = 0;
break;
case 204: {
unsigned long startaddr;
unsigned long endaddr;
 
/* if ((startaddr = eval_mem32(eval_reg("r4"))) == -1)
startaddr = (freemem & ~(PAGE_SIZE)) + PAGE_SIZE; */
startaddr = 0x80000000;
printf("sys 204: startaddr=%x virtphy=%x\n", startaddr, eval_reg(5));
fflush(stdout);
endaddr = loadcode(simgetstr(stackaddr, eval_reg(3)), startaddr, eval_reg(5));
set_reg32 (LINK_REGNO, endaddr);
/* setsim_mem32(eval_reg(4), startaddr);
setsim_mem32(eval_reg(5), endaddr);*/
break;
break;
case 204:
{
unsigned long startaddr;
unsigned long endaddr;
/* if ((startaddr = eval_mem32(eval_reg("r4"))) == -1)
startaddr = (freemem & ~(PAGE_SIZE)) + PAGE_SIZE; */
startaddr = 0x80000000;
printf("sys 204: startaddr=%x virtphy=%x\n", startaddr, eval_reg(5));
fflush(stdout);
endaddr = loadcode(simgetstr(stackaddr, eval_reg(3)), startaddr, eval_reg(5));
set_reg32 (LINK_REGNO, endaddr);
/* setsim_mem32(eval_reg(4), startaddr);
setsim_mem32(eval_reg(5), endaddr);*/
break;
}
}
}
}
else except_handle(EXCEPT_SYSCALL, 0);
} else
#endif
except_handle(EXCEPT_SYSCALL, 0);
}
 
void l_trap() {
/trunk/or1ksim/cpu/or1k/sprs.c
72,22 → 72,6
case SPR_TTCR:
tt_stopped = 0;
break;
case 0x1234:
printf("MTSPR(0x1234, 0x%x);\n", value);
break;
case 0x1235:
{
FILE *f;
if (!(f = fopen("stdout.txt", "a+")))
{
perror(strerror(errno));
return;
}
fprintf(f, "%c", value);
if (fclose(f))
perror(strerror(errno));
}
break;
case SPR_SR:
if(value & SPR_SR_F)
flag = 1;
/trunk/or1ksim/testbench/basic.S
6,7 → 6,7
.section .except
.org 0x100
_reset:
l.nop
l.nop 0
l.movhi r1,hi(_regs)
l.ori r1,r1,lo(_regs)
l.jr r1
48,7 → 48,8
l.sub r17,r18,r15
l.sub r16,r17,r16
 
l.mtspr r0,r16,0x1234 /* Should be 0xffff0012 */
l.or r3,r0,r16
l.nop NOP_REPORT /* Should be 0xffff0012 */
 
l.movhi r31, hi(MEM_RAM)
l.ori r31,r31, lo(MEM_RAM)
102,7 → 103,8
l.lwz r4,4(r31)
l.add r8,r8,r4
 
l.mtspr r0,r8,0x1234 /* Should be 0x12352af7 */
l.or r3,r0,r8
l.nop NOP_REPORT /* Should be 0x12352af7 */
 
l.lwz r9,0(r31)
l.add r8,r9,r8
125,7 → 127,8
l.divu r7,r7,r4
l.add r8,r8,r7
 
l.mtspr r0,r8,0x1234 /* Should be 0x7ffffffe */
l.or r3,r0,r8
l.nop NOP_REPORT /* Should be 0x7ffffffe */
 
l.lwz r9,0(r31)
l.add r8,r9,r8
147,7 → 150,8
l.ori r8,r8,2
l.or r8,r8,r4
 
l.mtspr r0,r8,0x1234 /* Should be 0xffffa5a7 */
l.or r3,r0,r8
l.nop NOP_REPORT /* Should be 0xffffa5a7 */
 
l.lwz r9,0(r31)
l.add r8,r9,r8
169,7 → 173,8
l.srai r8,r8,2
l.sra r8,r8,r4
 
l.mtspr r0,r8,0x1234 /* Should be 0x000fffff */
l.or r3,r0,r8
l.nop NOP_REPORT /* Should be 0x000fffff */
 
l.lwz r9,0(r31)
l.add r8,r9,r8
380,7 → 385,8
l.andi r4,r5,0x200
l.add r8,r8,r4
 
l.mtspr r0,r8,0x1234 /* Should be 0x00002800 */
l.or r3,r0,r8
l.nop NOP_REPORT /* Should be 0x00002800 */
 
l.lwz r9,0(r31)
l.add r8,r9,r8
430,7 → 436,8
 
l.addi r8,r8,1
 
_T7: l.mtspr r0,r8,0x1234 /* Should be 0x000000009 */
_T7: l.or r3,r0,r8
l.nop NOP_REPORT /* Should be 0x000000009 */
 
l.lwz r9,0(r31)
l.add r8,r9,r8
441,8 → 448,9
l.ori r3,r3,0xe5f7
l.add r8,r8,r3
 
l.mtspr r0,r8,0x1234 /* Should be 0xdeaddead */
l.or r3,r0,r8
l.nop NOP_REPORT /* Should be 0xdeaddead */
 
l.addi r3,r0,0
l.sys 203
l.nop NOP_EXIT
 
/trunk/or1ksim/testbench/test
30,8 → 30,8
fi
 
# Last two lines should look like:
echo "MTSPR(0x1234, 0xdeaddead);" >$temp1
echo "syscall exit(0)" >>$temp1
echo "report(0xdeaddead);" >$temp1
echo "exit(0)" >>$temp1
 
# run the simulator
$1 $2 $sim_param 2>$temp4 >$temp2
/trunk/or1ksim/testbench/cfg.S
16,11 → 16,11
l.addi r2,r0,0
 
l.mfspr r3,r0,SPR_VR /* Version */
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
 
l.mfspr r3,r0,SPR_UPR /* Unit Present */
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
l.mfspr r4,r0,SPR_PMR /* Power Management */
28,7 → 28,7
l.mtspr r0,r3,SPR_PMR
l.mfspr r3,r0,SPR_PMR
l.andi r3,r3,0xff
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
 
l.addi r3,r0,5
35,47 → 35,47
l.mtspr r0,r3,SPR_PMR
l.mfspr r3,r0,SPR_PMR
l.andi r3,r3,0xff
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
l.mtspr r0,r4,SPR_PMR
 
l.mfspr r3,r0,SPR_CPUCFGR
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
 
l.mfspr r3,r0,SPR_DMMUCFGR
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
 
l.mfspr r3,r0,SPR_IMMUCFGR
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
 
l.mfspr r3,r0,SPR_DCCFGR
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
 
l.mfspr r3,r0,SPR_ICCFGR
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
l.mfspr r3,r0,SPR_DCFGR
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
l.mfspr r3,r0,SPR_PCCFGR
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.add r2,r2,r3
 
/* Configurations may differ, so we will insert another report*/
l.movhi r3,hi(0xdeacf5cc)
l.ori r3,r3,lo(0xdeacf5cc)
l.add r2,r2,r3
l.mtspr r0,r2,0x1234
l.add r3,r2,r3
l.nop NOP_REPORT
 
l.movhi r3,hi(0xdeaddead)
l.ori r3,r3,lo(0xdeaddead)
l.mtspr r0,r3,0x1234
l.nop NOP_REPORT
l.addi r3,r0,0
l.sys 203
l.nop NOP_EXIT
/trunk/or1ksim/testbench/uos/except_or32.S
155,7 → 155,7
#define PRINTF(REG,STR) \
l.movhi REG,hi(STR); \
l.addi REG,r0,lo(STR); \
l.sys 202
l.nop NOP_PRINTF
#else
#define PRINTF(REG,STR)
#endif
166,8 → 166,10
.org 0x100
_reset_vector:
l.nop
l.j _reset
l.nop
l.movhi r2,hi(_reset)
l.ori r2,r2,lo(_reset)
l.jr r2
l.nop
 
/*
* Bus Error Exception handler
210,7 → 212,10
l.movhi r3,hi(_kernel_context)
l.addi r3,r0,lo(_kernel_context)
LOADREGS
l.j _int_main
l.movhi r3,hi(_int_main)
l.addi r3,r0,lo(_int_main)
l.jr r3
l.nop
 
_extint_str:
/trunk/or1ksim/testbench/support/support.c
1,6 → 1,7
/* Support */
 
#include <sys/time.h>
#include "spr_defs.h"
#include "support.h"
#include "int.h"
 
34,7 → 35,8
void exit (int i)
{
asm("l.add r3,r0,%0": : "r" (i));
asm("l.sys 203");
asm("l.nop %0": :"K" (NOP_EXIT));
while (1);
}
 
/* activate printf support in simulator */
44,15 → 46,14
va_start(args, fmt);
asm("l.addi\tr3,%0,0": :"r" (fmt));
asm("l.addi\tr4,%0,0": :"r" (args));
asm("l.sys 202");
asm("l.nop %0": :"K" (NOP_PRINTF));
}
 
/* print long */
void report(unsigned long value)
{
unsigned long spr = 0x1234;
asm("l.mtspr\t\t%0,%1,0x0" : : "r" (spr), "r" (value));
return;
asm("l.addi\tr3,%0,0": :"r" (value));
asm("l.nop %0": :"K" (NOP_REPORT));
}
 
/* just to satisfy linker */
73,7 → 74,7
 
/* Read the Time Stamp Counter */
/* asm("simrdtsc %0" :"=r" (count)); */
asm("l.sys 201");
/*asm("l.sys 201"); */
return count;
}
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.