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Rev 511 → Rev 512
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.20 2001/12/04 05:02:36 lampret |
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 |
// |
154,7 → 157,7
// (at the moment correct operation |
// only with registered outputs) |
// |
`define OR1200_REGISTERED_OUTPUTS |
//`define OR1200_REGISTERED_OUTPUTS |
|
// |
// Register OR1200 WISHBNE inputs |
214,7 → 217,7
// (at the moment works only with |
// registered outputs) |
// |
//`define OR1200_REGISTERED_OUTPUTS |
`define OR1200_REGISTERED_OUTPUTS |
|
// |
// Register OR1200 WISHBONE inputs |