URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/
- from Rev 517 to Rev 518
- ↔ Reverse comparison
Rev 517 → Rev 518
/openrisc/trunk/gnu-src/gcc-4.5.1/gcc/BASE-VER
1,2 → 1,2
4.5.1-or32-1.0rc3 |
4.5.1-or32-1.0rc4 |
|
/openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.md
364,7 → 364,11
"GET_CODE (operands[1]) != CONST_INT" |
"l.movhi \t%0,hi(%1)\;l.ori \t%0,%0,lo(%1)" |
;; the switch of or32 bfd to Rela allows us to schedule insns separately. |
"&& reload_completed |
"(GET_CODE (operands[1]) != CONST_INT |
|| ! (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]),'I', \"I\") |
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]),'K', \"K\") |
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'M', \"M\"))) |
&& reload_completed |
&& GET_CODE (operands[1]) != HIGH && GET_CODE (operands[1]) != LO_SUM" |
[(pc)] |
{ |
707,13 → 711,19
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
;; |
;; |
(define_insn "movdi" |
(define_insn_and_split "movdi" |
[(set (match_operand:DI 0 "nonimmediate_operand" "=r, r, m, r") |
(match_operand:DI 1 "general_operand" " r, m, r, i"))] |
(match_operand:DI 1 "general_operand" " r, m, r, n"))] |
"" |
"* |
return or32_output_move_double (operands); |
" |
"&& reload_completed && CONSTANT_P (operands[1])" |
[(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))] |
"operands[2] = operand_subword (operands[0], 0, 0, DImode); |
operands[3] = operand_subword (operands[1], 0, 0, DImode); |
operands[4] = operand_subword (operands[0], 1, 0, DImode); |
operands[5] = operand_subword (operands[1], 1, 0, DImode);" |
[(set_attr "length" "2,2,2,3")]) |
|
;; Moving double and single precision floating point values |
/openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.c
922,16 → 922,6
else |
abort (); |
} |
else if (GET_CODE (operands[1]) == CONST_INT) |
{ |
if (INTVAL (operands[1]) < 0) |
output_asm_insn ("\tl.addi \t%0, r0, -1", operands); |
else |
output_asm_insn ("\tl.or \t%0, r0, r0", operands); |
output_asm_insn ("\tl.movhi \t%H0, hi(%1)", operands); |
output_asm_insn ("\tl.ori \t%H0, %H0, lo(%1)", operands); |
return ""; |
} |
else |
abort (); |
case MEM: |