OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 52 to Rev 53
    ↔ Reverse comparison
  •

Rev 52 → Rev 53

/trunk/rtl/verilog/aeMB_scon.v
1,4 → 1,4
// $Id: aeMB_scon.v,v 1.3 2007-11-04 05:24:59 sybreon Exp $
// $Id: aeMB_scon.v,v 1.4 2007-11-09 20:51:52 sybreon Exp $
//
// AEMB SYSTEM CONTROL UNIT
//
20,6 → 20,9
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2007/11/04 05:24:59 sybreon
// Fixed spurious interrupt latching during long bus cycles (spotted by J Lee).
//
// Revision 1.2 2007/11/02 19:20:58 sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
34,8 → 37,8
// Outputs
rXCE, grst, gclk, gena,
// Inputs
rOPC, rATOM, rDWBSTB, dwb_ack_i, iwb_ack_i, rMSR_IE, rMSR_BIP,
rBRA, rDLY, sys_clk_i, sys_rst_i, sys_int_i
rOPC, rATOM, rDWBSTB, rFSLSTB, dwb_ack_i, iwb_ack_i, fsl_ack_i,
rMSR_IE, rMSR_BIP, rBRA, rDLY, sys_clk_i, sys_rst_i, sys_int_i
);
 
// INTERNAL
44,8 → 47,11
input [1:0] rATOM;
input rDWBSTB;
input rFSLSTB;
input dwb_ack_i;
input iwb_ack_i;
input iwb_ack_i;
input fsl_ack_i;
input rMSR_IE;
input rMSR_BIP;
56,10 → 62,9
input sys_clk_i, sys_rst_i;
input sys_int_i;
 
assign gclk = sys_clk_i;
assign gena = !((rDWBSTB ^ dwb_ack_i) | !iwb_ack_i);
assign gena = !((rDWBSTB ^ dwb_ack_i) | (rFSLSTB ^ fsl_ack_i) | !iwb_ack_i);
 
// --- INTERRUPT LATCH --------------------------------------
// Debounce and latch onto the positive edge. This is independent
/trunk/rtl/verilog/aeMB_xecu.v
1,4 → 1,4
// $Id: aeMB_xecu.v,v 1.4 2007-11-08 14:17:47 sybreon Exp $
// $Id: aeMB_xecu.v,v 1.5 2007-11-09 20:51:52 sybreon Exp $
//
// AEMB MAIN EXECUTION ALU
//
20,6 → 20,9
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2007/11/08 14:17:47 sybreon
// Parameterised optional components.
//
// Revision 1.3 2007/11/03 08:34:55 sybreon
// Minor code cleanup.
//
35,10 → 38,11
 
module aeMB_xecu (/*AUTOARG*/
// Outputs
dwb_adr_o, dwb_sel_o, rRESULT, rDWBSEL, rMSR_IE, rMSR_BIP,
dwb_adr_o, dwb_sel_o, fsl_adr_o, rRESULT, rDWBSEL, rMSR_IE,
rMSR_BIP,
// Inputs
rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rMXALU, rBRA, rDLY, rALT,
rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY,
rALT, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
);
parameter DW=32;
 
48,6 → 52,9
// DATA WISHBONE
output [DW-1:2] dwb_adr_o;
output [3:0] dwb_sel_o;
 
// FSL WISHBONE
output [14:2] fsl_adr_o;
// INTERNAL
output [31:0] rRESULT;
57,7 → 64,7
input [1:0] rXCE;
input [31:0] rREGA, rREGB;
input [1:0] rMXSRC, rMXTGT;
input [4:0] rRA;
input [4:0] rRA, rRB;
input [2:0] rMXALU;
input rBRA, rDLY;
input [10:0] rALT;
307,17 → 314,27
 
always @(/*AUTOSENSE*/rOPC or wADD)
case (rOPC[1:0])
2'o0: case (wADD[1:0])
2'o0: case (wADD[1:0]) // 8'bit
2'o0: xDWBSEL <= 4'h8;
2'o1: xDWBSEL <= 4'h4;
2'o2: xDWBSEL <= 4'h2;
2'o3: xDWBSEL <= 4'h1;
endcase // case (wADD[1:0])
2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC;
2'o2: xDWBSEL <= 4'hF;
default: xDWBSEL <= 4'hX;
2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit
2'o2: xDWBSEL <= 4'hF; // 32'bit
2'o3: xDWBSEL <= 4'h0; // FSL
endcase // case (rOPC[1:0])
 
// --- FSL WISHBONE --------------------
 
reg [14:2] rFSLADR, xFSLADR;
assign fsl_adr_o = rFSLADR[14:2];
 
always @(/*AUTOSENSE*/rALT or rRB) begin
xFSLADR <= {rALT, rRB[3:2]};
end
// --- SYNC ---
 
always @(posedge gclk)
325,6 → 342,7
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBSEL <= 4'h0;
rFSLADR <= 13'h0;
rMSR_BE <= 1'h0;
rMSR_BIP <= 1'h0;
rMSR_C <= 1'h0;
337,7 → 355,8
rMSR_C <= #1 xMSR_C;
rMSR_IE <= #1 xMSR_IE;
rMSR_BE <= #1 xMSR_BE;
rMSR_BIP <= #1 xMSR_BIP;
rMSR_BIP <= #1 xMSR_BIP;
rFSLADR <= #1 xFSLADR;
end
 
endmodule // aeMB_xecu
/trunk/rtl/verilog/aeMB_ctrl.v
1,4 → 1,4
// $Id: aeMB_ctrl.v,v 1.4 2007-11-08 17:48:14 sybreon Exp $
// $Id: aeMB_ctrl.v,v 1.5 2007-11-09 20:51:52 sybreon Exp $
//
// AEMB CONTROL UNIT
//
20,6 → 20,9
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2007/11/08 17:48:14 sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.3 2007/11/08 14:17:47 sybreon
// Parameterised optional components.
//
35,11 → 38,11
 
module aeMB_ctrl (/*AUTOARG*/
// Outputs
rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,
dwb_wre_o,
rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
// Inputs
rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
dwb_ack_i, iwb_ack_i, gclk, grst, gena
dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
);
// INTERNAL
//output [31:2] rPCLNK;
47,7 → 50,9
output [1:0] rMXSRC, rMXTGT, rMXALT;
output [2:0] rMXALU;
output [4:0] rRW;
output rDWBSTB;
output rDWBSTB;
output rFSLSTB;
input [1:0] rXCE;
input rDLY;
input [15:0] rIMM;
66,6 → 71,11
// INST WISHBONE
input iwb_ack_i;
// FSL WISHBONE
output fsl_stb_o;
output fsl_wre_o;
input fsl_ack_i;
// SYSTEM
input gclk, grst, gena;
 
91,6 → 101,8
wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
wire fLDST = (&rOPC[5:4]);
 
wire fPUT = (rOPC == 6'o33) & rRB[4];
wire fGET = (rOPC == 6'o33) & !rRB[4];
// --- OPERAND SELECTOR ---------------------------------
 
130,14 → 142,6
end
// --- RAM CONTROL ---------------------------------------
 
reg rDWBSTB, xDWBSTB;
reg rDWBWRE, xDWBWRE;
 
assign dwb_stb_o = rDWBSTB;
assign dwb_wre_o = rDWBWRE;
// --- DELAY SLOT REGISTERS ------------------------------
reg [31:2] rPCLNK, xPCLNK;
145,22 → 149,9
reg [4:0] rRW, xRW;
wire fSKIP = (rBRA & !rDLY);
wire fDACK = !(rDWBSTB ^ dwb_ack_i);
always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
if (fSKIP | |rXCE) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xDWBSTB <= 1'h0;
xDWBWRE <= 1'h0;
// End of automatics
end else begin
xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
xDWBWRE <= fSTR & iwb_ack_i;
end
always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
or rRD or rXCE)
always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
or fSTR or rRD or rXCE)
if (fSKIP) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
171,7 → 162,7
case (rXCE)
2'o2: xMXDST <= 2'o1;
default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
(fLOD) ? 2'o2 :
(fLOD | fGET) ? 2'o2 :
(fBRU) ? 2'o1 :
2'o0;
endcase
182,23 → 173,31
endcase
end // else: !if(fSKIP)
 
 
// --- DATA WISHBONE ----------------------------------
 
wire fDACK = !(rDWBSTB ^ dwb_ack_i);
reg rDWBSTB, xDWBSTB;
reg rDWBWRE, xDWBWRE;
 
assign dwb_stb_o = rDWBSTB;
assign dwb_wre_o = rDWBWRE;
// --- PIPELINE CONTROL DELAY ----------------------------
 
always @(posedge gclk)
if (grst) begin
always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
if (fSKIP | |rXCE) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rMXDST <= 2'h0;
rRW <= 5'h0;
xDWBSTB <= 1'h0;
xDWBWRE <= 1'h0;
// End of automatics
end else if (gena) begin
//rPCLNK <= #1 xPCLNK;
rMXDST <= #1 xMXDST;
rRW <= #1 xRW;
end else begin
xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
xDWBWRE <= fSTR & iwb_ack_i;
end
 
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
211,5 → 210,55
rDWBWRE <= #1 xDWBWRE;
end
 
// --- FSL WISHBONE -----------------------------------
 
wire fFACK = !(rFSLSTB ^ fsl_ack_i);
reg rFSLSTB, xFSLSTB;
reg rFSLWRE, xFSLWRE;
 
assign fsl_stb_o = rFSLSTB;
assign fsl_wre_o = rFSLWRE;
 
always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)
if (fSKIP | |rXCE) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xFSLSTB <= 1'h0;
xFSLWRE <= 1'h0;
// End of automatics
end else begin
xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
xFSLWRE <= fPUT & iwb_ack_i;
end
 
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rFSLSTB <= 1'h0;
rFSLWRE <= 1'h0;
// End of automatics
end else if (fFACK) begin
rFSLSTB <= #1 xFSLSTB;
rFSLWRE <= #1 xFSLWRE;
end
// --- PIPELINE CONTROL DELAY ----------------------------
 
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rMXDST <= 2'h0;
rRW <= 5'h0;
// End of automatics
end else if (gena) begin
//rPCLNK <= #1 xPCLNK;
rMXDST <= #1 xMXDST;
rRW <= #1 xRW;
end
 
endmodule // aeMB_ctrl
/trunk/rtl/verilog/aeMB_edk32.v
1,4 → 1,4
// $Id: aeMB_edk32.v,v 1.5 2007-11-08 17:48:14 sybreon Exp $
// $Id: aeMB_edk32.v,v 1.6 2007-11-09 20:51:52 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
20,6 → 20,9
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2007/11/08 17:48:14 sybreon
// Fixed data WISHBONE arbitration problem (reported by J Lee).
//
// Revision 1.4 2007/11/08 14:17:47 sybreon
// Parameterised optional components.
//
38,11 → 41,11
 
module aeMB_edk32 (/*AUTOARG*/
// Outputs
iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
dwb_adr_o,
iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o, fsl_dat_o, fsl_adr_o,
dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
// Inputs
sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
dwb_ack_i
sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
fsl_ack_i, dwb_dat_i, dwb_ack_i
);
// Bus widths
parameter IW = 32; /// Instruction bus address width
59,6 → 62,10
output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v
output dwb_stb_o; // From ctrl of aeMB_ctrl.v
output dwb_wre_o; // From ctrl of aeMB_ctrl.v
output [14:2] fsl_adr_o; // From xecu of aeMB_xecu.v
output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
output fsl_stb_o; // From ctrl of aeMB_ctrl.v
output fsl_wre_o; // From ctrl of aeMB_ctrl.v
output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
output iwb_stb_o; // From ibuf of aeMB_ibuf.v
// End of automatics
66,6 → 73,8
// Beginning of automatic inputs (from unused autoinst inputs)
input dwb_ack_i; // To scon of aeMB_scon.v, ...
input [31:0] dwb_dat_i; // To regf of aeMB_regf.v
input fsl_ack_i; // To scon of aeMB_scon.v, ...
input [31:0] fsl_dat_i; // To regf of aeMB_regf.v
input iwb_ack_i; // To scon of aeMB_scon.v, ...
input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v
input sys_clk_i; // To scon of aeMB_scon.v
84,6 → 93,7
wire [31:0] rDWBDI; // From regf of aeMB_regf.v
wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
wire rDWBSTB; // From ctrl of aeMB_ctrl.v
wire rFSLSTB; // From ctrl of aeMB_ctrl.v
wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
wire rMSR_BIP; // From xecu of aeMB_xecu.v
wire rMSR_IE; // From xecu of aeMB_xecu.v
117,8 → 127,10
.rOPC (rOPC[5:0]),
.rATOM (rATOM[1:0]),
.rDWBSTB (rDWBSTB),
.rFSLSTB (rFSLSTB),
.dwb_ack_i (dwb_ack_i),
.iwb_ack_i (iwb_ack_i),
.fsl_ack_i (fsl_ack_i),
.rMSR_IE (rMSR_IE),
.rMSR_BIP (rMSR_BIP),
.rBRA (rBRA),
157,8 → 169,11
.rMXALU (rMXALU[2:0]),
.rRW (rRW[4:0]),
.rDWBSTB (rDWBSTB),
.rFSLSTB (rFSLSTB),
.dwb_stb_o (dwb_stb_o),
.dwb_wre_o (dwb_wre_o),
.fsl_stb_o (fsl_stb_o),
.fsl_wre_o (fsl_wre_o),
// Inputs
.rXCE (rXCE[1:0]),
.rDLY (rDLY),
173,6 → 188,7
.rMSR_IE (rMSR_IE),
.dwb_ack_i (dwb_ack_i),
.iwb_ack_i (iwb_ack_i),
.fsl_ack_i (fsl_ack_i),
.gclk (gclk),
.grst (grst),
.gena (gena));
206,6 → 222,7
.rREGB (rREGB[31:0]),
.rDWBDI (rDWBDI[31:0]),
.dwb_dat_o (dwb_dat_o[31:0]),
.fsl_dat_o (fsl_dat_o[31:0]),
// Inputs
.rOPC (rOPC[5:0]),
.rRA (rRA[4:0]),
219,6 → 236,7
.rBRA (rBRA),
.rDLY (rDLY),
.dwb_dat_i (dwb_dat_i[31:0]),
.fsl_dat_i (fsl_dat_i[31:0]),
.gclk (gclk),
.grst (grst),
.gena (gena));
228,6 → 246,7
// Outputs
.dwb_adr_o (dwb_adr_o[DW-1:2]),
.dwb_sel_o (dwb_sel_o[3:0]),
.fsl_adr_o (fsl_adr_o[14:2]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
.rMSR_IE (rMSR_IE),
239,6 → 258,7
.rMXSRC (rMXSRC[1:0]),
.rMXTGT (rMXTGT[1:0]),
.rRA (rRA[4:0]),
.rRB (rRB[4:0]),
.rMXALU (rMXALU[2:0]),
.rBRA (rBRA),
.rDLY (rDLY),
/trunk/rtl/verilog/aeMB_regf.v
1,4 → 1,4
// $Id: aeMB_regf.v,v 1.1 2007-11-02 03:25:41 sybreon Exp $
// $Id: aeMB_regf.v,v 1.2 2007-11-09 20:51:52 sybreon Exp $
//
// AEMB REGISTER FILE
//
20,13 → 20,18
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2007/11/02 03:25:41 sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
 
module aeMB_regf (/*AUTOARG*/
// Outputs
rREGA, rREGB, rDWBDI, dwb_dat_o,
rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
// Inputs
rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
rDLY, dwb_dat_i, gclk, grst, gena
rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
);
// INTERNAL
output [31:0] rREGA, rREGB;
42,6 → 47,10
// DATA WISHBONE
output [31:0] dwb_dat_o;
input [31:0] dwb_dat_i;
 
// FSL WISHBONE
output [31:0] fsl_dat_o;
input [31:0] fsl_dat_i;
// SYSTEM
input gclk, grst, gena;
50,10 → 59,12
// Moves the data bytes around depending on the size of the
// operation.
 
wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian
reg [31:0] rDWBDI;
always @(/*AUTOSENSE*/rDWBSEL or wDWBDI)
always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI)
case (rDWBSEL)
// 8'bit
4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
65,6 → 76,8
4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
// 32'bit
4'hF: rDWBDI <= wDWBDI;
// FSL
4'h0: rDWBDI <= wFSLDI;
// Undefined
default: rDWBDI <= 32'hX;
endcase
106,6 → 119,15
// Replicates the data bytes across depending on the size of the
// operation.
 
wire [31:0] xFSL;
wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;
assign fsl_dat_o = rDWBDO;
assign xFSL = (fFFWD_M) ? rDWBDI :
(fFFWD_R) ? rRESULT :
rREGA;
 
wire [31:0] xDST;
wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
116,7 → 138,7
(fDFWD_R) ? rRESULT :
rREGD;
always @(/*AUTOSENSE*/rOPC or xDST)
always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
case (rOPC[1:0])
// 8'bit
2'h0: xDWBDO <= {(4){xDST[7:0]}};
124,7 → 146,9
2'h1: xDWBDO <= {(2){xDST[15:0]}};
// 32'bit
2'h2: xDWBDO <= xDST;
default: xDWBDO <= 32'hX;
// FSL
2'h3: xDWBDO <= xFSL;
//default: xDWBDO <= 32'hX;
endcase // case (rOPC[1:0])
 
always @(posedge gclk)
/trunk/sim/verilog/edk32.v
1,4 → 1,4
// $Id: edk32.v,v 1.4 2007-11-08 14:18:00 sybreon Exp $
// $Id: edk32.v,v 1.5 2007-11-09 20:51:53 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core TEST
//
20,6 → 20,9
// USA
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2007/11/08 14:18:00 sybreon
// Parameterised optional components.
//
// Revision 1.3 2007/11/05 10:59:31 sybreon
// Added random seed for simulation.
//
71,6 → 74,12
 
// FAKE MEMORY ////////////////////////////////////////////////////////
 
wire [14:2] fsl_adr_o;
wire fsl_stb_o;
wire fsl_wre_o;
wire [31:0] fsl_dat_o;
wire [31:0] fsl_dat_i;
wire [15:2] iwb_adr_o;
wire iwb_stb_o;
77,7 → 86,7
wire dwb_stb_o;
reg [31:0] rom [0:65535];
wire [31:0] iwb_dat_i;
reg iwb_ack_i, dwb_ack_i;
reg iwb_ack_i, dwb_ack_i, fsl_ack_i;
 
reg [31:0] ram[0:65535];
wire [31:0] dwb_dat_i;
92,10 → 101,14
assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
assign {dwb_dat_t} = ram[dwb_adr_o];
 
assign fsl_dat_i = fsl_adr_o;
always @(negedge sys_clk_i) begin
iwb_ack_i <= #1 iwb_stb_o;
dwb_ack_i <= #1 dwb_stb_o;
fsl_ack_i <= #1 fsl_stb_o;
iadr <= #1 iwb_adr_o;
dadr <= dwb_adr_o;
215,7 → 228,17
2'o2: $write("BSLLI");
default: $write("XXX");
endcase // case (dut.rALT[10:9])
6'o33: $write("GETPUT");
6'o33: case (dut.rRB[4:2])
3'o0: $write("GET");
3'o4: $write("PUT");
3'o2: $write("NGET");
3'o6: $write("NPUT");
3'o1: $write("CGET");
3'o5: $write("CPUT");
3'o3: $write("NCGET");
3'o7: $write("NCPUT");
endcase // case (dut.rRB[4:2])
 
6'o40: $write("OR");
6'o41: $write("AND");
318,7 → 341,10
if (dut.regf.fRDWE) begin
case (dut.rMXDST)
2'o2: $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
2'o2: begin
if (dut.dwb_stb_o) $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
if (dut.fsl_stb_o) $writeh("R",dut.rRW,"=FSL(h",dut.regf.xWDAT,")");
end
2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");
2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");
endcase // case (dut.rMXDST)
342,6 → 368,14
.dwb_dat_i(dwb_dat_i),
.dwb_wre_o(dwb_we_o),
.dwb_sel_o(dwb_sel_o),
 
.fsl_ack_i(fsl_ack_i),
.fsl_stb_o(fsl_stb_o),
.fsl_adr_o(fsl_adr_o),
.fsl_dat_o(fsl_dat_o),
.fsl_dat_i(fsl_dat_i),
.fsl_wre_o(fsl_we_o),
 
.iwb_adr_o(iwb_adr_o),
.iwb_dat_i(iwb_dat_i),
.iwb_stb_o(iwb_stb_o),
/trunk/sw/c/aeMB_testbench.c
1,5 → 1,5
/*
* $Id: aeMB_testbench.c,v 1.8 2007-11-03 08:40:18 sybreon Exp $
* $Id: aeMB_testbench.c,v 1.9 2007-11-09 20:51:53 sybreon Exp $
*
* AEMB Function Verification C Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
25,6 → 25,9
*
* HISTORY
* $Log: not supported by cvs2svn $
* Revision 1.8 2007/11/03 08:40:18 sybreon
* Minor code cleanup.
*
* Revision 1.7 2007/11/02 18:32:19 sybreon
* Enable MSR_IE with software.
*
264,7 → 267,30
return 0;
}
 
 
/**
FSL TEST ROUTINE
*/
 
int fsl_test ()
{
// TEST FSL1 ONLY
int FSL = 0xCAFEF00D;
 
asm ("PUT %0, RFSL1" :: "r"(FSL));
asm ("GET %0, RFSL1" : "=r"(FSL));
if (FSL != 0x04) return -1;
asm ("PUT %0, RFSL31" :: "r"(FSL));
asm ("GET %0, RFSL31" : "=r"(FSL));
if (FSL != 0x7C) return -1;
return 0;
}
 
/**
MAIN TEST PROGRAMME
 
This is the main test procedure. It will output signals onto the
280,6 → 306,9
// Number of each test to run
int max = 10;
 
// FSL TEST
if (fsl_test() == -1) { *mpi = 0x4641494C; }
 
// Enable Global Interrupts
int_enable();
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.