URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
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- from Rev 53 to Rev 54
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Rev 53 → Rev 54
/trunk/bench/verilog/pci_testbench_defines.v
65,8 → 65,8
//=================================================================================== |
|
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation |
`define Tsetup 0.5 |
`define Thold 0.5 |
`define Tsetup 3 |
`define Thold 1 |
|
// how many clock cycles should model wait for design's response - integer 32 bit value |
`define WAIT_FOR_RESPONSE 6 |