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URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

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Rev 53 → Rev 54

/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.7 2003-05-07 09:45:28 rherveille Exp $
// $Id: test_bench_top.v,v 1.8 2003-05-07 14:39:19 rherveille Exp $
//
// $Date: 2003-05-07 09:45:28 $
// $Revision: 1.7 $
// $Date: 2003-05-07 14:39:19 $
// $Revision: 1.8 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/05/07 09:45:28 rherveille
// Numerous updates and added checks
//
// Revision 1.6 2003/03/19 17:22:19 rherveille
// Added WISHBONE revB.3 sanity checks
//
204,8 → 207,12
// reg_test;
// tim_test;
 
pd1_test;
pd2_test;
// pd1_test;
// pd2_test;
`ifdef VGA_12BIT_DVI
dvi_pd_test;
`endif
 
// ur_test;
end
/trunk/bench/verilog/tests.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tests.v,v 1.7 2003-05-07 09:45:28 rherveille Exp $
// $Id: tests.v,v 1.8 2003-05-07 14:39:19 rherveille Exp $
//
// $Date: 2003-05-07 09:45:28 $
// $Revision: 1.7 $
// $Date: 2003-05-07 14:39:19 $
// $Revision: 1.8 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/05/07 09:45:28 rherveille
// Numerous updates and added checks
//
// Revision 1.6 2003/03/19 12:20:53 rherveille
// Changed timing section in VGA core, changed testbench accordingly.
// Fixed bug in 'timing check' test.
1056,26 → 1059,6
 
cbar = 32'h0000_0800;
 
thsync = 0;
thgdel = 0;
thgate = 340;
thlen = 345;
 
tvsync = 0;
tvgdel = 0;
tvgate = 240;
tvlen = 245;
 
thsync = 39;
thgdel = 124;
thgate = 646;
thlen = 832;
 
tvsync = 2;
tvgdel = 25;
tvgate = 484;
tvlen = 520;
 
thsync = 6;
thgdel = 20;
thgate = 319;
1086,29 → 1069,6
tvgate = 239;
tvlen = 280;
 
/*
thsync = 0;
thgdel = 0;
thgate = 63;
thlen = 70;
 
tvsync = 0;
tvgdel = 0;
tvgate = 32;
tvlen = 36;
 
thsync = 119;
thgdel = 61;
thgate = 805;
thlen = 1038;
 
tvsync = 5;
tvgdel = 20;
tvgate = 600;
tvlen = 665;
 
*/
 
hpol = 0;
vpol = 0;
cpol = 0;
1202,108 → 1162,367
endtask
 
 
//////////////////////////////////////
//
// DVI test section
//
 
 
task dvi_pd_test;
 
integer mode;
integer n, p, l;
reg [ 2:0] dvi_odf;
reg [31:0] pn;
reg [31:0] pra, paa, tmp;
reg [23:0] pd;
reg [11:0] pda, pdb;
reg [ 1:0] cd;
reg pc;
reg [31:0] data;
reg [31:0] cbar;
reg [ 7:0] vbl;
reg [ 5:0] delay;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** DVI Pixel Data Test ***");
$display("*****************************************************\n");
 
m0.wb_wr1( `VBARA, 4'hf, 0 );
m0.wb_wr1( `VBARB, 4'hf, 123456 );
 
cbar = 32'h0000_0800;
 
thsync = 0;
thgdel = 0;
thgate = 320;
thlen = 345;
 
tvsync = 0;
tvgdel = 0;
tvgate = 240;
tvlen = 245;
 
thsync = 39;
thgdel = 124;
thgate = 646;
thlen = 832;
 
tvsync = 2;
tvgdel = 25;
tvgate = 484;
tvlen = 520;
 
thsync = 6;
thgdel = 20;
thgate = 319;
thlen = 390;
 
tvsync = 1;
tvgdel = 8;
tvgate = 239;
tvlen = 280;
 
hpol = 0;
vpol = 0;
cpol = 0;
bpol = 0;
 
m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
// Choose mode, vbl, and delay
// These should have been tested & verified by previous tests
mode = 3;
vbl = 4;
delay = 0;
s0.set_delay(delay);
 
for(dvi_odf=0; dvi_odf<4;dvi_odf=dvi_odf +1)
begin
// -------------------------------
// Turn Off VGA before Mode Change
 
m0.wb_wr1( `CTRL, 4'hf, {
2'h0, // Reserved
dvi_odf[1:0],
12'h0, // Reserved
bpol,
cpol,
vpol,
hpol,
pc, // PC
cd, // CD
2'h0, // VBL
1'b0, // CBSWE
1'b0, // VBSWE
1'b0, // CBSIE
1'b0, // VBSIE
1'b0, // HIE
1'b0, // VIE
1'b0 // Video Enable
});
 
s0.fill_mem(1);
 
`ifdef USE_VC
// Fill internal Color Lookup Table
repeat(10) @(posedge clk);
for(n=0;n<512;n=n+1)
begin
//m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
data = s0.mem[ cbar[31:2] + n];
m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
end
repeat(10) @(posedge clk);
`endif
 
case(mode)
0:
begin
cd = 2'h2;
pc = 1'b0;
end
1:
begin
cd = 2'h0;
pc = 1'b0;
end
2:
begin
cd = 2'h0;
pc = 1'b1;
end
3:
begin
cd = 2'h1;
pc = 1'b0;
end
endcase
 
//repeat(50) @(posedge clk);
 
// -------------------------------
// Turn VGA back On ...
m0.wb_wr1( `CTRL, 4'hf, {
2'h0, // Reserved
dvi_odf[1:0],
12'h0, // Reserved
bpol,
cpol,
vpol,
hpol,
pc, // PC
cd, // CD
2'h0, // VBL
1'b0, // CBSWE
1'b0, // VBSWE
1'b0, // CBSIE
1'b0, // VBSIE
1'b0, // HIE
1'b0, // VIE
1'b1 // Video Enable
});
 
$display("DVI output data format: %0h", dvi_odf);
repeat(2) @(posedge vsync);
 
// For Each Line
for(l=0;l<tvgate;l=l+1)
// For each Pixel
for(p=0;p<thgate+1;p=p+1)
begin
while(~dvi_de_o) @(pclk); // wait for viewable data
 
//$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
// Depending on Mode, determine pixel data
// pixel number = line * (thgate + 1) + p
pn = l * (thgate + 1) + p;
 
//
// Get the correct pixel data
case(mode)
0: // 24 bit/pixel mode
begin
pra = pn[31:2] * 3; // Pixel relative Address
paa = pra + 0; // Pixel Absolute Address
 
// Pixel Data
case(pn[1:0])
0:
begin
tmp = s0.mem[paa];
pd = tmp[31:8];
end
1:
begin
tmp = s0.mem[paa];
pd[23:16] = tmp[7:0];
tmp = s0.mem[paa+1];
pd[15:0] = tmp[31:16];
end
2:
begin
tmp = s0.mem[paa+1];
pd[23:8] = tmp[15:0];
tmp = s0.mem[paa+2];
pd[7:0] = tmp[31:24];
end
3:
begin
tmp = s0.mem[paa+2];
pd = tmp[23:0];
end
endcase
end
 
1: // 8 bit/pixel grayscale mode
begin
pra = pn[31:2]; // Pixel relative Address
paa = pra + 0; // Pixel Absolute Address
case(pn[1:0])
0:
begin
tmp = s0.mem[paa];
pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
end
1:
begin
tmp = s0.mem[paa];
pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
end
2:
begin
tmp = s0.mem[paa];
pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
end
3:
begin
tmp = s0.mem[paa];
pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
end
endcase
end
 
2: // 8 bit/pixel Pseudo Color mode
begin
pra = pn[31:2]; // Pixel relative Address
paa = pra + 0; // Pixel Absolute Address
case(pn[1:0])
0:
begin
tmp = s0.mem[paa];
tmp = s0.mem[cbar[31:2] + tmp[31:24]];
pd = tmp[23:0];
end
1:
begin
tmp = s0.mem[paa];
tmp = s0.mem[cbar[31:2] + tmp[23:16]];
pd = tmp[23:0];
end
2:
begin
tmp = s0.mem[paa];
tmp = s0.mem[cbar[31:2] + tmp[15:8]];
pd = tmp[23:0];
end
3:
begin
tmp = s0.mem[paa];
tmp = s0.mem[cbar[31:2] + tmp[7:0]];
pd = tmp[23:0];
end
endcase
end
 
3: // 16 bit/pixel mode
begin
pra = pn[31:1]; // Pixel relative Address
paa = pra + 0; // Pixel Absolute Address
case(pn[0])
0:
begin
tmp = s0.mem[paa];
tmp[15:0] = tmp[31:16];
pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
end
1:
begin
tmp = s0.mem[paa];
pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
end
endcase
end
 
endcase
 
//
// convert pixel data in DVI output format
case (dvi_odf)
2'b00:
begin
pda = pd[11:0];
pdb = pd[23:12];
end
 
2'b01:
begin
pda = {pd[12:10],pd[7:3],pd[8],pd[2:0]};
pdb = {pd[23:19],pd[15:13],pd[18:16],pd[9]};
end
 
2'b10:
begin
pda = {pd[12:10],pd[7:3],4'h0};
pdb = {pd[23:19],pd[15:13],4'h0};
end
 
2'b11:
begin
pda = {pd[13:11],pd[7:3],4'h0};
pdb = {1'b0,pd[23:19],pd[15:14],4'h0};
end
endcase
 
//
// verify pixel data
 
// rising edge data
if (pda !== dvi_d_o)
begin
$display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h",
pda, dvi_d_o);
$display(" pixel=%0d, line=%0d, (%0t)",p,l,$time);
error_cnt = error_cnt + 1;
if(error_cnt > 10) $stop;
end
 
@(dvi_pclk_p_o);
 
// falling edge data
if (pdb !== dvi_d_o)
begin
$display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h",
pdb, dvi_d_o);
$display(" pixel=%0d, line=%0d, (%0t)",p,l,$time);
error_cnt = error_cnt + 1;
if(error_cnt > 10) $stop;
end
 
@(dvi_pclk_p_o);
end
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
end
endtask

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