OpenCores
URL https://opencores.org/ocsvn/bluespec-h264/bluespec-h264/trunk

Subversion Repositories bluespec-h264

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 54 to Rev 55
    ↔ Reverse comparison
  •

Rev 54 → Rev 55

/trunk/enc-pwr/par.tcl
0,0 → 1,152
#=========================================================================
# Command file for place/route using cadence encounter
#-------------------------------------------------------------------------
# $Id: par.tcl,v 1.1 2008-06-26 18:01:02 jamey.hicks Exp $
#
# This file specifies commands which encounter will execute when
# performing place and route for your design.
 
#------------------------------------------------------------
# Setup
#------------------------------------------------------------
 
source make_generated_vars.tcl
 
# Read in the config file which also reads in the synthesized design
source par.conf
commitConfig
 
# Load the floorplan if it exists
if {${FLOORPLAN} != ""} {
loadFPlan ${FLOORPLAN}
}
 
generateTracks
 
# Connect all the power and ground pins
# Note that these aren't specified in the verilog
globalNetConnect VDD -type pgpin -pin VDD -inst *
globalNetConnect VSS -type pgpin -pin VSS -inst *
 
checkDesign -io -physicalLibrary -timingLibrary
 
clearClockDomains
setClockDomains -all
 
#------------------------------------------------------------
# Placement
#------------------------------------------------------------
 
# This does the actual placement
amoebaPlace -timingdriven
 
# Optimize the placement
setOptMode -reclaimArea
setOptMode -highEffort
optDesign -preCTS
 
#------------------------------------------------------------
# Clock tree synthesis
#------------------------------------------------------------
 
setCTSMode \
-topPreferredLayer 6 \
-bottomPreferredLayer 5 \
-noUseLibMaxFanout \
-addClockRootProp \
-useCTSRouteGuide
 
createClockTreeSpec \
-bufferList inv0d0 inv0d1 inv0d2 inv0d4 inv0d7 inv0da \
buffd1 buffd2 buffd3 buffd4 buffd7 buffda \
bufbd1 bufbd2 bufbd3 bufbd4 bufbd7 bufbda bufbdf bufbdk \
invbd2 invbd4 invbd7 invbda invbdf invbdk \
-output par.ctstch \
-routeClkNet
 
specifyClockTree -clkfile par.ctstch
ckSynthesis -rguide par_clk.rguide
 
# The clock router sometimes (incorrectly) routes M2 over pins,
# causing violations this allows those routes to be moved later
changeUseClockNetStatus -noFixedNetWires
 
# Save design for debugging
saveDesign postclksynth -netlist -tcon -rc
 
#------------------------------------------------------------
# preroute reports
#------------------------------------------------------------
 
trialRoute -guide par_clk.rguide
 
setAnalysisMode -setup -async -skew -clockTree
buildTimingGraph
reportSlacks -setup -outfile preroute_setup_slacks.rpt
reportViolation -outfile preroute_setup_timing.rpt -num 200 -plusNonViolating
reportMostCritPath -outfile preroute_critpath.rpt
 
setAnalysisMode -hold -async -skew -clockTree
buildTimingGraph
reportSlacks -hold -outfile preroute_hold_slacks.rpt
reportViolation -outfile preroute_hold_timing.rpt -num 200 -plusNonViolating
 
reportGateCount -level 5 -limit 100 -stdCellOnly -outfile preroute_area.rpt
reportWire preroute_wire.rpt
 
saveDesign preroute -netlist -tcon -rc
 
#------------------------------------------------------------
# Routing
#------------------------------------------------------------
 
# Add filler/feedthrough cells
addFiller -cell feedth feedth3 feedth9 -prefix feedth
 
# Wire up cells to power network
sroute -noStripes -noPadRings -jogControl { preferWithChanges differentLayer }
 
# Do signal routing
setNanoRouteMode -drouteFixAntenna true
setNanoRouteMode -routeInsertAntennaDiode false
setNanoRouteMode -timingEngine CTE
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeWithEco false
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeTdrEffort 0
setNanoRouteMode -routeSiEffort low
setNanoRouteMode -siNoiseCTotalThreshold 0.050000
setNanoRouteMode -siNoiseCouplingCapThreshold 0.005000
setNanoRouteMode -routeWithSiPostRouteFix false
setNanoRouteMode -drouteAutoStop true
setNanoRouteMode -routeSelectedNetOnly false
setNanoRouteMode -envNumberProcessor 1
setNanoRouteMode -drouteOptimizeUseMultiCutVia true
globalDetailRoute
 
delayCal -sdf postroute.sdf
 
#------------------------------------------------------------
# postroute reports
#------------------------------------------------------------
 
extractRC -outfile par.cap
 
setAnalysisMode -setup -async -skew -clockTree
buildTimingGraph
reportSlacks -setup -outfile postroute_setup_slacks.rpt
reportViolation -outfile postroute_setup_timing.rpt -num 200 -plusNonViolating
reportMostCritPath -outfile postroute_critpath.rpt
 
setAnalysisMode -hold -async -skew -clockTree
buildTimingGraph
reportSlacks -hold -outfile postroute_hold_slacks.rpt
reportViolation -outfile postroute_hold_timing.rpt -num 200 -plusNonViolating
 
reportGateCount -level 5 -limit 100 -stdCellOnly -outfile postroute_area.rpt
reportWire postroute_wire.rpt
 
saveDesign postroute -netlist -tcon -rc
saveNetlist par.v
 
exit
/trunk/enc-pwr/par.conf
0,0 → 1,81
#=========================================================================
# Command file for place/route using cadence encounter
#-------------------------------------------------------------------------
# $Id: par.conf,v 1.1 2008-06-26 18:01:02 jamey.hicks Exp $
#
# This file specifies setup information for encounter.
#
 
global rda_Input
set rda_Input(import_mode) { -treatUndefinedCellAsBbox 0 -keepEmptyModule 1 }
set rda_Input(ui_netlist) ${VERILOG_SRC}
set rda_Input(ui_netlisttype) {Verilog}
set rda_Input(ui_ilmlist) {}
set rda_Input(ui_ilmspef) {}
set rda_Input(ui_settop) {1}
set rda_Input(ui_topcell) ${VERILOG_TOPLEVEL}
set rda_Input(ui_celllib) {}
set rda_Input(ui_iolib) {}
set rda_Input(ui_areaiolib) {}
set rda_Input(ui_blklib) {}
set rda_Input(ui_kboxlib) {}
set rda_Input(ui_gds_file) {}
set rda_Input(ui_timelib,min) ${TIMELIBS_MIN}
set rda_Input(ui_timelib,max) ${TIMELIBS_MAX}
set rda_Input(ui_timelib) ${TIMELIBS_TYP}
set rda_Input(ui_smodDef) {}
set rda_Input(ui_smodData) {}
set rda_Input(ui_dpath) {}
set rda_Input(ui_tech_file) {}
set rda_Input(ui_io_file) {}
set rda_Input(ui_timingcon_file) { par.sdc }
set rda_Input(ui_buf_footprint) {buffd1}
set rda_Input(ui_delay_footprint) {dl01d1}
set rda_Input(ui_inv_footprint) {inv0d1}
set rda_Input(ui_latency_file) {}
set rda_Input(ui_scheduling_file) {}
set rda_Input(ui_leffile) ${LEF_FILES}
set rda_Input(ui_core_cntl) {aspect}
set rda_Input(ui_aspect_ratio) {1.0}
set rda_Input(ui_core_util) {0.6}
set rda_Input(ui_core_height) {}
set rda_Input(ui_core_width) {}
set rda_Input(ui_core_to_left) {20.16}
set rda_Input(ui_core_to_right) {20.16}
set rda_Input(ui_core_to_top) {22.4}
set rda_Input(ui_core_to_bottom) {22.4}
set rda_Input(ui_max_io_height) {0}
set rda_Input(ui_row_height) {5.6}
set rda_Input(ui_isHorTrackHalfPitch) {0}
set rda_Input(ui_isVerTrackHalfPitch) {1}
set rda_Input(ui_ioOri) {R0}
set rda_Input(ui_isOrigCenter) {0}
set rda_Input(ui_exc_net) {}
set rda_Input(ui_delay_limit) {1000}
set rda_Input(ui_net_delay) {1000.0ps}
set rda_Input(ui_net_load) {0.5pf}
set rda_Input(ui_in_tran_delay) {0.07ps}
set rda_Input(ui_captbl_file) {}
set rda_Input(ui_defcap_scale) {1.0}
set rda_Input(ui_detcap_scale) {1.0}
set rda_Input(ui_xcap_scale) {1.0}
set rda_Input(ui_res_scale) {1.0}
set rda_Input(ui_shr_scale) {1.0}
set rda_Input(ui_time_unit) {none}
set rda_Input(ui_cap_unit) {}
set rda_Input(ui_oa_reflib) {}
set rda_Input(ui_oa_abstractname) {}
set rda_Input(ui_oa_layoutname) {}
set rda_Input(ui_sigstormlib) {}
set rda_Input(ui_cdb_file) {}
set rda_Input(ui_echo_file) {}
set rda_Input(ui_xilm_file) {}
set rda_Input(ui_qxtech_file) {}
set rda_Input(ui_qxlib_file) {}
set rda_Input(ui_qxconf_file) {}
set rda_Input(ui_pwrnet) {VDD}
set rda_Input(ui_gndnet) {VSS}
set rda_Input(flip_first) {1}
set rda_Input(double_back) {1}
set rda_Input(assign_buffer) {1}
set rda_Input(ui_gen_footprint) {1}
/trunk/enc-pwr/par.sdc
0,0 → 1,31
#=========================================================================
# Constraints file
#-------------------------------------------------------------------------
# $Id: par.sdc,v 1.1 2008-06-26 18:01:02 jamey.hicks Exp $
#
# This file contains various constraints for your chip including the
# target clock period, the capacitive load of output pins, and any
# input/output delay constraints.
#
 
# This constraint sets the target clock period for the chip in
# nanoseconds. Note that the first parameter is the name of the clock
# signal in your verlog design. If you called it something different than
# clk you will need to change this. You should set this constraint
# carefully. If the period is unrealistically small then the tools will
# spend forever trying to meet timing and ultimately fail. If the period
# is too large the tools will have no trouble but you will get a very
# conservative implementation.
 
create_clock CLK -name ideal_clock1 -period 10.0
 
# This constrainst sets the load capacitance in picofarads of the
# output pins of your design. 4fF is reasonable if your design is
# driving another block of on-chip logic.
 
set_load -pin_load 0.004 [all_outputs]
 
# Encounter doesn't seem to have its own way to specify dont_touch
# so we must do it in the SDC file
 
 
/trunk/enc-pwr/Makefile
0,0 → 1,91
#=======================================================================
# 6.375 Makefile for enc-par
#-----------------------------------------------------------------------
# $Id: Makefile,v 1.1 2008-06-26 18:01:02 jamey.hicks Exp $
#
# This makefile will use Cadence Encounter to place and route
# a gate-level verilog netlist.
#
 
default : all
 
basedir = ../..
 
#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------
 
vsrcs = ../dc/current/synthesized.v
 
# Specify what the toplevel verilog module is
 
toplevel = mkH264
 
# Specify the floorplan if it exists.
 
#floorplan = ../enc-fp/current/floorplan.fp
 
#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------
 
build_suffix := $(shell date +%Y-%m-%d_%H-%M)
build_dir := build-$(build_suffix)
curr_build_dir := current
curr_build_dir_tstamp := current/timestamp.txt
par_verilog := $(curr_build_dir)/par.v
vsrc_unique := synthesized_unique.v
 
par_conf := par.conf
par_tcl := par.tcl
par_sdc := par.sdc
scripts := $(par_conf) $(par_tcl) $(par_sdc)
makegen_tcl := make_generated_vars.tcl
 
libdir = $(MIT6375_HOME)/libs/tsl180/tsl18fs120
par_vars = \
set VERILOG_SRC { $(vsrc_unique) }; \
set VERILOG_TOPLEVEL $(toplevel); \
set FLOORPLAN "$(addprefix ../, $(floorplan))"; \
set TIMELIBS_MAX { $(libdir)/lib/tsl18fs120_max.lib }; \
set TIMELIBS_MIN { $(libdir)/lib/tsl18fs120_min.lib }; \
set TIMELIBS_TYP { $(libdir)/lib/tsl18fs120_typ.lib }; \
set LEF_FILES { $(libdir)/lef/tsl18_6lm.lef $(libdir)/lef/tsl18fs120.lef }; \
 
define new-build-dir-cmds
mkdir $(build_dir)
rm -f $(curr_build_dir)
ln -s $(build_dir) $(curr_build_dir)
cp $(scripts) $(curr_build_dir)
echo '$(par_vars)' > $(curr_build_dir)/$(makegen_tcl)
endef
 
new-build-dir :
$(new-build-dir-cmds)
 
$(par_verilog) : $(vsrcs) $(floorplan) $(scripts)
$(new-build-dir-cmds)
cd $(curr_build_dir); \
uniquifyNetlist -top $(toplevel) $(vsrc_unique) $(addprefix ../, $(vsrcs)); \
encounter -nowin -init $(par_tcl) | tee enc.log; \
cd ..
 
par : $(par_verilog)
 
junk +=
 
.PHONY : par new-build-dir
 
#--------------------------------------------------------------------
# Default make target
#--------------------------------------------------------------------
 
all : par
 
#--------------------------------------------------------------------
# Clean up
#--------------------------------------------------------------------
 
clean :
rm -rf build-[0-9][0-9][0-9][0-9]-[0-9][0-9]-[0-9][0-9]_[0-9][0-9]-[0-9][0-9] \
current $(junk) *~ \#*

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.