URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- from Rev 54 to Rev 55
- ↔ Reverse comparison
Rev 54 → Rev 55
/trunk/or1ksim/support/dumpverilog.h
0,0 → 1,41
#define DW 32 /* Data width of memory model generated by dumpverilog in bits */ |
#define DWQ (DW/8) /* Same as DW but units are bytes */ |
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#define OR1K_MEM_VERILOG_HEADER(MODNAME, FROMADDR, TOADDR) "\n\ |
`include \"general.h\"\n\n\ |
`timescale 1ns/100ps\n\n\ |
// Simple dw-wide Sync SRAM with initial content generated by or1ksim.\n\ |
// All control, data in and addr signals are sampled at rising clock edge \n\ |
// Data out is not registered. Address bits specify dw-word (narrowest \n\ |
// addressed data is not byte but dw-word !). \n |
// There are still some bugs in generated output (dump word aligned regions)\n\n\ |
module %s(clk, data, addr, ce, we);\n\n\ |
parameter dw = 32;\n\ |
parameter amin = %d;\n\n\ |
parameter amax = %d;\n\n\ |
input clk;\n\ |
inout [dw-1:0] data;\n\ |
input [31:0] addr;\n\ |
input ce;\n\ |
input we;\n\n\ |
reg [dw-1:0] mem [amax:amin];\n\ |
reg [199:0] dis [amax:amin];\n\ |
reg [dw-1:0] dataout;\n\ |
tri [dw-1:0] data = (ce && ~we) ? dataout : 'bz;\n\n\ |
initial begin\n", MODNAME, FROMADDR, TOADDR |
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#define OR1K_MEM_VERILOG_FOOTER "\n\ |
end\n\n\ |
always @(posedge clk) begin\n\ |
if (ce && ~we) begin\n\ |
dataout = #1 mem[addr];\n\ |
$display(\"or1k_mem: reading mem[%%0d]:%%h dis: %%0s\", addr, dataout, dis[addr]);\n\ |
end else\n\ |
if (ce && we) begin\n\ |
mem[addr] = data;\n\ |
dis[addr] = \"(data)\";\n\ |
$display(\"or1k_mem: writing mem[%%0d]:%%h dis: %%0s\", addr, mem[addr], dis[addr]);\n\ |
end\n\ |
end\n\n\ |
endmodule\n" |
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/trunk/or1ksim/support/dumpverilog.c
0,0 → 1,97
/* dumpverilog.c -- Dumps memory region as Verilog representation |
Copyright (C) 2000 Damjan Lampret, lampret@opencores.org |
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This file is part of OpenRISC 1000 Architectural Simulator. |
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This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
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You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
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/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */ |
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#include <stdio.h> |
#include <ctype.h> |
#include <string.h> |
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#include "config.h" |
#include "sim-config.h" |
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#include "parse.h" |
#include "abstract.h" |
#include "arch.h" |
#include "trace.h" |
#include "execute.h" |
#include "sprs.h" |
#include "stats.h" |
#include "except.h" |
#include "dumpverilog.h" |
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extern struct mem_entry mem[MEMORY_LEN]; |
extern char rcsrev[]; |
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void dumpverilog(char *verilog_modname, unsigned int from, unsigned int to) |
{ |
unsigned int i, done = 0; |
struct label_entry *tmp; |
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printf("// This file was generated by or1ksim %s\n", rcsrev); |
printf(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ)); |
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for(i = from; i < to && i < (MEMORY_START + MEMORY_LEN); i++) { |
if (mem[i].insn) { |
tmp = mem[i].label; |
for(; tmp; tmp = tmp->next) |
printf("\n//\t%s%s", tmp->name, LABELEND_CHAR); |
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printf("\n\tmem['h%x] = %d'h%.2x%.2x", i/DWQ, DW, mem[i].data, mem[i+1].data); |
printf("%.2x%.2x;", mem[i+2].data, mem[i+3].data); |
if (mem[i].insn) |
printf("\n\tdis['h%x] = {\"%s\t%s\"", i/DWQ, mem[i].insn->insn, mem[i].insn->op1); |
if (strlen(mem[i].insn->op2)) |
printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op2); |
if (strlen(mem[i].insn->op3)) |
printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op3); |
if (strlen(mem[i].insn->op4)) |
printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op4); |
printf("};"); |
i += (insn_len(mem[i].insn->insn) - 1); |
} else |
{ |
if (i % 64 == 0) |
printf("\n"); |
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printf("\n\tmem['h%x] = 'h%.2x;", i/DWQ, (unsigned char)mem[i].data); |
} |
done = 1; |
} |
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if (done) { |
printf(OR1K_MEM_VERILOG_FOOTER); |
return; |
} |
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/* this needs to be fixed */ |
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for(i = from; i < to; i++) { |
if (i % 8 == 0) |
printf("\n%.8x: ", i); |
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/* don't print ascii chars below 0x20. */ |
if (eval_mem32(i) < 0x20) |
printf("0x%.2x ", (unsigned char)eval_mem32(i)); |
else |
printf("0x%.2x'%c' ", (unsigned char)eval_mem32(i), (unsigned char)eval_mem32(i)); |
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} |
printf(OR1K_MEM_VERILOG_FOOTER); |
} |