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https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/
- from Rev 542 to Rev 543
- ↔ Reverse comparison
Rev 542 → Rev 543
/openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_bit_ctrl.v
193,6 → 193,14
// state machine variable |
reg [17:0] c_state; // synopsys enum_state |
reg [4:0] slave_state; |
// A counter to indicate a too-long wait has occurred for the next set |
// of clocks for the read, and in fact it's likely the master has simply |
// released SCL and wants to issue a stop. |
reg [3:0] slave_read_timeout_cnt; |
wire slave_read_timeout; |
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// |
// module body |
// |
202,11 → 210,15
always @(posedge clk) |
dscl_oen <= scl_oen; |
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// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low |
// slave_wait is asserted when master wants to drive SCL high, but the |
// slave pulls it low. |
// slave_wait remains asserted until the slave releases SCL |
always @(posedge clk or negedge nReset) |
if (!nReset) slave_wait <= 1'b0; |
else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL); |
if (!nReset) |
slave_wait <= 1'b0; |
else |
slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | |
(slave_wait & ~sSCL) ; |
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// master drives SCL high, but another master pulls it low |
// master start counting down its low cycle now (clock synchronization) |
236,7 → 248,6
clk_en <= 1'b0; |
end |
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// generate bus status controller |
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// capture SDA and SCL |
630,9 → 641,7
slave_act <= 1'b0; |
end |
end |
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parameter [4:0] slave_idle = 5'b0_0000; |
parameter [4:0] slave_wr = 5'b0_0001; |
parameter [4:0] slave_wr_a = 5'b0_0010; |
640,8 → 649,22
parameter [4:0] slave_rd_a = 5'b0_1000; |
parameter [4:0] slave_wait_next_cmd_1 = 5'b1_0000; |
parameter [4:0] slave_wait_next_cmd_2 = 5'b1_0001; |
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// Slave timeout counter during read |
always @(posedge clk or negedge nReset) |
if (~nReset) |
slave_read_timeout_cnt <= 0; |
else if (rst) |
slave_read_timeout_cnt <= 0; |
else if (slave_state==slave_wr) |
slave_read_timeout_cnt <= 0; |
else if (slave_state==slave_wr_a && sSCL && cnt==1) |
slave_read_timeout_cnt <= slave_read_timeout_cnt + 1; |
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assign slave_read_timeout = (&slave_read_timeout_cnt) & cnt==1; |
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always @(posedge clk or negedge nReset) |
if (!nReset) |
begin |
slave_state <= slave_idle; |
694,6 → 717,11
if (~sSCL & dSCL) begin //SCL FALLING EDGE |
cmd_slave_ack <= 1'b1; |
slave_state <= slave_wait_next_cmd_1; |
end |
// Timeout! Go back to idle, release SDA |
else if(slave_read_timeout) begin |
slave_state <= slave_idle; |
sda_oen_slave <= 1; |
end |
end |
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