URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 55 to Rev 56
- ↔ Reverse comparison
Rev 55 → Rev 56
/trunk/sim/rtl_sim/oc8051_eax.in
0,0 → 1,8
/// |
/// input for external access (ea signal) |
/// |
/// ea=0 program is in external rom |
/// ea=1 program is in internal rom |
/// |
/// |
|
/trunk/sim/rtl_sim/oc8051_eai.in
0,0 → 1,8
/// |
/// input for external access (ea signal) |
/// |
/// ea=0 program is in external rom |
/// ea=1 program is in internal rom |
/// |
/// |
1 |
/trunk/sim/rtl_sim/src/verilog/oc8051_xrom.v
0,0 → 1,99
////////////////////////////////////////////////////////////////////// |
//// //// |
//// 8051 exteranl program rom //// |
//// //// |
//// This file is part of the 8051 cores project //// |
//// http://www.opencores.org/cores/8051/ //// |
//// //// |
//// Description //// |
//// external program rom for 8051 core //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Simon Teran, simont@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// |
|
module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o); |
|
parameter DELAY=5; |
|
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input rst, clk, stb_i, cyc_i; |
input [15:0] addr; |
output ack_o; |
output [31:0] data; |
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reg ack_o; |
reg [31:0] data; |
reg [7:0] buff [65535:0]; |
reg [2:0] cnt; |
integer i; |
|
|
initial |
begin |
for (i=0; i<65536; i=i+1) |
buff [i] = 8'h00; |
$readmemh("../../../asm/in/oc8051_xrom.in", buff); |
end |
|
always @(posedge clk or posedge rst) |
begin |
if (rst) begin |
data <= #1 31'h0; |
ack_o <= #1 1'b0; |
end else if (stb_i && ((DELAY==3'b000) || (cnt==3'b000))) begin |
data <= #1 {buff [addr], buff[addr+1], buff[addr+2], buff[addr+3]}; |
ack_o <= #1 1'b1; |
end else |
ack_o <= #1 1'b0; |
end |
|
always @(posedge clk or posedge rst) |
begin |
if (rst) |
cnt <= #1 DELAY; |
else if (cnt == 3'b000) |
cnt <= #1 DELAY; |
else if (stb_i) |
cnt <= #1 cnt - 3'b001; |
else cnt <= #1 DELAY; |
end |
|
|
endmodule |
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trunk/sim/rtl_sim/src/verilog/oc8051_xrom.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/sim/rtl_sim/oc8051_ea.in
===================================================================
--- trunk/sim/rtl_sim/oc8051_ea.in (nonexistent)
+++ trunk/sim/rtl_sim/oc8051_ea.in (revision 56)
@@ -0,0 +1,8 @@
+///
+/// input for external access (ea signal)
+///
+/// ea=0 program is in external rom
+/// ea=1 program is in internal rom
+///
+///
+0