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Rev 55 → Rev 56

/ft816float/trunk/rtl/verilog2/BCDMath.v
503,3 → 503,36
endgenerate
 
endmodule
 
// Perform a logical shift to the right.
module BCDSRL(ci, i, o, co);
parameter N=4;
input ci;
input [N*4-1:0] i;
output reg [N*4-1:0] o;
output co;
 
reg [N:0] c;
 
genvar g;
generate begin
always @*
c[N] = ci;
for (g = N - 1; g >= 0; g = g - 1)
always @*
c[g] = i[g*4];
for (g = N - 1; g >= 0; g = g - 1)
always @*
begin
o[g*4+3:g*4] = {1'b0,i[g*4+3:g*4+1]};
// Because there is a divide by two, the value will range between 0 and 4.
// Adding 5 keeps it within deicmal boundaries of 0 to 9. No carry can be
// generated
if (c[N+1])
o[g*4+3:g*4] = o[g*4+3:g*4] + 4'd5;
end
assign co = c[0];
end
endgenerate
 
endmodule
/ft816float/trunk/rtl/verilog2/DFPSqrt.sv
0,0 → 1,178
// ============================================================================
// __
// \\__/ o\ (C) 2018-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPSqrt.v
// - decimal floating point square root
// - parameterized width
// - IEEE 754 representation
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import fp::*;
 
module DFPSqrt(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
parameter N=33;
localparam pShiftAmt =
FPWID==80 ? 48 :
FPWID==64 ? 36 :
FPWID==32 ? 7 : (FMSB+1-16);
input rst;
input clk;
input ce;
input ld;
input [N*4+16+4-1:0] a;
output reg [(N+1)*4*2+16+4-1:0] o;
output done;
output sqrinf;
output sqrneg;
 
// registered outputs
reg sign_exe;
reg inf;
reg overflow;
reg underflow;
 
wire so;
wire [15:0] xo;
wire [(N+1)*4*2-1:0] mo;
 
// constants
wire [15:0] infXp = 16'h9999; // infinite / NaN - all ones
// The following is a template for a quiet nan. (MSB=1)
wire [N*4-1:0] qNaN = {4'h1,{N*4-4{1'b0}}};
 
// variables
wire [15:0] ex1; // sum of exponents
wire ex1c;
wire [(N+1)*4*2-1:0] sqrto;
 
// Operands
wire sa; // sign bit
wire sx; // sign of exponent
wire [15:0] xa; // exponent bits
wire [N*4-1:0] siga;
wire a_dn; // a/b is denormalized
wire az;
wire aInf;
wire aNan;
wire done1;
wire [7:0] lzcnt;
wire [N*4-1:0] aa;
 
// -----------------------------------------------------------
// - decode the input operand
// - derive basic information
// - calculate exponent
// - calculate fraction
// -----------------------------------------------------------
 
DFPDecomposeReg u1
(
.clk(clk),
.ce(ce),
.i(a),
.sgn(sa),
.sx(sx),
.exp(xa),
.sig(siga),
.xz(a_dn),
.vz(az),
.inf(aInf),
.nan(aNan)
);
 
BCDAddN #(.N(4)) u4 (.ci(1'b0), .a(xa), .b(16'h0001), .o(ex1), .co() );
BCDSRL #(.N(4)) u5 (.ci(1'b0), .i(ex1), .o(xo), .co());
 
assign so = 1'b0; // square root of positive numbers only
assign mo = aNan ? {4'h1,aa[N*4-1:0],{N*4{1'b0}}} : sqrto; //(sqrto << pShiftAmt);
assign sqrinf = aInf;
assign sqrneg = !az & so;
 
wire [(N+1)*4-1:0] siga1 = xa[0] ? {siga,4'h0} : {4'h0,siga};
 
wire ldd;
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(ld), .o(ldd));
 
// Ensure an even number of digits are processed.
dfisqrt #((N+2)&-2) u2
(
.rst(rst),
.clk(clk),
.ce(ce),
.ld(ldd),
.a({4'h0,siga1}),
.o(sqrto),
.done(done)
);
 
always @*
casez({aNan,sqrinf,sqrneg})
3'b1??: o <= {1'b1,sa,1'b0,sx,xa,mo};
3'b01?: o <= {1'b1,sa,1'b1,sx,4'h1,qNaN|4'h5,{N*4-4{1'b0}}};
3'b001: o <= {1'b1,sa,1'b0,sx,4'h1,qNaN|4'h6,{N*4-4{1'b0}}};
default: o <= {1'b0,1'b1,1'b0,sx,xo,mo};
endcase
 
endmodule
 
module DFPSqrtnr(rst, clk, ce, ld, a, o, rm, done, inf, sqrinf, sqrneg);
parameter N=33;
input rst;
input clk;
input ce;
input ld;
input [N*4+16+4-1:0] a;
output [N*4+16+4-1:0] o;
input [2:0] rm;
output done;
output inf;
output sqrinf;
output sqrneg;
 
wire [(N+1)*4*2+16+4-1:0] o1;
wire inf1;
wire [N*4+16+4-1+4:0] fpn0;
wire done1;
wire done2;
 
DFPSqrt #(.N(N)) u1 (rst, clk, ce, ld, a, o1, done1, sqrinf, sqrneg);
DFPNormalize #(.N(N)) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
DFPRound #(.N(N)) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done2));
assign done = done1&done2;
 
endmodule
/ft816float/trunk/rtl/verilog2/DPD1000Decode.sv
1,3 → 1,39
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DPD1000Decode.sv
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module DPD1000Decode(clk, i, o);
input clk;
/ft816float/trunk/rtl/verilog2/DPD1000Encode.sv
1,3 → 1,39
// ============================================================================
// __
// \\__/ o\ (C) 2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DPD1000Encode.sv
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module DPD1000Encode(i, o);
input [11:0] i;
/ft816float/trunk/rtl/verilog2/dfisqrt.v
0,0 → 1,288
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2010-2020 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// dfisqrt.v
// - integer square root
// - uses the standard long form calc.
// - geared towards use in an decimal floating point unit
// - calculates to WID fractional precision (double width output)
//
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module dfisqrt(rst, clk, ce, ld, a, o, done);
parameter N=34;
parameter WID = N*4;
localparam MSB = WID-1;
input rst;
input clk;
input ce;
input ld;
input [MSB:0] a;
output reg [WID*2-1:0] o;
output reg done;
 
reg [3:0] state;
parameter SKIPLZ = 4'd1;
parameter A0 = 4'd2;
parameter S3 = 4'd3;
parameter INCJ = 4'd4;
parameter DONE = 4'd5;
parameter S1 = 4'd6;
parameter S4 = 4'd7;
parameter S2 = 4'd8;
 
reg [3:0] tbl [0:255];
reg [7:0] tbl5 [0:9];
reg [7:0] sqra [0:9];
 
initial begin
sqra[0] = 8'h00;
sqra[1] = 8'h01;
sqra[2] = 8'h04;
sqra[3] = 8'h09;
sqra[4] = 8'h16;
sqra[5] = 8'h25;
sqra[6] = 8'h36;
sqra[7] = 8'h49;
sqra[8] = 8'h64;
sqra[9] = 8'h81;
end
 
genvar g;
generate begin
for (g = 0; g < 256; g = g + 1)
initial begin
if (g >= 8'h81)
tbl[g] = 4'h9;
else if (g >= 8'h64)
tbl[g] = 4'h8;
else if (g >= 8'h49)
tbl[g] = 4'h7;
else if (g >= 8'h36)
tbl[g] = 4'h6;
else if (g >= 8'h25)
tbl[g] = 4'h5;
else if (g >= 8'h16)
tbl[g] = 4'h4;
else if (g >= 8'h09)
tbl[g] = 4'd3;
else if (g >= 8'h04)
tbl[g] = 4'h2;
else if (g >= 8'h01)
tbl[g] = 4'h1;
else
tbl[g] = 4'h0;
end
end
endgenerate
 
initial begin
tbl5[0] = 8'h05;
tbl5[1] = 8'h15;
tbl5[2] = 8'h25;
tbl5[3] = 8'h35;
tbl5[4] = 8'h45;
tbl5[5] = 8'h55;
tbl5[6] = 8'h65;
tbl5[7] = 8'h75;
tbl5[8] = 8'h85;
tbl5[9] = 8'h95;
end
 
 
reg [7:0] dcnt;
reg [7:0] j;
reg [N*2*4-1:0] b;
reg [N*4*2-1:0] ii;
wire [N*4*2-1:0] firstRa;
reg [N*4*2-1+4:0] ai, Rbx5;
wire [(N*2+1)*4-1:0] Rax2, Rax4, Rax5i, newRax5a;
reg [(N*2+1)*4-1:0] Rax5, pRax5, newRax5;
wire tooBig;
 
BCDAddN #(.N(N*2+1)) ua1 (.ci(1'b0), .a({4'h0,firstRa}), .b({4'h0,firstRa}), .o(Rax2), .co());
BCDAddN #(.N(N*2+1)) ua2 (.ci(1'b0), .a(Rax2), .b(Rax2), .o(Rax4), .co());
BCDAddN #(.N(N*2+1)) ua3 (.ci(1'b0), .a({4'h0,firstRa}), .b(Rax4), .o(Rax5i), .co());
 
BCDSubN #(.N(N*2+1)) ua4 (.ci(1'b0), .a(Rax5), .b(Rbx5), .o(newRax5a), .co(tooBig));
 
 
wire [3:0] a0 = tbl[ii[N*4*2-1:N*4*2-8]];
wire [7:0] sqra00 = sqra[a0];
wire [N*2*4+3:0] srqa0 = {4'h0,sqra00,{N*2*4-8{1'b0}}};
 
BCDSubN #(.N(N*2)) ua5 (.ci(1'b0), .a(ii), .b(srqa0), .o(firstRa), .co());
 
wire [WID*2-1:0] tbl5x = {tbl5[b[3:0]],{(N*2-3)*4{1'b0}}};
wire [WID*2-1:0] tbl5s = tbl5x >> {j,2'h0};
 
wire [N*2*4-1:0] sum_ai;
BCDAddN #(.N(N*2)) ua6 (.ci(1'b0), .a(ai), .b(tbl5s), .o(sum_ai), .co());
 
always @(posedge clk)
begin
case(state)
SKIPLZ:
begin
Rax5 <= {N*2*4+4{1'd0}};
Rbx5 <= {N*2*4+4{1'd0}};
if (ii[N*4*2-1:N*4*2-8]==8'h00) begin
ii <= {ii[N*4*2-9:0],8'h00};
dcnt <= dcnt - 8'd2;
if (dcnt==8'h00) begin
o <= {WID*2{1'b0}};
state <= DONE;
end
end
else
state <= A0;
end
// Get the first digit of the square root.
A0:
begin
b <= 4'd0;
ai <= {4'd0,a0,{(N*2-2)*4{1'b0}}};
state <= S1;
end
// Set initial Ra5
S1:
begin
Rax5 <= Rax5i;
Rbx5 <= {4'h0,sum_ai};
pRax5 <= Rax5i;
state <= S2;
end
S2:
begin
newRax5 <= newRax5a;
if (tooBig) begin
Rax5 <= {Rax5,4'h0};
ai <= ai | (b << (N*2-j)*4-8);
state <= INCJ;
end
else begin
b <= b + 1'd1;
state <= S3;
end
end
S3:
begin
pRax5 <= Rax5;
Rax5 <= newRax5;
Rbx5 <= {4'h0,sum_ai};
state <= S2;
end
INCJ:
begin
b <= 4'd0;
j <= j + 1'd1;
dcnt <= dcnt - 1'd1;
if (dcnt==0) begin
state <= DONE;
o <= ai;
end
else
state <= S4;
end
S4:
begin
Rbx5 <= {4'h0,sum_ai};
state <= S2;
end
DONE:
begin
done <= 1'b1;
end
endcase
if (ld) begin
state <= SKIPLZ;
dcnt <= N*2;
j <= 8'd1;
b <= 4'd0;
ii <= {a,{N*4{1'b0}}};
done <= 1'b0;
end
end
 
endmodule
 
 
module dfisqrt_tb();
parameter N=34;
 
reg clk;
reg rst;
reg [N*4-1:0] a;
wire [N*4*2-1:0] o;
reg ld;
wire done;
reg [7:0] state;
 
initial begin
clk = 1;
rst = 0;
#100 rst = 1;
#100 rst = 0;
end
 
always #10 clk = ~clk; // 50 MHz
 
always @(posedge clk)
if (rst) begin
state <= 8'd0;
a <= 64'h987654321;
end
else
begin
ld <= 1'b0;
case(state)
8'd0:
begin
a <= 64'h987654321;
ld <= 1'b1;
state <= 8'd1;
end
8'd1:
if (done) begin
$display("i=%h o=%h", a, o);
end
endcase
end
 
dfisqrt #(.N(N)) u1 (.rst(rst), .clk(clk), .ce(1'b1), .ld(ld), .a(a), .o(o), .done(done));
 
endmodule
 
 
/ft816float/trunk/test_bench/DFPDivide_tb.v
54,7 → 54,7
reg clk;
reg [15:0] adr;
reg [N*4+16+4-1:0] a,b;
wire [N*4+16+4-1:0] o;
wire [N*4+16+4-1:0] o, sqrto;
reg [N*4+16+4-1:0] ad,bd;
wire [N*4+16+4-1:0] od;
reg [3:0] rm;
106,11 → 106,11
begin
if (adr==0) begin
outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/DFPDivide_tvo.txt", "wb");
$fwrite(outfile, "rm ------ A ------ ------- B ------ - DUT Quotient - - SIM Quotient -\n");
$fwrite(outfile, "rm ------ A ------ ------- B ------ - DUT Quotient - - Square root -\n");
sum_cc = 0;
end
count <= count + 1;
if (count > 750)
if (count > 1000)
count <= 1'd1;
if (count==2) begin
a[N*4+16+4-1:0] <= a1;
145,9 → 145,17
a <= 152'h50000100000000000000000000000000000000;
b <= 152'h50000300000000000000000000000000000000;
end
if (count > 750) begin
if (adr==5 && count==2) begin
a <= 152'h50002100000000000000000000000000000000;
b <= 152'h50000300000000000000000000000000000000;
end
if (adr==6 && count==2) begin
a <= 152'h50002987654321000000000000000000000000;
b <= 152'h50000300000000000000000000000000000000;
end
if (count > 1000) begin
sum_cc = sum_cc + u6.u1.u2.clkcnt;
$fwrite(outfile, "%h\t%h\t%h\t%h\t%d\t%f\n", rm, a, b, o, u6.u1.u2.clkcnt, $itor(sum_cc) / $itor(adr));
$fwrite(outfile, "%h\t%h\t%h\t%h\t%h\t%d\t%f\n", rm, a, b, o, sqrto, u6.u1.u2.clkcnt, $itor(sum_cc) / $itor(adr));
adr <= adr + 1;
end
end
170,4 → 178,6
.underflow()
);
 
DFPSqrtnr #(.N(N)) u1 (rst, clk, 1'b1, count==3, a, sqrto, rm);//, sign_exe, inf, overflow, underflow);
 
endmodule

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